Control method and device for suppressing leakage current of two-level converter and power supply equipment

Abstract

The invention provides a control method and device for suppressing leakage current of a two-level converter and power supply equipment, and belongs to the technical field of power supplies. The control method for suppressing the leakage current of the two-level converter comprises the following steps: acquiring a target voltage vector of the two-level converter; and three non-zero basic voltage vectors with the same common-mode voltage are selected to synthesize a target voltage vector. The target voltage vector is synthesized through the three non-zero basic voltage vectors with the same common-mode voltage, so that the common-mode voltage of the two-level converter in a single switching period can be kept unchanged, namely, the change rate of the common-mode voltage of the two-level converter can be reduced, leakage current caused by the common-mode voltage can be relieved, and the reliability of the two-level converter is improved. Therefore, the electromagnetic interference can be weakened, and the possibility that the normal operation of the two-level converter is affected by the electromagnetic interference is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power supplies, and particularly to a control method, device, and power supply device for suppressing leakage current in a two-level converter. Background Art

[0002] The two-level converter has the advantages of simple structure, convenient control, and high conversion efficiency, and is widely used in the fields of industrial control, power electronic equipment, and renewable energy power generation.

[0003] In the related art, when synthesizing the target voltage vector of the two-level converter, usually two non-zero basic vectors and a zero vector in the sector where the target voltage vector is located are selected for synthesis. However, this method results in a large change rate of the common-mode voltage of the two-level converter, thereby causing a large leakage current and enhancing electromagnetic interference. Summary of the Invention

[0004] Embodiments of the present invention provide a control method, device, and power supply device for suppressing leakage current in a two-level converter to solve the problem in the prior art that the common-mode voltage of the two-level converter is large, resulting in a large leakage current and enhanced electromagnetic interference.

[0005] In a first aspect, embodiments of the present invention provide a control method for suppressing leakage current in a two-level converter, including:

[0006] Obtain the target voltage vector of the two-level converter;

[0007] Select three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector.

[0008] In a possible implementation manner, before selecting three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector, it further includes:

[0009] Determine the region where the target voltage vector is located;

[0010] Correspondingly, selecting three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector includes:

[0011] If the region where the target voltage vector is located is the first preset region, select three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector;

[0012] Among them, the first preset region includes a first sub-region and a second sub-region; the first sub-region includes a triangular region in the space vector hexagon with three non-zero first fundamental voltage vectors as vertices, and the common-mode voltages of the three first fundamental voltage vectors are all the first voltage; the second sub-region includes a triangular region in the space vector hexagon with three non-zero second fundamental voltage vectors as vertices, and the common-mode voltages of the three second fundamental voltage vectors are all the second voltage.

[0013] In a possible implementation, if the region where the target voltage vector is located is the first preset region, then three non-zero fundamental voltage vectors with the same common-mode voltage are selected to synthesize the target voltage vector, including:

[0014] If the region where the target voltage vector is located is the first sub-region, then the target voltage vector is synthesized based on the three first fundamental voltage vectors;

[0015] If the range where the target voltage vector is located is the second sub-region, then the target voltage vector is synthesized based on the three second fundamental voltage vectors.

[0016] In a possible implementation, the three first fundamental voltage vectors include NNP, PNN, and NPN; the three second fundamental voltage vectors include NPP, PPN, and PNP.

[0017] In a possible implementation, after determining the region where the target voltage vector is located, it further includes:

[0018] If the region where the target voltage vector is located is the second preset region, then two first fundamental voltage vectors are selected from the three non-zero first fundamental voltage vectors, and two second fundamental voltage vectors are selected from the three non-zero second fundamental voltage vectors to jointly synthesize the target voltage vector;

[0019] Among them, the second preset region is the region in the space vector hexagon except the first preset region.

[0020] In a possible implementation, determining the region where the target voltage vector is located includes:

[0021] Obtain the fundamental wave of the modulation wave of the three phases of the two-level converter;

[0022] Add the first zero-sequence component to the fundamental wave of the modulation wave of the three phases to obtain the first modulation wave of the three phases;

[0023] If the peak values of the first modulation wave of the three phases are all less than or equal to the preset standard peak value, then it is determined that the region where the target voltage vector is located is the first sub-region; the first zero-sequence component is the zero-sequence component corresponding to the first sub-region;

[0024] If the peak value of the first modulation wave of at least one phase is greater than a preset standard peak value, then add a second zero-sequence component to the fundamental wave of the modulation waves of the three phases to obtain the second modulation waves of the three phases;

[0025] If the valley values of the second modulation waves of the three phases are all greater than or equal to a preset standard valley value, then determine that the region where the target voltage vector is located is the second sub-region; the second zero-sequence component is the zero-sequence component corresponding to the second sub-region;

[0026] If the valley value of the second modulation wave of at least one phase is less than the preset standard valley value, then determine that the region where the target voltage vector is located is the second preset region; the second preset region is the region in the space vector hexagon except the first preset region.

[0027] In a possible implementation, during the process of synthesizing the target voltage vector, select the phase with the minimum current or the maximum current among the three phases of the two-level converter as the phase with the most switching times within one cycle.

[0028] In a second aspect, an embodiment of the present invention provides a control device for suppressing leakage current of a two-level converter, including:

[0029] An acquisition module, configured to acquire the target voltage vector of the two-level converter;

[0030] A synthesis module, configured to select three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector.

[0031] In a third aspect, an embodiment of the present invention provides a control device, including a processor and a memory, where the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the control method for suppressing leakage current of the two-level converter as described in the first aspect or any possible implementation manner of the first aspect above.

[0032] In a fourth aspect, an embodiment of the present invention provides a two-level converter, including conversion units corresponding to three phases respectively and the control device as described in the third aspect; the conversion units are controlled by the control device.

[0033] In a fifth aspect, an embodiment of the present invention provides a power supply device, including the two-level converter as described in the fourth aspect.

[0034] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps of the control method for suppressing leakage current of the two-level converter as described in the first aspect or any possible implementation manner of the first aspect above.

[0035] An embodiment of the present invention provides a control method, device and power supply device for suppressing leakage current of a two-level converter. The method synthesizes a target voltage vector through three non-zero basic voltage vectors with the same common-mode voltage, so that the common-mode voltage of the two-level converter can be kept unchanged within a single switching period, that is, the change rate of the common-mode voltage of the two-level converter can be reduced, the leakage current caused by the common-mode voltage can be alleviated, and further the electromagnetic interference can be weakened, and the possibility of affecting the normal operation of the two-level converter due to electromagnetic interference can be reduced. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic flowchart of the control method for suppressing leakage current of a two-level converter provided by an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of a first preset area provided by an embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of a first sub-area provided by an embodiment of the present invention;

[0040] Figure 4 It is a schematic diagram of a second sub-area provided by an embodiment of the present invention;

[0041] Figure 5 It is a schematic diagram of the control waveform signals of three phases corresponding to synthesizing a target voltage vector by using three first basic voltage vectors provided by an embodiment of the present invention;

[0042] Figure 6 It is a schematic diagram of the control waveform signals of three phases corresponding to synthesizing a target voltage vector by using three second basic voltage vectors provided by an embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of a second preset area provided by an embodiment of the present invention;

[0044] Figure 8 It is a schematic diagram of the control waveform signals of three phases corresponding to jointly synthesizing a target voltage vector by using two first basic voltage vectors and two second basic voltage vectors provided by an embodiment of the present invention;

[0045] Figure 9 It is a schematic diagram of the common-mode voltage and leakage current of a two-level converter provided by an embodiment of the present invention;

[0046] Figure 10 It is a schematic diagram of the control waveform signals of three-phase corresponding to three first basic voltage vectors provided by an embodiment of the present invention under different sorting methods;

[0047] Figure 11 It is a schematic structural diagram of a control device for suppressing leakage current of a two-level converter provided by an embodiment of the present invention;

[0048] Figure 12 It is a schematic diagram of a control device provided by an embodiment of the present invention. Detailed implementation manners

[0049] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0050] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will be described through specific embodiments with reference to the accompanying drawings.

[0051] See Figure 1 , which shows a flowchart of the implementation of a control method for suppressing leakage current of a two-level converter provided by an embodiment of the present invention. The execution subject of the control method for suppressing leakage current of the two-level converter is a control device, and the control device can be a device such as a controller. The two-level converter is a two-level three-phase converter, and specifically can be a two-level three-phase half-bridge inverter.

[0052] The control method for suppressing leakage current of the two-level converter is described in detail as follows:

[0053] In S101, obtain the target voltage vector of the two-level converter.

[0054] The target voltage vector of the two-level converter can be understood as the voltage vector that the two-level converter expects to output, and can be determined according to the three-phase voltages that the two-level converter expects to output.

[0055] In S102, select three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector.

[0056] There are 8 basic voltage vectors related to the two-level converter, which are NNP(001), PNN(100), NPN(010), NPP(011), PPN(110), PNP(101), NNN(000), and PPP(111). Among them, NNN and PPP are zero vectors, and the other basic voltage vectors are non-zero vectors.

[0057] Among the six non - zero basic voltage vectors, the common - mode voltages of NNP, PNN, and NPN are the same, all being -V DC / 6, and the common - mode voltages of NPP, PPN, and PNP are the same, all being V DC / 6. Wherein, V DC is the DC bus voltage of the two - level converter.

[0058] In the embodiment of the present application, three non - zero basic voltage vectors with the same common - mode voltage are selected to synthesize the target voltage vector, that is, NNP, PNN, and NPN are selected, or NPP, PPN, and PNP are selected to synthesize the target voltage vector, so that the common - mode voltage within a single switching period can be kept constant, always being -V DC / 6, or always being V DC / 6.

[0059] In the embodiment of the present application, the target voltage vector is synthesized by three non - zero basic voltage vectors with the same common - mode voltage, so that the common - mode voltage of the two - level converter can be kept constant within a single switching period. That is, the change rate of the common - mode voltage of the two - level converter can be reduced, the leakage current caused by the common - mode voltage can be alleviated, and further the electromagnetic interference can be weakened, and the possibility that the normal operation of the two - level converter is affected by the electromagnetic interference can be reduced, or the cost of electromagnetic compatibility (EMC) can be reduced.

[0060] In some embodiments, before the above - mentioned S102, the control method for the two - level converter to suppress the leakage current may further include:

[0061] Determine the region where the target voltage vector is located;

[0062] Correspondingly, the above - mentioned selection of three non - zero basic voltage vectors with the same common - mode voltage to synthesize the target voltage vector includes:

[0063] If the region where the target voltage vector is located is the first preset region, then select three non - zero basic voltage vectors with the same common - mode voltage to synthesize the target voltage vector;

[0064] Among them, the first preset region includes a first sub - region and a second sub - region; the first sub - region includes a triangular region in the space vector hexagon with three non - zero first basic voltage vectors as vertices, and the common - mode voltages of the three first basic voltage vectors are all the first voltage; the second sub - region includes a triangular region in the space vector hexagon with three non - zero second basic voltage vectors as vertices, and the common - mode voltages of the three second basic voltage vectors are all the second voltage.

[0065] See Figures 2 to 4 ,Figure 2 shows a space vector hexagon, a target voltage vector 21, a first sub-region 23, and a second sub-region 24; Figure 3 shows the space vector hexagon and the first sub-region 23; Figure 4 shows the space vector hexagon and the second sub-region 24. As Figure 2 and Figure 3 shown, the first sub-region 23 is a triangular region with three non-zero first basic voltage vectors as vertices, that is, the triangular region with NNP, PNN, and NPN as vertices. As Figure 2 and Figure 4 shown, the second sub-region 24 is a triangular region with three non-zero second basic voltage vectors as vertices, that is, the triangular region with NPP, PPN, and PNP as vertices.

[0066] See Figure 2 , there is an overlapping region between the first sub-region 23 and the second sub-region 24. Therefore, the first preset region is the union of the first sub-region and the second sub-region.

[0067] Figure 2 The target voltage vector 21 is also shown, Figure 2 The 22 in [] is the circular range obtained by rotating the target voltage vector 21 one full circle, which can be understood as the maximum range of the target voltage vector that can be completely synthesized by three non-zero basic voltage vectors with the same common-mode voltage.

[0068] The target voltage vector 21 can only be synthesized by three non-zero basic voltage vectors with the same common-mode voltage when it is within the first preset region. Therefore, in the embodiments of the present application, first, the region where the target voltage vector is located is determined. When the region where the target voltage vector is located is within the first preset region, three non-zero basic voltage vectors with the same common-mode voltage are selected to synthesize the target voltage vector.

[0069] Among them, the common-mode voltages of the three first basic voltage vectors are all the first voltage, and the first voltage is -V DC / 6; the common-mode voltages of the three second basic voltage vectors are all the second voltage, and the second voltage is V DC / 6. That is to say, in the embodiments of the present application, the non-zero basic voltage vector with the common-mode voltage being the first voltage is called the first basic voltage vector, and the non-zero basic voltage vector with the common-mode voltage being the second voltage is called the second basic voltage vector. The first voltage and the second voltage are different.

[0070] In some embodiments, if the region where the target voltage vector is located is the first preset region, then selecting three non-zero basic voltage vectors with the same common-mode voltage to synthesize the target voltage vector includes:

[0071] If the target voltage vector is in the first sub-region, the target voltage vector is synthesized based on three first basic voltage vectors;

[0072] If the target voltage vector is in the second sub-region, the target voltage vector is synthesized based on three second basic voltage vectors.

[0073] See Figures 2 to 4 , if the target voltage vector is in the first sub-region 23, three first basic voltage vectors corresponding to the first sub-region are used to synthesize the target voltage vector; if the target voltage vector is in the second sub-region 24, three second basic voltage vectors corresponding to the second sub-region are used to synthesize the target voltage vector.

[0074] It should be noted that if the target voltage vector is both in the first sub-region and in the second sub-region, the target voltage vector can be synthesized either based on three first basic voltage vectors or based on three second basic voltage vectors. It can be selected according to actual needs whether to use three first basic voltage vectors or three second basic voltage vectors to synthesize the target voltage vector. For example, the switching loss can be considered, and the three first basic voltage vectors or the three second basic voltage vectors can be selected to synthesize the target voltage vector with the minimum switching loss as the goal.

[0075] In some embodiments, as described above, the three first basic voltage vectors include NNP, PNN, and NPN; the three second basic voltage vectors include NPP, PPN, and PNP.

[0076] Exemplarily, the control waveform signals of the three phases corresponding to synthesizing the target voltage vector using three first basic voltage vectors are as Figure 5 shown, and the corresponding common-mode voltage is always -V DC / 6. The control waveform signals of the three phases corresponding to synthesizing the target voltage vector using three second basic voltage vectors are as Figure 6 shown, and the corresponding common-mode voltage is always V DC / 6.

[0077] As Figure 2 shown, in the space vector hexagon, in addition to the first preset region, there are other regions, that is, the space vector hexagon is not completely covered by the first preset region, and the method in the foregoing embodiments is only applicable to the target voltage vector located in the first preset region to achieve leakage current suppression, that is, it is only applicable to the working condition of a low modulation ratio and cannot be applied to the working condition of a high modulation ratio. Therefore, how to minimize the leakage current in the full modulation ratio range is an urgent problem to be solved. The following is a detailed introduction.

[0078] In some embodiments, after determining the region where the target voltage vector is located, it further includes:

[0079] If the region where the target voltage vector is located is the second preset region, two first basic voltage vectors are selected from the three non-zero first basic voltage vectors, and two second basic voltage vectors are selected from the three non-zero second basic voltage vectors to jointly synthesize the target voltage vector;

[0080] Among them, the second preset region is the region in the space vector hexagon except the first preset region.

[0081] See Figure 7 , in the space vector hexagon, the region except the first preset region is used as the second preset region 25. That is, the space vector hexagon is composed of the first preset region and the second preset region 25.

[0082] At a high modulation ratio, the target voltage vector 21 may be located in the second preset region 25. As Figure 7 shown, at this time, it is not possible to synthesize using three first basic voltage vectors or three second basic voltage vectors. Therefore, in the embodiment of the present application, when the region where the target voltage vector is located is the second preset region, two first basic voltage vectors are randomly selected from the three first basic voltage vectors, and at the same time, two second basic voltage vectors are randomly selected from the three second basic voltage vectors. Two first basic voltage vectors and two second basic voltage vectors are used to jointly synthesize the target voltage vector. In this case, the common-mode voltage switches between -V DC / 6 and V DC / 6, and the amplitude of the common-mode voltage decreases. Similarly, the leakage current caused by the common-mode voltage can be reduced, and thus the leakage current can be minimized within the full modulation ratio range.

[0083] In some possible implementation manners, the above selection of two first basic voltage vectors from the three non-zero first basic voltage vectors may include: selecting two first basic voltage vectors adjacent to the target voltage vector from the three non-zero first basic voltage vectors. As Figure 7 shown, the two first basic voltage vectors adjacent to the target voltage vector in Figure 7 are NPN and PNN, and there is still NPN or PNN between NNP and the target voltage vector.

[0084] The above selection of two second basic voltage vectors from the three non-zero second basic voltage vectors may include: selecting two second basic voltage vectors adjacent to the target voltage vector from the three non-zero second basic voltage vectors. As Figure 7 shown, the two second basic voltage vectors adjacent to the target voltage vector in Figure 7 are PPN and PNP, and there is still PPN or PNP between NPP and the target voltage vector.

[0085] Exemplarily, when synthesizing a target voltage vector using two first basic voltage vectors and two second basic voltage vectors, the control waveform signals of the three phases are as follows Figure 8 shown, and the corresponding common-mode voltage switches between -V DC / 6 and V DC / 6.

[0086] Refer to Figure 9 , from top to bottom are the current, common-mode voltage, and leakage current of the two-level converter after being controlled by the method provided in the embodiment of the present application. As Figure 9 shown, the leakage current is significantly smaller.

[0087] In some embodiments, determining the region where the target voltage vector is located includes:

[0088] Obtaining the fundamental modulation waves of the three phases of the two-level converter;

[0089] Adding a first zero-sequence component to the fundamental modulation waves of the three phases to obtain the first modulation waves of the three phases;

[0090] If the peak values of the first modulation waves of the three phases are all less than or equal to a preset standard peak value, it is determined that the region where the target voltage vector is located is the first sub-region; the first zero-sequence component is the zero-sequence component corresponding to the first sub-region;

[0091] If the peak value of at least one phase of the first modulation waves is greater than the preset standard peak value, then add a second zero-sequence component to the fundamental modulation waves of the three phases to obtain the second modulation waves of the three phases;

[0092] If the valley values of the second modulation waves of the three phases are all greater than or equal to a preset standard valley value, it is determined that the region where the target voltage vector is located is the second sub-region; the second zero-sequence component is the zero-sequence component corresponding to the second sub-region;

[0093] If the valley value of at least one phase of the second modulation waves is less than the preset standard valley value, it is determined that the region where the target voltage vector is located is the second preset region; the second preset region is the region in the space vector hexagon except the first preset region.

[0094] Among them, the fundamental modulation waves of the three phases include the fundamental modulation wave of phase A, the fundamental modulation wave of phase B, and the fundamental modulation wave of phase C. The fundamental modulation wave of each phase is a sine wave, which can be understood as a sine wave signal with the same frequency as the expected output sine wave voltage. The fundamental modulation waves of the three phases have a certain phase difference. After adding the zero-sequence component to the fundamental modulation wave of each phase, the corresponding modulation wave of each phase is obtained.

[0095] Both the first sub-region and the second sub-region have their respective corresponding zero-sequence components. In the embodiments of the present application, the zero-sequence component corresponding to the first sub-region is referred to as the first zero-sequence component, and the zero-sequence component corresponding to the second sub-region is referred to as the second zero-sequence component. The modulation wave fundamental wave of each phase plus the first zero-sequence component is called the first modulation wave of each phase. The modulation wave fundamental wave of each phase plus the second zero-sequence component is called the second modulation wave of each phase.

[0096] The peak value of the modulation wave of each phase has a maximum limit value, which is called the preset standard peak value, and the symbol is U m ; the valley value of the modulation wave of each phase has a minimum valley value, which is called the preset standard valley value, and the preset standard valley value is usually the opposite of the preset standard peak value. If the peak value of the modulation wave of any one phase is greater than the preset standard peak value or the valley value of the modulation wave of any one phase is less than the preset standard valley value, it indicates that overshoot has occurred, that is, the basic voltage vectors in the corresponding region cannot be used to synthesize the target voltage vector.

[0097] In some possible implementation manners, the preset standard peak value is U m , and the preset standard valley value is -U m . Correspondingly, the first zero-sequence component is 1 / 3U m , and the second zero-sequence component is -1 / 3U m . Exemplarily, assuming that the modulation waves of each phase are all waveforms after normalization, then, the preset standard peak value is 1, and the preset standard valley value is -1. Correspondingly, the first zero-sequence component is 1 / 3, and the second zero-sequence component is -1 / 3.

[0098] In the embodiments of the present application, first, the modulation wave fundamental wave of each phase is added with the first zero-sequence component to obtain the first modulation wave of each phase. Then, it is judged whether the peak values of the first modulation waves of each phase are all less than or equal to the preset standard peak value; if the peak values of the first modulation waves of each phase are all less than or equal to the preset standard peak value, it indicates that overshoot has not occurred, and the three first basic voltage vectors corresponding to the first sub-region can be used to synthesize the target voltage vector. Therefore, it can be determined that the region where the target voltage vector is located is the first sub-region; if there is at least one phase whose first modulation wave peak value is greater than the preset standard peak value, it indicates that overshoot has occurred, and the three first basic voltage vectors corresponding to the first sub-region cannot be used to synthesize the target voltage vector. Therefore, it can be determined that the region where the target voltage vector is located is not the first sub-region.

[0099] Next, the fundamental wave of the modulation wave of each phase can be added with the second zero-sequence component to obtain the second modulation wave of each phase. Then, it is determined whether the valley values of the second modulation waves of all phases are greater than or equal to a preset standard valley value; if the valley values of the second modulation waves of all phases are greater than or equal to the preset standard valley value, it indicates that there is no overshoot phenomenon, and the target voltage vector can be synthesized using the three second basic voltage vectors corresponding to the second sub-region. Therefore, it can be determined that the region where the target voltage vector is located is the second sub-region; if the valley value of at least one phase of the second modulation wave is less than the preset standard valley value, it indicates that an overshoot phenomenon has occurred, and the target voltage vector cannot be synthesized using the three second basic voltage vectors corresponding to the second sub-region. Therefore, it can be determined that the region where the target voltage vector is located is not the second sub-region. At this time, it can be determined that the region where the target voltage vector is located is the second preset region.

[0100] In some embodiments, during the process of synthesizing the target voltage vector, the phase with the minimum current or the maximum current among the three phases of the two-level converter is selected as the phase with the most switching times within one period.

[0101] The number of switching times within one period can be understood as the number of times of switching between N and P within one period. Among them, the period can be the switching period.

[0102] See Figure 5 and Figure 6 , there is a phenomenon that the number of switching times of one phase within one period of the control waveform signals of the three phases is more than that of the other two phases within one period. Figure 5 For the control waveform signals of the three phases shown, the number of switching times of the control waveform signal in the first row is 4, and the number of switching times of the control waveform signals in the second row and the third row is 2. Figure 6 For the control waveform signals of the three phases shown, the number of switching times of the control waveform signal in the third row is 4, and the number of switching times of the control waveform signals in the first row and the second row is 2.

[0103] By the sorting method of the basic voltage vectors for synthesizing the target voltage vector, the number of switching times of different phases within one period can be changed.

[0104] Exemplarily, see Figure 10 , taking the synthesis of the target voltage vector by three first basic voltage vectors as an example, assuming that the three control waveform signals from top to bottom are the control waveform signal of phase A, the control waveform signal of phase B, and the control waveform signal of phase C. If the sorting of the three first basic voltage vectors is NNP, PNN, NPN, PNN, and NNP, then the control waveform signals of the three phases are Figure 10 For the leftmost control waveform signal, the phase with the most switching times within one period is phase A. If the sorting of the three first basic voltage vectors is NNP, NPN, PNN, NPN, and NNP, then the control waveform signals of the three phases are Figure 10The middle control waveform signal. Among the three phases, the phase with the most switching times within one period is phase B. If the sorting of the three first basic voltage vectors is PNN, NNP, NPN, NNP, and PNN, then the control waveform signals of the three phases are Figure 10 The rightmost control waveform signal. Among the three phases, the phase with the most switching times within one period is phase C.

[0105] In the embodiment of the present application, the phase with the smallest current among the three phases can be selected as the phase with the most switching times within one period. Since the larger the current, the greater the switching loss, therefore, selecting the phase with the smallest current as the phase with the most switching times within one period can reduce the switching loss.

[0106] If there are two phases with the most switching times within one period of the control waveform signals, the phase with the smallest current and the phase with the second smallest current can be selected as these two phases to reduce the switching loss.

[0107] In another implementation manner, the phase with the largest current among the three phases can be selected as the phase with the most switching times within one period, so that the current ripple of this phase can be minimized, and further optimize the quality of the output current. Specifically, the point with the largest current ripple amplitude is usually at the current peak, and the phase with the largest current has a larger ripple due to the large saturation degree of the magnetic powder core inductor. Therefore, selecting the phase with the largest current as the phase with the most switching times within one period can optimize the current ripple of this phase, and further optimize the quality of the output current.

[0108] If there are two phases with the most switching times within one period of the control waveform signals, the phase with the largest current and the phase with the second largest current can be selected as these two phases to optimize the quality of the output current.

[0109] Specifically, whether to select the phase with the largest current or the phase with the smallest current as the phase with the most switching times within one period can be determined according to actual requirements.

[0110] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0111] Figure 11 The structural schematic diagram of the control device for suppressing leakage current of the two-level converter provided by the embodiment of the present invention is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown, and are described in detail as follows:

[0112] As Figure 11 shown, the control device 30 for suppressing leakage current of the two-level converter includes: an acquisition module 31 and a synthesis module 32.

[0113] The acquisition module 31 is used to acquire the target voltage vector of the two-level converter;

[0114] A synthesis module 32, configured to select three non - zero basic voltage vectors with the same common - mode voltage and synthesize a target voltage vector.

[0115] In a possible implementation manner, the control device 30 for suppressing leakage current of the two - level converter further includes: a region determination module.

[0116] The region determination module is configured to: before selecting three non - zero basic voltage vectors with the same common - mode voltage to synthesize a target voltage vector, determine the region where the target voltage vector is located.

[0117] Correspondingly, the synthesis module 32 is specifically configured to:

[0118] If the region where the target voltage vector is located is the first preset region, select three non - zero basic voltage vectors with the same common - mode voltage and synthesize the target voltage vector;

[0119] Wherein, the first preset region includes a first sub - region and a second sub - region; the first sub - region includes a triangular region in the space vector hexagon with three non - zero first basic voltage vectors as vertices, and the common - mode voltages of the three first basic voltage vectors are all the first voltage; the second sub - region includes a triangular region in the space vector hexagon with three non - zero second basic voltage vectors as vertices, and the common - mode voltages of the three second basic voltage vectors are all the second voltage.

[0120] In a possible implementation manner, in the synthesis module 32, if the region where the target voltage vector is located is the first preset region, selecting three non - zero basic voltage vectors with the same common - mode voltage and synthesizing the target voltage vector includes:

[0121] If the region where the target voltage vector is located is the first sub - region, synthesize the target voltage vector based on the three first basic voltage vectors;

[0122] If the range where the target voltage vector is located is the second sub - region, synthesize the target voltage vector based on the three second basic voltage vectors.

[0123] In a possible implementation manner, the three first basic voltage vectors include NNP, PNN, and NPN; the three second basic voltage vectors include NPP, PPN, and PNP.

[0124] In a possible implementation manner, the synthesis module 32 can also be configured to:

[0125] If the region where the target voltage vector is located is the second preset region, select two first basic voltage vectors from the three non - zero first basic voltage vectors and select two second basic voltage vectors from the three non - zero second basic voltage vectors, and jointly synthesize the target voltage vector;

[0126] Among them, the second preset region is the region in the space vector hexagon except the first preset region.

[0127] In a possible implementation manner, the region determination module is specifically configured to:

[0128] Obtain the fundamental wave of the modulation wave of the three phases of the two-level converter;

[0129] Add the first zero-sequence component to the fundamental wave of the modulation wave of the three phases to obtain the first modulation wave of the three phases;

[0130] If the peak values of the first modulation wave of the three phases are all less than or equal to the preset standard peak value, determine that the region where the target voltage vector is located is the first sub-region; the first zero-sequence component is the zero-sequence component corresponding to the first sub-region;

[0131] If the peak value of the first modulation wave of at least one phase is greater than the preset standard peak value, add the second zero-sequence component to the fundamental wave of the modulation wave of the three phases to obtain the second modulation wave of the three phases;

[0132] If the valley values of the second modulation wave of the three phases are all greater than or equal to the preset standard valley value, determine that the region where the target voltage vector is located is the second sub-region; the second zero-sequence component is the zero-sequence component corresponding to the second sub-region;

[0133] If the valley value of the second modulation wave of at least one phase is less than the preset standard valley value, determine that the region where the target voltage vector is located is the second preset region; the second preset region is the region in the space vector hexagon except the first preset region.

[0134] In a possible implementation manner, during the process of synthesizing the target voltage vector, select the phase with the minimum current or the maximum current among the three phases of the two-level converter as the phase with the most switching times in one cycle.

[0135] Figure 12 It is a schematic diagram of the control device provided by the embodiment of the present invention. As Figure 12 shown, the control device 4 of this embodiment includes: a processor 40 and a memory 41. The memory 41 is used to store a computer program 42, and the processor 40 is used to call and run the computer program 42 stored in the memory 41 to execute the steps in the above-mentioned embodiments of the control method for suppressing leakage current of each two-level converter, such as Figure 1 shown S101 to S102. Or, the processor 40 is used to call and run the computer program 42 stored in the memory 41 to implement the functions of each module / unit in the above-mentioned device embodiments, such as Figure 11 the functions of each module shown.

[0136] Exemplarily, the computer program 42 may be divided into one or more modules / units, which are stored in the memory 41 and executed by the processor 40 to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program 42 in the control device 4. For example, the computer program 42 may be divided into Figure 11 each of the modules shown.

[0137] The control device 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art can understand that Figure 12 merely being examples of the control device 4 does not constitute a limitation on the control device 4. It may include more or fewer components than shown in the figure, or combine certain components, or have different components. For example, the control device may further include input / output devices, network access devices, a bus, etc.

[0138] The processor 40 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0139] The memory 41 may be an internal storage unit of the control device 4, such as the hard disk or memory of the control device 4. The memory 41 may also be an external storage device of the control device 4, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the control device 4. Further, the memory 41 may also include both the internal storage unit and the external storage device of the control device 4. The memory 41 is used to store the computer program and other programs and data required by the control device 4. The memory 41 may also be used to temporarily store data that has been output or is to be output.

[0140] Corresponding to the above control device, an embodiment of the present invention further provides a two-level converter, including conversion units corresponding to three phases respectively and any one of the above control devices; the conversion units are controlled by the control device.

[0141] Specifically, each phase's conversion unit may include two switching tubes, one switching tube is located on the upper arm of the corresponding phase, and the other switching tube is located on the lower arm of the corresponding phase. The switching tubes of each phase are all controlled by the above control device.

[0142] For the related description of the two-level converter, reference can be made to the description in the foregoing embodiments, and details will not be repeated here.

[0143] Corresponding to the above two-level converter, an embodiment of the present application further provides a power supply device, including the above two-level converter.

[0144] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

[0145] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0147] In the embodiments provided by the present invention, it should be understood that the disclosed device / control equipment and method can be implemented in other ways. For example, the device / control equipment embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0148] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0150] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above embodiments of the control method for suppressing leakage current of each two-level converter can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device that can carry the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0151] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A control method for suppressing leakage current of a two-level converter, characterized in that: include: Obtaining a target voltage vector of a two-level converter; Three non-zero basic voltage vectors with the same common mode voltage are selected to synthesize the target voltage vector.

2. The control method for suppressing leakage current of a two-level converter according to claim 1, characterized in that: Before selecting three non-zero basic voltage vectors with the same common mode voltage to synthesize the target voltage vector, the method further includes: Determining a region where the target voltage vector is located; Accordingly, the selecting three non-zero basic voltage vectors with the same common mode voltage to synthesize the target voltage vector includes: If the region where the target voltage vector is located is the first preset region, three non-zero basic voltage vectors with the same common mode voltage are selected to synthesize the target voltage vector; Among them, the first preset area includes a first sub-area and a second sub-area; the first sub-area includes a triangular area with three non-zero first basic voltage vectors as vertices in the space vector hexagon, and the common mode voltages of the three first basic voltage vectors are all the first voltage; the second sub-area includes a triangular area with three non-zero second basic voltage vectors as vertices in the space vector hexagon, and the common mode voltages of the three second basic voltage vectors are all the second voltage.

3. The control method for suppressing leakage current of a two-level converter according to claim 2, characterized in that: If the region where the target voltage vector is located is the first preset region, three non-zero basic voltage vectors with the same common mode voltage are selected to synthesize the target voltage vector, including: If the region where the target voltage vector is located is the first sub-region, synthesizing the target voltage vector based on the three first basic voltage vectors; If the range where the target voltage vector is located is the second sub-area, the target voltage vector is synthesized based on three second basic voltage vectors.

4. The control method for suppressing leakage current of a two-level converter according to claim 3, characterized in that: The three first basic voltage vectors include NNP, PNN and NPN; the three second basic voltage vectors include NPP, PPN and PNP.

5. The control method for suppressing leakage current of a two-level converter according to claim 2, characterized in that: After determining the area where the target voltage vector is located, the method further includes: If the area where the target voltage vector is located is the second preset area, two first basic voltage vectors are selected from the three non-zero first basic voltage vectors, and two second basic voltage vectors are selected from the three non-zero second basic voltage vectors to synthesize the target voltage vector together; The second preset area is an area in the space vector hexagon except the first preset area.

6. The control method for suppressing leakage current of a two-level converter according to claim 2, characterized in that: The determining the area where the target voltage vector is located includes: Obtaining a three-phase modulation wave fundamental wave of the two-level converter; Adding a first zero-sequence component to the three-phase modulation wave fundamental wave to obtain a three-phase first modulation wave; If the peak values ​​of the first modulation waves of the three phases are all less than or equal to the preset standard peak values, it is determined that the region where the target voltage vector is located is the first sub-region; the first zero-sequence component is the zero-sequence component corresponding to the first sub-region; If the peak value of the first modulation wave of at least one phase is greater than the preset standard peak value, the second zero-sequence component is added to the modulation wave fundamental wave of the three phases to obtain the second modulation wave of the three phases; If the valley values ​​of the second modulation waves of the three phases are all greater than or equal to the preset standard valley values, it is determined that the region where the target voltage vector is located is the second sub-region; the second zero-sequence component is the zero-sequence component corresponding to the second sub-region; If the valley value of the second modulation wave of at least one phase is smaller than the preset standard valley value, the region where the target voltage vector is located is determined to be the second preset region; the second preset region is the region in the space vector hexagon excluding the first preset region.

7. The control method for suppressing leakage current of a two-level converter according to any one of claims 1 to 6, characterized in that: In the process of synthesizing the target voltage vector, the phase with the smallest current or the phase with the largest current among the three phases of the two-level converter is selected as the phase with the largest number of switching times in one cycle.

8. A control device for suppressing leakage current of a two-level converter, characterized in that: include: An acquisition module, used for acquiring a target voltage vector of a two-level converter; The synthesis module is used to select three non-zero basic voltage vectors with the same common mode voltage to synthesize the target voltage vector.

9. A two-level converter, characterized in that: It comprises conversion units and control devices corresponding to three phases respectively; the control device is used to execute the control method for suppressing leakage current of a two-level converter as described in any one of claims 1 to 7; the conversion unit is controlled by the control device.

10. A power supply device, characterized in that: Comprising the two-level inverter as claimed in claim 9.

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