Relaxation oscillator, chip and electronic device

Abstract

The present application provides a relaxation oscillator, a chip, and an electronic device. The relaxation oscillator includes: a bias module, a first generating module, a first comparator, a second generating module, a second comparator, and a control logic module. The first generating module and the second generating module alternately enter a first working mode and a second working mode. In the first working mode, a reference voltage is input to the non-inverting input terminal. When the voltage at the inverting input terminal rises from a preset starting voltage to a reference voltage, a discharge signal is output to reduce the voltage at the inverting input terminal. When the voltage at the inverting input terminal drops to the reference voltage, the discharge signal is stopped from being output to maintain the voltage at the inverting input terminal at the reference voltage. In the second working mode, a reference voltage is input to the inverting input terminal. The first comparator or the second comparator is reset when the non-inverting input terminal is grounded and reset until the voltage at the non-inverting input terminal reaches the reference voltage, and the first output signal or the second output signal is correspondingly output.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a relaxation oscillator, a chip, and an electronic device. Background Art

[0002] Ideally, the RC value determines the nominal frequency of the relaxation oscillator. The main issues that arise in relaxation oscillators are offset voltage, delay time, leakage and tunneling currents, and current mismatch. The offset voltage is primarily due to mismatch between the quasi-differential transistors in the comparator. Transistor sizing can minimize the offset voltage. Typically, the offset voltage increases linearly with temperature and varies slightly with supply voltage. The comparator's delay time primarily determines the overall circuit delay time. The delay time is also sensitive to temperature and power supply variations. It exhibits nonlinear behavior over temperature and is directly related to the comparator's bandwidth.

[0003] Relaxation oscillators typically employ current-mode, exponential RC-time-mode, or voltage-mode architectures. Frequency stability is often affected by process, voltage, and temperature (PVT) variations. Comparator offset during PVT variations is often the primary challenge in achieving stable frequency in ultra-low-power relaxation oscillators. Summary of the Invention

[0004] The present application provides a relaxation oscillator, a chip, and an electronic device for providing an oscillation clock frequency with higher precision without increasing power consumption.

[0005] In a first aspect, an embodiment of the present application provides a relaxation oscillator, comprising:

[0006] Bias module;

[0007] a first generating module, the first generating module being connected to the bias module to obtain a reference voltage provided by the bias module;

[0008] a first comparator, wherein an inverting input terminal of the first comparator is connected to a first output terminal of the first generating module, and a non-inverting input terminal of the first comparator is connected to a second output terminal of the first generating module;

[0009] a second generating module, the second generating module being connected to the bias module to obtain a reference voltage provided by the bias module;

[0010] a second comparator, wherein an inverting input terminal of the second comparator is connected to the first output terminal of the second generating module, and a non-inverting input terminal of the second comparator is connected to the second output terminal of the second generating module;

[0011] a control logic module, the control logic module being connected to the output terminal of the first comparator and the output terminal of the second comparator respectively, and the control logic module being configured to generate a clock pulse according to a first output signal of the first comparator and a second output signal of the second comparator;

[0012] In which, the first generating module and the second generating module alternately enter a first working mode and a second working mode. In the first working mode, the reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage of the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage of the inverting input terminal decreases, and stops outputting the discharge signal when the voltage of the inverting input terminal decreases to the reference voltage, so that the voltage of the inverting input terminal remains at the reference voltage; in the second working mode, the reference voltage is input to the inverting input terminal, and the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator outputs the first output signal or the second output signal correspondingly in the interval from when the non-inverting input terminal is grounded and reset to when the voltage of the non-inverting input terminal reaches the reference voltage.

[0013] In a second aspect, an embodiment of the present application provides a chip, comprising a relaxation oscillator as described in any one of the embodiments of the present application.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a relaxation oscillator as described in any one of the embodiments of the present application.

[0015] The embodiment of the present application provides a relaxation oscillator, comprising: a bias module, a first generating module, a first comparator, a second generating module, a second comparator, and a control logic module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; the inverting input terminal of the first comparator is connected to the first output terminal of the first generating module, and the non-inverting input terminal of the first comparator is connected to the second output terminal of the first generating module; the second generating module is connected to the bias module to obtain the reference voltage provided by the bias module; the inverting input terminal of the second comparator is connected to the first output terminal of the second generating module, and the non-inverting input terminal of the second comparator is connected to the second output terminal of the second generating module; the control logic module is respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the control logic module is used to generate a reference voltage according to the first output terminal of the first comparator. The output signal and the second output signal of the second comparator generate a clock pulse; wherein, the first generating module and the second generating module alternately enter the first working mode and the second working mode, in the first working mode, a reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage of the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage of the inverting input terminal decreases, and stops outputting the discharge signal when the voltage of the inverting input terminal decreases to the reference voltage, so that the voltage of the inverting input terminal remains at the reference voltage; in the second working mode, a reference voltage is input to the inverting input terminal, and the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator outputs the first output signal or the second output signal correspondingly in the interval from the non-inverting input terminal being grounded and reset to the voltage of the non-inverting input terminal reaching the reference voltage.Through the relaxation oscillator, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the first generating module or the second generating module provides a reference voltage to the non-inverting input terminal of the comparator, and increases the voltage of the inverting input terminal of the comparator from a preset starting voltage until the voltage of the inverting input terminal of the comparator reaches the reference voltage. Under the influence of the discharge signal of the comparator, the voltage of the inverting input terminal of the comparator is discharged and reduced until the voltage of the inverting input terminal of the comparator is reduced to the reference voltage, so that the comparator stops outputting the discharge signal. At the moment of starting discharge, due to the delay, the part of the first actual voltage of the inverting input terminal of the comparator that is greater than the reference voltage is the delay. Delay voltage. At the moment of stopping discharge, the second actual voltage at the inverting input terminal of the comparator is the reference voltage minus the delay voltage, that is, the reference voltage. It can be seen that in the second working mode, the inverting input terminal of the comparator obtains a reference voltage less than the reference voltage. When the comparator generates a clock pulse based on the reference voltage, it starts level reversal when the non-inverting input terminal reaches the reference voltage, and completes the level reversal when the non-inverting input terminal reaches the reference voltage, thereby correcting the delay of the comparator. Since the delay voltage changes with the comparator, it is suitable for delay correction of different types of comparators, and is also suitable for delay correction of a comparator in different usage situations. At the same time, the reference voltage (V) of the embodiment of the present application. REF -ΔV) can be in a lower range, for example, VDD / 2≥V REF -ΔV≥VDD / 4, in the second working mode, the clock pulse generation time can be reduced, that is, the oscillation frequency of the clock pulse can be increased without requiring a larger charging current (I REF ) ensures a higher charging and discharging speed at a higher oscillation frequency, thereby achieving a higher oscillation frequency without increasing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a circuit diagram of a conventional oscillator;

[0018] Figure 2 A voltage waveform diagram of a comparison voltage of a conventional relaxation oscillator;

[0019] Figure 3 A schematic block diagram of a first relaxation oscillator provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a waveform of an input voltage of a first comparator provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of a waveform of a voltage at the VP1 terminal provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of a waveform of an input voltage of a second comparator provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of a clock pulse waveform provided in an embodiment of the present application;

[0024] Figure 8 A circuit diagram of a second relaxation oscillator provided in an embodiment of the present application;

[0025] Figure 9 A circuit diagram of a first voltage generating unit provided in an embodiment of the present application;

[0026] Figure 10 A circuit diagram of a bias module and a first clock generation unit provided in an embodiment of the present application.

[0027] Figure Number:

[0028] 100. Relaxation oscillator; 11. Bias module; 12. First generating module; 121. First voltage generating unit; 122. First clock generating unit; 123. First multiplexing unit; 13. First comparator; 14. Second generating module; 141. Second voltage generating unit; 142. Second clock generating unit; 143. Second multiplexing unit; 15. Second comparator; 16. Control logic module; IS1. First current source; IS2. Second current source; Q1. First switch tube; Q2. Second switch tube; Q3. Third switch tube; Q4. Fourth switch tube; Q5. Fifth switch tube; Q6. Sixth switch tube; Q7. Seventh switch tube; R1. First resistor; R2. Second resistor; C1. First capacitor; C2. Second capacitor. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0031] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0032] It should be further understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0033] See also Figure 1 , Figure 1 : is a circuit diagram of a conventional oscillator provided in an embodiment of the present application. Figure 1 As shown in Figure 1, a conventional relaxation oscillator contains two comparators, an RS latch, a bias reference and a timing circuit. The working principle of a conventional relaxation oscillator is achieved by charging and discharging a capacitor. The comparator compares the capacitor voltage with the reference voltage V REF When the capacitor voltage reaches the reference voltage V REF When the comparator generates a pulse, the pulse is maintained by the RS-FF latch until the next comparison. The output signal of the RS-FF latch is controlled by the charging or discharging of the capacitor.

[0034] Relaxation oscillators typically use current mode, exponential RC constant mode, or voltage mode structures. Frequency stability is often affected by process, voltage, and temperature (PVT) variations.

[0035] See also Figure 2 , Figure 2 The voltage waveform diagram of the comparative voltage of a conventional relaxation oscillator provided in an embodiment of the present application is shown. Figure 2 As shown, in a conventional relaxation oscillator, the comparison voltage is input to the non-inverting input of the comparator, and the comparator compares the comparison voltage with the reference voltage. The comparison voltage rises in a ramp and when it reaches the reference voltage When the conventional relaxation oscillator resets the ramp voltage and generates the ramp voltage again. By repeating the charging and discharging operations, the conventional relaxation oscillator generates a clock pulse. The oscillation frequency of the conventional relaxation oscillator is The specific calculation formula is:

[0036] ;

[0037] in, and They are the boost capacitor and the reference current used to generate the ramp voltage respectively.

[0038] However, if Figure 2 As shown, due to the comparator delay time τ and offset voltage , the ramp voltage will not Reset on, resulting in a change in oscillation frequency. Rewritten as:

[0039] ;

[0040] It can be seen from this that compensation technology to correct frequency changes is very necessary.

[0041] See also Figure 3 , Figure 3 The schematic block diagram of the first relaxation oscillator provided in the embodiment of the present application is shown. Figure 3 As shown, the relaxation oscillator 100 includes: a bias module 11 , a first generating module 12 , a first comparator 13 , a second generating module 14 , a second comparator 15 and a control logic module 16 .

[0042] The first generating module 12 is connected to the bias module 11 to obtain the reference voltage V provided by the bias module 11. REF The inverting input terminal of the first comparator 13 is connected to the first output terminal of the first generating module 12, and the non-inverting input terminal (VP1 terminal) of the first comparator 13 is connected to the second output terminal of the first generating module 12. The second generating module 14 is connected to the bias module 11 to obtain the reference voltage V provided by the bias module 11. REF The inverting input terminal (VN1 terminal) of the second comparator 15 is connected to the first output terminal of the second generating module 14, and the non-inverting input terminal of the second comparator 15 is connected to the second output terminal of the second generating module 14. The control logic module 16 is connected to the output terminal of the first comparator 13 and the output terminal of the second comparator 15 respectively. The control logic module 16 is used to generate a clock pulse based on the first output signal (CLK_L) of the first comparator 13 and the second output signal (CLK_H) of the second comparator 15.

[0043] The relaxation oscillator 100 includes a first working mode and a second working mode. The first comparator 13 and the second comparator 15 alternately execute the first working mode and the second working mode. That is, when the first comparator 13 is in the first working mode, the second comparator 15 is in the second working mode. The first working mode is used to generate a reference voltage V REF-ΔV, the second working mode is used to adjust the reference voltage V REF -ΔV supports the generation of the first output signal (CLK_L) by the first comparator 13 or the second output signal (CLK_H) by the second comparator 15. Because both the first output signal (CLK_L) and the second output signal (CLK_H) are low-level signals, the control logic module 16 needs to invert one of them when generating the clock pulse.

[0044] The first generating module 12 and the second generating module 14 alternately enter the first working mode and the second working mode. In the first working mode, the non-inverting input terminal (VP1 terminal or VP2 terminal) inputs the reference voltage V REF , the voltage at the inverting input terminal (VN1 terminal or VN2 terminal) of the first comparator 13 or the second comparator 15 rises from the preset starting voltage to the reference voltage V REF Output discharge signal when the inverting input voltage drops to the reference voltage V REF When the discharge signal is stopped, the voltage at the inverting input terminal is kept at the reference voltage V REF -ΔV. In the second working mode, the inverting input terminal inputs the reference voltage V REF -ΔV, the non-inverting input terminal is grounded and reset, the first comparator 13 or the second comparator 15 is grounded and reset until the voltage of the non-inverting input terminal reaches the reference voltage V REF The -ΔV interval corresponds to outputting the first output signal (CLK_L) or the second output signal (CLK_H).

[0045] It should be noted that, in the embodiment of the present application, the first generating module 12 and the second generating module 14 are the same. For the convenience of explanation, the specific explanation of the first generating module 12 is also applicable to the second generating module 14. Similarly, the first comparator 13 and the second comparator 15 are also the same. The specific explanation of the first comparator 13 is also applicable to the second comparator 15. For example, the explanation of the voltage change of the non-inverting input terminal (VP1) of the first comparator 13 is also applicable to the non-inverting input terminal (VP2) of the second comparator 15.

[0046] It should be noted that, in this embodiment, the VP1 terminal is the non-inverting input terminal of the first comparator, and the VN1 terminal is the inverting input terminal of the first comparator.

[0047] See also Figure 4 , Figure 4 The waveform diagram of the input voltage of a first comparator provided by an embodiment of the present application is shown. Figure 4 As shown, VP1 terminal is connected to the reference voltage V REF , VN1 terminal is connected to the preset initial voltage VX , initial voltage V X Slightly less than the reference voltage V REF , since the reference voltage V REF Greater than the initial voltage V X , the first comparator 13 outputs a high level. At time t1, the first generating module 12 charges the VN1 terminal, so that the VN1 terminal reaches the reference voltage V at time t2. REF Due to the delay, the first comparator 13 will output the inverted signal at time t3, and output the discharge signal. The discharge signal is low level, so that the first generating module 12 discharges the VN1 terminal, and at time t4, the voltage of the VN1 terminal drops to the reference voltage V REF Due to the delay, the first comparator 13 completes the output inversion at time t5 and stops outputting the discharge signal. The VN1 terminal drops to the reference voltage V at time t5. REF -ΔV, and maintain it for a period of time, and maintain it in the second working mode. Through the above technical solution, a voltage lower than the reference voltage V REF The reference voltage V REF -ΔV, for the second operating mode.

[0048] In the second working mode, the voltage at the VN1 terminal is kept at the reference voltage V REF -ΔV. At t6, the VP1 terminal is grounded by the first generating module 12 to achieve voltage reset, that is, the voltage of the VP1 terminal drops to 0, and then the first generating module 12 charges the VP1 terminal, causing the voltage of the VP1 terminal to rise in a ramp. The voltage of the VP1 terminal reaches the reference voltage V at t7. REF -ΔV, due to the delay, the first comparator 13 outputs the inverted signal at time t8. At [t6, t8], the first comparator 13 outputs a low level signal, which is the first output signal (CLK_L).

[0049] V REF The value range of -ΔV can be set to a relatively low range, for example, VDD / 2≥V REF -ΔV≥VDD / 10. In the second working mode, the clock pulse generation time can be reduced, that is, the interval length of [t6, t8] is shortened, and a shorter clock pulse is generated, that is, the oscillation frequency of the clock pulse is increased without requiring a larger charging current (I REF ) ensures a higher oscillation frequency charge and discharge speed, thereby achieving a higher oscillation frequency without increasing power consumption

[0050] It should be noted that V REF >V REF -ΔV≥VDD / 10 is within the protection scope of the embodiments of the present application.

[0051] See also Figure 5 , Figure 5 The waveform diagram of the voltage at the VP1 terminal provided in the embodiment of the present application is shown. When the voltage at the VP1 terminal reaches V REF At this moment, VP1 is reset.

[0052] Through the above solution, the first comparator 13 corrects the delay voltage ΔV. REF -ΔV is generated during the previous first operating mode. The time interval between the first and second operating modes is extremely short. Therefore, the delay voltage ΔV is not easily affected by external factors and is suitable for delay correction of a comparator under different usage conditions. Furthermore, the delay voltage ΔV varies with process variations of the first comparator 13, making it suitable for delay correction of different types of comparators.

[0053] The above embodiments illustrate the working principles of the first generating module 12 and the first comparator 13 in the first working mode and the second working mode. It should be noted that the above process is also applicable to the second generating module 14 and the second comparator 15, which will not be repeated here.

[0054] In one embodiment, see Figure 6 , Figure 6 The waveform diagram of the input voltage of the second comparator provided by the embodiment of the present application is shown. Figure 6 As shown, at [t1, t6], the second comparator 15 is in the second working mode, for generating a second output signal (CLK_H). Figure 6 The t1 and t6 moments in Figure 4 Corresponding to the time t1 and the time t6 in FIG, the first comparator 13 and the second comparator 15 alternately enter the first working mode and the second working mode.

[0055] See also Figure 7 , Figure 7 The waveform diagram of a clock pulse provided by an embodiment of the present application is shown in FIG. Figure 7 As shown, the control logic module 16 generates a clock pulse according to the first output signal (CLK_L) and the second output signal (CLK_H). It should be noted that, Figure 7 The second output signal (CLK_H) is inverted.

[0056] The embodiment of the present application provides a relaxation oscillator, comprising: a bias module, a first generating module, a first comparator, a second generating module, a second comparator, and a control logic module, wherein the first generating module is connected to the bias module to obtain a reference voltage provided by the bias module; the inverting input terminal of the first comparator is connected to the first output terminal of the first generating module, and the non-inverting input terminal of the first comparator is connected to the second output terminal of the first generating module; the second generating module is connected to the bias module to obtain the reference voltage provided by the bias module; the inverting input terminal of the second comparator is connected to the first output terminal of the second generating module, and the non-inverting input terminal of the second comparator is connected to the second output terminal of the second generating module; the control logic module is respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the control logic module is used to generate a reference voltage according to the first output terminal of the first comparator. The output signal and the second output signal of the second comparator generate a clock pulse; wherein, the first generating module and the second generating module alternately enter the first working mode and the second working mode, in the first working mode, a reference voltage is input to the non-inverting input terminal, and the first comparator or the second comparator outputs a discharge signal when the voltage of the inverting input terminal rises from a preset starting voltage to the reference voltage, so that the voltage of the inverting input terminal decreases, and stops outputting the discharge signal when the voltage of the inverting input terminal decreases to the reference voltage, so that the voltage of the inverting input terminal remains at the reference voltage; in the second working mode, a reference voltage is input to the inverting input terminal, and the non-inverting input terminal is grounded and reset, and the first comparator or the second comparator outputs the first output signal or the second output signal correspondingly in the interval from the non-inverting input terminal being grounded and reset to the voltage of the non-inverting input terminal reaching the reference voltage.Through the relaxation oscillator, the first generating module and the second generating module alternately enter the first working mode and the second working mode. In the first working mode, the first generating module or the second generating module provides a reference voltage to the non-inverting input terminal of the comparator, and increases the voltage of the inverting input terminal of the comparator from a preset starting voltage until the voltage of the inverting input terminal of the comparator reaches the reference voltage. Under the influence of the discharge signal of the comparator, the voltage of the inverting input terminal of the comparator is discharged and reduced until the voltage of the inverting input terminal of the comparator is reduced to the reference voltage, so that the comparator stops outputting the discharge signal. At the moment of starting discharge, due to the delay, the part of the first actual voltage of the inverting input terminal of the comparator that is greater than the reference voltage is the delay. Delay voltage. At the moment of stopping discharge, the second actual voltage at the inverting input terminal of the comparator is the reference voltage minus the delay voltage, that is, the reference voltage. It can be seen that in the second working mode, the inverting input terminal of the comparator obtains a reference voltage less than the reference voltage. When the comparator generates a clock pulse based on the reference voltage, it starts level reversal when the non-inverting input terminal reaches the reference voltage, and completes the level reversal when the non-inverting input terminal reaches the reference voltage, thereby correcting the delay of the comparator. Since the delay voltage changes with the comparator, it is suitable for delay correction of different types of comparators, and is also suitable for delay correction of a comparator in different usage situations. At the same time, the reference voltage (V) of the embodiment of the present application. REF -ΔV) can be in a lower range, for example, VDD / 2≥V REF -ΔV≥VDD / 10, in the second working mode, the clock pulse generation time can be reduced, that is, the oscillation frequency of the clock pulse can be increased without requiring a larger charging current (I REF ) ensures a higher charging and discharging speed at a higher oscillation frequency, thereby achieving a higher oscillation frequency without increasing power consumption.

[0057] In order to more clearly introduce the technical solution of the present application, the technical solution of the present application will be introduced through specific embodiments below. It should be noted that the specific embodiments are used to expand the technical solution of the present application, but are not intended to limit the present application.

[0058] In some embodiments, see Figure 8 , Figure 8 The circuit diagram of the second first voltage generating unit provided in the embodiment of the present application is shown. Figure 8 As shown, the first generating module 12 includes: a first voltage generating unit 121 , a first clock generating unit 122 and a first multiplexing unit 123 ; the second generating module 14 includes: a second voltage generating unit 141 , a second clock generating unit 142 and a second multiplexing unit 143 .

[0059] The first terminal of the first voltage generating unit 121 is connected to the preset voltage source, the output terminal of the first voltage generating unit 121 is connected to the inverting input terminal of the first comparator 13, the output terminal of the first voltage generating unit 121 is the first output terminal of the first generating module 12, the second terminal of the first voltage generating unit 121 is grounded, and the first terminal of the first clock generating unit 122 is connected to the preset current I REF The second end of the first clock generating unit 122 is grounded, the output end of the first clock generating unit 122 is connected to the first voltage generating unit 121, the output end of the first clock generating unit 122 is also connected to the first end of the first multiplexing unit 123, and the second end of the first multiplexing unit 123 is connected to the reference voltage V REF , the output end of the first multiplexing unit 123 is connected to the non-inverting input end of the first comparator 13, and the output end of the first multiplexing unit 123 is the second output end of the first generating module 12;

[0060] The first end of the second voltage generating unit 141 is connected to the preset voltage source, the output end of the second voltage generating unit 141 is connected to the inverting input end of the second comparator 15, the output end of the second voltage generating unit 141 is the first output end of the second generating module 14, the second end of the first voltage generating unit 121 is grounded, the first end of the second clock generating unit 142 is connected to the preset current, the second end of the second clock generating unit 142 is grounded, the output end of the second clock generating unit 142 is connected to the second voltage generating unit 141, the output end of the second clock generating unit 142 is also connected to the first end of the second multiplexing unit 143, and the second end of the second multiplexing unit 143 is connected to the reference voltage V REF The output end of the second multiplexing unit 143 is connected to the non-inverting input end of the second comparator 15 , and the output end of the second multiplexing unit 143 is the second output end of the second generating module 14 .

[0061] In some embodiments, in the first working mode, the first multiplexing unit 123 controls the reference voltage V REF The first multiplexing unit 123 controls the output of the first clock generating unit 122 to be connected to the non-inverting input of the first comparator 13. In the second working mode, the first multiplexing unit 123 controls the output of the first clock generating unit 122 to be connected to the non-inverting input of the first comparator 13, and the non-inverting input is grounded and reset through the first multiplexing unit 123 and the first clock generating unit 122.

[0062] In some embodiments, see Figure 9 , Figure 9 The following is a circuit diagram of a first voltage generating unit provided in an embodiment of the present application. Figure 9As shown, the first voltage generating unit 121 includes: a first current source IS1, a second current source IS2, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4 and a first capacitor C1.

[0063] An input end of the first current source IS1 is connected to a preset voltage source, a control end of the first current source IS1 is connected to the bias module 11, an output end of the first current source IS1 is respectively connected to a first end of the first switch tube Q1 and a first end of the second switch tube Q2, a second end of the first switch tube Q1 is respectively connected to a first end of the third switch tube Q3 and a controlled end of the third switch tube Q3, a second end of the third switch tube Q3 is respectively connected to a ground, a second end of the second switch tube Q2 is respectively connected to a first end of the fourth switch tube Q4, a first end of the first capacitor C1, and an inverting input end of the first comparator 13, a second end of the fourth switch tube Q4 is connected to an input end of the second current source IS2, an output end of the second current source IS2 and a second end of the first capacitor C1 are both grounded, and the controlled ends of the first switch tube Q1, the second switch tube Q2, and the fourth switch tube Q4 are all connected to a control logic module 16.

[0064] Exemplarily, the first switch tube Q1, the second switch tube Q2 and the fourth switch tube Q4 are all switch transistors, for example, triodes or MOS tubes. The third switch tube Q3 is a diode-connected transistor, and the third switch tube Q3 is used to generate the initial voltage V X The first current source IS1 and the second current source IS2 are connected to the bias circuit and are controlled to be turned on by the bias circuit. Figure 4 、 Figure 7 and Figure 9 , turn on the second switch tube Q2, charge the first capacitor C1 through the first current source IS1, so that the voltage across the first capacitor C1 rises, so that the voltage at the VN1 end at time t1 increases from the initial voltage V X At time t3, based on the discharge signal, the second switch tube Q2 is turned off and the fourth switch tube Q4 is turned on, so that the voltage across the first capacitor C1 drops, reducing the voltage at the VN1 terminal. At time t5, since the first comparator 13 stops outputting the discharge signal, the second switch tube Q2 and the fourth switch tube Q4 are both in the off state, and the voltage across the first capacitor C1 is the reference voltage V REF -ΔV.

[0065] It should be noted that the circuit of the second voltage generating unit 141 is the same as that of the first voltage generating unit 121 , and will not be described in detail herein.

[0066] In some embodiments, see Figure 10 , Figure 10 The following is a circuit diagram of a bias module and a first clock generating unit provided in an embodiment of the present application. Figure 10As shown, the bias module 11 includes: a fifth switch tube Q5, a sixth switch tube Q6, a first resistor R1 and a second resistor R2.

[0067] The fifth switching tube Q5 and the sixth switching tube Q6 form a current mirror. The first end of the fifth switching tube Q5 and the first end of the sixth switching tube Q6 are both connected to a preset voltage source. The controlled end of the fifth switching tube Q5 is respectively connected to the controlled end of the sixth switching tube Q6, the second end of the fifth switching tube Q5, and the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is grounded.

[0068] In some embodiments, the temperature coefficient of the first resistor R1 and the temperature coefficient of the second resistor R2 are opposite, and the resistance value of the first resistor R1 and the second resistor R2 is the output current of the first current source IS1 and the reference voltage V REF Sure.

[0069] For example, the temperature dependence of ROSC is compensated by using a first resistor R1 and a second resistor R2 with opposite temperature coefficients. The specific calculation formula for the sum of the resistance values of the first resistor R1 and the second resistor R2 is:

[0070] ;

[0071] In this way, after the preset voltage source (VDD), the specifications of the fifth switch tube Q5 and the specifications of the sixth switch tube Q6 are determined, the resistance values of the first resistor R1 and the second resistor R2 are determined, and the voltage of the controlled terminal of the fifth switch tube Q5 and the voltage of the controlled terminal of the sixth switch tube Q6 are both the reference voltage V REF The current at the second end of the fifth switch tube Q5 and the current at the second end of the sixth switch tube Q6 are both I REF .

[0072] like Figure 10 As shown, the first clock generating unit 122 includes: a seventh switch tube Q7 and a second capacitor C2.

[0073] A first terminal of the seventh switch Q7 is connected to the second terminal of the sixth switch Q6, the first terminal of the second capacitor C2, and the non-inverting input terminal of the first comparator 13. A second terminal of the seventh switch Q7 and the second terminal of the second capacitor C2 are both grounded. A controlled terminal of the seventh switch Q7 is connected to the control logic module 16.

[0074] For example, combined Figure 4 、 Figure 7 and Figure 10The first terminal of the seventh switch tube Q7 is connected to the VP1 terminal through the first multiplexing unit 123. At time t6, the VP1 terminal is grounded and reset by turning off the sixth switch tube Q6 and turning on the seventh switch tube Q7. After the VP1 terminal is grounded and reset, the sixth switch tube Q6 is turned on again to charge the second capacitor C2, so that the voltage of the VP1 terminal increases. At time t7, the voltage of the VP1 terminal reaches the reference voltage V REF -ΔV, at time t8, the first comparator 13 starts to output a high level, and the voltage across the second capacitor C2 is the reference voltage V REF , turn off the sixth switch tube Q6 and the seventh switch tube Q7, and enter the next cycle. At [t1, t8], the first comparator 13 generates a first output signal (CLK_L).

[0075] In some embodiments, in the second working mode, the non-inverting input terminal is grounded and reset through the seventh switch tube Q7, the second capacitor C2 is charged and boosted by the output current of the sixth switch tube Q6, and the non-inverting input terminal reaches the reference voltage V through the second capacitor C2. REF -ΔV, the current required for charging and boosting the second capacitor C2 is half of the output current of the sixth switch tube Q6.

[0076] For example, by changing the current mirror ratio, the charging current of the second capacitor C2 can be set to I REF / 2, thus, the specific calculation formula of the oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application is:

[0077] ;

[0078] in, is the oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application, and C2 is the capacitance of the second capacitor.

[0079] The relaxation oscillator 100 proposed in the embodiment of the present application can compensate for the delay time of the comparator and is not affected by the offset voltage.

[0080] The oscillation frequency of the relaxation oscillator 100 in the embodiment of the present application is determined by Rewrite as , The specific calculation formula is:

[0081] ;

[0082] in, is the capacitance of the second capacitor C2. The temperature coefficient of the second capacitor C2 is very small and can be eliminated by adjusting the temperature coefficient of the first resistor R1 and the temperature coefficient of the second resistor R2.

[0083] An embodiment of the present application provides a chip, which includes a relaxation oscillator as described in any one of the embodiments of the present application.

[0084] An embodiment of the present application provides an electronic device, which includes a relaxation oscillator as described in any one of the embodiments of the present application.

[0085] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A relaxation oscillator, characterized in that: The relaxation oscillator comprises: Bias module; a first generating module, the first generating module being connected to the bias module to obtain a reference voltage provided by the bias module; a second generating module, the second generating module being connected to the bias module to obtain a reference voltage and a preset current provided by the bias module, the first generating module and the second generating module alternately entering a first operating mode and a second operating mode; a first comparator, wherein the inverting input of the first comparator is connected to the first output of the first generating module, and the non-inverting input of the first comparator is connected to the second output of the first generating module. In the first operating mode, the second output of the first generating module outputs the reference voltage to the non-inverting input of the first comparator. The output voltage of the first output of the first generating module begins to rise from a preset starting voltage. When the output voltage of the first output of the first generating module rises to the reference voltage, the output of the first comparator outputs a first discharge signal. The first discharge signal is used to control the first generating module to reduce the output voltage of the first output of the first generating module. When the output voltage of the first output of the first generating module drops to the reference voltage, the first comparator stops outputting the first discharge signal to maintain the output voltage of the first output of the first generating module at the reference voltage. In the second operating mode, the inverting input of the first comparator inputs the reference voltage. The output voltage of the second output of the first generating module begins to rise after being grounded and reset. When the output voltage of the second output of the first generating module reaches the reference voltage, the first comparator outputs the first output signal. a second comparator, wherein the inverting input of the second comparator is connected to the first output of the second generating module, and the non-inverting input of the second comparator is connected to the second output of the second generating module. In the first operating mode, the second output of the second generating module outputs the reference voltage to the non-inverting input of the second comparator. The output voltage of the first output of the second generating module begins to rise from a preset starting voltage. When the output voltage of the first output of the second generating module rises to the reference voltage, the output of the second comparator outputs a second discharge signal. The second discharge signal is used to control the second generating module to reduce the output voltage of the first output of the second generating module. When the output voltage of the first output of the second generating module drops to the reference voltage, the second comparator stops outputting the second discharge signal to maintain the output voltage of the first output of the second generating module at the reference voltage. In the second operating mode, the inverting input of the second comparator inputs the reference voltage. The output voltage of the second output of the second generating module begins to rise after being grounded and reset. When the output voltage of the second output of the second generating module reaches the reference voltage, the second comparator outputs a second output signal. A control logic module is connected to the output end of the first comparator and the output end of the second comparator respectively, and the control logic module is used to generate a clock pulse according to the first output signal of the first comparator and the second output signal of the second comparator.

2. The relaxation oscillator according to claim 1, wherein The first generating module includes: a first voltage generating unit, a first clock generating unit and a first multiplexing unit; the second generating module includes: a second voltage generating unit, a second clock generating unit and a second multiplexing unit; A first end of the first voltage generating unit is connected to a preset voltage source, an output end of the first voltage generating unit is connected to an inverting input end of the first comparator, an output end of the first voltage generating unit is a first output end of the first generating module, a second end of the first voltage generating unit is grounded, a first end of the first clock generating unit is connected to a preset current, a second end of the first clock generating unit is grounded, an output end of the first clock generating unit is connected to the first voltage generating unit, an output end of the first clock generating unit is further connected to a first end of the first multiplexing unit, a second end of the first multiplexing unit is connected to the reference voltage, an output end of the first multiplexing unit is connected to a non-inverting input end of the first comparator, and an output end of the first multiplexing unit is a second output end of the first generating module; The first end of the second voltage generating unit is connected to the preset voltage source, the output end of the second voltage generating unit is connected to the inverting input end of the second comparator, the output end of the second voltage generating unit is the first output end of the second generating module, the second end of the second voltage generating unit is grounded, the first end of the second clock generating unit is connected to the preset current, the second end of the second clock generating unit is grounded, the output end of the second clock generating unit is connected to the second voltage generating unit, the output end of the second clock generating unit is also connected to the first end of the second multiplexing unit, the second end of the second multiplexing unit is connected to the reference voltage, the output end of the second multiplexing unit is connected to the non-inverting input end of the second comparator, and the output end of the second multiplexing unit is the second output end of the second generating module.

3. The relaxation oscillator according to claim 2, wherein: In the first working mode, the first multiplexing unit controls the reference voltage to be connected to the non-inverting input of the first comparator; in the second working mode, the first multiplexing unit controls the output of the first clock generation unit to be connected to the non-inverting input of the first comparator, and the non-inverting input is grounded and reset through the first multiplexing unit and the first clock generation unit.

4. The relaxation oscillator according to claim 2, wherein: The first voltage generating unit includes: a first current source, a second current source, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor; The input end of the first current source is connected to the preset voltage source, the control end of the first current source is connected to the bias module, the output end of the first current source is respectively connected to the first end of the first switching tube and the first end of the second switching tube, the second end of the first switching tube is respectively connected to the first end of the third switching tube and the controlled end of the third switching tube, the second end of the third switching tube is grounded, the second end of the second switching tube is respectively connected to the first end of the fourth switching tube, the first end of the first capacitor, and the inverting input end of the first comparator, the second end of the fourth switching tube is connected to the input end of the second current source, the output end of the second current source and the second end of the first capacitor are both grounded, and the controlled ends of the first switching tube, the second switching tube, and the fourth switching tube are all connected to the control logic module.

5. The relaxation oscillator according to claim 4, wherein: The bias module includes: a fifth switch tube, a sixth switch tube, a first resistor and a second resistor; The fifth switching tube and the sixth switching tube form a current mirror, the first end of the fifth switching tube and the first end of the sixth switching tube are both connected to the preset voltage source, the controlled end of the fifth switching tube is respectively connected to the controlled end of the sixth switching tube, the second end of the fifth switching tube, and the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded.

6. The relaxation oscillator according to claim 5, wherein: The temperature coefficient of the first resistor and the temperature coefficient of the second resistor are opposite, and the sum of the resistances of the first resistor and the second resistor is determined according to the output current of the first current source and the reference voltage.

7. The relaxation oscillator according to claim 5, wherein: The first clock generating unit includes: a seventh switch tube and a second capacitor; The first end of the seventh switch tube is respectively connected to the second end of the sixth switch tube, the first end of the second capacitor, and the non-inverting input end of the first comparator, and the second end of the seventh switch tube and the second end of the second capacitor are both grounded.

8. The relaxation oscillator according to claim 7, wherein: In the second operating mode, the non-inverting input terminal is grounded and reset through the seventh switch tube, the second capacitor is charged and boosted by the output current of the sixth switch tube, the non-inverting input terminal reaches the reference voltage through the second capacitor, and the current required for charging and boosting the second capacitor is half of the output current of the sixth switch tube.

9. A chip, characterized in that: The chip includes the relaxation oscillator according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the relaxation oscillator according to any one of claims 1 to 8.

Images