Method, device, medium and system for accurately measuring phase mismatch of interleaved sampling ADC (Analog to Digital Converter)
Through multiple short-time sampling and small-point number FFT, combined with a multi-frame phase parameter accumulation method based on covariance, the phase mismatch of interleaved sampling ADC is accurately measured, which solves the problems of large resource consumption and low measurement accuracy in the prior art, and achieves high-precision phase mismatch correction.
Patent Information
- Application Number
- CN202510107190.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-27
AI Technical Summary
In the prior art, when measuring the phase mismatch of interleaved sampling ADC, processing resources are consumed greatly, the measurement accuracy is not high, and it is difficult to effectively correct the phase mismatch error.
Through multiple short-time sampling, small-point number FFT is performed, and a multi-frame phase parameter accumulation method based on covariance is used to accurately measure the phase mismatch of interleaved sampling ADC.
The processing resource consumption is reduced, the processing gain is improved, and the phase mismatch error measurement accuracy is obtained, so that the corrected phase mismatch value is at least one order of magnitude smaller.
Smart Images
Figure CN120049885A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of interleaved sampling ADC calibration, and more specifically, to a method, device, medium, and system for accurately measuring the phase mismatch of an interleaved sampling ADC. Background Art
[0002] An interleaved sampling ADC with a sampling frequency of fs is composed of M sub-ADCs with a sampling frequency of fs / M. Ideally, the sampling time interval between adjacent sub-ADCs is 1 / fs. Due to the existence of sampling time errors, each clock phase is equivalent to adding a fixed offset at the ideal sampling time point, resulting in periodic sampling errors, which are manifested as high-energy harmonics in the frequency domain and severely restrict the dynamic range of the ADC. The main method for correcting such errors is the analog-digital hybrid correction method, that is, detecting the phase mismatch error in the digital domain and then performing correction in the analog domain.
[0003] Currently, the main methods for measuring the phase mismatch error in the digital domain are as follows: (1) increasing the single-sampling time length and performing a large-point FFT, but this method consumes a large amount of processing resources; (2) dividing the large-point FFT into multiple frames of small-point FFTs for non-coherent accumulation. Although this method can better reduce the consumption of processing resources, the improvement of signal processing gain is limited and the measurement accuracy is not high. Summary of the Invention
[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, device, medium, and system for accurately measuring the phase mismatch of an interleaved sampling ADC, reducing the consumption of processing resources, improving the processing gain, and obtaining higher measurement accuracy of the phase mismatch error.
[0005] The purpose of the present invention is achieved through the following solutions:
[0006] A method for accurately measuring the phase mismatch of an interleaved sampling ADC measures the phase mismatch of the interleaved sampling ADC by performing multiple short-time samplings, performing small-point FFTs, and performing multi-frame coherent accumulation based on covariance, including the following sub-steps:
[0007] Step 1: Use M low-sampling-frequency ADCs to collect K groups of data for each of N frequency points;
[0008] Step 2: Process the data collected by the M sub-ADCs respectively and output M peak IQs;
[0009] Step 3: Calculate the peak IQ values corresponding to the K groups of data collected for each frequency point to form a peak IQ matrix X;
[0010] Step 4: Calculate the covariance matrix R of X, then perform eigenvalue decomposition on R to obtain matrices D and V. According to the position of the maximum value on the diagonal of matrix D, select the corresponding column of matrix V and denote it as matrix Y M ;
[0011] Step 5: Calculate matrix Y for N frequency points respectively M , and form the phase information matrix Y;
[0012] Step 6: Multiply the 2nd to Mth columns of matrix Y by the conjugates of the 1st to M - 1th columns, and denote it as matrix Z; then calculate the phase difference ΔΦ between adjacent sub - ADCs according to matrix Z;
[0013] Step 7: Substitute ΔΦ into the formula Δτ = ΔΦ / 2πf n - 1 / fs to calculate the delay jitter Δτ between adjacent sub - ADCs, where f s is the sampling frequency, f n is the frequency of the nth frequency point, n = 1, 2, ……, N; then calculate the delay jitter Δτ of the 2nd to Mth sub - ADCs relative to the 1st sub - ADC m-1 , Δτ m-1 is an N×(M - 1) - dimensional matrix. Finally, calculate the average value ΔT of the delay jitter of the N frequency points of the 2nd to Mth sub - ADCs, and this ΔT is the full - analog - bandwidth phase mismatch value of the 2nd to Mth sub - ADCs.
[0014] Further, in Step 1, the frequencies of the N frequency points are different and cover the ADC analog bandwidth.
[0015] Further, in Step 2, the sequential processing of the data collected by the M sub - ADCs specifically includes performing FFT operations, modulus operations, and peak - searching operations on the data collected by the M sub - ADCs in sequence.
[0016] Further, in Step 3, X is an M×K - dimensional matrix.
[0017] Further, in Step 4, Y M is an M×1 - dimensional matrix.
[0018] Further, in Step 5, Y is an N×M - dimensional matrix.
[0019] Further, in Step 6, Z is an N×(M - 1) - dimensional matrix, and ΔΦ is an N×(M - 1) - dimensional matrix.
[0020] An apparatus for accurately measuring the phase mismatch of an interleaved sampling ADC, including a processor and a memory. A computer program is stored in the memory, and when the computer program is loaded by the processor, it executes the method described in any one of the above.
[0021] A computer-readable storage medium stores a computer program, and when the computer program is loaded by a processor, it executes the method described in any one of the above.
[0022] A system for accurately measuring the phase mismatch of an interleaved sampling ADC includes the device for accurately measuring the phase mismatch of an interleaved sampling ADC as described above.
[0023] The beneficial effects of the present invention include:
[0024] The present invention proposes a method for accurately measuring the phase mismatch of an interleaved sampling ADC. Without increasing the single-sampling time length, by performing multiple short-time samplings and performing a small-point FFT, the consumption of processing resources can be reduced; through covariance-based multi-frame coherent accumulation, the processing gain is improved, and the measurement accuracy of the phase mismatch error is relatively high, such that the corrected phase mismatch value is at least one order of magnitude smaller than the phase mismatch value before correction. Description of the Drawings
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0026] Figure 1 is a flowchart of the steps of the method of the present invention;
[0027] Figure 2 is a flowchart of the steps of the method of the embodiment of the present invention;
[0028] Figure 3 is the full-scale power (dBFS) curve of input signals at different frequency points;
[0029] Figure 4 is the maximum harmonic power of the spectra of input signals at different frequency points;
[0030] Figure 5 is the maximum harmonic power after phase mismatch correction. Detailed Embodiments
[0031] All the features disclosed in all the embodiments in this specification, or all the steps in the methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended and replaced in any manner.
[0032] In the inventive concept of the preferred embodiment of the present invention, a method for accurately measuring the phase mismatch of an interleaved sampling ADC is specifically provided, as Figure 1As shown, the interleaved sampling ADC with a sampling frequency of fs is composed of M sub-ADCs with a sampling frequency of fs / M, and specifically includes the following steps:
[0033] Step 1: Use M low-sampling-frequency ADCs to collect K groups of data for each of the N frequency points. These N frequency points have different frequencies and cover the analog bandwidth of the ADC.
[0034] Step 2: Perform FFT operations, modulus operations, and peak search operations on the data collected by the M sub-ADCs in sequence, and output M peak IQs.
[0035] Step 3: Calculate the peak IQ values corresponding to the K groups of data collected for each frequency point to form a peak IQ matrix X. X is an M×K-dimensional matrix.
[0036] Step 4: Calculate the covariance matrix R of X, then perform eigenvalue decomposition on R to obtain matrices D and V. According to the position of the maximum value on the diagonal of matrix D, select the corresponding column of matrix V, denoted as matrix Y M , Y M is an M×1 matrix;
[0037] Step 5: Calculate matrix Y for each of the N frequency points M , to form a phase information matrix Y. Y is an N×M-dimensional matrix;
[0038] Step 6: Multiply the 2nd to Mth columns of matrix Y by the conjugate of the 1st to M-1th columns, denoted as matrix Z. Z is an N×(M-1)-dimensional matrix; then calculate the phase difference ΔΦ between adjacent sub-ADCs according to matrix Z. ΔΦ is an N×(M-1)-dimensional matrix;
[0039] Step 7: Substitute ΔΦ into the formula Δτ = ΔΦ / 2πf n -1 / fs to calculate the delay jitter Δτ between adjacent sub-ADCs. In the formula, f s is the sampling frequency, f n is the frequency of the nth frequency point, n = 1, 2, ……, N; then calculate the delay jitter Δτ of the 2nd to Mth sub-ADCs relative to the 1st sub-ADC m-1 , Δτ m-1 is an N×(M-1)-dimensional matrix, and finally calculate the average delay jitter ΔT of the N frequency points of the 2nd to Mth sub-ADCs. This ΔT is the phase mismatch value of the full analog bandwidth of the 2nd to Mth sub-ADCs.
[0040] In other preferred embodiments of the present invention, as Figure 2 shown, the following specific implementation process is further described: The interleaved sampling ADC with a sampling frequency of fs = 5000 MHz is composed of M = 4 sub-ADCs with a sampling frequency of 1250 MHz. In this embodiment, the following steps are specifically executed:
[0041] Step 1: Use a 4-channel low-sampling-frequency ADC to collect 30 groups of data for each of the 79 frequency points. These 79 frequency points have different frequencies and cover the ADC analog bandwidth from 1300 MHz to 2300 MHz. When collecting data, control the input signal power to be 1 - 2 dB below the full-scale power. The full-scale power (dBFS) curve of the input signals at the 79 frequency points is as shown in Figure 3 shown, and the maximum harmonic power of the corresponding spectrum is as shown in Figure 4 shown, with a range of -64 dB to -61 dB.
[0042] Step 2: Perform FFT operations, modulus calculations, and peak search operations on the data collected by the 4 sub-ADCs in sequence, and output M-channel peak IQs;
[0043] Step 3: Calculate the peak IQ values corresponding to the 30 groups of data collected at each frequency point to form a peak IQ matrix, X. X is a 4×30-dimensional matrix;
[0044] Step 4: Calculate the covariance matrix R of X, then perform eigenvalue decomposition on R to obtain matrices D and V. According to the position of the maximum value on the diagonal of matrix D, select the corresponding column of matrix V, denoted as matrix Y M , Y M is a 4×1 matrix;
[0045] Step 5: Calculate matrix Y M for each of the 79 frequency points to form a phase information matrix Y. Y is a 79×4-dimensional matrix;
[0046] Step 6: Multiply the 2nd to 4th columns of matrix Y by the conjugates of the 1st to 3rd columns, denoted as matrix Z. Z is a 79×3-dimensional matrix; then calculate the phase difference ΔΦ between adjacent sub-ADCs according to matrix Z. ΔΦ is a 79×3-dimensional matrix;
[0047] Step 7: Substitute ΔΦ into the formula Δτ = ΔΦ / 2πf n - 1 / fs to calculate the delay jitter Δτ between adjacent sub-ADCs. In the formula, f n is the frequency of the nth frequency point, n = 1, 2, ……, 79; f s = 5000 MHz. Then calculate the delay jitter Δτ of the 2nd to 4th sub-ADCs relative to the 1st sub-ADC m-1 , Δτ m-1 is a 79×3-dimensional matrix. Finally, calculate the average value of the delay jitter ΔT of the 79 frequency points of the 2nd to 4th sub-ADCs. This ΔT is the phase mismatch value of the 2nd to 4th sub-ADCs in the analog bandwidth from 1300 MHz to 2300 MHz.
[0048] After calculating through the above steps, the phase mismatch values ΔT of the analog bandwidth from 1300 MHz to 2300 MHz of the second to fourth sub-ADCs are shown in the data of the second row of Table 1. After substituting ΔT into the acquired data for correction and then calculating the phase mismatch value ΔT again 校正后 See the data in the third row of Table 1. By comparing the data in the second row and the third row, it can be seen that the phase mismatch value after correction is at least one order of magnitude smaller than that before correction.
[0049] Table 1 Phase Mismatch Values
[0050]
[0051] Substitute the phase mismatch value ΔT into the acquired data of 79 frequency points for phase mismatch correction, and the correction effect is as Figure 5 shown. The maximum harmonic frequency drops from -64 dB to -61 dB before correction to -76 to -66 dB after correction, improving the dynamic range of the ADC by 6 dB to 13 dB. The correction effect is obvious, indicating that the measurement of the phase mismatch value ΔT is accurate and the measurement accuracy is high.
[0052] The units involved in the embodiments of the present invention can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.
[0053] According to one aspect of the embodiments of the present invention, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various optional implementation manners.
[0054] As another aspect, the embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist alone without being assembled into the electronic device. The above computer-readable medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.
Claims
1. A method for accurately measuring phase mismatch of interleaved sampling ADC, characterized in that: The interleaved sampling ADC phase mismatch is measured by multiple short-time sampling, small-point FFT, and multi-frame coherent accumulation based on covariance, including the following sub-steps: Step 1: Use M low sampling frequency ADCs to collect K groups of data at N frequency points; Step 2: Process the data collected by the M-channel ADCs in sequence and output the M-channel peak IQ; Step 3: Calculate the peak IQ value corresponding to the K groups of data collected at each frequency point to form a peak IQ matrix X; Step 4: Calculate the covariance matrix R of X, then perform eigenvalue decomposition on R to obtain matrices D and V. According to the position of the maximum value of the diagonal of matrix D, select the corresponding column of matrix V and record it as matrix Y M ; Step 5: Calculate the matrix Y of N frequency points respectively M , forming a phase information matrix Y; Step 6: Conjugate multiply columns 2 to M and columns 1 to M-1 of matrix Y to obtain a matrix Z. Then, the phase difference ΔΦ between adjacent sub-ADCs is calculated based on matrix Z. Step 7: Substitute ΔΦ into the formula Δτ=ΔΦ / 2πf n -1 / f s Calculate the delay jitter Δτ of adjacent sub-ADCs, where f s is the sampling frequency, f n is the frequency of the nth frequency point, n=1,2,……,N; then calculate the delay jitter Δτ of the 2nd to Mth ADC relative to the 1st ADC m-1 , Δτ m-1 It is an N×(M-1) dimensional matrix. Finally, the delay jitter average ΔT of the N frequency points of the 2nd to Mth ADCs is calculated. This ΔT is the full analog bandwidth phase mismatch value of the 2nd to Mth ADCs.
2. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 1, the N frequency points have different frequencies and cover the ADC analog bandwidth.
3. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 2, the processing of the data collected by the M-channel ADCs in sequence specifically includes performing FFT operations, modulus calculations, and peak search operations on the data collected by the M-channel ADCs in sequence.
4. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 3, X is an M×K dimensional matrix.
5. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 4, Y M It is an M×1 matrix.
6. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 5, Y is an N×M dimensional matrix.
7. The method for accurately measuring interleaved sampling ADC phase mismatch according to claim 1, characterized in that: In step 6, Z is an N×(M-1) dimensional matrix, and ΔΦ is an N×(M-1) dimensional matrix.
8. A device for accurately measuring interleaved sampling ADC phase mismatch, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 7 is executed.
9. A computer-readable storage medium, characterized in that: A computer program is stored in the readable storage medium, and when the computer program is loaded by a processor, the method according to any one of claims 1 to 7 is executed.
10. A system for accurately measuring interleaved sampling ADC phase mismatch, characterized in that: The invention comprises the device for accurately measuring the phase mismatch of the interleaved sampling ADC as described in claim 8.