Calibration circuit, signal processing device and signal processing system

Abstract

The embodiment of the invention provides a calibration circuit, signal processing equipment and a signal processing system. The calibration circuit comprises a signal generation circuit; the signal generation circuit comprises a clock module which generates a first clock signal, wherein the first clock signal is at least used for generating a working clock signal of a control module and an input clock signal of a frequency division module; the control module sends a first frequency division reset signal to the frequency division module to trigger starting of a timer in the control module, and the timer carries out timing based on a work clock signal; the first frequency division reset signal controls the interval between the starting moment of the frequency division signal output by the frequency division module and the starting moment of the timer for a first preset duration; the low-pass filter filters the frequency division signal to obtain a first calibration signal, and the interval between the starting moment of the first calibration signal and the starting moment of the timer is a second preset duration; the first calibration signal is used for analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration of an interval between an initial moment of the first digital signal and a starting moment of the timer.

Description

Technical Field

[0001] The present invention relates to the technical field of signal measurement, and in particular, to a calibration circuit, a signal processing device, and a signal processing system. Background Art

[0002] In some application scenarios, devices usually need to perform time delay calibration, multi-channel synchronization calibration, etc. each time they are powered on. Usually, after the device is powered on, a series of calibrations are required so that the time relationships between various channels and between various modules of the device meet the corresponding index requirements of the device. For example, for a signal source device, after each power-on, it is required that the time delay from trigger to output remains a fixed value, and the deviation of the time delay change is less than 10 ps. The first calibration signal is usually used for calibration between various channels and / or between various modules. How to generate a first calibration signal having a fixed phase relationship with the working clock of the control module and improve the calibration accuracy is an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a calibration circuit, a signal processing device, and a signal processing system.

[0004] According to a first aspect of the embodiments of the present disclosure, a calibration circuit is proposed. The calibration circuit includes a signal generation circuit; the signal generation circuit includes: a clock module, a control module, a frequency division module, and a low-pass filter, where

[0005] The clock module is configured to generate a first clock signal based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module and the input clock signal of the frequency division module;

[0006] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, where the timer counts based on the working clock signal;

[0007] The first frequency division reset signal is used to control the start time of the frequency division signal output by the frequency division module to be separated from the start time of the timer by a first predetermined duration;

[0008] The low-pass filter is configured to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, where the start time of the first calibration signal is separated from the start time of the timer by a second predetermined duration;

[0009] The first calibration signal is at least used for an analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between an initial moment of the first digital signal and a start moment of the timer, wherein the first measurement duration is at least used for determining a transmission delay associated with the first calibration signal.

[0010] In some embodiments, the calibration circuit includes the analog-to-digital conversion module.

[0011] The control module is configured to receive the first digital signal and determine a first measurement duration between an initial moment of the first digital signal and a start moment of the timer.

[0012] The control module is configured to determine a sampling delay associated with the analog-to-digital conversion module at least based on the second predetermined duration and the first measurement duration.

[0013] In some embodiments, the calibration circuit includes a selection switch for selecting one of the first calibration signal and N signals to be calibrated and inputting it to the analog-to-digital conversion module; wherein

[0014] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the signal to be calibrated that will be selected to obtain a digital signal to be calibrated.

[0015] The control module is configured to receive the digital signal to be calibrated and determine an arrival moment of the digital signal to be calibrated.

[0016] The arrival moment of the digital signal to be calibrated, the sampling delay, and a predetermined signal transmission delay of a calibration channel corresponding to the selected signal to be calibrated are used to synchronize a timer of the calibration circuit and a timer of a calibration channel corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the calibration channel.

[0017] In some embodiments, the calibration circuit includes a selection switch for selecting a second calibration signal outside the calibration circuit and inputting it to the analog-to-digital conversion module; wherein

[0018] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal.

[0019] The control module is configured to receive the second digital signal and determine an arrival moment of the second digital signal, wherein the arrival moment of the second digital signal is used to determine a delay between a start moment of a timer of the control module and a start moment of a timer associated with the second calibration signal.

[0020] In some embodiments, the signal generation circuit further includes a fan-out module.

[0021] The fan-out module is connected to the low-pass filter and is configured to fan out at least one path of the first calibration signal.

[0022] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider;

[0023] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0024] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0025] The signal delay sub-module is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of a predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0026] The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0027] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0028] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0029] The second synchronous reset control module is configured to generate a first frequency division reset signal based on the working clock signal;

[0030] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal meets the setup time of a predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0031] The second frequency divider is configured to be triggered by the first frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0032] In some embodiments, the first clock signal includes the operating clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the operating clock is used to input into the counting frequency divider as the input clock;

[0033] The third synchronous reset control module is configured to generate a first frequency division reset signal based on the operating clock signal;

[0034] The start moment includes a predetermined edge of the operating clock signal after the generation moment of the first frequency division reset signal;

[0035] The counting frequency divider is configured to be triggered by the first frequency division reset signal at the predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result of the counting.

[0036] According to a second aspect of the embodiments of the present disclosure, a signal processing device is provided, and the signal processing device includes at least one calibration circuit as described in the first aspect.

[0037] In some embodiments, the calibration circuit includes a first calibration circuit, wherein the first calibration circuit includes the analog-to-digital conversion module,

[0038] The control module of the first calibration circuit is configured to receive the first digital signal and determine a first measurement duration of the interval between the initial moment of the first digital signal and the start moment of the timer;

[0039] The control module of the first calibration circuit is configured to determine the sampling time delay associated with the analog-to-digital conversion module at least based on the second predetermined duration and the first measurement duration.

[0040] In some embodiments, the signal processing device further includes N channels to be calibrated, wherein the channels to be calibrated are respectively configured to output signals to be calibrated;

[0041] The first calibration circuit includes a selection switch configured to select one of the first calibration signal and at least one signal to be calibrated and input it into the analog-to-digital conversion module; wherein,

[0042] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the signal to be calibrated to be selected to obtain a digital signal to be calibrated;

[0043] The control module is configured to receive the digital signal to be calibrated and determine the arrival moment of the digital signal to be calibrated;

[0044] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the calibration channel corresponding to the selected signal to be calibrated are used to synchronize the timer of the first calibration circuit and the timer of the calibration channel corresponding to the selected signal to be calibrated, where the signal to be calibrated is output from the calibration channel.

[0045] In some embodiments, the first calibration circuit includes a selection switch for selecting a second calibration signal outside the first calibration circuit and inputting it into the analog-to-digital conversion module; where

[0046] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0047] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, where the arrival time of the second digital signal is used to determine the delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0048] In some embodiments, the calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module;

[0049] The fan-out module is connected to the low-pass filter and is configured to fan out at least one first calibration signal of the second calibration circuit.

[0050] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

[0051] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal sent by an external signal processing device.

[0052] According to a third aspect of the embodiments of the present disclosure, a signal processing system is proposed, and the signal processing system includes at least one signal processing device as described in the second aspect.

[0053] An embodiment of the present disclosure provides a calibration circuit, a signal processing device, and a signal processing system. The calibration circuit includes a signal generation circuit; the signal generation circuit includes: a clock module, a control module, a frequency division module, and a low-pass filter, wherein, the clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is at least used to generate an operating clock signal of the control module and an input clock signal of the frequency division module; the control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts time based on the operating clock signal; the first frequency division reset signal is used to control the start time of the frequency division signal output by the frequency division module and the start time of the timer to be separated by a first predetermined duration; the low-pass filter is configured to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, wherein the start time of the first calibration signal and the start time of the timer are separated by a second predetermined duration; the first calibration signal is at least used to be subjected to analog-to-digital conversion by an analog-to-digital conversion module to obtain a first digital signal, so as to determine a first measurement duration between the start time of the first digital signal and the start time of the timer, wherein the first measurement duration is at least used to determine a transmission delay associated with the first calibration signal. In this way, based on the first frequency division reset signal, the start time of the frequency division signal is adjusted, and the corresponding relationship between the first frequency division reset signal and the start time of the timer is used to control the duration between the start position of the first calibration signal and the start time of the timer. Furthermore, based on the fixed position relationship between the first calibration signal and the start time of the timer, the determination and calibration of the signal transmission delay can be realized to improve the calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 FIG. 1 is a schematic structural diagram of a calibration circuit according to an exemplary embodiment;

[0055] Figure 2 FIG. 2 is a schematic timing diagram of signal generation according to an exemplary embodiment;

[0056] Figure 3 FIG. 3 is a schematic structural diagram of another calibration circuit according to an exemplary embodiment;

[0057] Figure 4 FIG. 4 is a schematic timing diagram of another signal generation according to an exemplary embodiment;

[0058] Figure 5 FIG. 5 is a schematic flowchart of a signal generation method according to an exemplary embodiment;

[0059] Figure 6Schematic diagram of another calibration circuit shown according to an exemplary embodiment;

[0060] Figure 7 Schematic diagram of another signal generation timing shown according to an exemplary embodiment;

[0061] Figure 8 Schematic diagram of another signal generation method flow shown according to an exemplary embodiment;

[0062] Figure 9 Schematic diagram of yet another calibration circuit shown according to an exemplary embodiment;

[0063] Figure 10 Schematic diagram of yet another signal generation timing shown according to an exemplary embodiment;

[0064] Figure 11 Schematic diagram of another signal generation method flow shown according to an exemplary embodiment;

[0065] Figure 12 Schematic diagram of yet another signal generation method flow shown according to an exemplary embodiment;

[0066] Figure 13 Schematic diagram of a delay calibration method flow shown according to an exemplary embodiment;

[0067] Figure 14 Schematic diagram of a delay calibration timing shown according to an exemplary embodiment;

[0068] Figure 15 Schematic diagram of yet another calibration circuit shown according to an exemplary embodiment;

[0069] Figure 16 Schematic diagram of a signal processing device shown according to an exemplary embodiment;

[0070] Figure 17 Schematic diagram of another delay calibration timing shown according to an exemplary embodiment;

[0071] Figure 18 Schematic diagram of yet another calibration circuit shown according to an exemplary embodiment;

[0072] Figure 19 Schematic diagram of yet another calibration circuit shown according to an exemplary embodiment;

[0073] Figure 20 Schematic diagram of a signal processing device shown according to an exemplary embodiment;

[0074] Figure 21It is a schematic structural diagram of a signal processing system shown according to an exemplary embodiment. Detailed implementation manners

[0075] To make the technical solutions and beneficial effects of the present invention more obvious and understandable, the following will be described in detail by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0076] The embodiments of the present disclosure are not exhaustive, but only schematic of some embodiments, and do not constitute a specific limitation on the protection scope of the present disclosure. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution obtained by removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be arbitrarily exchanged. Additionally, the optional implementation manners in an embodiment can be combined arbitrarily; furthermore, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and an embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0077] In each embodiment of the present disclosure, if there is no special explanation and logical conflict, the terms and / or descriptions between the embodiments are consistent and can be cited from each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0078] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and do not constitute a limitation on the present disclosure.

[0079] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0080] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0081] In some embodiments, terms such as "at least one (at least one of, at least one item, at least one), "one or more," "a plurality of," "multiple," etc. may be used interchangeably.

[0082] In some embodiments, notations such as "at least one of A and B," "A and / or B," "A in one case, B in another case," "A in one situation, B in another situation," etc. may, depending on the circumstances, include the following technical solutions: In some embodiments, A is performed (A is performed independently of B); in some embodiments, B is performed (B is performed independently of A); in some embodiments, either A or B is selected for execution (A and B are selectively executed); in some embodiments, both A and B are performed (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0083] In some embodiments, notations such as "A or B" may, depending on the circumstances, include the following technical solutions: In some embodiments, A is performed (A is performed independently of B); in some embodiments, B is performed (B is performed independently of A); in some embodiments, either A or B is selected for execution (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0084] The prefix words such as "first," "second," etc. in the embodiments of the present disclosure are merely for distinguishing different described objects and do not impose limitations on the position, order, priority, value, or content of the described objects. For the statements of the described objects, refer to the description in the claims or the context of the embodiments. There should be no redundant limitations due to the use of prefix words. For example, if the described object is "field," the ordinal numbers before "field" in "first field" and "second field" do not limit the position or order between the "fields." "First" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of "first field" and "second field." Another example, if the described object is "level," the ordinal numbers before "level" in "first level" and "second level" do not limit the priority between the "levels." Another example, the value of the described object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, if the described object is "device," "first device" and "second device" can be the same device or different devices, and their types can be the same or different; another example, if the described object is "information," "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0085] In some embodiments, "including A", "containing A", "used to indicate A", "carrying A" can be interpreted as directly carrying A or as indirectly indicating A.

[0086] In some embodiments, terms such as "……", "determining……", "in the case of……", "when……", "when……", "if……", "if……" can be replaced with each other.

[0087] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", etc. can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. can be replaced with each other.

[0088] In some embodiments, a device, etc. can be interpreted as physical or virtual, and its name is not limited to the name recorded in the embodiment. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", "subject", etc. can be replaced with each other.

[0089] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure can be implemented as an independent embodiment, and any combination of any element, any row, and any column can also be implemented as an independent embodiment.

[0090] Figure 1 is a calibration circuit shown according to the embodiments of the present disclosure. The calibration circuit includes a signal generation circuit; the signal generation circuit includes: a clock module, a control module, a frequency division module, and a low-pass filter, where

[0091] The clock module is used to generate a first clock signal based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module and the input clock signal of the frequency division module;

[0092] The control module is used to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, where the timer counts based on the working clock signal;

[0093] The first frequency division reset signal is used to control the start time of the frequency division module outputting the frequency division signal to be separated from the start time of the timer by a first predetermined duration;

[0094] A low-pass filter is used to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, where the start time of the first calibration signal is separated from the start time of the timer by a second predetermined duration;

[0095] The first calibration signal is at least used for an analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between the initial time of the first digital signal and the start time of the timer, where the first measurement duration is at least used to determine the transmission delay associated with the first calibration signal.

[0096] In a possible implementation manner, the calibration circuit can be implemented by an integrated circuit, or can be implemented by a combination of at least one integrated circuit and at least one discrete component.

[0097] Here, the calibration circuit can be applied to a signal processing device. For example, the calibration circuit can be applied to signal source electronic devices such as an Arbitrary Waveform Generator (AWG) signal source, an Arbitrary Function Generator (AFG) signal source, that is, a signal source, a radio frequency signal source, and a vector signal source, and can also be applied to electronic devices such as an oscilloscope and a spectrum analyzer. The calibration circuit can exist in the form of an independent functional module, such as an independent functional module in a PXIe architecture; it can also be combined with other functional circuits to implement a composite function.

[0098] In a possible implementation manner, the calibration circuit can be included on a module card carried in a PXIe architecture.

[0099] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal, or can be a clock signal sent by the main board in a PXIe architecture to each functional module board.

[0100] The control module can be implemented by components such as a Field Programmable Gate Array (FPGA) with signal processing capabilities and / or data calculation and processing capabilities. The control module can also be implemented by a Micro Processing Unit (MCU), etc.

[0101] The clock module is used to perform at least one of buffering and frequency division on the reference clock signal to generate clock signals with frequencies required for the operation of each module.

[0102] In a possible implementation, the first clock signal is used to generate at least one of a working clock signal and an input clock signal. For example, the first clock signal can generate a working clock signal and an input clock signal through fan-out or other means.

[0103] Here, the control module can control the reset of the frequency division module and / or perform frequency division work through a reset signal. For example, the control module can control the frequency division module to enter the reset state and / or perform frequency division work through two level states of the reset signal. The first frequency division reset signal can be a level that triggers the frequency division of the input clock signal. As Figure 2 shown, the first frequency division reset signal is Figure 2 the low level state of the reset signal in

[0104] In a possible implementation, the frequency division module is in a reset state before performing frequency division on the input clock signal.

[0105] In a possible implementation, the first frequency division reset signal is edge-triggered based on a working level.

[0106] In a possible implementation, the control module triggering the start of a timer associated with the first frequency division reset signal in the control module can include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the input working clock signal after the first frequency division reset signal is generated.

[0107] In a possible implementation, the predetermined edge is the first rising edge after the starting moment of the first frequency division reset signal (as Figure 2 indicated by arrow A).

[0108] In a possible implementation, the starting moment of the timer (as Figure 2 indicated by arrow B) is the edge moment of the predetermined edge.

[0109] Since the timer counts time based on the working clock signal, the timing result of the timer is synchronized with the working clock signal. For example, for each cycle of the working clock signal, the timer counts once.

[0110] Both the working clock signal and the input clock signal are generated by the first clock signal, so the working clock signal and the input clock signal have an associated relationship. In a possible implementation, the working clock signal and the input clock signal have a fixed phase difference.

[0111] In a possible implementation, the start time domain position of the first frequency division reset signal can be adjusted to adjust the start time of the frequency division signal output by the frequency division module. For example, the frequency division module can be triggered by the first frequency division reset signal at the edge of the input clock signal to output the frequency division signal. Therefore, based on the start time domain position of the first frequency division reset signal and the start time domain position of the edge of the input clock signal, the start time of the frequency division signal output by the frequency division module triggered by the first frequency division reset signal can be determined. Since there is a fixed phase difference between the working clock signal and the input clock signal, the time interval between the start time of the frequency division signal triggered by the input clock signal and the start time of the timer is fixed, that is, the time interval between the start time of the frequency division signal and the start time of the timer can be determined, that is, the first predetermined duration (such as Figure 2 shown as T1 in

[0112] In a possible implementation, the frequency division module can be used to divide the input clock signal by N to output a frequency division signal. Wherein, N is a positive integer greater than or equal to 1.

[0113] As Figure 2 shown, the frequency division signal obtained after passing through the frequency division module is approximately a square wave and has high-frequency harmonic components. Here, it can be filtered by a low-pass filter to obtain a smooth first calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the frequency division signal to filter out harmonic components with frequencies higher than the frequency of the frequency division signal.

[0114] As Figure 2 shown, there is a filtering time delay ( Figure 2 shown as T2 in Figure 2 when the low-pass filter performs filtering. Therefore, the second predetermined duration between the start time of the first calibration signal obtained after filtering and the start time of the timer (

[0115] the sum of T1 and T2 in

[0116] In a possible implementation, the analog-to-digital conversion module can be located inside the calibration circuit or outside the calibration circuit.

[0117] The first calibration signal reaches the analog-to-digital conversion module through a transmission path and is subjected to analog-to-digital conversion by the analog-to-digital conversion module to obtain a first digital signal. Here, the first digital signal can include the digitized first calibration signal. The first calibration signal can be an analog signal, and after analog-to-digital conversion, a digitized first calibration signal is obtained.

[0118] In a possible implementation, the control module connected to the analog-to-digital conversion module may include a control module within the calibration circuit or a control module outside the calibration circuit.

[0119] In a possible implementation, the analog-to-digital conversion module may perform analog-to-digital conversion in a streaming manner, and the first digital signal is transmitted to the control module connected to the analog-to-digital conversion module in a streaming manner. That is, the first digital signal is directly sent to the control module connected to the analog-to-digital conversion module without data buffering.

[0120] The control module connected to the analog-to-digital conversion module can determine the moment when the first digital signal is received, that is, the starting moment of the first digital signal. Furthermore, the first measurement duration between the starting moment of the first digital signal and the starting moment of the timer is determined.

[0121] The transmission delay associated with the first calibration signal may include the transmission delay of part or all of the transmission paths for transmitting the first calibration signal. For example, the transmission delay associated with the first calibration signal includes at least one of the following: the sampling delay of the analog-to-digital conversion module for analog-to-digital conversion; the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital conversion module; the transmission delay of at least one of the cable, connector, and selection switch for transmitting the first calibration signal.

[0122] For example, if the transmission path of the first calibration signal from the low-pass filter to the analog-to-digital conversion module is short or the transmission delay is known, then the sampling delay of the analog-to-digital conversion module can be determined based on the first measurement duration. If the sampling delay of the analog-to-digital conversion module can be determined based on the components used in the analog-to-digital conversion module, then the transmission delay from the low-pass filter to the analog-to-digital conversion module can be determined based on the first measurement duration.

[0123] In this way, based on the first frequency division reset signal, the adjustment of the starting moment of the frequency division signal and the corresponding relationship between the first frequency division reset signal and the starting moment of the timer are realized, and the control of the duration between the starting position of the first calibration signal and the starting moment of the timer is realized. Furthermore, based on the fixed position relationship between the first calibration signal and the starting moment of the timer, the determination and calibration of the signal transmission delay can be realized to improve the calibration accuracy.

[0124] In some embodiments, as Figure 3 shown, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider;

[0125] The first clock buffer is used to generate the working clock signal and the input clock signal based on the first clock signal;

[0126] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0127] The signal delay sub-module is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of a predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0128] The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0129] The first clock buffer is configured to generate two clock signals, a working clock signal and an input clock signal, from one path of the first clock signal through frequency replication or the like. The phase when the working clock signal is input to the control module can be determined based on the transmission path of the control module that can transmit based on the working clock signal, and the phase when the input clock signal is input to the first frequency divider can be determined based on the path where the input clock signal is transmitted to the first frequency divider. That is, since the circuit for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0130] Here, the first synchronous reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0131] Figure 4 For Figure 3 the timing diagram of the signal generation circuit shown. The timer can be triggered and started at a predetermined edge of the working clock signal after the first frequency division reset signal. As Figure 4 shown, the predetermined edge after the first frequency division reset signal can include the first rising edge after the first frequency division reset signal

[0132] In a possible implementation manner, the predetermined trigger edge of the input clock signal ( Figure 4 shown as C in) can include the Mth trigger edge (such as a rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. As Figure 4 shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined.

[0133] In a possible implementation, the predetermined delay duration can be determined based on the time interval between the starting moment of the first divided-frequency reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the second divided-frequency reset signal after the delay meets the setup time of the predetermined trigger edge (such as Figure 4 as described by t in

[0134] In a possible implementation, the predetermined delay duration can be pre-written into the signal delay sub-module. In an FPGA, the signal delay sub-module can be implemented by an input / output delay (IOdelay) circuit.

[0135] Through the second divided-frequency reset signal, the first divider can be enabled to perform frequency division at the predetermined trigger edge and output a divided-frequency signal. Figure 4 In

[0136] To sum up, the time interval between the predetermined trigger edge and the start moment of the timer is known, and the response duration of the first divider can be determined based on the first divider. Therefore, the time interval, i.e., the first predetermined duration, between the start moment of the divided-frequency signal and the start moment of the timer is fixed.

[0137] By filtering the divided-frequency signal to obtain a first calibration signal, the filtering delay duration is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the time interval, i.e., the second predetermined duration T, between the start moment of the first calibration signal and the start moment of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start moment of the timer can be determined by comparing the phases of the first calibration signal and the signal to be calibrated, and further the calibration of the signal to be calibrated can be realized.

[0138] In practical applications, the start moment of the timer, the start moment of the divided-frequency signal, and the moment when the first divider is triggered at the predetermined trigger edge are all related to the release moment of the second divided-frequency reset signal. That is, the falling edge of the second reset signal needs to be sampled by the working clock signal and the input clock signal respectively, which requires that the falling edge of the second reset signal has sufficient setup and hold time with respect to the sampling moment of the second reset signal. The start moment of the timer is triggered by the edge of the working clock signal, the start moment of the divided-frequency signal and the first divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviations between the above-mentioned start moment of the timer, the start moment of the divided-frequency signal, and the moment when the first divider is triggered at the predetermined trigger edge are fixed with respect to each other, so that high-precision calibration can be achieved.

[0139] Exemplarily, such asFigure 5 As shown in the figure, the specific steps of the first calibration signal generation method include:

[0140] Step 501: Power on and initialize each module in signal generation.

[0141] Step 502: Configure the clock module to generate the input clock signal of the first frequency divider and the working clock signal of the FPGA (control module).

[0142] Step 503: Synchronize the first synchronous reset control module to control the first frequency divider to be in the reset state and the timer to be in the reset state.

[0143] Step 504: Configure the delay value (predetermined delay duration) of the signal delay sub-module. The delay value can be a factory calibration value used to control the setup / hold time of the second frequency division reset signal and the input clock signal.

[0144] Step 505: The control module determines whether to generate the first calibration signal. If yes, execute Step 506; otherwise, execute Step 505.

[0145] Step 506: Issue the second frequency division reset signal to release the first frequency divider.

[0146] Step 507: Start the internal timer of the FPGA. (As the count of the starting reference time of the first calibration signal).

[0147] Step 508: The frequency division signal passes through a low-pass filter.

[0148] Step 509: The output signal of the low-pass filter is the first calibration signal.

[0149] In the above steps, the signal delay sub-module obtains the delay value during factory calibration. This delay value is used to control the FPGA to output a second frequency division reset signal and the input clock signal to have sufficient setup / hold timing, ensuring that each time power is applied, the frequency division signal output by the first frequency divider and the start time of the internal timer of the FPGA have a fixed delay relationship. In this way, it can ensure that the first calibration signal output by the low-pass filter has a fixed delay relationship with the start time of the internal timer of the FPGA.

[0150] In some embodiments, as Figure 6 shown, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0151] The second clock buffer is used to generate a second clock signal and the input clock signal based on the first clock signal;

[0152] The second synchronous reset control module is used to generate a first divided-frequency reset signal based on the working clock signal;

[0153] The phase adjustment module is used to adjust the phase of the second clock signal to obtain the working clock signal, so that the first divided-frequency reset signal triggered based on the working clock signal meets the setup time of the predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0154] The second frequency divider is used to be triggered by the first divided-frequency reset signal at the predetermined trigger edge and generate the divided-frequency signal based on the input clock signal.

[0155] The first clock buffer is used to generate two clock signals: a second clock signal and an input clock signal by means of frequency replication and the like for one path of the first clock signal.

[0156] Here, there is a corresponding relationship between the first divided-frequency reset signal and the timer. The corresponding relationship between the first divided-frequency reset signal and the timer includes one of the following: there is a predetermined interval between the start time of the first divided-frequency reset signal and the start time of the timer; the first divided-frequency reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0157] The phase adjustment module can be used to adjust the phase of the second clock signal to obtain the working clock signal. The phase adjustment module can be implemented by at least one of the following to achieve the adjustment of the phase of the clock signal: Phase Locked Loop (PLL), Delay Locked Loop (DLL), Digital Clock Manager (DCM).

[0158] In a possible implementation manner, the phase adjustment amount that the phase adjustment module can be used to adjust the phase of the second clock signal can be preset.

[0159] The phase of the second clock signal can be determined based on the transmission path of the control module through which the second clock signal is transmitted, and the phase of the input clock signal can be determined based on the path through which the input clock signal is transmitted to the first frequency divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the working clock signal and the input clock signal can be determined based on the phase adjustment amount of the phase adjustment module.

[0160] Figure 7 For Figure 6 The timing diagram of the shown signal generation circuit. The predetermined trigger edge ( Figure 7 shown as C) can include the Mth trigger edge (such as a rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. For exampleFigure 7 As shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined.

[0161] Here, the phase adjustment amount can be determined based on at least one of the following: the first divided-frequency reset signal satisfies the setup time of the predetermined trigger edge (such as Figure 7 shown as t); the second divided-frequency reset signal does not trigger the edge before the predetermined trigger edge in the input clock signal.

[0162] Through the first divided-frequency reset signal, the second divider can trigger division at the predetermined trigger edge and output a divided-frequency signal. Figure 7 Among them, the time interval between the divided-frequency signal and the start time of the timer, the first predetermined duration T1, can include the response duration of the first divider.

[0163] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response duration of the second divider can be determined based on the second divider. Therefore, the time interval between the start time of the divided-frequency signal and the start time of the timer, the first predetermined duration T1, is fixed.

[0164] By filtering the divided-frequency signal to obtain the first calibration signal, the filtering delay duration is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the time interval between the start time of the first calibration signal and the start time of the timer, the second predetermined duration T, is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phases of the first calibration signal and the signal to be calibrated, and then the calibration of the signal to be calibrated can be realized.

[0165] In practical applications, the start time of the timer is determined by the edge (such as the rising edge) of the working clock signal, and the start time of the divided-frequency signal is determined by the edge (such as the rising edge) of the input clock signal. The working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviations between the start time of the above-mentioned timer and the start time of the divided-frequency signal are fixed with respect to each other, so that high-precision calibration can be achieved.

[0166] Exemplarily, as Figure 8 shown, the specific steps of the first calibration signal generation method include:

[0167] Step 801: Power on and initialize each module in the signal generation.

[0168] Step 802: Configure the clock module to generate the input clock signal and the second clock signal of the divider.

[0169] Step 803: The synchronization reset control module controls the second frequency divider to be in a reset state and the timer to be in a reset state.

[0170] Step 804: Configure the parameters of the phase adjustment module in the FPGA (control module) to adjust the phase of the second clock signal. The phase adjustment amount can be a factory calibration value used to control the setup / hold time of the first frequency division reset signal and the input clock of the second frequency divider.

[0171] Step 805: The control module determines whether a first calibration signal needs to be generated. If yes, execute Step 806; otherwise, execute Step 805.

[0172] Step 806: Issue the first frequency division reset signal to release the second frequency divider.

[0173] Step 807: Start the internal timer of the FPGA to count as the starting reference time of the first calibration signal.

[0174] Step 808: The frequency division signal passes through a low-pass filter.

[0175] Step 809: The output signal of the low-pass filter is the first calibration signal.

[0176] In the above steps, the internal clock unit of the FPGA, i.e., the phase adjustment module (such as PLL, DLL, DCM, etc.), is used to adjust the phase of the FPGA working clock signal, so as to control the first frequency division reset signal given by the FPGA to the second frequency divider and the input clock of the second frequency divider to have sufficient setup / hold timing. Thus, each time power is applied, there is a fixed time delay relationship between the output signal of the second frequency divider and the start time of the internal timer of the FPGA.

[0177] In some embodiments, as Figure 9 shown, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronization reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0178] The third synchronization reset control module is used to generate a first frequency division reset signal based on the working clock signal;

[0179] The start time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0180] The counting frequency divider is used to be triggered by the first frequency division reset signal at the predetermined edge, count the working clock signal from the predetermined edge, and generate the frequency division signal based on the counting result of the counting.

[0181] Here, the clock module outputs a first clock signal based on a reference clock signal as the working clock signal of the control module. Inside the control module, the working clock signal is transmitted to the counting frequency divider as the input clock signal.

[0182] In a possible implementation, the counting frequency divider is used to count the input clock signal, and when the count value reaches the counting threshold, the level is inverted to generate a periodic frequency-divided signal.

[0183] For example, the required frequency-divided signal is an N-frequency division signal of the working clock signal. Then the counting threshold can be set to N / 2. When the counting frequency divider counts the working clock signal, when the count value reaches N / 2, the level is inverted to generate an N-frequency division signal.

[0184] Figure 10 For Figure 9 the timing diagram of the signal generation circuit shown. As Figure 10 shown, there is a corresponding relationship between the first frequency division reset signal and the timer. The start time of the timer is located at a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal.

[0185] In a possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the working clock signal after the generation time of the first frequency division reset signal.

[0186] The counting frequency divider counts based on the trigger of the first frequency division reset signal to output a frequency-divided signal.

[0187] Here, the counting frequency divider is triggered at the start time of the timer. Therefore, the time interval between the start time of the frequency-divided signal and the start time of the timer is fixed. For example, the start time of the frequency-divided signal is the same as the start time of the timer. The filtering delay of the low-pass filter is fixed. Therefore, the interval T between the start time of the first calibration signal generated by the frequency-divided signal and the start time of the timer is a fixed value.

[0188] Exemplarily, as Figure 11 shown, the specific steps of the first calibration signal generation method include:

[0189] Step 1101: Power on and initialize each module in the signal generation.

[0190] Step 1102: The third synchronous reset control module controls the counting frequency divider to be in the reset state and the timer to be in the reset state.

[0191] Step 1103: The control module determines whether to generate the first calibration signal. If so, execute Step 1104, otherwise execute Step 1103.

[0192] Step 1104: Send out the first frequency division reset signal for releasing the counting frequency divider.

[0193] Step 1105: Start the internal timer of the FPGA (control module) to count as the starting reference time of the first calibration signal.

[0194] Step 1106: The frequency division signal passes through a low-pass filter.

[0195] Step 1107: The output signal of the low-pass filter is the first calibration signal.

[0196] In the above steps, this solution does not adopt an external frequency divider, nor does it require adjusting the phase of the third synchronous reset control module and the input clock signal of the external frequency divider. This solution directly based on the FPGA working clock signal, starts the internal frequency division counter, realizes the N-fold frequency division signal, and outputs the signal through a low-pass filter to obtain the first calibration signal, which is simple and easy to implement.

[0197] In some embodiments, as Figure 12 shown, the calibration circuit includes the analog-to-digital conversion module,

[0198] The control module is configured to receive the first digital signal and determine a first measurement duration of the interval between the initial moment of the first digital signal and the start moment of the timer;

[0199] The control module is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

[0200] It can be understood that Figure 12 in, the signal generation circuit composed of the control module, the clock module, the first clock buffer, the first frequency divider and the low-pass filter is an implementation manner of the signal generation circuit. Without contradiction, the signal generation circuit may include the signal generation circuit in any of the above embodiments.

[0201] Here, the sampling delay associated with the analog-to-digital conversion module may include at least one of the following: the delay of the analog-to-digital conversion module for analog-to-digital conversion, the response delay of the analog-to-digital conversion module, and the transmission delay between the analog-to-digital conversion module and the control module.

[0202] In the related art, when the analog-to-digital conversion module in the calibration circuit is powered on each time, it may be affected by various factors, resulting in changes in the time delay of the sampling link of the analog-to-digital conversion module. For example: the internal timing of the Analog-to-Digital Converter (ADC) chip is re-established, the timing of the data transmission interface between the ADC chip and the control module (such as FPGA) is re-established, the cross-clock domain signal conversion inside the FPGA, and the change in the phase relationship between the sampling clock and the working clock of the FPGA, etc. That is, the sampling delay of the analog-to-digital conversion module may change each time it is powered on, thus affecting the calibration progress of the calibration circuit. In some specific application scenarios, it is required that the analog-to-digital conversion module has stable time delay characteristics each time it is powered on. For example, using the analog-to-digital conversion module to sample external trigger signals, using the ADC chip to achieve synchronous output calibration of multi-channel and multi-device signal source devices, etc. In these application scenarios, the time delay deviation of the ADC sampling circuit each time it is powered on may need to be controlled within 5 ps. Therefore, it is necessary to determine the sampling delay of the analog-to-digital conversion module in a timely manner to improve the calibration accuracy of the calibration circuit.

[0203] In a possible implementation, the analog-to-digital conversion module can transmit the first digital signal to the control module connected to the analog-to-digital conversion module through a digital signal transmission channel such as a data bus. The analog-to-digital conversion module and the control module are in the same calibration circuit.

[0204] In a possible implementation, the analog-to-digital conversion module can perform analog-to-digital conversion in a streaming mode, and the first digital signal is transmitted to the control module connected to the analog-to-digital conversion module in a streaming mode. That is, the first digital signal is directly sent to the control module connected to the analog-to-digital conversion module without passing through data caching.

[0205] The control module can determine the moment when the first digital signal is received, that is, the starting moment of the first digital signal. Furthermore, it can determine the first measurement duration of the interval between the starting moment of the first digital signal and the starting moment of the timer.

[0206] In a possible implementation, as Figure 2 shown, after the control module receives the first digital signal, it can first search for the peak value of the first digital signal. After determining the peak value of the first digital signal, it can intercept the data at the position of 1 / 4 cycle before the peak value, and based on this data, perform the phase calculation of the first digital signal, and then determine the first measurement duration.

[0207] As Figure 2 shown, the interval between the first calibration signal and the starting moment of the timer is the second predetermined duration ( Figure 2The interval between the start time of the first digital signal and the start time of the timer is the first measurement time length T. Therefore, based on the first measurement time length T and the second predetermined time length, the total delay of the sampling delay of the analog-to-digital conversion module for analog-to-digital conversion and the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital conversion module can be determined.

[0208] Since the transmission path of the first calibration signal from the low-pass filter to the analog-to-digital conversion module is fixed, the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital conversion module can be determined. Therefore, the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital conversion module is subtracted from the first measurement time length T to determine the sampling delay of the analog-to-digital conversion by the analog-to-digital conversion module.

[0209] In a possible implementation, the determined sampling delay may be used to perform delay compensation on the analog-to-digital conversion module.

[0210] For example, Figure 12 For example, the control module can be an FPGA, combined with Figure 14 The timing diagram of the calibration circuit in FIG. 1 shows the specific steps of the calibration circuit for performing delay calibration on the analog-to-digital conversion module. Figure 13 As shown, including:

[0211] Step 1301: Power on and initialize each module in signal generation.

[0212] Step 1302: Configure the clock module to generate an input clock signal for the first frequency divider and a working clock signal for the control module (FPGA).

[0213] Step 1303: Configure the signal delay submodule (such as FPGA IODelay) delay value (predetermined delay length) to ensure that the second frequency division reset signal and the input clock of the frequency division module (first frequency divider) have a stable setup / hold timing relationship. The delay value can be a factory calibration value.

[0214] Step 1304: Determine whether to measure the delay of the analog-to-digital conversion module (ADC). If yes, execute step 1305; otherwise, execute step 1304.

[0215] Step 1305: Switch the selection switch so that the selection switch is used to collect the first calibration signal.

[0216] Step 1306: Synchronize the first synchronous reset control module to control the frequency division module (first frequency divider) to be in a reset state and the timer to be in a reset state.

[0217] Step 1307: Sending a second frequency division reset signal to release the first frequency divider.

[0218] Step 1308: Start the internal timer of the control module. As the count for the starting reference time of the first calibration signal. Since there is a stable setup / hold timing relationship between the synchronous reset control signal and the input clock of the N-divider, there is a stable time-phase relationship between the divided calibration signal output by the N-divider and the release time of the internal reset signal of the FPGA, recorded as T1.

[0219] Step 1309: The divided signal passes through a low-pass filter to obtain the first calibration signal. After the divided calibration signal passes through the low-pass filter, the harmonic components are filtered out, and only the fundamental component is retained, thus generating the ADC delay calibration signal. Record the filter delay as T2.

[0220] Step 1310: The first calibration signal is processed through ADC sampling, First In First OUT (FIFO), delay adjustment module, etc.

[0221] Step 1311: Calculate the accurate delay value T3 of the analog-to-digital conversion module (ADC).

[0222] Step 13111: Search for the peak of the first sine wave of the first digital signal and record the current timer time, converted to delay t0.

[0223] Step 13112: Intercept a section of data from the first digital signal and send it to the calibration data delay calculation module.

[0224] Step 13113: The calibration data delay calculation module calculates the accurate phase based on the intercepted data and converts it to the delay value t1.

[0225] Step 13114: The delay value T3 of the analog-to-digital conversion module = t0 + t1.

[0226] Step 1312: Determine whether it is necessary to compensate for the delay of the analog-to-digital conversion module. If so, then determine the difference between the accurate delay value T3 of the analog-to-digital conversion module and the reference delay Tr: delata; otherwise, the accurate delay value T3 can be recorded.

[0227] Step 1313: Determine whether the difference delata is less than the error threshold. If so, the delay calibration process ends; otherwise, compensation is performed based on the difference delata.

[0228] It can be understood that the signal generation steps of different signal generation circuits are different and will not be elaborated one by one here.

[0229] In practical applications, such as Figure 12As shown, at the beginning of each power-on of the calibration circuit, the first calibration signal enters the ADC sampling circuit. After analog-to-digital conversion (ADC) by the ADC module and asynchronous clock domain conversion, the delay value of the first calibration signal is calculated. This delay value can be recorded and processed by other means to eliminate the influence caused by the change in the link delay of the analog-to-digital conversion module; or it can be adjusted by the delay adjustment module to adjust the delay of the data after conversion by the analog-to-digital conversion module, ensuring that the delay entering the signal processing module remains a fixed value.

[0230] In this way, based on the fixed time-domain position relationship between the first calibration signal and the start time of the timer, the sampling delay associated with the analog-to-digital conversion module can be determined by the time when the control module receives the first digital signal, thereby realizing the delay compensation of the analog-to-digital conversion module, and further improving the accuracy of the signal processing device when calibrating the signal to be calibrated.

[0231] In some embodiments, as Figure 15 shown, the calibration circuit includes a selection switch for selecting one of the first calibration signal and N signals to be calibrated and inputting it to the analog-to-digital conversion module; where

[0232] the analog-to-digital conversion module is used to perform analog-to-digital conversion on the signal to be calibrated to be selected to obtain a digital signal to be calibrated;

[0233] the control module is used to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated;

[0234] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the calibration channel corresponding to the signal to be calibrated selected are used to synchronize the timer of the calibration circuit and the timer of the calibration channel corresponding to the signal to be calibrated selected, where the signal to be calibrated is output from the calibration channel.

[0235] It can be understood that Figure 15 only as a schematic diagram, Figure 15 and the signal generation circuit composed of a control module, a clock module, a frequency division module, a low-pass filter, etc. in any of the following embodiments is an implementation manner of the signal generation circuit. Without contradiction, the signal generation circuit can include the signal generation circuit in any of the above embodiments. Without contradiction, the internal structure of the control module is like the control module in any of the above embodiments.

[0236] Here, N is a positive integer greater than or equal to 1.

[0237] In a possible implementation, a selection switch is used to select one of N signals to be calibrated and a first calibration signal and input it into the analog-to-digital conversion module. Here, the selection switch can be implemented by an electronic switch such as a relay switch. When the selection switch selects the first calibration signal to be input into the analog-to-digital conversion module, it can be used to calibrate the analog-to-digital conversion module as shown in the above embodiments.

[0238] When the selection switch selects the signal to be calibrated and inputs it into the analog-to-digital conversion module, it can be used to determine the time delay of the channel to be calibrated corresponding to the signal to be calibrated.

[0239] In this embodiment, the function of the signal to be calibrated is not limited. For example, the signal to be calibrated can be an external trigger signal or a signal specifically used for channel calibration sent by other channels to be calibrated.

[0240] In a possible implementation, the channel to be calibrated can include a signal source channel in a signal processing device. The channel to be calibrated can convert a digital signal into an analog signal based on digital-to-analog conversion and output it.

[0241] In a possible implementation, the calibration circuit and the channel to be calibrated can respectively output a first calibration signal and a signal to be calibrated based on the same reference signal. Exemplarily, Figure 16 is a schematic structural diagram of a signal processing device (such as a signal generator). The signal processing device includes a calibration circuit and a channel to be calibrated. As Figure 16 shown, the signal processing device can be implemented using a modular architecture such as a PXIe architecture. The calibration circuit and the channel to be calibrated can be respectively carried on daughter cards in the modular architecture. The modular architecture can include a backplane, and the daughter cards are connected to the backplane through slots or the like. A backplane clock module and a backplane control module (which can be implemented by an FPGA and / or a processor, etc.) are provided on the backplane. The backplane clock module can be used to provide a reference clock signal to each daughter card, and the backplane control module is used to manage and control the daughter cards through communication and control lines.

[0242] As Figure 16 shown, the channel to be calibrated can include a signal source daughter card, and the signal source daughter card can output a signal to the outside as a signal source. The signal source daughter card includes a daughter card clock module, a daughter card FPGA, a DAC, an AFE, a relay switch, and channel output ports (CH1~CH4), etc. The daughter card clock module is used to output clock signals to the daughter card FPGA, DAC, etc. based on the reference clock. The FPGA is used to output a digital signal to the DAC. The DAC performs digital-to-analog conversion to obtain an analog signal, and outputs it to the outside through the AFE, relay switch, etc. When the signal source daughter card is used to output a signal to be calibrated, the relay can connect the selection switch so that the signal to be calibrated is input to the selection switch.

[0243] It can be understood thatFigure 16 Among them, each functional module in the control module is just one implementation manner, and the implementation manner of the control module may include the control module in any of the above embodiments. Figure 16 The signal generation circuit shown is just one implementation manner of the signal generation circuit, and can be replaced by the signal generation circuit in any of the above embodiments without contradiction.

[0244] The signal to be calibrated is converted by the analog-to-digital conversion module to obtain the digital signal to be calibrated, and the control module determines the arrival time of the digital signal to be calibrated at the control module.

[0245] Here, the predetermined signal transmission delay of the channel to be calibrated may include the predetermined delay between the generation of the signal to be calibrated by the waveform generator of the FPGA of the signal source sub-card and the reception of the digital signal to be calibrated by the control module of the calibration circuit. Since the transmission paths from the waveform generator to the control module of the calibration circuit are all known, the transmission delay of the transmission of the predetermined signal can be determined in advance. Since the sampling delay of the analog-to-digital conversion module in the control module is determined based on the first calibration signal.

[0246] In a possible implementation manner, the sampling delay can be used to calibrate the predetermined signal transmission delay to obtain the calibrated signal transmission delay. In a possible implementation manner, the calibrated signal transmission delay is used to synchronize the timer of the signal to be calibrated and the timer of the calibration circuit.

[0247] The channel to be calibrated may have a timer to record the generation time of the signal to be calibrated by the waveform generator of the FPGA. Therefore, the channel to be calibrated can be synchronized based on the arrival time of the digital signal to be calibrated, the calibrated signal transmission delay, and the generation time of the signal to be calibrated. For example, the generation time of the signal to be calibrated is updated by subtracting the calibrated signal transmission delay from the arrival time of the digital signal to be calibrated to synchronize the timer in the calibration circuit and the timer in the channel to be calibrated.

[0248] Exemplarily, taking Figure 16 the calibration circuit as an example, the specific steps for calibrating the delay of the channel to be calibrated are as Figure 17 shown, including:

[0249] Step 1701: Power on and initialize each module in the signal generation circuit.

[0250] Step 1702: The control module issues an instruction to synchronously reset the frequency division module and start the timer.

[0251] Step 1703: Switch the selection switch of the calibration circuit to collect the first calibration signal.

[0252] Step 1704: Calculate the exact delay value associated with the start time of the analog-to-digital conversion module's relative timer, and record this delay value Tr.

[0253] Step 1705: Calculate the delay difference Td that the analog-to-digital conversion module needs to compensate; (if the delay value recorded during factory calibration of the analog-to-digital conversion module is Ta, then Td = Ta - Tr).

[0254] Step 1706: Calculate the reference delay values for each channel to be calibrated (the channels to be calibrated are represented by Chi, and i represents the serial number of the channel to be calibrated).

[0255] Reference delay value of Chi = Fixed reference delay of the DAC channel + Offset (skew) value set by the user for Chi + Delay compensation value of Chi - Td. The fixed reference delay of the DAC channel can be the parameter value recorded during factory calibration; it is calculated and saved based on the delay values of all channels at the time of factory shipment. The skew value of Chi set by the user can be the delay value set by the user for fine-tuning each channel; the delay compensation value of Chi can be the compensation value recorded during factory calibration; Td is the delay compensation value calculated through calibration of the analog-to-digital conversion module each time the device is powered on.

[0256] Step 1707: Determine whether all channels to be calibrated have completed synchronous calibration compensation; if so, end the calibration process, otherwise, proceed to these steps 1708.

[0257] Step 1708: Select the next channel to be calibrated.

[0258] Step 1709: Switch the selection switch inside the calibration circuit to select the signal to be calibrated for the Chi channel.

[0259] Step 1710: Calculate the channel delay value from the Chi channel to the synchronous calibration card.

[0260] Step 1711: Is abs(channel delay of Chi - reference delay of Chi) less than the error threshold? If so, execute step 1707, otherwise execute step 1712.

[0261] Step 1712: Calculate the delay difference value to be adjusted for Chi, where the delay difference value to be adjusted for Chi = reference delay value of Chi - channel delay value of Chi.

[0262] Step 1713: Calculate the coarse adjustment delay value (integer sampling period) of Chi and the fine adjustment delay value (fractional sampling period) of Chi.

[0263] Step 1714: 1. Adjust the coarse adjustment delay and fine adjustment delay of the Chi channel.

[0264] In some embodiments, such as Figure 18As shown, the calibration circuit includes a selection switch for selecting a second calibration signal outside the calibration circuit and inputting it into the analog-to-digital conversion module; where,

[0265] The analog-to-digital conversion module is used to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0266] The control module is used to receive the second digital signal and determine the arrival time of the second digital signal. Wherein, the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0267] In a possible implementation manner, the second calibration signal is generated by an external signal generation circuit. Here, the first calibration signal and the second calibration signal are used to distinguish the calibration signals generated by the calibration circuit and the external signal generation circuit. Relatively speaking, the second calibration signal is received from the outside for the calibration circuit; relatively speaking, the second calibration signal is also the first calibration signal for the external signal generation circuit.

[0268] It can be understood that, Figure 18 The signal generation circuit shown is only one implementation manner of the signal generation circuit. Without contradiction, it can be replaced by the signal generation circuit in any of the above embodiments.

[0269] In a possible implementation manner, the external signal generation circuit is similar to the signal generation circuit disclosed in any of the above embodiments. The start time of the timer associated with the second calibration signal includes the start time of the timer of the control module in the external signal generation circuit. That is, the time interval between the start time of the second calibration signal and the start time of the timer of the control module in the external signal generation circuit can be determined. For example, the time interval between the start time of the second calibration signal and the start time of the timer of the control module in the external signal generation circuit can also be the second predetermined duration.

[0270] Here, the transmission path of the second calibration signal to the signal calibration circuit can be determined (for example, the cables, connectors, selection switches, etc. in the transmission path). Therefore, the transmission delay of the second calibration signal transmitted to the analog-to-digital conversion module in the calibration circuit for conversion, converted into a second digital signal by the analog-to-digital conversion module in the calibration circuit, and reaching the control module of the calibration circuit can be determined.

[0271] Here, the transmission delay of the second calibration signal to the calibration circuit control module (the second digital signal arrival control module) can be preset based on the transmission path. Among them, the transmission delay includes the preset delay of the analog-to-digital conversion module in the calibration circuit. After the calibration circuit determines the sampling time delay of the analog-to-digital conversion module in the calibration circuit, the transmission delay can be calibrated. In this way, the accuracy of the transmission delay after calibration can be improved.

[0272] Based on the arrival time of the second digital signal determined by the calibration circuit, the start time of the second calibration signal, and the transmission delay after calibration, the delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal can be determined, thereby realizing the synchronization between the timer of the control module and the timer associated with the second calibration signal.

[0273] In some embodiments, as Figure 19 shown, the signal generation circuit further includes a fan-out module;

[0274] The fan-out module is connected to the low-pass filter and is used to fan out at least one path of the first calibration signal.

[0275] It can be understood that Figure 19 the signal generation circuit shown is only one implementation manner of the signal generation circuit. Without contradiction, it can be replaced by the signal generation circuit in any of the above embodiments.

[0276] Here, the fan-out module is used to copy the signal output by the low-pass filter to obtain multiple first calibration signals.

[0277] In a possible implementation manner, the fan-out module can adjust the level of the first calibration signal to meet the requirements of the first calibration signal receiving end.

[0278] In a possible implementation manner, the first calibration signal can be received by an external calibration circuit. Here, the implementation manner of the external calibration circuit can include any of the above calibration circuits containing an analog-to-digital conversion module. The external calibration circuit can determine the arrival time of the received first calibration signal based on its own timer. Here, the arrival time of the first calibration signal can include the start time of the digital signal obtained by converting the first calibration signal received by the control module of the external calibration circuit.

[0279] In a possible implementation, the first calibration signal is used to calibrate the timers of the control module and the external calibration circuit that receives the first calibration signal. It can be understood that the external calibration circuit can also determine the sampling delay of the analog-to-digital conversion module in the external calibration circuit to calibrate the transmission delay of the first calibration signal when it is transmitted to the external calibration circuit. The calibrated transmission delay, the determined arrival time of the first calibration signal at the external calibration circuit, and the start time of the first calibration signal determined by the control module in the calibration circuit can be used to determine the time delay between the start time of the timer of the control module in the calibration circuit that sends the first calibration signal and the start time of the timer of the control module in the external calibration circuit, thereby realizing the synchronization of timers between different calibration circuits.

[0280] In a possible implementation, the external calibration circuit may include a calibration circuit in the same signal processing device as the calibration circuit that sends the first calibration signal, and / or a calibration circuit in a different signal processing device from the calibration circuit that sends the first calibration signal.

[0281] A signal processing device shown in an embodiment of the present disclosure, such as Figure 20 shown, the signal processing device includes at least one calibration circuit described in any of the above embodiments. The specific implementation manner of the calibration circuit is as described in any of the above embodiments and will not be elaborated here.

[0282] Here, the signal processing device may include multiple calibration circuits, and each calibration circuit may be the same or different and is used to implement different functions. For example, as Figure 20 shown, the signal processing device may include a first calibration circuit and a second calibration circuit.

[0283] In some embodiments, as Figure 20 shown, the calibration circuit includes a first calibration circuit, wherein the first calibration circuit includes the analog-to-digital conversion module,

[0284] The control module of the first calibration circuit is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer;

[0285] The control module of the first calibration circuit is configured to determine the sampling delay associated with the analog-to-digital conversion module at least based on the second predetermined duration and the first measurement duration.

[0286] It can be understood that Figure 20 in, the signal generation circuit composed of the control module, the clock module, the frequency division module, and the low-pass filter is an implementation manner of the signal generation circuit. Without contradiction, the signal generation circuit may include the signal generation circuit in any of the above embodiments. That is Figure 20In the [description], the signal generation circuits in the first calibration circuit and the second calibration circuit may include Figure 1 , Figure 3 , Figure 6 or Figure 9 any one of the implementation manners in any of the embodiments.

[0287] Here, the first calibration circuit determines that the implementation manner of the sampling time delay associated with the analog-to-digital conversion module in the first calibration circuit is similar to that in the above embodiments (such as Figure 12 the calibration circuit embodiments disclosed), which will not be elaborated here.

[0288] In some embodiments, as Figure 20 shown, the signal processing device further includes N channels to be calibrated, where the channels to be calibrated are respectively used to output signals to be calibrated;

[0289] The first calibration circuit includes a selection switch for selecting one of the first calibration signal and at least one signal to be calibrated and inputting it to the analog-to-digital conversion module; where

[0290] The analog-to-digital conversion module is used to perform analog-to-digital conversion on the signal to be calibrated to be selected to obtain a digital signal to be calibrated;

[0291] The control module is used to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated;

[0292] The arrival time of the digital signal to be calibrated, the sampling time delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the signal to be calibrated selected are used to synchronize the timer of the first calibration circuit and the timer of the channel to be calibrated corresponding to the signal to be calibrated selected, where the signal to be calibrated is output from the channel to be calibrated.

[0293] Here, N is a positive integer greater than or equal to 1.

[0294] As Figure 20 described, the channels to be calibrated can be carried on the signal source sub-card. One signal source sub-card can carry 1 or more channels to be calibrated.

[0295] The implementation manner for the first calibration circuit to determine the arrival time of the digital signal to be calibrated, and the implementation manner for synchronizing the timer of the first calibration circuit and the timer of the channel to be calibrated through the arrival time of the digital signal to be calibrated, etc., are as described in any of the above embodiments, which will not be elaborated here.

[0296] In some embodiments, as Figure 20 , the calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module;

[0297] The fan-out module is connected to the low-pass filter and is configured to fan out at least one first calibration signal of the second calibration circuit.

[0298] Here, the signal processing device may include a first calibration circuit and a second calibration circuit.

[0299] In a possible implementation, the first calibration circuit and the second calibration circuit may be carried on different daughter cards respectively. For example, the first calibration circuit and the second calibration circuit may be carried on different daughter cards of a signal processing device with a PXIe architecture.

[0300] In a possible implementation, the fan-out module may adjust the level of the first calibration signal to meet the requirements of the receiving end of the first calibration signal.

[0301] In a possible implementation, the first calibration signal may be received by an external calibration circuit. The external calibration circuit may include a calibration circuit that is the same as or different from the first calibration circuit in a different signal processing device.

[0302] Here, the implementation of the external calibration circuit may include any of the above calibration circuits including an analog-to-digital conversion module. The external calibration circuit may determine the arrival time of the received first calibration signal based on its own timer. Here, the arrival time of the first calibration signal may include the starting time when the control module of the external calibration circuit receives the digital signal obtained by converting the first calibration signal.

[0303] In a possible implementation, the first calibration signal is used to calibrate the timer of the control module and the timer of the external calibration circuit that receives the first calibration signal. It can be understood that the external calibration circuit can also determine the sampling delay of the analog-to-digital conversion module in the external calibration circuit to calibrate the transmission delay of the first calibration signal when it is transmitted to the external calibration circuit. The calibrated transmission delay, the determined arrival time of the first calibration signal at the external calibration circuit, and the starting time of the first calibration signal determined by the control module in the calibration circuit can determine the time delay between the starting time of the timer of the control module in the calibration circuit that sends the first calibration signal and the starting time of the timer of the control module in the external calibration circuit, thereby realizing the synchronization of the timers between different calibration circuits.

[0304] In some embodiments, the first calibration circuit includes a selection switch for selecting a second calibration signal external to the first calibration circuit and inputting it into the analog-to-digital conversion module; wherein,

[0305] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0306] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, where the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0307] The implementation manner in which the first calibration circuit determines the arrival time of the second digital signal, and the implementation manner in which the time delay between the start time of the timer of the control module in the first calibration circuit and the start time of the timer associated with the second calibration signal is determined by the arrival time of the second digital signal are as described in any of the above embodiments and will not be elaborated here.

[0308] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

[0309] As Figure 20 shown, the first calibration signal of the second calibration circuit is used as the second calibration signal input to the first calibration circuit by being input to the input end of the selection switch of the first calibration circuit. Thus, the time delay between the start time of the timer in the first calibration circuit and the start time of the timer in the second calibration circuit can be determined, and further, the synchronization between the timer in the first calibration circuit and the timer in the second calibration circuit can be achieved.

[0310] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal sent by an external signal processing device.

[0311] It can be understood that the second calibration signal can also be sent by an external signal processing device other than the signal processing device to which the first calibration circuit belongs. Through the arrival time of the second digital signal determined by the calibration circuit, the start time of the second calibration signal determined by the external signal processing device, and the transmission time delay of the calibrated second calibration signal, the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal can be determined, and further, the synchronization between the timer of the control module and the timer associated with the second calibration signal can be achieved.

[0312] As Figure 21 shown, the first calibration circuit of the second signal processing device receives the calibration signal of the second calibration circuit of the first signal processing device. The manner in which the first calibration circuit of the second signal processing device and the second calibration circuit of the first signal processing device determine the time delay through the calibration signal is similar to the manner in which the time delay is determined between the internal calibration circuits of the signal processing device and will not be elaborated here.

[0313] A signal processing system shown in an embodiment of the present disclosure, as Figure 21 shown, the signal processing system includes at least one signal processing device as described in any of the above embodiments.

[0314] As Figure 21 shown, the signal processing system may include multiple signal processing devices, such as a first signal processing device, a second signal processing device, etc.

[0315] The specific implementation manner of the signal processing device is as described in any of the above embodiments.

[0316] It can be understood that Figure 21 in the second signal processing device, the signal source sub - card is a simplified block diagram, and its implementation manner may include the implementation manner of the signal source sub - card in any of the above embodiments. There may be multiple second signal processing devices in the signal processing system.

[0317] In a possible implementation manner, the first signal processing device may be used as the master device, and the second signal processing device may be used as the slave device. The first signal processing device may send a reference signal to the second signal device through an electrical connection to achieve synchronization of the clock frequency, etc. The first signal processing device may also achieve control of the second signal device through an electrical connection to synchronize operations in the determination of the time delay.

[0318] In the signal processing system, the first signal processing device may synchronize the timers of the first calibration circuits in each signal processing device (including the first signal processing device and the second signal processing device) with the timer of the second calibration circuit in the first signal processing device through a second calibration circuit.

[0319] The manner in which the signal processing device determines the start - time delay of the timer by transmitting a calibration signal and then achieves synchronization between the timers is as described in the above embodiments, and will not be elaborated here.

[0320] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above - mentioned method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer - readable storage medium. When the program is executed, it executes the steps including the above - mentioned method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disk, or optical disc that can store program codes.

[0321] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0322] In the description of this specification, the descriptions referring to "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0323] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A calibration circuit, the calibration circuit comprising a signal generating circuit; The signal generating circuit comprises: Clock module, control module, frequency division module and low-pass filter, among which, The clock module is used to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used to generate at least a working clock signal of the control module and an input clock signal of the frequency division module; The control module is used to send a first frequency division reset signal to the frequency division module, and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer is timed based on the working clock signal; The first frequency division reset signal is used to control the start time of the frequency division module outputting the frequency division signal and the start time of the timer to be separated by a first predetermined time length; A low-pass filter, used for performing low-pass filtering on the frequency-divided signal to obtain a first calibration signal, wherein a start time of the first calibration signal is separated from a start time of the timer by a second predetermined time length; The first calibration signal is at least used for an analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between an initial moment of the first digital signal and a start moment of the timer, wherein the first measurement duration is at least used to determine a transmission delay associated with the first calibration signal.

2. The calibration circuit according to claim 1, characterized in that: The calibration circuit includes the analog-to-digital conversion module, The control module is configured to receive the first digital signal and determine a first measurement duration between an initial moment of the first digital signal and a start moment of the timer; The control module is used to determine a sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

3. The calibration circuit according to claim 2, characterized in that: The calibration circuit includes a selection switch for selecting one of the first calibration signal and N signals to be calibrated to be input to the analog-to-digital conversion module; wherein, The analog-to-digital conversion module is used to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated; The control module is used to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated; The arrival time of the digital signal to be calibrated, the sampling delay and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

4. The calibration circuit according to claim 2, characterized in that: The calibration circuit includes a selection switch for selecting a second calibration signal outside the calibration circuit to be input into the analog-to-digital conversion module; wherein, The analog-to-digital conversion module is used to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal; The control module is used to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

5. The calibration circuit according to any one of claims 1 to 4, characterized in that: The signal generating circuit further comprises a fan-out module; The fan-out module is connected to the low-pass filter and is used to fan out at least one first calibration signal.

6. The calibration circuit according to claim 1, characterized in that: The signal generating circuit further comprises: a first clock buffer; the control module comprises: a first synchronous reset control module and a signal delay submodule; the frequency dividing module comprises a first frequency divider; The first clock buffer is used to generate the working clock signal and the input clock signal based on the first clock signal; The first synchronous reset control module is used to send the first frequency division reset signal to the frequency division module; The signal delay submodule is used to delay the first frequency-divided reset signal by a predetermined delay time to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and to generate the frequency division signal based on the input clock signal.

7. The calibration circuit according to claim 1, characterized in that: The signal generating circuit further comprises: a second clock buffer; the control module comprises: a phase adjustment module and a second synchronous reset control module; the frequency dividing module comprises a second frequency divider; The second clock buffer is used to generate a second clock signal and the input clock signal based on the first clock signal; The second synchronous reset control module is used to generate a first frequency-divided reset signal based on the working clock signal; The phase adjustment module is used to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency-divided reset signal triggered by the working clock signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is configured to be triggered by the first frequency division reset signal at the predetermined trigger edge and to generate the frequency division signal based on the input clock signal.

8. The calibration circuit according to claim 1, characterized in that: The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock is used to input the counting frequency divider as the input clock; The third synchronous reset control module is used to generate a first frequency-divided reset signal based on the working clock signal; The start-up time includes a predetermined edge of the working clock signal after the first frequency-divided reset signal is generated; The counting frequency divider is used to be triggered by the first frequency division reset signal at the predetermined edge, count the working clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

9. A signal processing device, characterized in that: The signal processing device comprises at least one calibration circuit according to any one of claims 1 to 7.

10. The signal processing device according to claim 9, characterized in that The calibration circuit comprises a first calibration circuit, wherein the first calibration circuit comprises the analog-to-digital conversion module, The control module of the first calibration circuit is used to receive the first digital signal and determine a first measurement duration between an initial moment of the first digital signal and a start moment of the timer; The control module of the first calibration circuit is used to determine a sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

11. The signal processing device according to claim 10, characterized in that The signal processing device further includes N channels to be calibrated, wherein the channels to be calibrated are respectively used to output signals to be calibrated; The first calibration circuit includes a selection switch for selecting one of the first calibration signal and at least one signal to be calibrated to be input to the analog-to-digital conversion module; wherein, The analog-to-digital conversion module is used to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated; The control module is used to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated; The arrival time of the digital signal to be calibrated, the sampling delay and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the first calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

12. The signal processing device according to claim 11, characterized in that The first calibration circuit includes a selection switch for selecting a second calibration signal outside the first calibration circuit to be input into the analog-to-digital conversion module; wherein, The analog-to-digital conversion module is used to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal; The control module is used to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

13. The signal processing device according to any one of claims 9 to 12, characterized in that: The calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module; The fan-out module is connected to the low-pass filter and is used to fan out at least one first calibration signal of the second calibration circuit.

14. The signal processing device according to claim 13, characterized in that The second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

15. The signal processing device according to claim 12, characterized in that The second calibration signal selected by the first calibration circuit includes a first calibration signal sent by an external signal processing device.

16. A signal processing system, characterized in that: The signal processing system comprises at least one signal processing device according to any one of claims 9 to 15.

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