Multiplication digital-to-analog converter and capacitance switching amplifying circuit thereof

Abstract

The invention provides a multiplication digital-to-analog converter and a capacitance switching amplification circuit thereof. The multiplication digital-to-analog converter is provided with two input ends and two output ends, and comprises an analog-to-digital converter, a selection circuit, a first sampling and amplifying circuit, a second sampling and amplifying circuit, an operational amplifier and an amplifying and level shifting circuit. The analog-to-digital converter generates a selection signal according to a first input signal and a second input signal. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to the reference voltage. The second sampling and amplifying circuit samples and amplifies the second input signal according to another reference voltage. The operational amplifier has a first output node and a second output node. An amplification and level shift circuit amplifies the first input signal and the second input signal, and level shifts a voltage of the first output node and a voltage of the second output node.

Description

Technical Field

[0001] The present invention relates to a multiplying digital-to-analog converter of a pipelined analog-to-digital converter (pipeline ADC, also known as pipelined ADC), and a capacitive switching amplifier circuit of the multiplying digital-to-analog converter. Background Art

[0002] Please refer to Figure 1A , Figure 1A which is a circuit diagram of a conventional correlated level shifting (CLS) switched capacitor (SC) circuit. Figure 1A The circuit of includes an operational amplifier 110, capacitors C1, C2, C3, C4, switches SW1, SW2, SW3, SW4, and switch SW5. The correlated level shifting circuit 120 includes capacitors C3, switch SW4, and switch SW5.

[0003] Figure 1B shows three clocks such as clock CLK1, clock CLKe, and clock CLK2, Figure 1A and the circuit of operates according to these three clocks. More specifically, when the sampling phase Φs ends, switch SW1 changes from conducting to non-conducting, switch SW2 switches from the input signal Vin to a reference voltage (e.g., ground), and switch SW3 switches from the input signal Vin to capacitors C3 and C4. During the estimation phase Φe, switch SW4 switches to the reference voltage, and switch SW5 conducts. During the amplification phase Φh, switch SW4 switches to the operational amplifier 110, and switch SW5 does not conduct.

[0004] Continuing from the above paragraph, during the estimation phase Φe, capacitors C3 and C4 are charged to the output voltage Vo of the operational amplifier 110. During the amplification phase Φh, the voltage at the output terminal of the operational amplifier 110 is level shifted so that the AC signal is 0.

[0005] Using the correlated level shifting technique can effectively reduce the required gain of the operational amplifier 110, thereby reducing the power consumption and area of the operational amplifier 110. However, Figure 1A the circuit of requires three clocks, causing practical difficulties and making it difficult to increase the circuit speed. In addition, when the correlated level shifting technique is applied to a multiplying digital-to-analog converter (MDAC) of a pipelined analog-to-digital converter (pipeline ADC, also known as pipelined ADC), another clock CLK3 is also required (as shown in Figure 2As shown, it is used to control the sub-analog-to-digital converter (sub-ADC), which also increases practical difficulties and reduces the circuit speed. Summary of the Invention

[0006] In view of the deficiencies of the prior art, the object of the present invention is to provide a multiplying digital-to-analog converter and its capacitive switching amplifier circuit to improve the deficiencies of the prior art.

[0007] An embodiment of the present invention provides a multiplying digital-to-analog converter (multiplying DAC, MDAC). The multiplying digital-to-analog converter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes: an analog-to-digital converter, a selection circuit, a first sampling and amplification circuit, a second sampling and amplification circuit, an operational amplifier, and an amplification and level-shifting circuit. The analog-to-digital converter is coupled to the first input terminal and the second input terminal for generating a selection signal according to a first input signal and a second input signal. The selection circuit is coupled to the analog-to-digital converter for selecting a first reference voltage and a second reference voltage from a plurality of preset voltages according to the selection signal. The first sampling and amplification circuit is coupled to the selection circuit and the first input terminal for sampling and amplifying the first input signal according to the first reference voltage. The second sampling and amplification circuit is coupled to the selection circuit and the second input terminal for sampling and amplifying the second input signal according to the second reference voltage. The operational amplifier is coupled to the first sampling and amplification circuit and the second sampling and amplification circuit, and has a first output node and a second output node. The amplification and level-shifting circuit is coupled to the first output node, the second output node, the first output terminal, the second output terminal, the first input terminal, the second input terminal, and the selection circuit for amplifying the first input signal and the second input signal, and for level-shifting the voltages of the first output node and the second output node.

[0008] Another embodiment of the present invention provides a capacitive switching amplifier circuit. The capacitive switching amplifier circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes: a first sampling and amplifying circuit, a second sampling and amplifying circuit, an operational amplifier, a first switched capacitor circuit, and a second switched capacitor circuit. The first sampling and amplifying circuit is coupled to the first input terminal for sampling and amplifying a first input signal. The second sampling and amplifying circuit is coupled to the second input terminal for sampling and amplifying a second input signal. The operational amplifier is coupled to the first sampling and amplifying circuit and the second sampling and amplifying circuit, and has a first output node and a second output node. The first switched capacitor circuit is coupled to the first output node and the first output terminal for amplifying the first input signal and the second input signal, and for level-shifting the voltage of the first output node. The second switched capacitor circuit is coupled to the second output node and the second output terminal for amplifying the first input signal and the second input signal, and for level-shifting the voltage of the second output node.

[0009] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention is easier to design and has a higher circuit speed compared to the prior art.

[0010] The features, practices, and effects of the present invention will be described in detail with reference to the accompanying drawings and embodiments as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a circuit diagram of a related prior art level-shifting capacitive switching circuit;

[0012] Figure 1B shows waveforms of multiple clocks;

[0013] Figure 2 shows waveforms of multiple clocks;

[0014] Figure 3 is a functional block diagram of an embodiment of a multiplication digital-to-analog converter of the present invention;

[0015] Figure 4 is a waveform diagram of a clock of the present invention;

[0016] Figure 5 is Figure 3 a circuit diagram of an embodiment of an amplification and level-shifting circuit of

[0017] Figure 6 is Figure 3 a circuit diagram of another embodiment of an amplification and level-shifting circuit of

[0018] Figure 7 is a functional block diagram of another embodiment of a multiplication digital-to-analog converter of the present invention;

[0019] Figure 8 is Figure 7 a circuit diagram of an embodiment of an amplification and level - shifting circuit;

[0020] Figure 9 is Figure 7 a circuit diagram of another embodiment of an amplification and level - shifting circuit;

[0021] Figure 10 is a functional block diagram of another embodiment of the multiplication digital - to - analog converter of the present invention;

[0022] Figure 11 is Figure 10 a circuit diagram of an embodiment of an amplification and level - shifting circuit;

[0023] Figure 12 is a functional block diagram of another embodiment of the multiplication digital - to - analog converter of the present invention; and

[0024] Figure 13 is Figure 12 a circuit diagram of an embodiment of a switched - capacitor circuit. Detailed implementation manners

[0025] The technical terms in the following description refer to the customary terms in the technical field. If the present specification explains or defines some terms, the explanations of these terms shall prevail according to the explanations or definitions in the present specification.

[0026] The disclosure of the present invention includes a multiplication digital - to - analog converter and its capacitive - switching amplification circuit. Since some of the components included in the multiplication digital - to - analog converter and its capacitive - switching amplification circuit of the present invention may be known components individually, the details of the known components will be omitted in the following description on the premise of not affecting the full disclosure and implementability of the device invention.

[0027] In the following description, a signal represents being active at a high level and inactive at a low level, and enabling / disabling a signal represents raising / lowering the level of the signal. However, this is only an example of implementation or illustration and is not used to limit the present invention. In other words, in different embodiments, a signal may also represent being inactive at a high level and active at a low level, and enabling / disabling a signal represents lowering / raising the level of the signal. A level conversion or a logic level conversion represents a signal changing from being enabled (active) to being disabled (inactive), or vice versa.

[0028] Please refer to Figure 3 , Figure 3It is a functional block diagram of an embodiment of a multiplying digital-to-analog converter (MDAC) of the present invention. The multiplying digital-to-analog converter 300 is a 1.5-bit multiplying digital-to-analog converter, having an input terminal Vinp, an input terminal Vinn, an output terminal Vp2, and an output terminal Vn2. The multiplying digital-to-analog converter 300 includes a capacitor switching and amplifying circuit 305, an analog-to-digital converter (ADC) 310, and a selection circuit 320. The capacitor switching and amplifying circuit 305 includes a sampling and amplifying circuit 330p, a sampling and amplifying circuit 330n, an operational amplifier 340, and an amplifying and level shifting circuit 350.

[0029] When the multiplying digital-to-analog converter 300 is applied to a pipelined analog-to-digital converter, the ADC 310 serves as a sub-analog-to-digital converter (sub-ADC) of the pipelined analog-to-digital converter. The ADC 310 is coupled to the input terminal Vinp and the input terminal Vinn, and is used to generate a selection signal SEL according to an input signal Vsp and an input signal Vsn. The input signal Vsp (=Vdc + dV) and the input signal Vsn (=Vdc - dV) can be a differential signal pair, where Vdc is the common-mode voltage of the two, and dV is the signal component.

[0030] The selection circuit 320 is coupled to the ADC 310, and is used to determine a reference voltage VR1, a reference voltage VR2, a reference voltage VRR1, and a reference voltage VRR2 from a plurality of preset voltages (including but not limited to a preset voltage Vx, 0.5 times the preset voltage Vx, a preset voltage Vy, 0.5 times the preset voltage Vy, and a common-mode voltage Vcm of the preset voltage Vx and the preset voltage Vy) according to the selection signal SEL, and respectively provide the reference voltage VR1 and the reference voltage VR2 to the sampling and amplifying circuit 330p and the sampling and amplifying circuit 330n, and provide the reference voltage VRR1 and the reference voltage VRR2 to the amplifying and level shifting circuit 350. The preset voltage Vx can be Vcm + Vz, the preset voltage Vy can be Vcm - Vz, and Vz is a DC voltage. In some embodiments, the selection circuit 320 can be a multiplexer.

[0031] Based on the operating principle of the pipelined analog-to-digital converter, those skilled in the art with ordinary knowledge can understand that the purpose of the ADC 310 and the selection circuit 320 is to prevent the output voltage of the multiplying digital-to-analog converter 300 (i.e., the voltage of the output terminal Vp2 and the voltage of the output terminal Vn2) from being too large, so the internal circuits and operation details of the ADC 310 and the selection circuit 320 will not be elaborated here.

[0032] The sampling and amplifying circuit 330p and the sampling and amplifying circuit 330n have corresponding components, each including two capacitors and six switches. Details are as follows.

[0033] The two ends of capacitor C0p (capacitor C0n) are node D1p (node D1n) and node D2p (node D2n) respectively. The two ends of capacitor C1p (capacitor C1n) are node D1p (node D1n) and node D3p (node D3n) respectively.

[0034] One end of switch S0p (switch S0n) is coupled or electrically connected to the input terminal Vinp (input terminal Vinn); the other end of switch S0p (switch S0n) is coupled or electrically connected to node D2p (node D2n).

[0035] One end of switch S1p (switch S1n) is coupled or electrically connected to the input terminal Vinp (input terminal Vinn); the other end of switch S1p (switch S1n) is coupled or electrically connected to node D3p (node D3n).

[0036] One end of switch S2p (switch S2n) is coupled or electrically connected to node D1p; the other end of switch S2p (switch S2n) receives or is coupled to the reference voltage Vref (e.g., grounded).

[0037] One end of switch S3p (switch S3n) is coupled or electrically connected to node D2p (node D2n); the other end of switch S3p (switch S3n) is coupled or electrically connected to the output terminal Vp2 (output terminal Vn2).

[0038] One end of switch S4p (switch S4n) is coupled or electrically connected to node D1p (node D1n); the other end of switch S4p (switch S4n) is coupled or electrically connected to the input terminal of operational amplifier 340 (more specifically, input node Vp0 (input node Vn0)).

[0039] One end of switch S5p (switch S5n) is coupled or electrically connected to node D3p (node D3n); the other end of switch S5p (switch S5n) receives the reference voltage VR1 (reference voltage VR2) (i.e., is coupled or electrically connected to the selection circuit 320).

[0040] The inverting input terminal of operational amplifier 340 (i.e., input node Vp0) is coupled or electrically connected to the sampling and amplifying circuit 330p; the non-inverting input terminal of operational amplifier 340 (i.e., input node Vn0) is coupled or electrically connected to the sampling and amplifying circuit 330n. The output node Vp1 is the non-inverting output terminal of operational amplifier 340; the output node Vn1 is the inverting output terminal of operational amplifier 340.

[0041] The amplification and level - shifting circuit 350 is coupled or electrically connected to the output node Vp1, the output node Vn1, the output terminal Vp2, the output terminal Vn2, the input terminal Vinp (for receiving the input signal Vsp), the input terminal Vinn (for receiving the input signal Vsn), and the selection circuit 320 (for receiving the reference voltage VR1 and the reference voltage VR2). The amplification and level - shifting circuit 350 amplifies the signal components (i.e., dV) of the input signal Vsp and the input signal Vsn, and level - shifts the voltages of the output node Vp1 and the output node Vn1.

[0042] Please refer to Figure 4 , Figure 4 which is the waveform diagram of the clock of the present invention. The clock CLK1, the clock CLK2, and the clock CLK3 are not simultaneously at the first level (e.g., high level).

[0043] During the phase Φ1 (i.e., when the clock CLK1 is at the first level and the clock CLK2 and the clock CLK3 are at the second level (e.g., low level)), the sampling and amplification circuits 330p and 330n sample the input signals Vsp and Vsn, and the amplification and level - shifting circuit 350 amplifies the signal components dV of the input signals Vsp and Vsn (which will be described in detail below in conjunction with Figure 5 ).

[0044] More specifically, during the phase Φ1, the switches S0p (switch S0n), S1p (switch S1n), and S2p (switch S2n) are turned on and the switches S3p (switch S3n), S4p (switch S4n), and S5p (switch S5n) are turned off, so that the capacitors C0p (capacitor C0n) and C1p (capacitor C1n) sample the input signal Vsp (input signal Vsn).

[0045] During the phase Φb (i.e., when the clock CLK2 is at the first level and the clock CLK1 and the clock CLK3 are at the second level), the ADC 310 generates the selection signal SEL, the selection circuit 320 generates the reference voltage VR1 and the reference voltage VR2 according to the selection signal SEL, and the amplification and level - shifting circuit 350 samples the reference voltage VR1 and the reference voltage VR2.

[0046] During the phase Φ2 (i.e., when the clock CLK3 is at the first level and the clock CLK1 and the clock CLK2 are at the second level), the sampling and amplification circuits 330p and 330n perform the amplification operation, and the amplification and level - shifting circuit 350 level - shifts the voltages of the output node Vp1 and the output terminal Vp2 according to at least the input signal Vsp, the input signal Vsn, the reference voltage VRR1, and the reference voltage VRR2 (which will be described in detail below in conjunction with Figure 5Detailed description).

[0047] More specifically, during phase Φ2, switches S0p (switch S0n), S1p (switch S1n), and S2p (switch S2n) are not conducting and switches S3p (switch S3n), S4p (switch S4n), and S5p (switch S5n) are conducting, such that capacitor C0p (capacitor C0n) becomes the feedback capacitor and capacitor C1p (capacitor C1n) is coupled between the selection circuit 320 and the operational amplifier 340, and the voltages at output terminals Vp2 and Vn2 are respectively given by Equation (1) and Equation (2), and the difference between the two is as shown in Equation (3).

[0048] Vp2 = {[dV*(C0p + C1p) / C0p] - VR1} + Vdc2 (1)

[0049] Vn2 = -{[-dV*(C0n + C1n) / C0n] - VR2} + Vdc2 (2)

[0050] Vp2 - Vn2 = {[dV*(C0p + C1p) / C0p] - VR1} - {[-dV*(C0n + C1n) / C0n] - VR2} (3)

[0052] Wherein, the voltage Vdc2 is the DC voltage value of output terminal Vp2 (output terminal Vn2).

[0053] In other words, the sampling and amplification circuit 330p (sampling and amplification circuit 330n) amplifies the signal component dV of the input signal Vsp (input signal Vsn) and generates a signal at output terminal Vp2 (output terminal Vn2).

[0054] Assuming C0p = C1p = C0n = C1n = 1, the signal component dV is amplified by a factor of 2 (as shown in Equation (3) and Equation (4)).

[0055] Vp2 = 2*dV - VR1 + Vdc2 (3)

[0056] Vn2 = -2*dV - VR2 + Vdc2 (4)

[0057] Please refer to Figure 5 , Figure 5 , which is a circuit diagram of an embodiment of the amplification and level - shifting circuit 350 of the present invention. The amplification and level - shifting circuit 350 includes a switched - capacitor circuit 350p and a switched - capacitor circuit 350n. The switched - capacitor circuit 350p and the switched - capacitor circuit 350n have corresponding elements, each including 2 capacitors and 7 switches. The details are as follows.

[0058] The two ends of capacitor Cs0p (capacitor Cs0n) are node N1p (node N1n) and node N2p (node N2n) respectively. The two ends of capacitor Cs1p (capacitor Cs1n) are node N3p (node N3n) and node N4p (node N4n) respectively.

[0059] One end of switch Ss0p (switch Ss0n) receives an input signal Vsp (input signal Vsn) (i.e., is coupled or electrically connected to input terminal Vinp (input terminal Vinn)); the other end of switch Ss0p (switch Ss0n) is coupled or electrically connected to node N1p (node N1n).

[0060] One end of switch Ss1p (switch Ss1n) receives an input signal Vsn (input signal Vsp) (i.e., is coupled or electrically connected to input terminal Vinn (input terminal Vinp)); the other end of switch Ss1p (switch Ss1n) is coupled or electrically connected to node N2p (node N2n).

[0061] One end of switch Ss2p (switch Ss2n) receives a reference voltage VRR2 (reference voltage VRR1) (i.e., is coupled or electrically connected to selection circuit 320); the other end of switch Ss2p (switch Ss2n) is coupled or electrically connected to node N4p (node N4n).

[0062] One end of switch Ss3p (switch Ss3n) receives a DC voltage Vbias; the other end of switch Ss3p (switch Ss3n) is coupled or electrically connected to node N3p (node N3n).

[0063] One end of switch Ss4p (switch Ss4n) is coupled or electrically connected to output terminal Vp2 (output terminal Vn2); the other end of switch Ss4p (switch Ss4n) is coupled or electrically connected to node N1p (node N1n).

[0064] One end of switch Ss5p (switch Ss5n) is coupled or electrically connected to node N2p (node N2n); the other end of switch Ss5p (switch Ss5n) is coupled or electrically connected to node N4p (node N4n).

[0065] One end of switch Ss6p (switch Ss6n) is coupled or electrically connected to output node Vp1 (output node Vn1); the other end of switch Ss6p (switch Ss6n) is coupled or electrically connected to node N3p (node N3n).

[0066] Please refer to Figure 4 and Figure 5. During phase Φ1, switches Ss0p (switch Ss0n) and switches Ss1p (switch Ss1n) are turned on, and the other switches are turned off, so that capacitor Cs0p (capacitor Cs0n) receives input signal Vsp and input signal Vsn. Therefore, when phase Φ1 ends, the voltage across capacitor Cs0p (capacitor Cs0n), V0p (voltage across V0n), is -2dV (+2dV).

[0067] During phase Φb, switches Ss2p (switch Ss2n) and switches Ss3p (switch Ss3n) are turned on, and the other switches are turned off, so that capacitor Cs1p (capacitor Cs1n) receives reference voltage VR2 (reference voltage VR1) and DC voltage Vbias. Therefore, when phase Φb ends, the voltage across capacitor Cs1p (capacitor Cs1n), V1p (voltage across V1n), is Vbias - VR2 (Vbias - VR1).

[0068] During phase Φ2, switches Ss4p (switch Ss4n), switches Ss5p (switch Ss5n) and switches Ss6p (switch Ss6n) are turned on, and the other switches are turned off, so that a voltage difference Vp21 (as shown in Equation (5)) is generated between output terminal Vp2 and output node Vp1, and a voltage difference Vn21 (as shown in Equation (6)) is generated between output terminal Vn2 and output node Vn1.

[0069] Vp21 = Vp2 - Vp1 = 2*dV + (VRR2 - Vbias) (5)

[0070] Vn21 = Vn2 - Vn1 = -2*dV + (VRR1 - Vbias) (6)

[0071] Based on Equation (3) and Equation (5), Equation (7) can be obtained, and based on Equation (4) and Equation (6), Equation (8) can be obtained.

[0072] Vp1 = Vp2 - Vp21 = -VR1 + Vdc2 - VRR2 + Vbias (7)

[0073] Vn1 = Vn2 - Vn21 = -VR2 + Vdc2 - VRR1 + Vbias (8)

[0074] By controlling selection circuit 320 such that VRR2 = -VR1 and VRR1 = -VR2, Equation (7) and Equation (8) become Equation (9) and Equation (10) respectively.

[0075] Vp1 = Vdc2 + Vbias (9)

[0076] Vn1 = Vdc2 + Vbias (10)

[0077] From Equation (9) and Equation (10), it can be seen that the output node Vp1 and the output node Vn1 of the operational amplifier 340 do not include the signal component dV, the preset voltage Vx, the preset voltage Vy, and the common-mode voltage Vcm. Therefore, the operational amplifier 340 can maintain better linearity and better gain. That is to say, by pre-sampling the input signal Vsp and the input signal Vsn, the amplification and level-shifting circuit 350 can implement the relevant level-shifting technique (so that the output node Vp1 and the output node Vn1 of the operational amplifier 340 do not include the signal component dV of the input signal Vsp and the input signal Vsn), but the multiplying digital-to-analog converter 300 only requires three clocks (that is, does not require Figure 2 the clock CLKe or the estimated phase). Therefore, the multiplying digital-to-analog converter 300 becomes easier to implement, and the circuit speed can be improved.

[0078] Please refer to Figure 6 , Figure 6 which is a circuit diagram of another embodiment of the amplification and level-shifting circuit 350 of the present invention. Figure 6 Similar to Figure 5 , the difference is that the switch Ss2p receives the DC voltage Vbias (instead of the reference voltage VRR2), the switch Ss3p receives the reference voltage VRR2 (instead of the DC voltage Vbias), the switch Ss2n receives the DC voltage Vbias (instead of the reference voltage VRR1), and the switch Ss3n receives the reference voltage VRR1 (instead of the DC voltage Vbias). Figure 6 The circuit of Figure 5 and the circuit of

[0079] Please refer to Figure 7 , Figure 7 which is a functional block diagram of another embodiment of the multiplying digital-to-analog converter of the present invention. The multiplying digital-to-analog converter 700 is a 2.5-bit multiplying digital-to-analog converter, having an input terminal Vinp, an input terminal Vinn, an output terminal Vp2, and an output terminal Vn2. The multiplying digital-to-analog converter 700 includes a capacitive switching amplification circuit 705, an ADC 710, and a selection circuit 720. The functions of the ADC 710, the selection circuit 720, and the operational amplifier 740 are respectively similar to those of the ADC 310, the selection circuit 320, and the operational amplifier 340, so they will not be elaborated here.

[0080] The sampling and amplification circuit 730p and the sampling and amplification circuit 730n have corresponding components, each including 4 capacitors and 10 switches. Compared with the sampling and amplification circuit 330p, the sampling and amplification circuit 730p further includes capacitor C2p, capacitor C3p, switch S6p, switch S7p, switch S8p, and switch S9p. The reference voltage VR1 includes reference voltage VR1_1, reference voltage VR1_2, and reference voltage VR1_3. Switch S5p receives reference voltage VR1_1. The reference voltage VR1_1, the reference voltage VR1_2, and the reference voltage VR1_3 are each one selected from the preset voltage Vx, the preset voltage Vy, the common mode voltage Vcm, 0.5Vx, and 0.5Vy.

[0081] The two ends of capacitor C2p are node D1p and node D4p respectively. The two ends of capacitor C3p are node D1p and node D5p respectively.

[0082] One end of switch S6p is coupled or electrically connected to the input terminal Vinp; the other end of switch S6p is coupled or electrically connected to node D4p.

[0083] One end of switch S7p is coupled or electrically connected to node D4p; the other end of switch S7p receives reference voltage VR1_2 (i.e., is coupled or electrically connected to the selection circuit 720).

[0084] One end of switch S8p is coupled or electrically connected to the input terminal Vinp; the other end of switch S8p is coupled or electrically connected to node D5p.

[0085] One end of switch S9p is coupled or electrically connected to node D5p; the other end of switch S9p receives reference voltage VR1_3 (i.e., is coupled or electrically connected to the selection circuit 720).

[0086] The states (conducting or non-conducting) of switch S6p and switch S8p are the same as that of switch S0p. The states of switch S7p and switch S9p are the same as that of switch S5p. Those skilled in the art with ordinary knowledge can Figure 3 and the sampling and amplification circuit 730p to understand the detailed circuit of the sampling and amplification circuit 730n, so it will not be elaborated here. Those skilled in the art with ordinary knowledge can understand the operation principle of the multiplication digital-to-analog converter 700 according to the description of the multiplication digital-to-analog converter 300, so it will not be elaborated here.

[0087] Please refer to Figure 8 , Figure 8It is a circuit diagram of an embodiment of the amplification and level - shifting circuit 750 of the present invention. The amplification and level - shifting circuit 750 includes a switched - capacitor circuit 750p and a switched - capacitor circuit 750n. The switched - capacitor circuit 750p (switched - capacitor circuit 750n) is similar to the switched - capacitor circuit 350p (switched - capacitor circuit 350n), except that the switched - capacitor circuit 750p (switched - capacitor circuit 750n) further includes a capacitor Cs2p (capacitor Cs2n), a switch Ss7p (switch Ss7n), a switch Ss8p (switch Ss8n), and a switch Ss9p (switch Ss9n).

[0088] The two ends of the capacitor Cs2p (capacitor Cs2n) are node N5p (node N5n) and node N6p (node N6n) respectively.

[0089] One end of the switch Ss7p (switch Ss7n) is coupled or electrically connected to the input terminal Vinn (input terminal Vinp); the other end of the switch Ss7p (switch Ss7n) is coupled or electrically connected to the node N5p (node N5n).

[0090] One end of the switch Ss8p (switch Ss8n) is coupled or electrically connected to the input terminal Vinp (input terminal Vinn); one end of the switch Ss8p (switch Ss8n) is coupled or electrically connected to the node N6p (node N6n).

[0091] One end of the switch Ss9p (switch Ss9n) is coupled or electrically connected to the node N2p (node N2n); one end of the switch Ss9p (switch Ss9n) is coupled or electrically connected to the node N6p (node N6n).

[0092] The states of the switch Ss7p (switch Ss7n) and the switch Ss8p (switch Ss8n) are the same as those of the switch Ss0p (switch Ss0n). The state of the switch Ss9p (switch Ss9n) is the same as that of the switch Ss5p (switch Ss5n). The switched - capacitor circuit 750p and the switched - capacitor circuit 750n can amplify the signal component dV of the input signal Vsp or the input signal Vsn by 4 times. Those of ordinary skill in the art can understand the operating principle of the amplification and level - shifting circuit 750 according to the description of the amplification and level - shifting circuit 350, so it will not be elaborated here.

[0093] Please refer to Figure 9 , Figure 9 It is a circuit diagram of another embodiment of the amplification and level - shifting circuit 750 of the present invention. Figure 9 And Figure 8Similar, the difference is that switch Ss2p receives DC voltage Vbias (instead of reference voltage VRR2), switch Ss3p receives reference voltage VRR2 (instead of DC voltage Vbias), switch Ss2n receives DC voltage Vbias (instead of reference voltage VRR1), and switch Ss3n receives reference voltage VRR1 (instead of DC voltage Vbias). Figure 9 The circuit of Figure 8 can both cause voltage level shifting.

[0094] Similarly, the amplification and voltage level shifting circuit 750 of the multiplication digital-to-analog converter 700 can implement relevant voltage level shifting techniques, but the multiplication digital-to-analog converter 700 only requires three clocks (i.e., does not require Figure 2 the clock CLKe or the estimated phase). Therefore, the multiplication digital-to-analog converter 700 becomes easier to practice, and the circuit speed can be improved.

[0095] Please refer to Figure 10 , Figure 10 which is a functional block diagram of another embodiment of the multiplication digital-to-analog converter of the present invention. The multiplication digital-to-analog converter 1000 is similar to the multiplication digital-to-analog converter 300, the difference being that the amplification and voltage level shifting circuit 1050 is different from the amplification and voltage level shifting circuit 350 (and thus the capacitor switching amplification circuit 1005 is different from the capacitor switching amplification circuit 305).

[0096] Please refer to Figure 11 , Figure 11 which is a circuit diagram of an embodiment of the amplification and voltage level shifting circuit 1050 of the present invention. The amplification and voltage level shifting circuit 1050 includes a switched capacitor circuit 1050p and a switched capacitor circuit 1050n. The switched capacitor circuit 1050p and the switched capacitor circuit 1050n have corresponding elements, each including 1 capacitor, 3 switches, 1 selection circuit, and 3 sub-switched capacitor circuits. Details are as follows.

[0097] The switched capacitor circuit 1050p (switched capacitor circuit 1050n) includes a capacitor Cs0p (capacitor Cs0n), switches Ss0p (switches Ss0n), switches Ss1p (switches Ss1n), switches Ss2p (switches Ss2n), a selection circuit 1105p (selection circuit 1105n), a sub-switched capacitor circuit 1110p (sub-switched capacitor circuit 1110n), a sub-switched capacitor circuit 1120p (sub-switched capacitor circuit 1120n), and a sub-switched capacitor circuit 1130p (sub-switched capacitor circuit 1130n). The sub-switched capacitor circuits 1110p, 1120p, and 1130p are substantially the same, each including one capacitor (capacitor Cs1p) and three switches (switches Ss3p, Ss4p, and Ss5p). The sub-switched capacitor circuits 1110n, 1120n, and 1130n are substantially the same, each including one capacitor (capacitor Cs1n) and three switches (switches Ss3n, Ss4n, and Ss5n). The sub-switched capacitor circuit 1110p is substantially the same as the sub-switched capacitor circuit 1110n.

[0098] The sub-switched capacitor circuit 1110p (sub-switched capacitor circuit 1120p, sub-switched capacitor circuit 1130p) is coupled between the selection circuit 1105p and the output node Vp1, and is used to generate a candidate voltage V1 (candidate voltage V2, candidate voltage V3) according to the DC voltage Vbias and the preset voltage Vx (common mode voltage Vcm, preset voltage Vy). The sub-switched capacitor circuits 1110n, 1120n, and 1130n are the same by the same token, so they will not be elaborated here.

[0099] The two ends of the capacitor Cs0p (capacitor Cs0n) are the node N1p (node N1n) and the node N2p (node N2n) respectively. The two ends of the capacitor Cs1p (capacitor Cs1n) are the node N3p (node N3n) and the node N4p (node N4n) respectively.

[0100] One end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the input terminal Vinp (input terminal Vinn); the other end of the switch Ss0p (switch Ss0n) is coupled or electrically connected to the node N2p (node N2n).

[0101] One end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the node N1p (node N1n); the other end of the switch Ss1p (switch Ss1n) is coupled or electrically connected to the input terminal Vinn (input terminal Vinp).

[0102] One end of switch Ss2p (switch Ss2n) is coupled or electrically connected to node N3p (node N3n). For sub-switch capacitor circuit 1110p and sub-switch capacitor circuit 1110n, the other end of switch Ss2p (switch Ss2n) receives a preset voltage Vx. For sub-switch capacitor circuit 1120p and sub-switch capacitor circuit 1120n, the other end of switch Ss2p (switch Ss2n) receives a preset voltage Vcm. For sub-switch capacitor circuit 1130p and sub-switch capacitor circuit 1130n, the other end of switch Ss2p (switch Ss2n) receives a preset voltage Vy.

[0103] One end of switch Ss3p (switch Ss3n) is coupled or electrically connected to node N4p (node N4n); the other end of switch Ss3p (switch Ss3n) receives a DC voltage Vbias.

[0104] One end of switch Ss4p (switch Ss4n) is coupled or electrically connected to node N2p (node N2n); the other end of switch Ss4p (switch Ss4n) is coupled or electrically connected to output terminal Vp2 (output terminal Vn2).

[0105] One end of switch Ss6p (switch Ss6n) is coupled or electrically connected to node N4p (node N4n); the other end of switch Ss6p (switch Ss6n) is coupled or electrically connected to output node Vp1 (output node Vn1).

[0106] Switch capacitor circuits 1050p and 1050n operate according to Figure 4 the clock. Switches Ss0p, Ss0n, Ss1p, and Ss1n are turned on during phase Φ1 and off at other times. Switches Ss2p, Ss2n, Ss3p, and Ss3n are turned on during phase Φb and off at other times. Switches Ss4p, Ss4n, Ss6p, and Ss6n are turned on during phase Φ2 and off at other times.

[0107] During phase Φ2, selection circuit 1105p (selection circuit 1105n) couples or electrically connects node N1p (node N1n) to a node N3p (node N3n) of one of sub-switch capacitor circuits 1110p (sub-switch capacitor circuits 1110n), sub-switch capacitor circuits 1120p (sub-switch capacitor circuits 1120n), and sub-switch capacitor circuits 1130p (sub-switch capacitor circuits 1130n) according to selection signal SEL (i.e., outputs one of candidate voltages V1, candidate voltage V2, and candidate voltage V3 to node N1p (node N1n)). During periods other than phase Φ2, selection circuit 1105p (selection circuit 1105n) does not couple or electrically connect node N1p (node N1n) to a node N3p (node N3n) of any of sub-switch capacitor circuits 1110p (sub-switch capacitor circuits 1110n), sub-switch capacitor circuits 1120p (sub-switch capacitor circuits 1120n), and sub-switch capacitor circuits 1130p (sub-switch capacitor circuits 1130n).

[0108] The purpose and function of amplification and level shift circuit 1050 are substantially the same as those of amplification and level shift circuit 350. However, compared with amplification and level shift circuit 350, amplification and level shift circuit 1050 can shorten the duration of phase Φb, so amplification and level shift circuit 1050 operates faster (i.e., multiplication digital-to-analog converter 1000 operates faster).

[0109] In a different embodiment, switches Ss2p, Ss2n, Ss3p, and Ss3n are turned on during phase Φ1 and are not turned on at other times. That is, amplification and level shift circuit 1050 can operate only according to clock CLK1 and clock CLK3, further improving the operating speed of multiplication digital-to-analog converter 1000.

[0110] Please refer to Figure 12 , Figure 12 is a functional block diagram of another embodiment of the multiplication digital-to-analog converter of the present invention. Multiplication digital-to-analog converter 1200 is similar to multiplication digital-to-analog converter 700, except that amplification and level shift circuit 1250 is different from amplification and level shift circuit 750 (and thus capacitance switching amplification circuit 1205 is different from capacitance switching amplification circuit 705). Amplification and level shift circuit 1250 includes switch capacitor circuit 1250p and switch capacitor circuit 1250n. Switch capacitor circuit 1250p is coupled to output node Vp1 and output terminal Vp2, and switch capacitor circuit 1250n is coupled to output node Vn1 and output terminal Vn2.

[0111] Please refer to Figure 13 ,Figure 13 This is a circuit diagram of an embodiment of the switched capacitor circuit 1250p of the present invention. The switched capacitor circuit 1250p includes a capacitor Cs0p, a capacitor Cs2p, switches Ss0p, Ss1p, Ss4p, Ss7p, Ss8p, Ss9p, a selection circuit 1305p, sub-switched capacitor circuits 1310p, 1320p, 1330p, 1340p, and 1350p. The sub-switched capacitor circuits 1310p, 1320p, 1330p, 1340p, and 1350p are substantially the same as the sub-switched capacitor circuit 1110p, and respectively output candidate voltages V1, V2, V3, V4, and V5. The selection circuit 1305p outputs one of the candidate voltages V1, V2, V3, V4, and V5 to the node N4p according to the selection signal SEL.

[0112] Those skilled in the art with ordinary knowledge can understand the operating principle of the switched capacitor circuit 1250p according to Figure 8 and Figure 11 the description, so it will not be elaborated here. Those skilled in the art with ordinary knowledge can understand the internal circuit of the switched capacitor circuit 1250n according to Figure 11 and Figure 13 so it will not be elaborated here. In other words, the multiplying digital-to-analog converter 1200 can operate only according to three clocks (as Figure 4 shown, without the need for the clock CLKe or the estimated phase); or, similar to the multiplying digital-to-analog converter 1000, the multiplying digital-to-analog converter 1200 can even operate only according to two clocks.

[0113] Although the foregoing embodiments take the multiplying digital-to-analog converters of 1.5 bits and 2.5 bits as examples, this is not a limitation to the present invention. Those skilled in the art can appropriately apply the present invention to multiplying digital-to-analog converters with more bits according to the disclosure of the present invention (the number of preset voltages will increase accordingly).

[0114] Please note that in the foregoing figures, the shapes, sizes, and proportions of the components are only schematic, for those skilled in the art with ordinary knowledge to understand the present invention, not to limit the present invention.

[0115] Although the embodiments of the present invention are as described above, these embodiments are not used to limit the present invention. Those skilled in the art with ordinary knowledge can make changes to the technical features of the present invention according to the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by what is defined in the claims of the present invention.

[0116] [Symbol Explanation]

[0117] 110, 340, 740: Operational Amplifier

[0118] 120: Related Voltage Shift Circuit

[0119] C1, C2, C3, C4, C0n, C0p, C1n, C1p, Cs0n, Cs0p, Cs1n, Cs1p, C2p, C3p, Cs2n, Cs2p: Capacitor

[0120] SW1, SW2, SW3, SW4, SW5, S0n, S0p, S1n, S1p, S2n, S2p, S3n, S3p, S4n, S4p, S5n, S5p, Ss0n, Ss0p, Ss1n, Ss1p, Ss2n, Ss2p, Ss3n, Ss3p, Ss4n, Ss4p, Ss5n, Ss5p, Ss6n, Ss6p, S6p, S7p, S8p, S9p, Ss7n, Ss7p, Ss8n, Ss8p, Ss9n, Ss9p: Switch

[0121] Vin, Vsn, Vsp: Input Signal

[0122] Vo: Output Voltage

[0123] Φs: Sampling Phase

[0124] Φe: Estimation Phase

[0125] Φh: Amplification Phase

[0126] CLK1, CLK2, CLKe, CLK3: Clock

[0127] 300, 700, 1000, 1200: MDAC (Multiplication Digital - to - Analog Converter)

[0128] 305, 705, 1005, 1205: Capacitor Switching Amplification Circuit

[0129] 310, 710: ADC (Analog - to - Digital Converter)

[0130] 320, 720, 1105n, 1105p, 1305p: Selection Circuit

[0131] 330n, 330p, 730n, 730p: Sampling and Amplification Circuit

[0132] Φ1, Φ2, Φb: Phase

[0133] 350, 750, 1050, 1250: Amplification and Voltage Shift Circuit

[0134] D1n, D1p, D2n, D2p, D3n, D3p, N1n, N1p, N2n, N2p, N3n, N3p, N4n, N4p, D4p, D5p, N5n, N5p, N6n, N6p: Nodes

[0135] SEL: Selection signal

[0136] Vbias: DC voltage

[0137] Vcm: Common-mode voltage

[0138] Vinn, Vinp: Input terminals

[0139] Vn0, Vp0: Input nodes

[0140] Vn1, Vp1: Output nodes

[0141] Vn2, Vp2: Output terminals

[0142] VR1, VR2, VRR1, VRR2, Vref, VR1_1, VR1_2, VR1_3: Reference voltages Vx, Vy: Preset voltages

[0143] 350n, 350p, 750n, 750p, 1050n, 1050p, 1250n, 1250p: Switched capacitor circuits

[0144] V0n, V0p, V1n, V1p: Cross voltages

[0145] 1110n, 1110p, 1120n, 1120p, 1130n, 1130p, 1310p, 1320p, 1330p, 1340p, 1350p: Sub-switched capacitor circuits

[0146] V1, V2, V3, V4, V5: Candidate voltages

Claims

1. A multiplying digital-to-analog converter having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the multiplying digital-to-analog converter comprises: an analog-to-digital converter coupled to the first input terminal and the second input terminal for generating a selection signal according to a first input signal and a second input signal; a selection circuit coupled to the analog-to-digital converter for selecting a first reference voltage and a second reference voltage from a plurality of preset voltages according to the selection signal; a first sampling and amplifying circuit coupled to the selection circuit and the first input terminal for sampling and amplifying the first input signal according to the first reference voltage; a second sampling and amplifying circuit coupled to the selection circuit and the second input terminal for sampling and amplifying the second input signal according to the second reference voltage; an operational amplifier coupled to the first sampling and amplifying circuit and the second sampling and amplifying circuit and having a first output node and a second output node; and an amplifying and level-shifting circuit coupled to the first output node, the second output node, the first output terminal, the second output terminal, the first input terminal, the second input terminal, and the selection circuit for amplifying the first input signal and the second input signal and for level-shifting the voltages of the first output node and the second output node.

2. The multiplying digital-to-analog converter according to claim 1, wherein, the first sampling and amplifying circuit and the second sampling and amplifying circuit each comprise: a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch coupled between the first end and the first input terminal or the second input terminal; a second switch coupled between the third end and the first input terminal or the second input terminal; a third switch coupled between a third reference voltage and the second end or the fourth end; a fourth switch coupled between the first end and the first output terminal or the second output terminal; a fifth switch coupled between the operational amplifier and the second end or the fourth end; and a sixth switch coupled between the third end and the selection circuit.

3. The multiplying digital-to-analog converter according to claim 2, wherein, the selection circuit further selects a fourth reference voltage and a fifth reference voltage from the preset voltages according to the selection signal, the amplifying and level-shifting circuit includes a first switched-capacitor circuit and a second switched-capacitor circuit, the first switched-capacitor circuit is coupled to the first output node and the first output terminal, the second switched-capacitor circuit is coupled to the second output node and the second output terminal, the first sampling and amplifying circuit amplifies the first input signal according to the first reference voltage, the second sampling and amplifying circuit amplifies the second input signal according to the second reference voltage, the first switched-capacitor circuit level-shifts the voltage of the first output node according to the fifth reference voltage, and the second switched-capacitor circuit level-shifts the voltage of the second output node according to the fourth reference voltage.

4. The multiplying digital-to-analog converter according to claim 2, wherein, The selection circuit further selects a fourth reference voltage and a fifth reference voltage from the preset voltages according to the selection signal. The amplification and level shifting circuit includes a first switched capacitor circuit and a second switched capacitor circuit. Each of the first switched capacitor circuit and the second switched capacitor circuit includes: A third capacitor having a fifth terminal and a sixth terminal; A fourth capacitor having a seventh terminal and an eighth terminal; A seventh switch coupled to the fifth terminal and receiving the first input signal or the second input signal; An eighth switch coupled to the sixth terminal and receiving the first input signal or the second input signal; A ninth switch coupled to the eighth terminal and receiving one of the fourth reference voltage, the fifth reference voltage, and the DC voltage; A tenth switch coupled to the seventh terminal and receiving one of the fourth reference voltage, the fifth reference voltage, and the DC voltage; An eleventh switch coupled between the fifth terminal and the first output terminal or the second output terminal; A twelfth switch coupled to the eighth terminal; and A thirteenth switch coupled between the seventh terminal and the first output node or the second output node.

5. The multiplying digital-to-analog converter according to claim 4, wherein, Each of the first switched capacitor circuit and the second switched capacitor circuit further includes: A fifth capacitor having a ninth terminal and a tenth terminal; A fourteenth switch coupled to the ninth terminal and receiving the first input signal or the second input signal; A fifteenth switch coupled to the tenth terminal and receiving the first input signal or the second input signal; and A sixteenth switch coupled between the sixth terminal and the tenth terminal.

6. The multiplying digital-to-analog converter according to claim 2, wherein, The selection circuit is a first selection circuit. The amplification and level shifting circuit includes a first switched capacitor circuit and a second switched capacitor circuit. Each of the first switched capacitor circuit and the second switched capacitor circuit includes: A third capacitor having a fifth terminal and a sixth terminal; A seventh switch coupled to the sixth terminal and receiving the first input signal or the second input signal; An eighth switch coupled to the fifth terminal and receiving the first input signal or the second input signal; A ninth switch coupled between the sixth terminal and the first output terminal or the second output terminal; A second selection circuit coupled to the fifth terminal; A first sub-switched capacitor circuit coupled to one of the first output node and the second output node and the second selection circuit for generating a first candidate voltage according to a first preset voltage and the DC voltage; A second sub-switched capacitor circuit coupled to one of the first output node and the second output node and the second selection circuit for generating a second candidate voltage according to a second preset voltage and the DC voltage; and A third sub-switched capacitor circuit coupled to one of the first output node and the second output node and the second selection circuit for generating a third candidate voltage according to a third preset voltage and the DC voltage.

7. The multiplying digital-to-analog converter according to claim 6, wherein, The second selection circuit is electrically connected to the fifth terminal, and outputs one of the first candidate voltage, the second candidate voltage, and the third candidate voltage to the fifth terminal according to the selection signal.

8. A capacitive switching amplifier circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the capacitive switching amplifier circuit comprises: A first sampling and amplifying circuit, coupled to the first input terminal, for sampling and amplifying a first input signal; A second sampling and amplifying circuit, coupled to the second input terminal, for sampling and amplifying a second input signal; An operational amplifier, coupled to the first sampling and amplifying circuit and the second sampling and amplifying circuit, and having a first output node and a second output node; A first switched capacitor circuit, coupled to the first output node and the first output terminal, for amplifying the first input signal and the second input signal, and for level-shifting the voltage of the first output node; and A second switched capacitor circuit, coupled to the second output node and the second output terminal, for amplifying the first input signal and the second input signal, and for level-shifting the voltage of the second output node.

9. The capacitive switching amplifier circuit according to claim 8, further comprises: An analog-to-digital converter, coupled to the first input terminal and the second input terminal, for generating a selection signal according to the first input signal and the second input signal; and A selection circuit, coupled to the analog-to-digital converter, for selecting a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage from a plurality of preset voltages according to the selection signal; wherein, the first sampling and amplifying circuit amplifies the first input signal according to the first reference voltage, the second sampling and amplifying circuit amplifies the second input signal according to the second reference voltage, the first switched capacitor circuit level-shifts the voltage of the first output node according to the fourth reference voltage, and the second switched capacitor circuit level-shifts the voltage of the second output node according to the third reference voltage.

10. The capacitive switching amplifier circuit according to claim 9, wherein, each of the first switched capacitor circuit and the second switched capacitor circuit comprises: A first capacitor having a first end and a second end; A second capacitor having a third end and a fourth end; A first switch, coupled to the first end and receiving the first input signal or the second input signal; A second switch, coupled to the second end and receiving the first input signal or the second input signal; A third switch, coupled to the fourth end and receiving one of the third reference voltage, the fourth reference voltage, and a DC voltage; A fourth switch, coupled to the third end and receiving one of the third reference voltage, the fourth reference voltage, and the DC voltage; A fifth switch, coupled between the first end and the first output terminal or the second output terminal; A sixth switch, coupled to the fourth end; and A seventh switch, coupled between the third end and the first output node or the second output node.

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