Text data loss recovery-oriented FPGA Cauchy coding and decoding system and method
By implementing the Cauchy codec system on FPGA hardware, the problems of low computing efficiency, weak recovery ability and high power consumption in text data loss recovery are solved, and efficient and fast text data recovery is achieved.
Patent Information
- Application Number
- CN202510129815.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-05
- Publication Date
- 2025-05-27
AI Technical Summary
The prior art has low computing efficiency, weak recovery ability and high power consumption in text data loss recovery, making it difficult to meet the needs of large-scale and high-precision data recovery.
Design a FPGA Cauchy codec system for text data loss recovery, and use the efficient computing power of Cauchy codec coefficient matrix and FPGA hardware to achieve fast and efficient data recovery.
The implementation of Cauchy codec through FPGA hardware solves the problems of weak recovery ability and high power consumption in traditional methods, and achieves efficient text data recovery, which is highly scalable and does not require GPU or CPU to participate in computing.
Smart Images
Figure CN120049897A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an FPGA Cauchy encoding and decoding system and method for text data loss recovery, belonging to the field of integrated circuit technology. Background Art
[0002] With the continuous development of information technology, especially in the fields of big data, cloud computing, and the Internet of Things, the demand for text data transmission and storage is increasing continuously. With the increase in data volume, how to ensure the integrity and accuracy of data during transmission has become a key problem to be solved urgently. Text data often faces problems such as loss and corruption during transmission, storage, or processing. Especially in a communication environment with limited bandwidth and a high transmission error rate, how to efficiently recover lost data and ensure the accuracy and integrity of data has become an important research topic in technology development.
[0003] Most of the existing data recovery technologies are based on traditional error correction coding methods, such as Hamming codes, Reed-Solomon codes, etc. Although these technologies can correct data errors to a certain extent, they often have defects such as low efficiency and limited recovery ability in scenarios of large-scale data transmission, real-time processing, and high-precision requirements. Especially when facing packet loss, they are difficult to play a role.
[0004] Cauchy encoding and decoding is a type of Forward Error Correction (FEC) technology. FEC enhances the reliability of data by adding extra redundant information to the original data. After encoding the original data, when a certain amount of data is lost, it can use this redundant information to recover the lost original data. FEC is widely used in various network transmission scenarios, especially in environments with high requirements for data integrity and real-time performance, such as satellite communication, wireless networks, streaming media services, distributed storage, etc.
[0005] The Cauchy matrix is a special type of matrix. When inverting the Cauchy matrix, a finite field binary matrix method is used to improve the operation efficiency, directly converting ordinary operations into exclusive OR logic operations, which greatly reduces the operation complexity.
[0006] Most of the existing data recovery systems based on hardware implementation focus on traditional coding methods and still cannot fully meet the requirements of large-scale and high-precision data recovery. Especially in scenarios where text data loss is relatively complex, traditional hardware implementation methods often need to call the CPU or GPU to participate in the operation, facing problems such as weak recovery ability, low computing efficiency, and high power consumption.
[0007] In view of the above problems, the present invention proposes an FPGA Cauchy encoding and decoding system for text data loss recovery, aiming to solve the problems of low computing efficiency, weak recovery ability and high power consumption in the existing technology for text data loss recovery by using the Cauchy coefficient matrix and combining the efficient computing power of FPGA hardware. Summary of the Invention
[0008] In view of the deficiencies of the existing technology, the present invention provides an FPGA Cauchy encoding and decoding system and method for text data loss recovery, which can quickly and efficiently restore the lost text data.
[0009] The technical solution of the present invention is as follows:
[0010] An FPGA Cauchy encoding and decoding method for text data loss recovery includes the following steps:
[0011] (1) Text data conversion;
[0012] When the user inputs text using the input method software, preprocess the text. The preprocessing method is: according to the text information selected by the user to write, use UTF-8 encoding to convert the text into binary data, and divide the data into a 512bit×28-row original data matrix in sequence, and store it on the hard disk in the form of a txt file; for the 512bit×28-row original data matrix, regard every 512bit×2 rows as a data packet, with a total of 14 data packets; if the text data is insufficient, fill 0 after the original data matrix, and if the text data exceeds, the exceeded part is used as the second original data matrix and arranged in sequence.
[0013] (2) FPGA data encoding processing;
[0014] Before calculating the Cauchy encoding coefficient matrix and the original data, write the Cauchy decoding coefficient matrix into the FIFO inside the FPGA first; transfer the text original data read in step (1) to the H2C_FIFO, and at the same time store it in the true dual-port RAM port A in sequence through the counting register as the address of the data, and output the H2C_FIFO to the calculation core of the Cauchy encoding circuit; perform exclusive OR calculation on the 512bit×28-row original data matrix and the 8bit×112-row Cauchy encoding coefficient matrix and perform finite field data processing to obtain 512bit×2-row encoding redundancy; allocate addresses to the 512bit×2-row redundancy obtained by encoding through the counting register, and write it into the true dual-port RAM port B in sequence, and the write address is the end of the original data. At this time, the data in the true dual-port RAM is the original data and the encoding redundancy;
[0015] (3) FPGA text loss determination;
[0016] The raw data without redundancy of 512 bits per line is compressed by combinational logic exclusive OR, and the data is compressed to 16 bits, obtaining the compressed data of the raw data of 16 bits × 28 lines and storing them in the register block in sequence for comparison after the next data loss; the register block includes multiple registers for holding the compressed data;
[0017] After the text is lost, the remaining text is converted into binary raw data through step (1), and the raw data is written into the RAM storing the raw data according to the corresponding address through step (2), but no encoding operation is performed. The raw data of the lost text is compressed by combinational logic exclusive OR and then compared with the register block to determine the specific position of the lost data; the position information is sent to the decoding end circuit for processing; at the decoding end, a digital selector is constructed to exhaustively enumerate the lost packet addresses, and according to the lost packets, the specific addresses corresponding to the lost packet data are exhausted;
[0018] (4) FPGA data decoding processing;
[0019] According to the lost packet position information obtained in step (3), the raw data and encoding redundancy of the lost packet in step (2) are read; the encoding redundancy is inserted into the lost packet position in the lost packet raw data according to the lost packet position information and stored through the true dual-port RAM port A as the new raw data for decoding;
[0020] N Cauchy decoding coefficient matrices of 8 bits × 112 lines are pre-stored, where N represents the number of exhaustive enumerations of data packets when the lost packets are in different positions. According to the lost packet position information, the corresponding Cauchy decoding coefficient matrix is selected and written into the FIFO of the calculation core module in the Cauchy decoding circuit, waiting for the arrival of the new raw data to participate in the decoding calculation to obtain the erasure-corrected data; the erasure-corrected data is sorted and written into the true dual-port RAM storing the raw data in sequence at port B according to the lost packet address and read out in order;
[0021] (5) Text restoration after decoding the data;
[0022] The erasure-corrected raw data obtained in step (4) is converted from binary to text using the UTF-8 encoding scheme, and the lost text in the obtained text has been restored, and the text is saved in the txt format.
[0023] Preferably according to the present invention, in step (2), the detailed steps of data encoding processing are:
[0024] The Cauchy encoding circuit includes a configuration register module, a computing core module, computing groups, computing units, FIFOs, and a true dual-port RAM. There are 8 computing groups in the computing core module, and each computing group contains 8 FIFOs and 8 computing units. The computing core module and the true dual-port RAM are interconnected. The input end of port A of the true dual-port RAM is connected to the original data, the output end of the computing core module is connected to the input end of port B of the true dual-port RAM, and the output of the configuration register module is connected to the computing core module.
[0025] The 8-bit × 112-row Cauchy encoding coefficient matrix is stored in the computer in advance. The computer is connected to the FPGA chip through the PICE physical interface. Before calculating the Cauchy encoding coefficient matrix and the original data, the Cauchy decoding coefficient matrix is written into the FIFO inside the FPGA first. The specific writing process is that the Cauchy encoding coefficient matrix is transmitted to the AXI_LITE protocol interface in the XDMA module (used for data connection at the top layer of the computing circuit) inside the FPGA through the PICE physical interface, and the Cauchy encoding coefficient matrix is written into the Cauchy encoding circuit through the AXI_LITE protocol. Through the configuration register module in the Cauchy encoding circuit, the data is written into the FIFO of the computing core module in the Cauchy encoding circuit, waiting for the arrival of the original data to participate in the encoding calculation.
[0026] The original text data read in step (1) is transmitted to the AXI protocol in the XDMA module through the PICE interface (AXI transmits the original data, and AXI_LITE transmits the coefficient matrix). The original text data is transmitted to the H2C_FIFO through the AXI protocol. At the same time, the counting register is used as the address of the data and is stored in port A of the true dual-port RAM in sequence. The output of the H2C_FIFO is sent to the computing core module of the Cauchy encoding circuit. There are 8 computing groups in the computing core module, and each computing group contains 8 computing units. Each computing unit performs an exclusive OR operation on 64-bit original data and 1-bit Cauchy encoding coefficient matrix. One computing group completes the encoding calculation of 512-bit original data. Through the cyclic shift calculation of 8 computing groups, the 512-bit × 28-row original data matrix is exclusive OR calculated with the 8-bit × 112-row Cauchy encoding coefficient matrix and undergoes finite field data processing to obtain 512-bit × 2-row data, which is denoted as the encoding redundancy.
[0027] The main function of the H2C_FIFO is to adjust the data bit width. The H2C_FIFO inputs 256-bit original data and outputs 512-bit original data. The C2H_FIFO is the same.
[0028] The encoded redundancy of 512 bits × 2 rows is assigned addresses through a counting register and sequentially written into port B of the true dual-port RAM. The write address is at the end of the original data. At this time, the data in the true dual-port RAM is the original data and the encoded redundancy.
[0029] Preferably according to the present invention, in step (3), the detailed steps of text loss determination are as follows:
[0030] The original data without redundancy of 512 bits per row is subjected to combinational logic XOR compression. The method is to XOR the first 256 bits with the last 256 bits, and 256-bit data is obtained after XOR; the data is compressed to 16 bits in this way to obtain the original data compression data of 16 bits × 28 rows and sequentially stored in the register block for comparison after the next data loss.
[0031] One set of original data of 512 bits × 28 rows contains 14 data packets. According to the redundant data calculated in step (2), it corresponds to 1 data packet. Then, the text within the range of 1 data packet of the lost original data can be recovered. If the lost text exceeds 1 data packet, the encoding and decoding circuit can be extended to multiple computing core modules to participate in the operation simultaneously, increasing the encoding redundancy to meet the recovery requirements; when 1 data packet of text is lost, the remaining data is converted into binary original data through step (1), and the data is written into the RAM storing the original data at the corresponding address through step (2), but no encoding operation is performed. The original data with the deleted text is subjected to combinational logic XOR compression and then compared with the register block to determine the specific position of the lost data; the position information is sent to the decoding end circuit for processing; at the decoding end, a digital selector is constructed to exhaustively enumerate the lost packet addresses, and the specific addresses corresponding to the lost packet data are enumerated according to the lost packet.
[0032] Preferably according to the present invention, in step (4), the detailed steps of data decoding processing are as follows:
[0033] The decoding circuit includes a configuration register module, a computing core module, computing groups, computing units, FIFOs, a true dual-port RAM, and a simple dual-port RAM; among them, there are 8 computing groups in the computing core module, and each computing group contains 8 FIFOs and 8 computing units: the output end of port A of the true dual-port RAM is connected to the original data input end of the computing core module, the output end of the computing core module is connected to the input of the simple dual-port RAM, and the output of the simple dual-port RAM is connected to the input of port B of the true dual-port RAM;
[0034] According to the lost packet position information obtained in step (3), the original data and encoded redundancy of the lost packet in step (2) are read; the encoded redundancy is inserted into the lost packet position in the lost packet original data according to the lost packet position information and stored through port A of the true dual-port RAM as the new original data for decoding.
[0035] Pre-store N Cauchy decoding coefficient matrices of 8-bit × 112 rows. N represents the number of cases that the data packets are exhausted when the packet loss occurs at different positions, that is, pre-store the corresponding Cauchy decoding coefficient matrices according to different packet loss positions; in the circuit, the data selector is used to select the corresponding Cauchy decoding coefficient matrix according to the position information of the packet loss, and through the configuration register module in the Cauchy decoding circuit, the selected Cauchy decoding coefficient matrix is written into the FIFO of the calculation core module in the Cauchy decoding circuit, and waits for the arrival of new original data to participate in the decoding calculation;
[0036] Transmit the new original data to the calculation core module of the Cauchy decoding circuit. There are 8 calculation groups in the calculation core module, and each calculation group contains 8 calculation units; each calculation unit performs an exclusive OR operation on 64-bit original data and 1-bit Cauchy decoding coefficient matrix; one calculation group completes the decoding calculation of 512-bit original data; through the cyclic shift calculation of 8 calculation groups, the exclusive OR operation between the 512-bit × 28-row new original data matrix and the 8-bit × 112-row Cauchy decoding coefficient matrix is performed and finite field data processing is carried out to obtain 512-bit × 2-row data. This obtained data is the data of the lost original data and is denoted as erasure correction data;
[0037] Store the erasure correction data in sequence through port A of the simple dual-port RAM, and reverse the address order at port B of the simple dual-port RAM, and read the erasure correction data in sequence;
[0038] For the above erasure correction data, determine the packet loss address according to the packet loss position information and write it into the true dual-port RAM storing the original data through port B of the true dual-port RAM in sequence. At this time, the data in the true dual-port RAM is the original data after erasure correction, and this data is the same as the original data without packet loss. Read the original data in the true dual-port RAM in sequence and write it into the C2H_FIFO. The output of the C2H_FIFO is 256-bit original data, which is transmitted to the XDMA module through the AXI protocol. The XDMA module sends the data to the PICE interface, and the PICE interface is physically connected to the computer.
[0039] Further preferably, in step (4), the calculation method of the Cauchy decoding coefficient matrix: determine the segment of the Cauchy encoding coefficient matrix corresponding to the calculation at the packet loss position during encoding, find the inverse matrix of this segment of the Cauchy encoding coefficient matrix and denote it as matrix A, and perform an exclusive OR operation on matrix A and the Cauchy encoding coefficient matrix to obtain matrix B. Finally, insert matrix A into the corresponding position of matrix B and denote it as matrix C, and this position corresponds to the packet loss position; matrix C is the Cauchy decoding coefficient matrix corresponding to the solved packet loss data.
[0040] According to the preference of the present invention, in step (5), the detailed steps for text recovery after decoding data are:
[0041] Convert the corrected and deleted original data obtained in step (4) from binary to text using the UTF-8 encoding scheme. The lost text in the obtained text has been restored, and the text is saved in the form of a txt file.
[0042] Further preferably, in order to correspond to the calculation results in the finite field of mathematics, in steps (2) and (4) of the present invention, after the exclusive OR calculation of the 512-bit×28-row original data matrix and the 8-bit×112-row Cauchy encoding and decoding coefficient matrix, finite field data processing is performed to obtain 512-bit×2-row data. The finite field data processing in the calculation group circuit is as follows: For the 512-bit data obtained by the calculation group, compress it to 128 bits by exclusive OR according to the dichotomy method and regard it as the compressed data A register; Set the signal as the replacement data B register of 512 bits, divided into groups of 128 bits each. Set the [511:384] of the first group of the initial value of the data matrix to 1, and the rest to 0; When the data A is not 0, the replacement data B circulates forward by 128 bits per cycle; Copy and expand the compressed data A to 4×64 bits, and perform an AND operation with the replacement data in the same cycle, denoted as data C; Perform an AND operation on the output encoded data and the negation of the replacement data to obtain data D; Perform an OR operation on data C and data D to obtain the final calculation result register Y.
[0043] Circuit mathematical expression:
[0044]
[0045] The Cauchy encoding and decoding coefficient matrix is a coefficient matrix constructed based on the finite field GF(2 1 ), where the finite field GF(2 1 ) is converted from the finite field GF(2 8 ).
[0046] An FPGA Cauchy encoding and decoding system for text data loss recovery, including an encoding circuit and a decoding circuit. The encoding circuit includes a configuration register module, a calculation core module, calculation groups, calculation units, a FIFO, and a true dual-port RAM. There are 8 calculation groups in the calculation core module, and each calculation group contains 8 FIFOs and 8 calculation units; The calculation core module and the true dual-port RAM are interconnected. The input end of port A of the true dual-port RAM is connected to the original data, the output end of the calculation core module is connected to the input end of port B of the true dual-port RAM, and the output of the configuration register module is connected to the calculation core module;
[0047] The decoding circuit includes a configuration register module, a computing core module, computing groups, computing units, FIFOs, a true dual-port RAM, and a simple dual-port RAM. The computing core module contains 8 computing groups, and each computing group contains 8 FIFOs and 8 computing units. The output end of port A of the true dual-port RAM is connected to the original data input end of the computing core module. The output end of the computing core module is connected to the input of the simple dual-port RAM, and the output of the simple dual-port RAM is connected to the input of port B of the true dual-port RAM.
[0048] A computer-readable storage medium stores a program thereon. When the program is executed by a processor, it implements the steps in a Cauchy encoding and decoding method for FPGA for text data loss recovery as described above.
[0049] An electronic device includes a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in a Cauchy encoding and decoding method for FPGA for text data loss recovery as described above.
[0050] The beneficial effects of the present invention are as follows:
[0051] The present invention provides an FPGA Cauchy encoding and decoding system for text data loss recovery, which uses FPGA hardware circuits to implement the encoding and decoding of text data. This method has strong scalability, and the encoding and decoding calculation process does not require the participation of a GPU or CPU, solving the problems of weak traditional text loss recovery ability, high power consumption, large overhead, and slow calculation speed. Description of the Drawings
[0052] Figure 1 It is a schematic diagram of the Cauchy encoding circuit;
[0053] Figure 2 It is a schematic diagram of the Cauchy decoding circuit;
[0054] Figure 3 It is a data flow diagram of Cauchy encoding and decoding;
[0055] Figure 4 It is a system structure block diagram;
[0056] Figure 5 It is the layout of the system after placement and routing;
[0057] Figure 6 It is the power consumption analysis of the FPGA chip after placement and routing;
[0058] Figure 7 It is a diagram of the FPGA test results. Detailed Embodiments
[0059] The present invention will be further described below by way of examples in conjunction with the drawings, but is not limited thereto.
[0060] Example 1:
[0061] An FPGA Cauchy encoding and decoding system for text data loss recovery includes the following steps:
[0062] (1) Text data conversion;
[0063] When the user inputs text using an input method software, the text is preprocessed. The preprocessing method is as follows: According to the text information selected by the user for writing, using UTF-8 encoding, the text is converted into binary data, and the data is divided into a 512bit×28 row as the original data matrix in sequence and stored on the hard disk in the form of a txt file; for the original data matrix of 512bit×28 rows, every 512bit×2 rows is regarded as a data packet, with a total of 14 data packets; if the text data is insufficient, 0 is filled after the original data matrix, and if the text data exceeds, the excess part is used as the second data matrix and arranged in sequence.
[0064] (2) FPGA data encoding processing;
[0065] The Cauchy encoding circuit includes a configuration register module, a calculation core module, calculation groups, calculation units, a FIFO, and a true dual-port RAM. There are 8 calculation groups in the calculation core module, and each calculation group contains 8 FIFOs and 8 calculation units; the calculation core module and the true dual-port RAM are interconnected. The input end of port A of the true dual-port RAM is connected to the original data, the output end of the calculation core module is connected to the input end of port B of the true dual-port RAM, and the output of the configuration register module is connected to the calculation core module;
[0066] An 8bit×112 row Cauchy encoding coefficient matrix is pre-stored. The computer memory is connected to the FPGA chip through the PICE physical interface. Before calculating the Cauchy encoding coefficient matrix and the original data, the Cauchy decoding coefficient matrix is first written into the FIFO inside the FPGA. The specific writing process is that the Cauchy encoding coefficient matrix is transmitted to the AXI_LITE protocol interface in the XDMA module (at the top layer of the calculation circuit, used for data connection) inside the FPGA through the PICE physical interface, and the Cauchy encoding coefficient matrix is written into the Cauchy encoding circuit through the AXI_LITE protocol. Through the configuration register module in the Cauchy encoding circuit, the data is written into the FIFO of the calculation core module in the Cauchy encoding circuit and waits for the arrival of the original data to participate in the encoding calculation;
[0067] The original text data read in step (1) is transmitted to the AXI protocol in the XDMA module through the PICE interface (AXI transmits the original data, and AXI_LITE transmits the coefficient matrix). The original text data is transmitted to the H2C_FIFO through the AXI protocol. At the same time, the counting register is used as the address of the data and is sequentially stored in the true dual-port RAM port A. The output of the H2C_FIFO is sent to the calculation core module of the Cauchy encoding circuit. There are 8 calculation groups in the calculation core module, and each calculation group contains 8 calculation units; each calculation unit performs an exclusive OR operation on 64-bit original data and 1-bit Cauchy encoding coefficient matrix. One calculation group completes the encoding calculation of 512-bit original data; through the cyclic shift calculation of 8 calculation groups, the exclusive OR calculation of the 512-bit×28-row original data matrix and the 8-bit×112-row Cauchy encoding coefficient matrix is performed, and after finite field data processing, 512-bit×2-row data is obtained, which is denoted as the encoding redundancy.
[0068] The main function of the H2C_FIFO is to adjust the data bit width. The H2C_FIFO is used to input 256-bit original data and output 512-bit original data; the C2H_FIFO is the same.
[0069] The 512-bit×2-row redundancy obtained by encoding is assigned an address through the counting register and sequentially written into the true dual-port RAM port B. The write address is the end of the original data. At this time, the data in the true dual-port RAM is the original data and the encoding redundancy.
[0070] (3) FPGA text loss determination;
[0071] The original data without redundancy of 512 bits per row is compressed by combinational logic exclusive OR. The method is to perform an exclusive OR operation on the first 256 bits and the last 256 bits. After the exclusive OR operation, 256-bit data is obtained; in this way, the data is compressed to 16 bits, and the 16-bit×28-row original data compression data is sequentially stored in the register block for comparison after the next data loss. The register block includes multiple registers for holding the compressed data; the configuration register module does not participate in the original data.
[0072] The original data of 512 bits × 28 rows at a time contains 14 data packets. The redundant data calculated according to step (2) corresponds to 1 data packet. Then, the text with the lost original data within the range of 1 data packet can be recovered. If the lost text exceeds 1 data packet, the encoding and decoding circuit can be extended to multiple computing core modules to participate in the operation simultaneously, increasing the encoding redundancy to meet the recovery requirements. When 1 data packet of text is lost, the remaining data is converted into binary original data through step (1), and the data is written into the RAM storing the original data at the corresponding address through step (2), but no encoding operation is performed. The original data of the deleted text is combined and logically XOR-compressed and compared with the register block to determine the specific position of the lost data. The position information is sent to the decoding end circuit for processing. At the decoding end, a digital selector is constructed to exhaustively list the lost packet addresses, and the specific addresses corresponding to the lost packet data are exhausted according to the lost packets.
[0073] (4) FPGA data decoding and processing;
[0074] The decoding circuit includes a configuration register module, a computing core module, computing groups, computing units, FIFOs, a true dual-port RAM, and a simple dual-port RAM. There are 8 computing groups in the computing core module, and each computing group contains 8 FIFOs and 8 computing units. The output end of port A of the true dual-port RAM is connected to the original data input end of the computing core module, the output end of the computing core module is connected to the input of the simple dual-port RAM, and the output of the simple dual-port RAM is connected to the input of port B of the true dual-port RAM.
[0075] According to the lost packet position information obtained in step (3), read the original data and encoding redundancy of the lost packet in step (2). Insert the encoding redundancy into the lost packet position in the lost packet original data according to the lost packet position information and store it through port A of the true dual-port RAM as the new original data for decoding.
[0076] Pre-store N Cauchy decoding coefficient matrices of 8 bits × 112 rows, where N represents the number of exhaustive data packets when the lost packets are in different positions, that is, pre-store the corresponding Cauchy decoding coefficient matrices according to different lost packet positions. In the circuit, the corresponding Cauchy decoding coefficient matrix is selected by the data selector according to the lost packet position information, and the selected Cauchy decoding coefficient matrix is written into the FIFO of the computing core module in the Cauchy decoding circuit through the configuration register module in the Cauchy decoding circuit, and waits to participate in the decoding calculation after the arrival of the new original data.
[0077] Transfer the new original data to the computing core module of the Cauchy decoding circuit. There are 8 computing groups in the computing core module, and each computing group contains 8 computing units; each computing unit performs an exclusive OR operation on 64-bit original data and 1-bit Cauchy decoding coefficient matrix; one computing group completes the decoding calculation of 512-bit original data; through the cyclic shift calculation of 8 computing groups, the exclusive OR operation between the 512-bit×28-row new original data matrix and the 8-bit×112-row Cauchy decoding coefficient matrix is performed and finite field data processing is done to obtain 512-bit×2-row data. This obtained data is the data where the original data is lost and is denoted as erasure data.
[0078] Store the erasure data sequentially through port A of the simple dual-port RAM, and reverse the address order at port B of the simple dual-port RAM to read the erasure data sequentially.
[0079] For the above erasure data, determine the lost packet address according to the lost packet position information and write it sequentially through port B of the true dual-port RAM into the true dual-port RAM that stores the original data. At this time, the data in the true dual-port RAM is the original data after erasure correction, and this data is the same as the original data when there is no packet loss. Sequentially read the original data in the true dual-port RAM and write it into the C2H_FIFO. The output of the C2H_FIFO is 256-bit original data, which is transmitted to the XDMA module through the AXI protocol. The XDMA module sends the data to the PICE interface, and the PICE interface is physically connected to the computer.
[0080] In step (4), the calculation method of the Cauchy decoding coefficient matrix: Determine the segment of the Cauchy encoding coefficient matrix corresponding to the calculation at the lost packet position during encoding. Find the inverse matrix of this segment of the Cauchy encoding coefficient matrix and denote it as matrix A. Perform an exclusive OR operation on matrix A and the Cauchy encoding coefficient matrix to obtain matrix B. Finally, insert matrix A into the corresponding position of matrix B and denote it as matrix C, and this position corresponds to the lost packet position; matrix C is the Cauchy decoding coefficient matrix corresponding to the lost packet data.
[0081] In steps (2) and (4), the finite field data processing in the computing group circuit is as follows: For the 512-bit data obtained by the computing group, compress it to 128 bits by exclusive OR according to the binary method and regard it as the compressed data A register; Set the signal as the replacement data B register of 512 bits, divided into groups of 128 bits each. Set the [511:384] of the first group of the initial value of this data matrix to 1, and the rest to 0; When the data A is not 0, the replacement data B circulates forward by 128 bits per cycle; Copy and expand the compressed data A to 4×64 bits, and perform an AND operation with the replacement data in the same cycle and denote it as data C; Perform an AND operation on the output encoded data and the complement of the replacement data to obtain data D; Perform an OR operation on data C and data D to obtain the final calculation result register Y.
[0082] Circuit mathematical expression:
[0083]
[0084] (5) Text restoration after decoding data;
[0085] The erased original data obtained in step (4) is converted from binary to text using the UTF-8 encoding scheme. The lost text in the obtained text has been restored, and the text is saved in the form of txt.
[0086] Embodiment 2:
[0087] The application scenario of the present invention is that after text generation, text data is continuously lost, and the lost range is within the text volume corresponding to the redundant packets generated by encoding. Through hardware encoding and decoding operations, the lost text is retrieved.
[0088] An FPGA Cauchy encoding and decoding system for text data loss recovery. The core of the present invention lies in the hardware encoding and decoding circuit. The data flow of the encoding and decoding circuit is from Figure 3 It can be seen from Figure 1 As can be seen from the Cauchy encoding circuit schematic diagram, the Cauchy encoding circuit includes a configuration register module, a calculation core module, calculation groups, calculation units, FIFOs, and a true dual-port RAM. There are 8 calculation groups in the calculation core module. Each calculation group has 8 FIFOs and 8 calculation units. Each calculation unit is paired with a FIFO. The FIFO stores single-bit data of 8-bit × N rows of Cauchy encoding coefficients. The register configuration information data_i[7:0] configures relevant registers in the configuration register module. The Cauchy encoding coefficient matrix is output from the configuration register module to the FIFO in the calculation core through data_i[7:0] for caching. The original data din[511:0] of each clock cycle is written into the true dual-port RAM. The original data din[511:0] of each clock cycle is divided into 64-bit portions in sequence through the calculation core module. Each 64-bit data portion is allocated to one calculation unit of 8 calculation groups. The 64-bit original data of the first calculation unit is XORed with the first-bit coefficient of the 8-bit Cauchy encoding coefficient to complete one-eighth of the encoding. The 64-bit original data of the second calculation unit is XORed with the second-bit coefficient of the 8-bit Cauchy encoding coefficient. At the same time, 8 calculation units are cyclically calculated to complete one encoding. By performing cyclic operations, all data can be Cauchy encoded. The calculated encoding redundancy is written to the end of the true dual-port RAM according to the address, and all data in this RAM is output in sequence.
[0089] From Figure 2As can be seen from the schematic diagram of the Cauchy decoding circuit, the Cauchy decoding circuit includes a decoding circuit module, an inverted output RAM, and an original data RAM. The decoding circuit module further includes a configuration register module, a calculation core module, a calculation group, a calculation unit, a FIFO, a true dual-port RAM, and a simple dual-port RAM. First, preselect the Cauchy decoding coefficient matrix corresponding to the stored packet loss information. When data arrives, according to the packet loss information indicated by info[7:0], select the corresponding Cauchy decoding coefficient matrix and store it in the decoding circuit. Write the original data with coding redundancy and packet loss into the original data RAM through din_in[511:0], and write the redundant data into the corresponding packet loss position. Read all the data in this RAM in sequence and write it into the decoding circuit. The working principle of the decoding circuit module is the same as that of the coding loop calculation part. After calculation, obtain the decoding redundancy. Output the redundant data through the inverted RAM in the inverted order of the decoding redundancy, write the decoding redundancy into the original data RAM according to the packet loss position, and finally complete the original data after decoding in sequence to complete the recovery of the packet loss data.
[0090] From Figure 4 it can be seen how the system structure works. First, the text is encoded into binary data. Through the PCIE physical interface, the Cauchy encoding and decoding coefficient matrix enters the AXI_LITE protocol in the XDMA. After passing through the AXI_LITE protocol, the Cauchy encoding and decoding coefficient matrix is stored in the corresponding RAM. During encoding, the original data enters the AXI protocol of the XDMA through the PCIE physical interface. The original data is input into the Cauchy encoding circuit by the H2C_FIFO. At this time, the original data is compressed and the compressed data is stored. Through the calculation of the original data and the Cauchy encoding coefficient matrix in the Cauchy encoding circuit, the encoding redundancy is obtained. The encoding redundancy is written to the end of the original data and stored in the encoding storage RAM. If the text is lost, the packet loss position information is obtained by comparing the stored compressed original data. According to this packet loss information, select the corresponding Cauchy decoding coefficient matrix and perform a decoding operation with the new original data. Invert the operation result and place it at the packet loss position of the original data. And output it to the C2H_FIFO in sequence, and transmit it to the computer through the AXI protocol and the PCIE. Use encoding to convert the data into text characters to complete the retrieval of the text characters.
[0091] The layout and wiring layout of the KU040 chip selected from XILINX company is as Figure 5 shown, and the overall chip power consumption is as Figure 6 shown, about 3.6w. Select a 200Mhz clock as the global clock for this project. Through the test of the project, the generated document is as Figure 7 shown. It can be seen that after the original text is lost and encoded and decoded through this project, the text is successfully retrieved, and the correctness is verified.
[0092] Example 3
[0093] A computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the steps in a Cauchy encoding and decoding method for FPGA for text data loss recovery as described in Embodiment 1 are implemented.
[0094] Embodiment 4
[0095] An electronic device, comprising a memory, a processor, and a program stored on the memory and executable on the processor, and when the processor executes the program, the steps in a Cauchy encoding and decoding method for FPGA for text data loss recovery as described in Embodiment 1 are implemented.
Claims
1. An FPGA Cauchy encoding and decoding method for text data loss recovery, characterized in that: The steps include: (1) Text data conversion; When the user inputs text using the input method software, the text is preprocessed; the preprocessing method is: according to the text information written by the user, the text is converted into binary data using UTF-8 encoding, and the data is divided into 512bit×28 rows in sequence as the original data matrix, and stored on the hard disk in the form of a txt file; the original data matrix of 512bit×28 rows is regarded as a data packet with each 512bit×2 rows, and a total of 14 data packets; if the text data is insufficient, 0 is added after the original data matrix, and if the text data exceeds, the excess part is regarded as the second original data matrix, and is arranged in sequence; (2) FPGA data encoding processing; Pre-store the 8-bit×112-row Cauchy coding coefficient matrix. Before calculating the Cauchy coding coefficient matrix and the original data, first write the Cauchy decoding coefficient matrix into the FIFO inside the FPGA. Transfer the original text data read in step (1) to the H2C_FIFO, and store it in the true dual-port RAM port A in sequence through the counting register as the address of the data. Send the output of H2C_FIFO to the calculation core of the Cauchy coding circuit. XOR the original data matrix of 512-bit×28-row and the Cauchy coding coefficient matrix of 8-bit×112-row and perform finite field data processing to obtain the coding redundancy of 512-bit×2-row. Allocate the address of the coded 512-bit×2-row redundancy through the counting register and write it into the true dual-port RAM port B in sequence. The write address is the tail end of the original data. At this time, the data in the true dual-port RAM is the original data and the coding redundancy. (3) FPGA text loss determination; Perform logical XOR compression on each row of 512-bit original data without redundancy, compress the data to 16 bits, obtain 16-bit×28 rows of original data compression data and store them in the register block in sequence for comparison after the next data loss; After the text is lost, the remaining text is converted into binary original data through step (1), and the original data is written into the RAM storing the original data according to the corresponding address through step (2), but no encoding operation is performed, and the original data of the lost text is subjected to combinational logic XOR compression and compared with the register block to determine the specific location of the lost data; the location information is sent to the decoding end circuit for processing; a digital selector is constructed at the decoding end to exhaustively enumerate the lost packet address, and the specific address corresponding to the lost packet data is exhaustively enumerated according to the lost packet; (4) FPGA data decoding processing; According to the packet loss position information obtained in step (3), read the original data and the coding redundancy of the packet loss in step (2); insert the coding redundancy into the packet loss position in the original data according to the packet loss position information and store it through the true dual-port RAM port A as the new original data used for decoding; Pre-store N 8-bit × 112-row Cauchy decoding coefficient matrices, where N represents the number of data packets exhausted when the packet is lost at different positions. Select the corresponding Cauchy decoding coefficient matrix according to the position information of the packet loss, write it into the FIFO of the calculation core module in the Cauchy decoding circuit, wait for the arrival of new original data, and then participate in the decoding calculation to obtain the erasure correction data; sort the erasure correction data, and write them into the true dual-port RAM storing the original data in sequence at port B according to the packet loss address, and read them out in sequence; (5) Text recovery after decoding data; The original data after erasure obtained in step (4) is converted from binary to text using the UTF-8 encoding scheme. The lost text has been restored in the obtained text, and the text is saved in txt format.
2. The FPGA Cauchy encoding and decoding method for text data loss recovery according to claim 1, characterized in that: In step (2), the detailed steps of data encoding processing are as follows: The Cauchy encoding circuit includes a configuration register module, a computing core module, a computing group, a computing unit, a FIFO and a true dual-port RAM, wherein the computing core module contains 8 computing groups, each computing group contains 8 FIFOs and 8 computing units; The computing core module and the true dual-port RAM are connected to each other, wherein the input end of port A of the true dual-port RAM is connected to the original data, the output end of the computing core module is connected to the input end of port B of the true dual-port RAM, and the output of the configuration register module is connected to the computing core module; The 8-bit×112-row Cauchy coding coefficient matrix is stored in the computer in advance. The computer memory is connected to the FPGA chip through the PICE physical interface. Before the Cauchy coding coefficient matrix and the original data are calculated, the Cauchy decoding coefficient matrix is first written into the FIFO inside the FPGA. The specific writing process is that the Cauchy coding coefficient matrix is transmitted to the AXI_LITE protocol interface in the XDMA module inside the FPGA through the PICE physical interface, and the Cauchy coding coefficient matrix is written into the Cauchy coding circuit through the AXI_LITE protocol. The data is written into the FIFO of the calculation core module in the Cauchy coding circuit through the configuration register module in the Cauchy coding circuit, and the coding calculation is participated in after waiting for the arrival of the original data; The original text data read in step (1) is transmitted to the AXI protocol in the XDMA module through the PICE interface, and the original text data is transmitted to the H2C_FIFO through the AXI protocol, and at the same time, the data address is sequentially stored in the true dual-port RAM port A through the counting register, and the output of the H2C_FIFO is transmitted to the calculation core module of the Cauchy coding circuit, wherein the calculation core module has 8 calculation groups, each of which contains 8 calculation units; each calculation unit is an XOR of 64-bit original data and 1-bit Cauchy coding coefficient matrix, and one calculation group completes the coding calculation of 512-bit original data; through the cyclic shift calculation of the 8 calculation groups, the original data matrix of 512 bits × 28 rows and the Cauchy coding coefficient matrix of 8 bits × 112 rows are XORed and finite field data processing is performed to obtain 512 bits × 2 rows of data, which is recorded as coding redundancy; The 512-bit × 2-row redundancy obtained by encoding is allocated addresses through the counting register and written into port B of the true dual-port RAM in sequence. The write address is the tail end of the original data. At this time, the data in the true dual-port RAM is the original data and the encoded redundancy.
3. The FPGA Cauchy encoding and decoding method for text data loss recovery according to claim 1, characterized in that: In step (3), the detailed steps of text loss determination are as follows: Each row of 512-bit original data without redundancy is subjected to combinational logic XOR compression, in which the first 256 bits are XORed with the last 256 bits, and 256 bits of data are obtained after XOR; in this way, the data is compressed to 16 bits, and 16 bits × 28 rows of original data compression data are obtained and stored in the configuration register module in sequence for comparison after the next data loss; The original data of 512 bits × 28 lines at a time includes 14 data packets; the redundant data calculated in step (2) corresponds to 1 data packet, so the text within the lost original data range of 1 data packet can be recovered. If the lost text exceeds 1 data packet, the encoding and decoding circuit is expanded to multiple computing core modules to participate in the operation at the same time, increasing the coding redundancy and meeting the recovery requirements; when the text of 1 data packet is lost, the remaining data is converted into binary original data through step (1), and the data is written into the RAM storing the original data according to the corresponding address through step (2), but no encoding operation is performed, the original data of the deleted text is combined with logical XOR compression and compared with the register block to determine the specific location of the lost data; the location information is sent to the decoding end circuit for processing; a digital selector is constructed at the decoding end to exhaustively enumerate the lost packet address, and the specific address corresponding to the lost packet data is exhaustively enumerated according to the lost packet.
4. The FPGA Cauchy encoding and decoding method for text data loss recovery according to claim 2, characterized in that: In step (4), the detailed steps of data decoding processing are as follows: The decoding circuit includes a configuration register module, a calculation core module, a calculation group, a calculation unit, a FIFO, a true dual-port RAM and a simple dual-port RAM; The computing core module contains 8 computing groups, each of which contains 8 FIFOs and 8 computing units: the output of the true dual-port RAM port A is connected to the original data input of the computing core module, the output of the computing core module is connected to the input of the simple dual-port RAM, and the output of the simple dual-port RAM is connected to the input of the true dual-port RAM port B; According to the packet loss position information obtained in step (3), read the original data and the coding redundancy of the packet loss in step (2); insert the coding redundancy into the packet loss position in the original data according to the packet loss position information and store it through the true dual-port RAM port A as the new original data used for decoding; Pre-store N 8-bit×112-row Cauchy decoding coefficient matrices, where N represents the number of data packets exhausted when packet loss occurs at different locations, i.e., store the corresponding Cauchy decoding coefficient matrices in advance according to different packet loss locations; The circuit uses a data selector to select the corresponding Cauchy decoding coefficient matrix according to the location information of the packet loss, and writes the selected Cauchy decoding coefficient matrix into the FIFO of the calculation core module in the Cauchy decoding circuit through the configuration register module in the Cauchy decoding circuit, and waits for the arrival of new original data to participate in the decoding calculation; The new original data is transmitted to the calculation core module of the Cauchy decoding circuit. The calculation core module has 8 calculation groups, each of which contains 8 calculation units. Each calculation unit is an XOR of 64-bit original data and 1-bit Cauchy decoding coefficient matrix. One calculation group completes the decoding calculation of 512-bit original data. Through the cyclic shift calculation of the 8 calculation groups, the 512-bit×28-row new original data matrix and the 8-bit×112-row Cauchy decoding coefficient matrix are XORed and finite field data processed to obtain 512-bit×2-row data. The obtained data is the data lost in the original data and is recorded as the erasure correction data. The erasure correction data are sequentially stored through port A of the simple dual-port RAM in sequence, and the address order is reversed at port B of the simple dual-port RAM to read the erasure correction data sequentially; The above-mentioned erasure data is used to determine the packet loss address according to the packet loss position information and is written into the true dual-port RAM storing the original data in sequence through port B of the true dual-port RAM. At this time, the data in the true dual-port RAM is the original data after erasure, which is consistent with the original data when there is no packet loss. The original data in the true dual-port RAM is read in sequence and written into C2H_FIFO. The output of C2H_FIFO is 256-bit original data, which is transmitted to the XDMA module through the AXI protocol. The XDMA module sends the data to the PICE interface, and the PICE interface is physically connected to the computer.
5. The FPGA Cauchy encoding and decoding method for text data loss recovery according to claim 4, characterized in that: In step (4), the calculation method of the Cauchy decoding coefficient matrix is as follows: determine the Cauchy coding coefficient matrix segment corresponding to the packet loss position when participating in the encoding, obtain the inverse matrix of the Cauchy coding coefficient matrix segment and record it as matrix A, and XOR the matrix A with the Cauchy coding coefficient matrix to obtain matrix B, and finally insert the matrix A into the corresponding position of the matrix B and record it as matrix C, which corresponds to the packet loss position; matrix C is the Cauchy decoding coefficient matrix corresponding to the packet loss data.
6. The FPGA Cauchy encoding and decoding method for text data loss recovery according to claim 4, characterized in that: In steps (2) and (4), the finite field data processing in the calculation group circuit is as follows: the 512-bit data obtained by the calculation group is compressed to 128 bits according to the binary XOR method and regarded as the compressed data A register; the signal is set to the 512-bit replacement data B register, which is divided into a group of 128 bits, and the first group [511:384] of the initial value of the data matrix is set to 1, and the remaining positions are set to 0; when data A is not 0, the replacement data B is circulated forward by 128 bits per cycle; the compressed data A is copied and expanded to 4×64 bits, and the replacement data is ANDed in the same cycle as the replacement data and recorded as data C; the output coded data and the replacement data are ANDed to obtain data D; data C and data D are ORed to obtain the final calculation result register Y; Circuit mathematical expression:
7. An FPGA Cauchy encoding and decoding system for text data loss recovery, characterized in that: The invention comprises an encoding circuit and a decoding circuit, wherein the encoding circuit comprises a configuration register module, a computing core module, a computing group, a computing unit, a FIFO and a true dual-port RAM, wherein the computing core module comprises 8 computing groups, and each computing group comprises 8 FIFOs and 8 computing units; The computing core module and the true dual-port RAM are connected to each other, wherein the input end of port A of the true dual-port RAM is connected to the original data, the output end of the computing core module is connected to the input end of port B of the true dual-port RAM, and the output of the configuration register module is connected to the computing core module; The decoding circuit includes a configuration register module, a calculation core module, a calculation group, a calculation unit, a FIFO, a true dual-port RAM and a simple dual-port RAM; The computing core module contains 8 computing groups, each of which contains 8 FIFOs and 8 computing units: the output of the true dual-port RAM port A is connected to the original data input of the computing core module, the output of the computing core module is connected to the input of the simple dual-port RAM, and the output of the simple dual-port RAM is connected to the input of the true dual-port RAM port B.
8. A computer-readable storage medium, characterized in that: A program is stored thereon, and when the program is executed by a processor, the steps in the FPGA Cauchy encoding and decoding method for text data loss recovery as described in any one of claims 1 to 6 are implemented.
9. An electronic device, characterized in that: The invention comprises a memory, a processor and a program stored in the memory and executable on the processor. When the processor executes the program, the steps in the FPGA Cauchy encoding and decoding method for text data loss recovery as claimed in any one of claims 1 to 6 are implemented.