Circuit board and manufacturing method thereof

Abstract

The invention discloses a circuit board and a manufacturing method thereof, and the method comprises the steps: providing a main board which comprises a first base layer, a first line pattern layer and a second line pattern layer, the first line pattern layer is located in a current transmission region, the second line pattern layer is located in an electromagnetic transmission region, then providing an auxiliary board which comprises a second base layer and a third line pattern layer, and finally, carrying out the manufacturing of the circuit board. The main board and the auxiliary board are pre-pressed, so that the third circuit pattern layer is aligned with a part of the second circuit pattern layer to form a laminated structure, and then the main board and the auxiliary board are subjected to thermal compression bonding, so that the second base layer is converted from a glassy state into a molten liquid state, flows towards the direction close to the laminated structure and wraps the laminated structure. The scheme has the advantages that multiple times of electroplating are not needed after the lamination auxiliary board is laminated on the main board, so that the production time is effectively shortened.

Description

Technical Field

[0001] The present invention relates to a circuit board having functions of current transmission and electromagnetic transmission and a manufacturing method thereof. Background Art

[0002] Wireless charging has been booming in the consumer electronics market and is also a mainstream trend for future development, which poses challenges to the delivery cycle and process capabilities of printed circuit boards.

[0003] Currently, the manufacturing method of a circuit board having a Universal Serial Bus (USB) area and a wireless charging area generally includes drilling, electroplating, etching, multiple electroplating, and covering with a protective film (coverlay, abbreviated as CVL).

[0004] However, the current circuit board manufacturing process has the following problems: 1. The wireless charging area needs to undergo multiple electroplating processes to meet the copper thickness (i.e., the thickness of the circuit) requirements, and there is a thickness limit for electroplated copper, resulting in a long and cumbersome manufacturing time. 2. The uniformity of electroplated copper in the wireless charging area is poor, and the distance between circuits is too large. 3. The fluidity of the coverlay (CVL) is limited, and air bubbles will be generated during filling, which may affect the reliability test.

[0005] Therefore, how to solve the above problems has become the focus of concern for relevant personnel in this field. Summary of the Invention

[0006] One aspect of the present invention is to provide a circuit board having functions of current transmission and electromagnetic transmission and a manufacturing method thereof to solve the problems caused by the foregoing prior art.

[0007] According to an embodiment of the present invention, a manufacturing method of a circuit board includes the following steps: providing a main board, the main board including a first base layer, a first circuit pattern layer, and a second circuit pattern layer, the first base layer including an adjacent current transmission area and electromagnetic transmission area, the first circuit pattern layer being located in the current transmission area, and the second circuit pattern layer being located in the electromagnetic transmission area; providing a sub-board, the sub-board including a second base layer and a third circuit pattern layer disposed on the second base layer; performing a pre-pressing process on the main board and the sub-board so that the third circuit pattern layer is aligned with a part of the second circuit pattern layer to form a stacked structure; performing a hot pressing process on the main board and the sub-board so that the second base layer is transformed from a glass state to a molten liquid state and flows towards the stacked structure and wraps the stacked structure.

[0008] According to one or more embodiments of the present invention, the above-mentioned first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, and the third circuit pattern layer includes a plurality of third circuits. Each second circuit includes a trapezoidal bump, and each third circuit includes an arc-shaped groove. During the pre-pressing process of the main board and the sub-board, the arc-shaped grooves of the plurality of third circuits are aligned with the trapezoidal bumps of some of the plurality of second circuits. A part of each trapezoidal bump is located in the corresponding arc-shaped groove, and there is a gap between each trapezoidal bump and the corresponding arc-shaped groove.

[0009] According to one or more embodiments of the present invention, during the hot pressing process of the main board and the sub-board, the arc-shaped groove of each third circuit and the trapezoidal bump of the corresponding second circuit are combined with each other, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

[0010] According to one or more embodiments of the present invention, the arc-shaped groove of each third circuit and the trapezoidal bump of the corresponding second circuit are combined with each other by diffusion welding.

[0011] According to one or more embodiments of the present invention, before the main board and the sub-board are subjected to the pre-pressing process, the following steps are further included: forming a first metal layer on the second circuit pattern layer; and forming a second metal layer on the third circuit pattern layer; during the hot pressing process of the main board and the sub-board, the first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump, and the arc-shaped groove of each third circuit is combined with the trapezoidal bump of the corresponding second circuit through the eutectic metal layer, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

[0012] According to one or more embodiments of the present invention, the manufacturing method of the sub-board includes the following steps: providing a second substrate, the second substrate includes a second base layer and a metal layer, the second base layer includes an upper surface and a lower surface opposite to each other, and the metal layer is disposed on the lower surface; etching the metal layer to form a patterned metal layer on the lower surface of the second base layer; and forming a third electroplated metal layer on the patterned metal layer to form a third circuit pattern layer.

[0013] According to one or more embodiments of the present invention, the above-mentioned first base layer includes a first surface and a second surface opposite to each other. The first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer. The first upper circuit pattern layer and the first lower circuit layer are respectively disposed on the first surface and the second surface and are located within the current transmission region. The second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer. The second upper circuit pattern layer and the second lower circuit layer are respectively disposed on the first surface and the second surface and are located within the electromagnetic transmission region. During the pre-pressing process, the third circuit pattern layer is located opposite to the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer form a stacked structure.

[0014] According to another embodiment of the present invention, a circuit board includes a main board and a sub-board. The main board includes a first base layer, a first circuit pattern layer, and a second circuit pattern layer. The first base layer includes an adjacent current transmission region and electromagnetic transmission region. The first circuit pattern layer is located within the current transmission region, and the second circuit pattern layer is located within the electromagnetic transmission region. The sub-board includes a second base layer and a third circuit pattern layer disposed on the second base layer. The third circuit pattern layer and a part of the second circuit pattern layer form a stacked structure, and the second base layer covers the stacked structure.

[0015] According to one or more embodiments of the present invention, the above-mentioned first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, and the third circuit pattern layer includes a plurality of third circuits. Each second circuit includes a trapezoidal bump, and each third circuit includes an arc-shaped groove.

[0016] According to one or more embodiments of the present invention, the arc-shaped grooves of the above-mentioned plurality of third circuits correspond to the trapezoidal bumps of the plurality of second circuits. A part of each trapezoidal bump is located within the corresponding arc-shaped groove, and there is a gap between each trapezoidal bump and the corresponding arc-shaped groove. A part of the second base layer is located within the gap between the arc-shaped groove and the trapezoidal bump.

[0017] According to one or more embodiments of the present invention, the above-mentioned main board further includes a first metal layer, and the sub-board further includes a second metal layer. The first metal layer is disposed on the second circuit pattern layer, and the second metal layer is disposed on the third circuit pattern layer. The first metal layer and the second metal layer form a eutectic metal layer within the gap between the arc-shaped groove and the trapezoidal bump.

[0018] According to one or more embodiments of the present invention, the above-mentioned first base layer includes a first surface and a second surface opposite to each other. The first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer. The first upper circuit pattern layer and the first lower circuit layer are respectively disposed on the first surface and the second surface and are located within the current transmission region. The second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer. The second upper circuit pattern layer and the second lower circuit layer are respectively disposed on the first surface and the second surface and are located within the electromagnetic transmission region. The third circuit pattern layer corresponds to the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer form a stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings illustrate one or more embodiments of the present disclosure and are used in conjunction with the written description to explain the principles of the present disclosure. In all the drawings, the same reference numerals are used, as far as possible, to refer to similar or identical elements of the embodiments, wherein:

[0020] Figure 1 is a schematic cross-sectional structure diagram of a circuit board according to an embodiment of the present invention.

[0021] Figure 2 is Figure 1 a top view schematic diagram of the electromagnetic transmission region of the circuit board shown.

[0022] Figure 3 is a schematic cross-sectional structure diagram of a circuit board according to another embodiment of the present invention.

[0023] Figures 4A to 4J is Figure 1 a schematic flow chart of a method for manufacturing the circuit board shown.

[0024] Figures 5A to 5F is Figure 3 a schematic flow chart of a method for manufacturing the circuit board shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following will disclose multiple embodiments of the present invention through the drawings. For the sake of clarity, many practical details will be described together in the following narrative. However, those skilled in the art should understand that in some embodiments of the present invention, these practical details are not necessary and thus should not be used to limit the present invention. In addition, for the purpose of simplifying the drawings, some conventional structures and elements in the prior art will be illustrated in a simple schematic manner in the drawings. Additionally, for the convenience of the reader, the dimensions of the elements in the drawings are not drawn to actual scale.

[0026] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic cross-sectional structure diagram of a circuit board according to an embodiment of the present invention. Figure 2 is Figure 1A top view schematic diagram of the electromagnetic transmission area of the circuit board shown.

[0027] As Figure 1 shown, the circuit board 1 of this embodiment includes a main board 11 and a sub-board 12. The main board 11 includes a first base layer 110, a first circuit pattern layer 111, and a second circuit pattern layer 112. The first base layer 110 includes a current transmission area R1 and an electromagnetic transmission area R2 adjacent to each other. The first circuit pattern layer 111 is disposed on the first base layer 110 and is located within the current transmission area R1. The second circuit pattern layer 112 is disposed on the first base layer 110 and is located within the electromagnetic transmission area R2. The sub-board 12 includes a second base layer 120 and a third circuit pattern layer 121 disposed on the second base layer 120. In this embodiment, the third circuit pattern layer 121 and a part of the second circuit pattern layer 112 form a stacked structure L, and the second base layer 120 covers the stacked structure L formed by the third circuit pattern layer 121 and a part of the second circuit pattern layer 112.

[0028] In this embodiment, the first circuit pattern layer 111 includes a plurality of first circuits 1110. The second circuit pattern layer 112 includes a plurality of second circuits 1120, and each second circuit 1120 of the second circuit pattern layer 112 includes a trapezoidal bump C1. The third circuit pattern layer 121 includes a plurality of third circuits 1210, and each third circuit 1210 of the third circuit pattern layer 121 includes an arc-shaped groove C2.

[0029] As described above, the third circuit pattern layer 121 of the sub-board 12 of this embodiment corresponds to the second circuit pattern layer 112 of the main board 11, and a part of the trapezoidal bump C1 of each second circuit 1120 is located within the arc-shaped groove C2 of the corresponding third circuit 1210, and there is a gap G between the arc-shaped groove C2 and the trapezoidal bump C1. In this embodiment, each trapezoidal bump C1 contacts the corresponding arc-shaped groove C2, that is, after each trapezoidal bump C1 extends into the corresponding arc-shaped groove C2, the two end points of the trapezoidal bump C1 will contact the arc-shaped groove C2.

[0030] In this embodiment, the material of the first base layer 110 is, for example, polyimide (PI), but the present invention is not limited thereto. In other embodiments, the material of the first base layer 110 can also be selected from one of polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).

[0031] In this embodiment, the material of the second base layer 120 is, for example, liquid crystal polymer (LCP), but the present invention is not limited thereto.

[0032] The following further describes other detailed structures of the circuit board 1 of this embodiment.

[0033] As Figure 1 shown, the second base layer 120 of the secondary board 12 of this embodiment covers the laminated structure L formed by the third circuit pattern layer 121 and a part of the second circuit pattern layer 112, and a part of the second base layer 120 is located in the gap G between the arc-shaped groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120.

[0034] Specifically, the first base layer 110 of this embodiment includes a first surface 1101 and a second surface 1102 that face each other. The first circuit pattern layer 111 includes a first upper circuit pattern layer 1111 and a first lower circuit pattern layer 1112. The first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 are respectively disposed on the first surface 1101 and the second surface 1102 and are located within the current transmission region R1. The second circuit pattern layer 112 includes a second upper circuit pattern layer 1121 and a second lower circuit pattern layer 1122. The second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122 are respectively disposed on the first surface 1101 and the second surface 1102 and are located within the electromagnetic transmission region R2.

[0035] In this embodiment, the third circuit pattern layer 121 of the secondary board 12 corresponds to the second upper circuit pattern layer 1121 located within the electromagnetic transmission region R2. That is to say, the third circuit pattern layer 121 and the second upper circuit pattern layer 1121 form the above-mentioned laminated structure L. It should be particularly noted that after the third circuit pattern layer 121 and the second upper circuit pattern layer 1121 located within the electromagnetic transmission region R2 form the laminated structure L, the thickness of the laminated structure L is greater than that of the first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 located within the current transmission region R1. In addition, the above-mentioned laminated structure L forms a coil structure as Figure 2 shown.

[0036] As Figure 1 shown, the circuit board 1 of this embodiment further includes a cover film 13. The cover film 13 is attached to the first upper circuit pattern layer 1111 of the first circuit pattern layer 111. Specifically, the cover film 13 of this embodiment includes an insulating layer 131 and an adhesive layer 132. The adhesive layer 132 is located between the insulating layer 131 and the first upper circuit pattern layer 1111. The insulating layer 131 is attached to the first upper circuit pattern layer 1111 through the adhesive layer 132.

[0037] As Figure 1As shown in the figure, each second circuit 1120 of the second circuit pattern layer 112 of this embodiment has a top surface S1, a bottom surface S2, a first inclined surface S3, and a second inclined surface S4. The top surface S1 and the bottom surface S2 of the second circuit 1120 face each other, the first inclined surface S3 and the second inclined surface S4 are connected between the top surface S1 and the bottom surface S2, and the first inclined surface S3 and the second inclined surface S4 are inclined towards each other.

[0038] In this embodiment, the top surface S1, the bottom surface S2, the first inclined surface S3, and the second inclined surface S4 of the second circuit 1120 together form a trapezoidal bump C1. The top surface S1 has a first width W1, the bottom surface S2 has a second width W2, and the second width W2 is greater than the first width W1. It can be seen from this that the lower line width of the second circuit 1120 is greater than the upper line width. Under such a structural design, when the thickness of the second circuit 1120 is 35 μm, the minimum line distance between every two adjacent second circuits 1120 is 65 μm.

[0039] As Figure 1 shown, each third circuit 1210 of the third circuit pattern layer 121 of this embodiment has a bottom surface F1, a first side surface F2, and a second side surface F3. The bottom surface F1 of the third circuit 1210 and the arc-shaped groove C2 face each other, and the first side surface F2 and the second side surface F3 are connected between the bottom surface F1 and the arc-shaped groove C2. In this embodiment, there is a third width W3 between the first side surface F2 and the second side surface F3, and the third width W3 is equal to the second width W2, and the third width W3 is greater than the first width W1.

[0040] It can be seen from this that the line width of the third circuit 1210 is equal to the lower line width of the second circuit 1120, and the line width of the third circuit 1210 is greater than the upper line width of the second circuit 1120. Under such a structural design, when the thickness of the third circuit 1210 is 35 μm, the minimum line distance between every two adjacent third circuits 1210 is 65 μm.

[0041] Please refer to Figure 3 , which is a schematic cross-sectional structure diagram of a circuit board according to another embodiment of the present invention.

[0042] As Figure 3 shown, the circuit board 1a of this embodiment and Figure 1The structure of the circuit board 1 shown is similar, except that in this embodiment, the main board 11a further includes a first metal layer 113, and the sub-board 12a further includes a second metal layer 114. The first metal layer 113 is disposed on the second circuit pattern layer 112, that is, the first metal layer 113 is formed on the outer surface of each second circuit 1120 of the second circuit pattern layer 112. The second metal layer 114 is disposed on the third circuit pattern layer 121, that is, the second metal layer 114 is formed on the outer surface of each third circuit 1210 of the third circuit pattern layer 121. In this embodiment, the first metal layer 113 and the second metal layer 114 form a eutectic metal layer 115 in the gap G between the arc-shaped groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120.

[0043] In this embodiment, the first metal layer 113 is, for example, gold (Au) or silver (Ag), but the present invention is not limited thereto. The second metal layer 114 is, for example, tin (Sn) or nickel-gold, but the present invention is not limited thereto.

[0044] The manufacturing method flow of the circuit board 1 of this embodiment will be further described below.

[0045] Please refer to Figures 4A to 4J which is Figure 1 a schematic diagram of the manufacturing method flow of the circuit board shown.

[0046] As shown in Figures 4A to 4J and please also refer to Figure 1 . The manufacturing method of the circuit board 1 of this embodiment includes the following steps: First, as shown in Figure 4A , provide a first substrate 100, the first substrate 100 includes a first base layer 110, a first metal layer 101, and a second metal layer 102. The first metal layer 101 is disposed on the first surface 1101 of the first base layer 110, and the second metal layer 102 is disposed on the second surface 1102 of the first base layer 110; then, as shown in Figure 4B , form a through hole 103 in the first substrate 100, and the through hole 103 penetrates through the first base layer 110 and the second metal layer 102; then, as shown in Figure 4C , form a first electroplated metal layer 104 on the surface of the first metal layer 101 away from the first base layer 110, and form a second electroplated metal layer 105 on the surface of the second metal layer 102 away from the first base layer 110. The second electroplated metal layer 105 extends into the through hole 103 and contacts the first metal layer 101.

[0047] It should be specifically noted that the first substrate 100 of this embodiment can be a double-sided copper-clad substrate. That is to say, the above-mentioned first metal layer 101 and second metal layer 102 are, for example, copper foil layers. However, the present invention is not limited thereto. In other embodiments, the first substrate 100 can also be a single-sided copper-clad substrate. In addition, the above-mentioned first electroplated metal layer 104 and second electroplated metal layer 105 are, for example, electroplated copper layers, but the present invention is not limited thereto.

[0048] Next, as Figure 4D shown, etch the stacked structure formed by the first metal layer 101 and the first electroplated metal layer 104, and the stacked structure formed by the second metal layer 102 and the second electroplated metal layer 105, so as to form a first upper circuit pattern layer 1111 and a first lower circuit pattern layer 1112 on a part of the first surface 1101 and a part of the second surface 1102 of the first base layer 110 respectively, and form a second upper circuit pattern layer 1121 and a second lower circuit pattern layer 1122 on another part of the first surface 1101 and another part of the second surface 1102 of the first base layer 110 respectively. Next, as Figure 4E shown, bond the cover film 13 to the first upper circuit pattern layer 1111.

[0049] In this embodiment, the first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 constitute the first circuit pattern layer 111, and the second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122 constitute the second circuit pattern layer 112. Since the appearance shape of each first circuit 1110 of the first circuit pattern layer 111 is different from the appearance shape of each second circuit 1120 of the second circuit pattern layer 112, two current transmission regions R1 and electromagnetic transmission regions R2 with different functions are defined on the first base layer 110. For example, the current transmission region R1 is, for example, a region with USB transmission function, and the electromagnetic transmission region R2 is, for example, a region with wireless charging function.

[0050] After Figures 4A to 4E the steps of Figure 1 are completed, the structure of the main board 11 as shown in

[0051] Next, as Figure 4F shown, provide a second substrate 200. The second substrate 200 includes a second base layer 120 and a metal layer 201. The second base layer 120 includes an upper surface 1201 and a lower surface 1202 that are opposite to each other, and the metal layer 201 is disposed on the lower surface 1202 of the second base layer 120. Next, as shown in Figure 4G, etch the metal layer 201 to form a patterned metal layer 202 on the lower surface 1202 of the second base layer 120; then, as shown in Figure 4H, form a third electroplated metal layer 203 on the patterned metal layer 202 to form a third circuit pattern layer 121 with an arc-shaped groove C2.

[0052] It should be particularly noted that, in the manufacturing process steps of Figure 4H , an arc-shaped groove C2 can be formed on the third electroplated metal layer 203 by adjusting the ratio of copper sulfate to sulfuric acid in the copper plating solution, and the depth of this arc-shaped groove C2 can be further controlled. Therefore, after electroplating is completed, each third circuit 1210 of the third circuit pattern layer 121 has an arc-shaped groove C2, that is, the appearance shape of each third circuit 1210 is similar to the structure of an arch-shaped concave block. For example, in this embodiment, the formula of the copper plating solution is copper sulfate (CuSO 4 5H 2 O), sulfuric acid (H 2 SO 4 ), chloride ions (Cl - ), brightener, inhibitor (or carrier), and leveling agent. Before adjusting the formula ratio of the copper plating solution, copper sulfate is 225 - 245 g / L, sulfuric acid is 30 - 50 ml / L, chloride ions are 60 - 80 ppm, brightener is 15 - 25 ml / L, inhibitor is 2 - 4 ml / L, and leveling agent is 15 - 25 ml / L. After adjusting the formula ratio of the copper plating solution, copper sulfate is 150 - 220 g / L, sulfuric acid is 40 - 100 ml / L, chloride ions are 60 - 80 ppm, brightener is 15 - 25 ml / L, inhibitor is 2 - 4 ml / L, and leveling agent is 10 - 20 ml / L.

[0053] After the steps of Figures 4F to 4H are completed, the structure of the sub-board 12 as shown in Figure 1 is formed.

[0054] Next, as shown in Figure 4I , a pre-pressing process is performed on the main board 11 and the sub-board 12, so that the third circuit pattern layer 121 on the sub-board 12 corresponds to a part of the second circuit pattern layer 112 on the main board 11, that is, the third circuit pattern layer 121 corresponds to the second upper circuit pattern layer 1121 and forms a stacked structure L, and a part of the trapezoidal convex block C1 of each second circuit 1120 is located in the arc-shaped groove C2 of the corresponding third circuit 1210, and a gap G is formed between each arc-shaped groove C2 and the corresponding trapezoidal convex block C1.

[0055] Then, as shown in Figure 4JAs shown, a hot pressing process is performed on the main board 11 and the auxiliary board 12, such that the arc-shaped grooves C2 of each third circuit 1210 and the trapezoidal bumps C1 of the corresponding second circuit 1120 are joined to each other by welding. During the hot pressing process, the second base layer 120 is transformed from a glassy state to a molten liquid state and flows towards the direction close to the stacked structure L and wraps the stacked structure L, and the second base layer 120 further flows into the gap G between the arc-shaped groove C2 and the trapezoidal bump C1, thereby forming the structure of the circuit board 1 as shown in Figure 1 shown.

[0056] It should be particularly noted that, in this embodiment, the material of the second base layer 120 is, for example, a thermoplastic dielectric material. Specifically, the second base layer 120 can be selected as a liquid crystal polymer material (LCP). The liquid crystal polymer material has fluidity at high temperatures. During the hot pressing process, the liquid crystal polymer material is transformed from a glassy state to a molten liquid state, thereby coating each third circuit 1210 and the corresponding second circuit 1120, and further filling the gap G between the arc-shaped groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120. In addition, soft magnetic ferrite is added to the liquid crystal polymer material for the effects of shielding external electromagnetic interference and guiding magnetism and reducing resistance.

[0057] It should be particularly noted that, in this embodiment, during the hot pressing process of the main board 11 and the auxiliary board 12, the arc-shaped grooves C2 of each third circuit 1210 and the trapezoidal bumps C1 of the corresponding second circuit 1120 are joined to each other, for example, by diffusion bonding technology (Diffusion Bonding Technology), but the present invention is not limited thereto. In addition, the liquid crystal polymer material fills the gap G between the arc-shaped groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120, which can also increase the bonding force between each third circuit 1210 and the corresponding second circuit 1120.

[0058] It is worth mentioning that, in this embodiment, since the line width of the third circuit 1210 is greater than the upper line width of the second circuit 1120, and each third circuit 1210 of the auxiliary board 12 has an arc-shaped groove C2, therefore, during the pre-pressing process, the top of the trapezoidal bump C1 of each second circuit 1120 will be confined within the corresponding arc-shaped groove C2. Even when the alignment between the second circuit 1120 and the third circuit 1210 is inaccurate, the subsequent hot pressing process can still be carried out and each third circuit 1210 and the corresponding second circuit 1120 can be joined by diffusion bonding, effectively preventing the problem that the main board 11 and the auxiliary board 12 are offset from each other during the hot pressing process.

[0059] It is worth mentioning that after the main board 11 and the sub-board 12 of this embodiment are subjected to the thermal lamination process, when the line thickness in the electromagnetic transmission area R2 (wireless charging area) is 70 μm, the line pitch is about 65 μm. Comparing with the prior art process of performing multiple electroplating on the lines in the wireless charging area, when the line thickness in the wireless charging area is 70 μm, the line pitch is about 135 μm. That is to say, under the same thickness, the line pitch of the embodiment of the present invention is reduced by 50% compared with the prior art process of performing multiple electroplating on the lines. In addition, the line thickness in the wireless charging area of the embodiment of the present invention can be higher than that of the prior art process of performing multiple electroplating on the lines. The higher the thickness, the greater the current. Since the prior art process of performing multiple electroplating on the lines is limited by the thickness and filling property of the dry film, it is impossible to further increase the line thickness.

[0060] Please refer to Figures 5A to 5F , which is Figure 3 a schematic flow chart of the manufacturing method of the circuit board shown.

[0061] As Figures 5A to 5F shown, and please also refer to Figure 3 . The manufacturing method of the circuit board 1a of this embodiment includes the following steps: First, as Figure 5A shown, provide a main board 11a, the main board 11a includes a first base layer 110, a first line pattern layer 111, a second line pattern layer 112 and a cover film 13. The first base layer 110 includes a current transmission area R1 and an electromagnetic transmission area R2 adjacent to each other. The first line pattern layer 111 is located in the current transmission area R1, and the second line pattern layer 112 is located in the electromagnetic transmission area R2. The first line pattern layer 111 includes a plurality of first lines 1110, the second line pattern layer 112 includes a plurality of second lines 1120, and each second line 1120 includes a trapezoidal bump C1. The cover film 13 is attached to the first upper line pattern layer 1111 of the first line pattern layer 111.

[0062] Next, as Figure 5B shown, provide a sub-board 12a, the sub-board 12a includes a second base layer 120 and a third line pattern layer 121 disposed on the second base layer 120. The third line pattern layer 121 includes a plurality of third lines 1210, and the first third line 1210 includes an arc-shaped groove C2.

[0063] It should be particularly noted that the detailed manufacturing method of the main board 11a of this embodiment is the same as the Figures 4A to 4F manufacturing method flow steps shown, so it will not be elaborated. The detailed manufacturing method of the sub-board 12a of this embodiment is the same as the Figures 4G to 4I manufacturing method flow steps shown, so it will not be elaborated.

[0064] Next, asFigure 5C As shown, a first metal layer 113 is formed on the second circuit pattern layer 112 of the main board 11a, that is, the first metal layer 113 is formed on the second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122 simultaneously. Then, as Figure 5D shown, a second metal layer 114 is formed on the third circuit pattern layer 121 of the auxiliary board 12a.

[0065] Then, as Figure 5E shown, a pre-pressing process is performed on the main board 11a and the auxiliary board 12a, so that the third circuit pattern layer 121 on the auxiliary board 12a corresponds to a part of the second circuit pattern layer 112 on the main board 11a, that is, the third circuit pattern layer 121 corresponds to the second upper circuit pattern layer 1121 and forms a stacked structure L, and the trapezoidal bump C1 of each second circuit 1120 is positioned within the arc-shaped groove C2 of the corresponding third circuit 1210, and a gap G is formed between each arc-shaped groove C2 and the corresponding trapezoidal bump C1.

[0066] Then, as Figure 5F shown, a hot pressing process is performed on the main board 11a and the auxiliary board 12a, so that the first metal layer 113 and the second metal layer 114 form a eutectic metal layer 115 within the gap G between the arc-shaped groove C2 and the trapezoidal bump C1. Each arc-shaped groove C2 of each third circuit 1210 is combined with the trapezoidal bump C1 of the corresponding second circuit 1120 through the eutectic metal layer 115. And during the hot pressing process, the second base layer 120 is transformed from a glassy state to a molten liquid state and flows towards the direction close to the stacked structure L and wraps the stacked structure L, and the second base layer 120 further flows into the gap G between the arc-shaped groove C2 and the trapezoidal bump C1, thereby forming the structure of the circuit board 1a as Figure 3 shown.

[0067] It should be particularly noted that in this embodiment, since a plurality of fine pores will still be generated when the first metal layer 113 and the second metal layer 114 form the eutectic metal layer 115 within the gap G between the arc-shaped groove R2 and the trapezoidal bump C1, therefore, when the second base layer 120 is transformed from a glassy state to a molten liquid state and flows into the gap G between the arc-shaped groove R2 and the trapezoidal bump C1, the liquid second base layer 120 will fill these fine pores, avoiding the formation of air bubbles within the gap G.

[0068] In summary, the present invention provides a method for manufacturing a circuit board with USB transmission function and wireless charging function, that is, providing a main board and a sub-board with liquid crystal polymer material (LCP) attached, and through a thermal lamination process, laminating the sub-board onto the electromagnetic transmission area of the main board (i.e., the area with wireless charging function) to realize the manufacturing of the circuit board, thereby replacing the process of multiple electroplating to increase copper on the main board in the prior art. The advantage of the circuit board manufacturing method described in the embodiments of the present invention is that after laminating the sub-board onto the main board, multiple electroplating is not required, effectively shortening the production time, and the lines after etching the sub-board have better uniformity and smaller line spacing compared to the lines manufactured by the prior art electroplating main board copper increasing process. The liquid crystal polymer material (LCP) will flow at high temperatures, can fill voids and reduce bubbles, and soft magnetic ferrite is added to the liquid crystal polymer material (LCP) to play a role in magnetic shielding and magnetic conduction and resistance reduction.

[0069] The selected and described embodiments are used to explain the content of this disclosure and their practical applications, thereby inspiring other technicians in the field to utilize this disclosure and various embodiments, and making various modifications to meet the expected specific uses. Without departing from the spirit and scope of this disclosure, alternative embodiments will be obvious to those skilled in the art. Therefore, the scope of this disclosure is defined by the appended claims rather than being limited by the foregoing specification and the exemplary embodiments described therein.

[0070]

Symbol Explanation

[0071] 1, 1a: Circuit board

[0072] 11, 11a: Main board

[0073] 12, 12a: Sub-board

[0074] 13: Cover film

[0075] 100: First substrate

[0076] 101: First metal layer

[0077] 102: Second metal layer

[0078] 103: Through hole

[0079] 104: First electroplated metal layer

[0080] 105: Second electroplated metal layer

[0081] 110: First base layer

[0082] 111: First circuit pattern layer

[0083] 112: Second circuit pattern layer

[0084] 113: First metal layer

[0085] 114: Second metal layer

[0086] 115: Eutectic metal layer

[0087] 120: Second base layer

[0088] 121: Third circuit pattern layer

[0089] 131: Insulating layer

[0090] 132: Adhesive layer

[0091] 200: Second substrate

[0092] 201: Metal layer

[0093] 202: Patterned metal layer

[0094] 203: Third electroplated metal layer

[0095] 1101: First surface

[0096] 1102: Second surface

[0097] 1110: First circuit

[0098] 1111: First upper circuit pattern layer

[0099] 1112: First lower circuit pattern layer

[0100] 1120: Second circuit

[0101] 1121: Second upper circuit pattern layer

[0102] 1122: Second lower circuit pattern layer

[0103] 1201: Upper surface

[0104] 1202: Lower surface

[0105] 1210: Third circuit

[0106] C1: Trapezoidal bump

[0107] C2: Arc-shaped groove

[0108] F1: Bottom surface

[0109] F2: First side surface

[0110] F3: Second side surface

[0111] G: Gap

[0112] L: Stacked structure

[0113] R1: Current transmission area

[0114] R2: Electromagnetic transmission area

[0115] S1: Top surface

[0116] S2: Bottom surface

[0117] S3: First inclined surface

[0118] S4: Second inclined surface

[0119] W1: First width

[0120] W2: Second width

[0121] W3: Third width.

Claims

1. A method for manufacturing a circuit board, characterized in that, it comprises the following steps: Providing a main board, the main board includes a first base layer, a first circuit pattern layer and a second circuit pattern layer, the first base layer includes an adjacent current transmission area and an electromagnetic transmission area, the first circuit pattern layer is located in the current transmission area, and the second circuit pattern layer is located in the electromagnetic transmission area; Providing a sub-board, the sub-board includes a second base layer and a third circuit pattern layer disposed on the second base layer; Performing a pre-pressing process on the main board and the sub-board, so that the third circuit pattern layer is aligned with a part of the second circuit pattern layer to form a stacked structure; and Performing a hot pressing process on the main board and the sub-board, so that the second base layer is transformed from a glassy state to a molten liquid state and flows towards the direction close to the stacked structure and wraps the stacked structure.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, the first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, the third circuit pattern layer includes a plurality of third circuits, each of the second circuits includes a trapezoidal bump, each of the third circuits includes an arc-shaped groove, during the pre-pressing process of the main board and the sub-board, the arc-shaped grooves of the plurality of third circuits are aligned with the trapezoidal bumps of a part of the plurality of second circuits, a part of each trapezoidal bump is located in the corresponding arc-shaped groove, and there is a gap between each trapezoidal bump and the corresponding arc-shaped groove.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, during the hot pressing process of the main board and the sub-board, the arc-shaped groove of each third circuit is combined with the trapezoidal bump of the corresponding second circuit, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

4. The method for manufacturing a circuit board according to claim 3, characterized in that, the arc-shaped groove of each third circuit is combined with the trapezoidal bump of the corresponding second circuit in a diffusion welding manner.

5. The method for manufacturing a circuit board according to claim 2, characterized in that, before performing the pre-pressing process on the main board and the sub-board, the following steps are further included: Forming a first metal layer on the second circuit pattern layer; and Forming a second metal layer on the third circuit pattern layer; wherein during the hot pressing process of the main board and the sub-board, the first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump, the arc-shaped groove of each third circuit is combined with the trapezoidal bump of the corresponding second circuit through the eutectic metal layer, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

6. A circuit board, characterized in that, it includes: The main board includes a first base layer, a first circuit pattern layer, and a second circuit pattern layer. The first base layer includes an adjacent current transmission area and an electromagnetic transmission area. The first circuit pattern layer is located in the current transmission area, and the second circuit pattern layer is located in the electromagnetic transmission area; and The sub-board includes a second base layer and a third circuit pattern layer disposed on the second base layer. The third circuit pattern layer and a part of the second circuit pattern layer form a stacked structure, and the second base layer covers the stacked structure.

7. The circuit board according to claim 6, wherein, The first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, the third circuit pattern layer includes a plurality of third circuits. Each of the second circuits includes a trapezoidal bump, and each of the third circuits includes an arc-shaped groove.

8. The circuit board according to claim 7, wherein, The arc-shaped grooves of the plurality of third circuits correspond to the trapezoidal bumps of the plurality of second circuits. A part of each trapezoidal bump is located in the corresponding arc-shaped groove, and there is a gap between each trapezoidal bump and the corresponding arc-shaped groove. A part of the second base layer is located in the gap between the arc-shaped groove and the trapezoidal bump.

9. The circuit board according to claim 8, wherein, The main board further includes a first metal layer, and the sub-board further includes a second metal layer. The first metal layer is disposed on the second circuit pattern layer, the second metal layer is disposed on the third circuit pattern layer, and the first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump.

10. The circuit board according to claim 6, wherein, The first base layer includes a first surface and a second surface opposite to each other. The first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer. The first upper circuit pattern layer and the first lower circuit layer are respectively disposed on the first surface and the second surface and are located in the current transmission area. The second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer. The second upper circuit pattern layer and the second lower circuit layer are respectively disposed on the first surface and the second surface and are located in the electromagnetic transmission area. The third circuit pattern layer corresponds to the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer form the stacked structure.

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