Barrier layer for word line contacts in three-dimensional NAND memories and methods of making same

Abstract

The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a step structure and a partition wall in the alternating dielectric stack. The stepped structure and the partition wall extend in a second direction parallel to the substrate, and the partition wall is adjacent to the stepped structure. The method further includes sequentially forming a first barrier layer and a second barrier layer different from the first barrier layer on the stepped structure. The method further includes forming a gate line slit (GLS) opening in the partition wall. The GLS opening penetrates the alternating dielectric stack in a first direction and is away from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

Description

[0001] This application is a divisional application for a patent with an application date of December 22, 2021, application number 202180005399.0, and invention name “Blocking layer for word line contacts in three-dimensional NAND memory and its manufacturing method”. Technical Field

[0002] The present disclosure relates generally to the field of semiconductor technology, and more particularly to a structure and a manufacturing method for forming a barrier layer to provide an etch stop for a word line contact in a three-dimensional NAND flash memory. Background Art

[0003] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

[0004] In 3D NAND flash memory, multiple layers of memory cells can be stacked vertically so that the storage density per unit area can be greatly increased. The vertically stacked memory cells can be addressed by word lines and bit lines, where each word line can control a memory cell on one layer. In order to form an electrical connection to the vertically stacked word lines, a staircase structure can be used to form a contact structure for each word line.

[0005] In order to further increase the storage density of 3D NAND flash memory, the number of vertically stacked word lines has been significantly increased. Therefore, the contact structure for the word line has a wide range of depths, wherein the shortest contact structure is used for the topmost word line and the longest contact structure is used for the bottommost word line. In order to simultaneously form the contact structure for the word line, an etch stop layer (e.g., silicon nitride) may be provided on the stepped structure to avoid over-etching on the upper word line. However, during various processes before manufacturing the contact structure, the etch stop layer may be lost. In addition, the etch stop layer may introduce other problems. For example, a thick etch stop layer may cause seams at the tungsten refill during word line formation. Therefore, it is necessary to provide an improved method for forming a 3D NAND flash memory. Summary of the invention

[0006] The present disclosure describes embodiments of improved structures and fabrication methods for forming a barrier layer to provide an etch stop for wordline contacts in a three-dimensional (3D) memory device.

[0007] One aspect of the present disclosure provides a method for forming a three-dimensional memory device. The method includes arranging an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a step structure and a partition wall in the alternating dielectric stack. The step structure and the partition wall extend in a second direction parallel to the substrate, and the partition wall is adjacent to the step structure. The method also includes sequentially forming a first barrier layer and a second barrier layer different from the first barrier layer on the step structure. The method also includes forming a gate line gap (GLS) opening in the partition wall. The GLS opening penetrates the alternating dielectric stack in the first direction and is away from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0008] In some embodiments, forming a first barrier layer on the stepped structure further comprises: disposing the first barrier layer to at least cover sidewalls of the step steps of the stepped structure.

[0009] In some embodiments, forming the second barrier layer on the step structure includes: disposing a dielectric material on the step structure and the partition wall; and removing a first portion of the dielectric material disposed on the partition wall.

[0010] In some embodiments, the method also includes: removing a second portion of the dielectric material disposed in a second region of the stepped structure adjacent to the partition wall to form a second barrier layer in a first region of the stepped structure, wherein the first region and the second region extend in a second direction and the first region is at the center of the stepped structure.

[0011] In some embodiments, the method further includes: providing a block mask to expose the partition wall and a second region of the step structure adjacent to the partition wall.

[0012] In some embodiments, the method further includes: disposing a GLS filler inside the GLS opening to form the GLS, wherein the GLS filler includes an insulating material.

[0013] In some embodiments, the method further comprises: removing the second dielectric layer from between the first dielectric layers through the GLS opening to form a lateral tunnel; and disposing a first conductive material inside the lateral tunnel to form a film stack comprising alternatingly stacked conductive layers and first dielectric layers.

[0014] In some embodiments, removing the second dielectric layer includes etching the second dielectric layer selectively relative to the first dielectric layer and the first barrier layer.

[0015] In some embodiments, the method further includes: disposing an insulating layer on the second barrier layer above the stepped structure.

[0016] In some embodiments, the method also includes: forming a contact structure to contact one of the conductive layers in the film stack, which includes: forming a contact opening that penetrates the insulating layer in a first direction to expose a portion of one of the conductive layers; and disposing a second conductive material inside the contact opening to contact the exposed portion of one of the conductive layers.

[0017] In some embodiments, forming the contact opening includes: etching the insulating layer selectively relative to the second barrier layer; and etching the second barrier layer and the first barrier layer to expose a portion of one of the conductive layers within the contact opening.

[0018] Another aspect of the present disclosure provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes: a step structure, the step structure is arranged in the film stack and extends in a second direction parallel to the substrate; and a partition wall, the partition wall extends in the second direction and is positioned adjacent to the step structure. The 3D memory device also includes a gate line gap (GLS), the GLS is arranged in the partition wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction. The 3D memory device also includes: a first barrier layer, the first barrier layer is arranged on the step structure; and a second barrier layer, the second barrier layer is arranged on the first barrier layer in the first region of the step structure, wherein the second barrier layer different from the first barrier layer is away from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0019] In some embodiments, the first barrier layer covers at least sidewalls of the step steps of the step structure.

[0020] In some embodiments, the 3D memory device further includes an insulating layer disposed on the second barrier layer to cover a top surface and sidewalls of the second barrier layer.

[0021] In some embodiments, the 3D memory device further includes a contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure contacts one of the conductive layers of the film stack.

[0022] In some embodiments, the first region is at the center of the stepped structure and extends in the second direction.

[0023] In some embodiments, the stepped structure further includes a second region, wherein the second region of the stepped structure extends in the second direction and is located between the partition wall and the first region.

[0024] In some embodiments, the first barrier layer includes silicon oxide and the second barrier layer includes silicon nitride.

[0025] In some embodiments, the first barrier layer comprises a thickness in a range between 10 nm and 100 nm.

[0026] In some embodiments, the second barrier layer comprises a thickness in a range between 50 nm and 500 nm.

[0027] In some embodiments, the GLS includes an insulating material and is configured to divide a memory cell into sub-memory cells that independently perform a read or program operation.

[0028] Another aspect of the present disclosure provides a memory storage system, including a three-dimensional memory device and a memory controller. The 3D memory device includes the above features. The memory controller is configured to control the operation of the three-dimensional memory device and is connected to the 3D memory device.

[0029] Another aspect of the present disclosure provides a 3D memory die, comprising a three-dimensional memory device and a peripheral circuit. The 3D memory device comprises the above features. The peripheral circuit is coupled to the 3D memory device and is configured to support the operation of the 3D memory device.

[0030] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0032] Figure 1 A schematic top view of an exemplary three-dimensional (3D) memory device according to some embodiments of the present disclosure is shown.

[0033] Figure 2 A schematic top view of a region of a 3D memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 3 A perspective view of a portion of an exemplary 3D memory array structure is shown according to some embodiments of the present disclosure.

[0035] Figure 4 A process flow for fabricating a 3D memory device according to some embodiments of the present disclosure is shown.

[0036] Figure 5 A cross-sectional view illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure.

[0037] Figure 6 A cross-sectional view illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure.

[0038] Figure 7-9 A cross-sectional view, a top view, and a perspective view respectively illustrate an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure.

[0039] Fig.10 A cross-sectional view illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure.

[0040] Fig.11 A cross-sectional view illustrating an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure.

[0041] Fig.12 A top view of an exemplary structure of a 3D memory device at a specific process step according to some embodiments of the present disclosure is shown.

[0042] Figures 13A-13D A top view and various cross-sectional views are shown of an exemplary structure of a 3D memory device at specific process steps according to some embodiments of the present disclosure.

[0043] Figures 14A-14C Various cross-sectional views of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure are shown.

[0044] Figures 15A-15B Top views and cross-sectional views are shown of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure.

[0045] Figures 16A-16C Various cross-sectional views of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure are shown.

[0046] Figures 17A-17C Various cross-sectional views of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure are shown.

[0047] Figures 18A-18B Top views and cross-sectional views are shown of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure.

[0048] Figures 19A-19BTop views and cross-sectional views are shown of exemplary structures of 3D memory devices at specific process steps according to some embodiments of the present disclosure.

[0049] Figures 20A-20D A top view and various cross-sectional views are shown of an exemplary structure of a 3D memory device at specific process steps according to some embodiments of the present disclosure.

[0050] Figures 21A-21C A cross-sectional view illustrating another exemplary structure of a 3D memory device according to some embodiments of the present disclosure.

[0051] Fig. 22 and Figures 23A-23B A memory system having one or more memory chips according to some embodiments of the present disclosure is shown.

[0052] Fig.24 A schematic diagram of a three-dimensional (3D) memory die is shown according to some embodiments of the present disclosure.

[0053] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements throughout. In the accompanying drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference numeral.

[0054] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used for various other applications.

[0056] Note that references in this specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it would be within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0057] Although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of the embodiment, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0058] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0059] It should be readily understood that the meaning of "on," "over," and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" means not only being "on" something directly, but also includes the meaning of being "on" something with intervening features or layers therebetween. Furthermore, "on" or "over" means not only being "on" or "over" something, but also includes the meaning of being "on" or "over" something with no intervening features or layers therebetween (i.e., directly on something).

[0060] Additionally, spatially relative terms, such as "below," "beneath," "down," "above," "upper," etc., may be used herein for ease of description to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0061] As used herein, the term "substrate" refers to a material to which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed at the top side of the substrate, unless otherwise specified. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0062] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire underlying structure or superstructure, or can have a range smaller than the range of the underlying structure or superstructure. In addition, the layer can be a region of a uniform or non-uniform continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, one or more layers can be included therein, and / or one or more layers can be provided thereon, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines, and / or vertical interconnect paths (VIA) are formed) and one or more dielectric layers.

[0063] In the present disclosure, for ease of description, "tier" is used to refer to elements having substantially the same height along a vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "tier", a word line and an underlying insulating layer together may be referred to as a "tier", word lines having substantially the same height may be referred to as a "word line tier" or the like, and so on.

[0064] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may result from slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate a value of a given quantity that varies within, for example, 10% to 30% of a value (e.g., ±10%, ±20%, or ±30% of a value).

[0065] In the present disclosure, the term "horizontal / horizontally / lateral / laterally" means nominally parallel to the lateral surface of the substrate, and the term "vertical" or "perpendicularly" means nominally perpendicular to the lateral surface of the substrate. Similarly, the term "parallel" or "perpendicular" also means nominally parallel or perpendicular.

[0066] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate.

[0067] Figure 1 A top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure is shown. The 3D memory device 100 (e.g., a 3D NAND flash memory) can be a memory chip (package), a memory die, or any portion of a memory die, and can include one or more memory planes 101, each of which can include a memory block 103. The same and concurrent operations can occur at each memory plane 101. The size of the memory block 103 can be megabytes (MB), which is the minimum size for performing erase operations. As shown in FIG. Figure 1 As shown in FIG. 1 , an exemplary 3D memory device 100 includes four memory planes 101, and each memory plane 101 includes six memory blocks 103. Each memory block 103 may include memory cells, wherein each memory cell may be addressed by interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The direction in which the bit lines and word lines extend is Figure 1 The memory blocks 103 are marked as “BL” and “WL” in FIG. 1 . And may also be referred to as the WL direction or the BL direction. In the present disclosure, the memory block 103 is also referred to as a “memory array” or “array”. The memory array is the core area in the memory device that performs storage functions.

[0068] The 3D memory device 100 also includes a peripheral region 105, which is an area surrounding the memory plane 101. The peripheral region 105 contains many digital, analog and / or mixed signal circuits (e.g., page buffers, row and column decoders, and sense amplifiers) to support the functions of the memory array. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which is obvious to those skilled in the art.

[0069] Notice, Figure 1The arrangement of the memory planes 101 in the 3D memory device 100 and the arrangement of the memory blocks 103 in each memory plane 101 shown in FIG. 1 are only used as examples, which do not limit the scope of the present disclosure.

[0070] refer to Figure 2 , showing some embodiments according to the present disclosure Figure 1 1. An enlarged top view of a region 108 of a memory block 103 in a 3D memory device 100. The region 108 of the 3D memory device 100 may include a step region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each memory string including stacked memory cells. The step region 210 may include a step structure and an array of contact structures 214 formed on the step structure. In some embodiments, a slit structure (also referred to as a gate line slit) 216 extending across the channel structure region 211 and the step region 210 in the WL direction may divide the memory block into a plurality of memory fingers 218. At least some of the slit structures 216 may be used as a common source contact (e.g., to an array common source) for the array of memory strings 212 in the channel structure region 211. A top select gate cutout 220 may be provided, for example, in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two parts, and thereby the memory finger may be divided into two memory slices 224, wherein the memory cells in the memory slices 224 that share the same word line form a programmable (read / write) memory page. Although the erase operation of the 3D NAND memory may be performed at the memory block level, the read and write operations may be performed at the memory page level. The size of the memory page may be kilobytes (KB). In some embodiments, the region 108 also includes a dummy memory string 222 for process variation control during manufacturing and / or for additional mechanical support.

[0071] Figure 3 A perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure is shown. The memory array structure 300 includes a substrate 330, an insulating film 331 above the substrate 330, a layer of a bottom select gate (BSG) 332 above the insulating film 331, and a layer of a control gate 333 (also called a "word line" (WL)) stacked on top of the BSG 332 to form a film stack 335 of alternating conductive layers and dielectric layers. For clarity, the layers are not shown in FIG. Figure 3 The dielectric layers at the level adjacent to the control gate are not shown.

[0072] The control gates of each level are separated by gap structures 216-1 and 216-2 that pass through the film stack 335. The memory array structure 300 also includes a level of top select gates (TSG) 334 formed above the stack of control gates 333. The stack of TSG 334, control gates 333, and BSG 332 is also referred to as a "gate electrode". The memory array structure 300 also includes memory strings 212 and doped source line regions 344 in portions of the substrate 330 between adjacent BSGs 332. Each memory string 212 includes a channel hole 336 extending through an insulating film 331 and a film stack 335 of alternating conductive layers and dielectric layers. The memory string 212 also includes a memory film 337 disposed on the sidewalls of the channel hole 336, a channel layer 338 disposed on the sidewalls of the memory film 337, and a core filler 339 surrounded by the channel layer 338. The memory cell 340 (e.g., 340-1, 340-2, 340-3) can be formed at the intersection of the control gate 333 (e.g., 333-1, 333-2, 333-3) and the memory string 212. A portion of the channel layer 338 that responds to the corresponding control gate is also referred to as a channel 338 of the memory cell. The memory array structure 300 also includes a bit line (BL) 341, and the BL 314 is connected to the memory string 212, wherein the BL 341 is located above the TSG 334. The memory array structure 300 also includes a metal interconnect line 343 connected to the gate electrode through the contact structure 214. The edge of the film stack 335 is configured in a stepped shape to allow electrical connection to each level of the gate electrode.

[0073] exist Figure 3 , three levels of control gates 333-1, 333-2, and 333-3 are shown along with one level of TSG 334 and one level of BSG 332 for illustrative purposes. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to the control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 300 may also include other structures, such as TSG cuts, common source contacts (i.e., array common sources), and dummy memory strings. For the sake of brevity, these structures are not shown in FIG. Figure 3 Shown in.

[0074] In order to further increase the storage density of 3D NAND memory, the number of vertically stacked word lines 333 has been continuously increased. Therefore, the contact structure 214 for the word line 333 has a wide range of depths, where the shortest one contact structure is used for the uppermost word line and the longest one contact structure is used for the lowermost word line. In order to form the contact structure 214 for all word lines 333 at the same time, an etch stop layer can be provided on the stepped structure to avoid over-etching on the upper word line. However, during various processes before manufacturing the contact structure, the etch stop layer may be lost. For example, as Fig.21A As shown, the etch stop layer (also referred to as the second barrier layer 1166 in the following specific embodiments) used to form the contact structure 214 and the sacrificial layer (also referred to as the second dielectric layer 454 in the following specific embodiments) used to form the word line 333 are generally made of the same material, for example, silicon nitride. During the replacement process for forming the word line 333, the etch stop layer 1166 can be removed through the gate line slit (GLS) opening 1582 at the same time as the sacrificial layer 454. Lateral tunnels 1684 and 2184 can be formed, as shown in FIG. Fig. 21B As shown. Additional conductive layer 2186 may be formed simultaneously with conductive layer 1786, which may be used as word line 333. Therefore, parasitic leakage paths may occur due to additional conductive layer 2186. In addition, thick etch stop layer 1166 may cause seams in additional conductive layer 2186, which may weaken the mechanical strength of the 3D memory structure. Therefore, it is desirable to provide an improved method for forming a 3D NAND memory.

[0075] Figure 4 A method 400 for forming a three-dimensional (3D) memory device according to some embodiments of the present disclosure is shown. It should be understood that the process steps shown in method 400 are not exhaustive, and other steps may also be performed before, after, or between any of the steps shown. In some embodiments, some steps of method 400 may be omitted or may also include other steps that are not described herein for simplicity. In some embodiments, the steps of method 400 may be performed in different orders and / or variations.

[0076] Figure 5-Figure 12 , Figures 13A-13D , Figure 14A-Figure 14C , Figure 15A-15B , Figure 16A-16C , Figure 17A-17C , Figure 18A-18B , Figure 19A-19B , Figures 20A-20D An exemplary structure of a 3D memory device at a specific process step according to method 400 is shown.

[0077] refer to Figure 4In process step S405 , an alternating dielectric stack may be provided on the substrate, wherein the alternating dielectric stack includes a first dielectric layer and a second dielectric layer alternately stacked on the substrate. Figure 5 4 shows a cross-sectional view of an exemplary 3D memory structure 500 according to process step S405 .

[0078] like Figure 5 As shown, the 3D memory structure 500 includes an alternating dielectric stack 450 disposed on a substrate 330 .

[0079] Substrate 330 may provide a platform for forming subsequent structures. In some embodiments, substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material, such as a single crystal, polycrystalline, or crystalline semiconductor. For example, substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 330 may include a semiconductor material layer formed on a processing wafer, such as glass, plastic, or another semiconductor substrate.

[0080] The front surface 330f of the substrate 330 is also referred to herein as the "main surface" or "top surface" of the substrate. Material layers may be disposed on the front surface 330f of the substrate 330. The "topmost" or "upper" layer is the layer that is farthest or farther from the front surface 330f of the substrate. The "bottommost" or "lower" layer is the layer that is closest or closer to the front surface 330f of the substrate.

[0081] The alternating dielectric stack 450 includes dielectric layer pairs alternately stacked along a vertical direction (i.e., z direction or first direction) perpendicular to the front surface 330 f of the substrate 330, wherein each dielectric layer pair includes a first dielectric layer 452 (also referred to as a “dielectric layer”) and a second dielectric layer 454 (also referred to as a “sacrificial layer”) different from the first dielectric layer 452. The alternating dielectric stack 450 extends in a lateral direction (e.g., WL direction or second direction) parallel to the front surface 330 f of the substrate 330.

[0082] In the alternating dielectric stack 450, the first dielectric layers 452 and the second dielectric layers 454 alternate in a vertical direction perpendicular to the substrate 330. That is, each second dielectric layer 454 may be sandwiched between two first dielectric layers 452, and each first dielectric layer 452 may be sandwiched between two second dielectric layers 454 (except for the bottommost and topmost layers).

[0083] The formation of the alternating dielectric stack 450 may include configuring the first dielectric layers 452 to each have the same thickness or to have different thicknesses. An example thickness of the first dielectric layer 452 may be in the range of 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layers 454 may each have the same thickness or to have different thicknesses. An example thickness of the second dielectric layer 454 may be in the range of 10 nm to 500 nm, preferably about 35 nm. It should be understood that Figure 5 The number of dielectric layer pairs in is for illustrative purposes only, and any suitable number of layers may be included in alternating dielectric stack 450 .

[0084] In some embodiments, the first dielectric layer 452 includes any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide with F-, C-, N-, and / or H-bonding. The first dielectric layer 452 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film. In some embodiments, the first dielectric layer 452 may be any combination of the above materials.

[0085] Forming the first dielectric layer 452 on the substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density-plasma CVD (HDP-CVD), sputtering, evaporation, thermal oxidation, nitridation, any other suitable deposition method, and / or combinations thereof.

[0086] In some embodiments, the second dielectric layer 454 includes any suitable material that is different from the first dielectric layer 452 and can be selectively removed relative to the first dielectric layer 452. For example, the second dielectric layer 454 can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, and any combination thereof. In some embodiments, the second dielectric layer 454 also includes an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The second dielectric layer 454 can be provided using similar techniques as the first dielectric layer 452, such as CVD, PVD, ALD, sputtering, evaporation, thermal oxidation or nitridation, or any combination thereof.

[0087] In some embodiments, the first dielectric layer 452 may be silicon oxide, and the second dielectric layer 454 may be silicon nitride.

[0088] In some embodiments, alternating dielectric stack 450 may include layers other than first dielectric layer 452 and second dielectric layer 454 and may be made of different materials and / or have different thicknesses.

[0089] refer to Figure 4 In process step S410 , a first stepped structure may be formed in the alternating dielectric stack. Figure 6 4 shows a cross-sectional view of an exemplary 3D memory structure 600 according to process step S410 .

[0090] like Figure 6 As shown, the 3D memory structure 600 includes a first stepped structure 656 having first stepped rungs 658 formed in the alternating dielectric stack 450. The first stepped rungs 658 or "staircase layers" refer to a stack of layers having the same lateral dimensions in a surface parallel to the substrate surface 330f. Each of the first stepped rungs terminates at a shorter length than the lower first stepped rung, the length having a length of Figure 6 In some embodiments, the first stepped structure 656 has first stepped steps 658 facing the WL direction, wherein each of the first stepped steps 658 includes a lateral dimension "a" along the WL direction. In this example, the first stepped structure 656 extends in the WL direction (or second direction) parallel to the substrate.

[0091] In some embodiments, each of the first stair steps 658 includes a pair of the first dielectric layer 452 and the second dielectric layer 454. In some embodiments, each of the first stair steps 658 may include two or more pairs of the first dielectric layer 452 and the second dielectric layer 454. Figure 6As shown, each of the first step steps 658 includes a pair of first dielectric layer 452 and second dielectric layer 454, wherein first dielectric layer 452 is on top of second dielectric layer 454. Each of the first step steps 658 exposes a portion of first dielectric layer 452.

[0092] The first stepped structure 656 can be formed by applying a repeated etching trimming process to the alternating dielectric stack 450. The etching trimming process includes an etching process and a trimming process. During the etching process, a portion of the first step step 658 having an exposed surface can be removed. The remaining portion of the first step step 658 covered by the upper step step or covered by the patterned mask is not etched. The etching depth is the thickness of the first step step 658. In some embodiments, the thickness of the first step step 658 is the thickness of a pair of first dielectric layers 452 and second dielectric layers 454. The etching process for the first dielectric layer 452 can have a high selectivity relative to the second dielectric layer 454, and / or vice versa. Therefore, the lower dielectric layer pair can be used as an etching stop layer. By switching the etching process for each layer, the first step step 658 can be etched during one etching cycle. As a result, one step step in the first step step 658 can be formed during each etching trimming cycle.

[0093] In some embodiments, the first stair step 658 may be etched using anisotropic etching (e.g., reactive ion etching (RIE) or other dry etching processes). In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, etching of the silicon oxide may include using a fluorine-based gas (e.g., carbon-fluorine (CF 4 ), hexafluoroethane (C 2 F 6 ), CHF 3 or C 3 F 6 In some embodiments, the silicon oxide layer can be removed by a wet chemical agent, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method can be used. In some embodiments, the second dielectric layer 454 is silicon nitride. In this example, the etching of silicon nitride can include using O 2 、N 2 CF 4 NF 3 , Cl 2 , HBr, BCl 3 The methods and etchants used to remove a single layer stack should not be limited by the embodiments of the present disclosure.

[0094] The trimming process includes applying a suitable etching process (e.g., isotropic dry etching or wet etching) on ​​the patterned mask so that the patterned mask can be pulled back laterally. The lateral pullback dimension determines the lateral dimension "a" of each step of the first stepped structure 656. After trimming the patterned mask, a portion of the topmost first step step 658 is exposed, and another portion of the topmost first step step 658 remains covered by the patterned mask. The next cycle of the etch trimming process starts over from the etching process. In some embodiments, the patterned mask trimming process may include dry etching, for example, using O 2 , Ar, N 2 etc. RIE.

[0095] refer to Figure 4 In process step S415 , a second stepped structure may be formed by removing the exposed portion of the first dielectric layer 452 . Figure 7-9 A cross-sectional view, a top view, and a perspective view of an exemplary 3D memory structure 700 according to process step S415 are respectively shown.

[0096] like Figure 7 As shown, the 3D memory structure 700 includes a second staircase structure 760 (also referred to as a staircase structure) having second staircase steps 762 (also referred to as staircase steps) formed in the alternating dielectric stack 450. The 3D memory structure 600 ( Figure 6 4 and 5. The exposed portion of the first dielectric layer 452 in the substrate 400 is formed into a second stepped structure 760. Similar to the first stepped structure 656, the second stepped steps 762 also face the WL direction, wherein the second stepped steps 762 have a lateral dimension "a" in the WL direction. In this example, the second stepped structure 760 extends in the WL direction (or the second direction) parallel to the substrate.

[0097] The first dielectric layer 452 can be etched using anisotropic etching (e.g., reactive ion etching (RIE) or other dry etching processes). In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, the etching of the silicon oxide may include using a fluorine-based gas (e.g., carbon-fluorine (CF 4 ), hexafluoroethane (C 2 F 6 ), CHF 3 or C 3 F 6and / or any other suitable gas). In some embodiments, the silicon oxide layer can be removed by a wet chemical agent, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method can be used. The etching process for the first dielectric layer 452 can have a high selectivity relative to the second dielectric layer 454. Therefore, the second dielectric layer 454 can be used as an etch stop layer.

[0098] In some embodiments, each of the second step steps 762 further includes a pair of first dielectric layer 452 and second dielectric layer 454, wherein second dielectric layer 454 is on top of first dielectric layer 452. Each of the second step steps 762 exposes a portion of second dielectric layer 454. In some embodiments, each of the second step steps 762 may also include two or more pairs of first dielectric layer 452 and second dielectric layer 454.

[0099] Figure 7 Shown along Figure 8 The cross-sectional view of the line CC' in FIG. Figure 8 and Fig. 9 As shown in , the stepped region 210 extends along the WL direction and may include one or more stepped structures in the second stepped structures 760 extending along the WL direction. Each of the second stepped structures 760 includes a second stepped step 762, which is gradually increased or decreased along the WL direction with a lateral dimension "a". As an example, Figure 8 Two second stepped structures 760 are shown, and Fig. 9 More dielectric layer pairs are shown of the first dielectric layer 452 and the second dielectric layer 454. It should be noted that the number of stepped structures and the number of dielectric layer pairs in the 3D memory structure 700 are not limited to the examples herein.

[0100] like Figure 8 and Fig. 9 As shown, the 3D memory structure 700 further includes a plurality of separation regions 863, and the separation regions 863 separate the second stepped structures 760. Figure 6 During the repeated etching trimming process of FIG. 7 , the portion of the alternating dielectric stack 450 in the separation region 863 is not etched, and the portion forms the separation wall 865. The separation region 863 is located adjacent to the second stepped structure 760. Thus, the separation wall 865 formed in the alternating dielectric stack 450 is located adjacent to the second stepped structure 760 and extends in the WL direction like the second stepped structure 760.

[0101] refer to Figure 4In the process step S420 , a first barrier layer may be disposed on the second stepped structure and the partition walls of the alternating dielectric stack. Fig.10 , a cross-sectional view of an exemplary 3D memory structure 1000 according to process step S420 is shown.

[0102] like Fig.10 As shown, the 3D memory structure 1000 includes a 3D memory structure 700 ( Figure 7-Figure 9 The first barrier layer 1064 covers the second stepped structure 760 and the partition walls 865 (such as the first barrier layer 1064) of the alternating dielectric stack 450 on the lateral surface and the vertical sidewall. Figure 8-Figure 9 1064 on the lateral surface and the vertical sidewalls. In some embodiments, the first barrier layer 1064 may be conformal, wherein the thickness of the first barrier layer 1064 on the lateral surface and the vertical sidewalls is approximately the same. The first barrier layer 1064 may include a thickness in a range between 10 nm and 100 nm. The portion of the first barrier layer 1064 formed on the lateral surface of the step structure may be used as an etch stop layer for an etching process in the z direction (first direction) perpendicular to the substrate 330. The portion of the first barrier layer 1064 formed on the sidewall of the step structure 760 may be used as an etch stop layer for an etching process in, for example, the WL direction (or second direction) parallel to the front surface 330 f of the substrate 330.

[0103] In some embodiments, the first barrier layer 1064 may be any suitable insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, a high-k dielectric material (Al 2 O 3 , HfO 2 、 2 O 3 、ZrO 2 ,La 2 O 3 The first barrier layer 1064 may be deposited by any suitable thin film deposition technique (e.g., CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, evaporation, etc.). In some embodiments, the first barrier layer 1064 may be silicon oxide.

[0104] refer to Figure 4 In process step S425 , a second barrier layer different from the first barrier layer may be disposed on the first barrier layer over the second stepped structure of the alternating dielectric stack and the partition wall. Fig.11 A cross-sectional view of an exemplary 3D memory structure 1100 according to process step S425 is shown.

[0105] like Fig.11 As shown, the 3D memory structure 1100 includes a 3D memory structure 1000 ( Fig.10 In some embodiments, the second barrier layer 1166 covers the first barrier layer 1064 on the lateral surfaces. In some embodiments, the second barrier layer 1166 also covers the first barrier layer 1064 on the vertical sidewalls. The second barrier layer 1166 on the lateral surfaces and the vertical sidewalls may have the same or different thicknesses. In some embodiments, the second barrier layer 1166 may be non-conformal, wherein the thickness of the second barrier layer 1166 on the vertical sidewalls is thinner than the thickness on the lateral surfaces. As discussed below, the second barrier layer 1166 may be used as an etch stop layer to form a contact structure on the stair steps. Therefore, a second barrier layer 1166 having a larger thickness on the lateral surfaces of the stair steps is preferred. In some embodiments, the second barrier layer 1166 and the first barrier layer 1064 may cover the alternating dielectric stack 450 ( Figure 8-Figure 9 ) and the lateral surfaces and vertical side walls of the second stepped structure 760 and the partition wall 865.

[0106] In some embodiments, the second barrier layer 1166 may include any suitable dielectric material different from the first barrier layer 1064. The second barrier layer 1166 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, a high-k dielectric material (Al 2 O 3 , HfO 2 、 2 O 3 、ZrO 2 ,La 2 O 3 The second barrier layer 1166 may be deposited by any suitable thin film deposition technique, such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, evaporation, etc. In some embodiments, the second barrier layer 1166 may be silicon nitride; the first barrier layer 1064 may be silicon oxide; the first dielectric layer 452 may be silicon oxide; and the second dielectric layer 454 may be silicon nitride. In this example, when the second dielectric layer 454 is removed, the first barrier layer 1064 and the first dielectric layer 452 may be used as an etch stop layer. Since the first barrier layer 1064 is located between the second dielectric layer 454 and the second barrier layer 1166 on the lateral surface and the vertical sidewall, the first barrier layer 1064 may protect the second barrier layer 1166 from being etched when the second dielectric layer 454 is removed.

[0107] refer to Figure 4 , in process step S430 , a blocking mask may be provided to cover a first region at a center of the second stepped structure. Fig.12 , a top view of an exemplary 3D memory structure 1200 according to process step S430 is shown.

[0108] like Fig.12 As shown, the 3D memory structure 1200 includes a 3D memory structure 1100 ( Fig.11 12. The blocking mask 1270 is configured to expose a portion of the alternating dielectric stack 450 adjacent to the second stepped structure 760. For example, the blocking mask 1270 exposes the partition wall 865 in the partition region 863 adjacent to the second stepped structure 760. In some embodiments, the blocking mask 1270 also exposes a portion of the second stepped structure 760 adjacent to the partition region 863 and the partition wall 865. That is, the blocking mask 1270 covers a first region 1272 at the center of the second stepped structure 760. The first region 1272 extends in the WL direction. The second stepped structure 760 may include a first region 1272 covered by the blocking mask 1270 and a second region 1274 exposed by the blocking mask 1270. In some embodiments, the second region 1274 does not include the second barrier layer 1166. The second region 1274 also extends in the WL direction and is located between the partition wall 865 and the first region 1272. The exposed portion of the second stepped structure 760 in the second region 1274 and the exposed partition wall 865 are also referred to as an exposed structure 1276. A block mask may be used in a subsequent process to remove a portion of the second barrier layer 1166 disposed on the exposed structure 1276.

[0109] The blocking mask 1270 may include any suitable photoresist. In some embodiments, the blocking mask 1270 may also include a hard mask, for example, silicon oxide, silicon nitride, TEOS, amorphous silicon or polycrystalline silicon, spin-on glass, or any combination thereof. In some embodiments, the blocking mask 1270 may also include a carbon-based polymer material, a silicon-containing anti-reflective coating (SiARC), or the like. The blocking mask 1270 may be formed by photolithography, wherein a pattern may be transferred from a mask to the blocking mask 1270. In some embodiments, forming the blocking mask 1270 may also include dry etching (e.g., reactive ion etching), wet etching, or a combination thereof.

[0110] It should be noted that for clarity, Fig.12 The second barrier layer 1166 and the first barrier layer 1064 are omitted in the top view.

[0111] refer to Figure 4 In process step S435, the second blocking layer may be removed from the structure exposed by the blocking mask. Figures 13A-13D4 shows a top view and various cross-sectional views of an exemplary 3D memory structure 1300 according to process step S435 .

[0112] Fig. 13B Shown along Fig.13A 12 is a cross-sectional view of line BB′ in FIG. 12 , where line BB′ is in the second region 1274 of the second stepped structure 760 . Fig. 13C Shown along Fig.13A , which is a cross-sectional view of line CC' in the first region 1272 of the second stepped structure 760. As previously discussed, the blocking mask 1270 covers the first region 1272 of the second stepped structure 760. The blocking mask exposes an exposed structure 1276 including the second region 1274 of the second stepped structure 760 and the partition wall 865 in the partition region 863. Therefore, the second barrier layer 1166 can be removed from, for example, the exposed structure 1276 in the second region 1274 of the second stepped structure 760. Similarly, the second barrier layer 1166 can also be removed from the partition wall 865 in the partition region 863. That is, a first portion of the second barrier layer 1166 (or dielectric material) can be removed from the partition wall 865. And a second portion of the second barrier layer 1166 can be removed from the second region 1274 of the second stepped structure 760. Therefore, the second barrier layer 1166 can be formed in the first region of the stepped structure.

[0113] In some embodiments, the second barrier layer 1166 can be removed selectively relative to the first barrier layer 1064. For example, the second barrier layer 1166 can be etched at a much higher rate than the first barrier layer 1064. The second barrier layer 1166 can be removed by using any suitable etching process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, the second barrier layer 1166 can be etched by RIE.

[0114] Fig.13D Shown along Fig.13A , which is a cross-sectional view of line AA' in FIG. 1 , where line AA' passes through the exposed structure 1276 and the first region 1272 of the second stepped structure 760. Due to the topological structure between the partition wall 865 and the second stepped rung 762, in some embodiments, the second barrier layer 1166 and the first barrier layer 1064 may cover the sidewalls of the partition wall 865. See also Fig. 9 In some embodiments, during process step S435, the second barrier layer 1166 on the sidewalls of the partition wall 865 may also be removed, stopping on the underlying first barrier layer 1064. In this example, the removal of the second barrier layer 1166 from the sidewalls of the partition wall 865 may be performed by an isotropic etching process (e.g., isotropic RIE, wet etching, etc.), wherein the second barrier layer 1166 may be etched laterally in addition to etching in the vertical direction.

[0115] As the storage capacity of the 3D NAND memory increases, the number of the first dielectric layer 452 and the second dielectric layer 454 also increases. As a result, the topology between the partition wall 865 and the second stepped structure 760 also increases. By using the blocking mask 1270, the second blocking layer 1166 can be etched isotropically (i.e., vertically and laterally), which can greatly reduce the etching time and the risk of over-etching on the lateral surface.

[0116] After removing the second barrier layer 1166 from the exposed structure 1276, the barrier mask 1270 may be stripped ( Fig.12 (in Chinese). Figures 13A-13D As shown, after the process step S435 is completed, the second barrier layer 1166 covers the first region 1272 of the second stepped structure 760 , wherein the second barrier layer 1166 may be removed from other regions.

[0117] refer to Figure 4 In the process step S440 , an insulating layer may be disposed on the second stepped structure and the partition walls of the alternating dielectric stack. Figure 14A-Figure 14C The lines AA', BB' and CC' according to the process step S440 are shown respectively (see Fig.13A ) is a cross-sectional view of an exemplary 3D memory structure 1400.

[0118] like Figure 14A-Figure 14C As shown, the 3D memory structure 1400 includes an insulating layer 1480, which is disposed on the second barrier layer 1166 and the first barrier layer 1064 and the partition wall 865 above the second stepped structure 760 of the alternating dielectric stack 450. The insulating layer 1480 covers at least the top surface (the surface away from the substrate 330) and the sidewalls of the second barrier layer 1166. The insulating layer 1480 can protect the second barrier layer 1166 from being etched in a subsequent process when the second dielectric layer 454 is removed.

[0119] The insulating layer 1480 may include any suitable insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on glass, low-k dielectric materials such as carbon-doped oxide (CDO or SiOC or SiOC:H) or fluorine-doped oxide (SiOF), etc. The insulating layer 1480 may be disposed by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the insulating layer 1480 may have a flat top surface above the second stepped structure 760 and the partition wall 865 of the alternating dielectric stack 450. CMP may be used to planarize the insulating layer 1480.

[0120] refer to Figure 4In process step S445, a gate line slit (GLS) opening may be formed in the partition wall, wherein the GLS opening vertically penetrates the alternating dielectric stack. Figure 15A-15B , a top view and a cross-sectional view of an exemplary 3D memory structure 1500 according to process step S445 are shown.

[0121] like Fig.15A As shown in FIG. 1 , the 3D memory structure 1500 includes a GLS opening 1582 extending laterally in the WL direction parallel to the second stepped structure 760 . In some embodiments, the GLS opening 1582 may be formed in the partition wall 865 of the alternating dielectric stack 450 .

[0122] Fig. 15B Shown along Fig.15A 14. The GLS opening 1582 penetrates the insulating layer 1480 and the partition wall 865 of the alternating dielectric stack 450 in the z direction perpendicular to the substrate 330. In some embodiments, the GLS opening 1582 further extends into the substrate 330. The GLS opening 1582 can be formed by a photolithography process and an etching process. The etching process can include any suitable dry etching, wet etching, or a combination thereof.

[0123] As described above, in process step S435, the second barrier layer 1166 may be removed from the exposed structure 1276. Therefore, the GLS opening 1582 is away from (or away from) the second barrier layer 1166 in the BL direction (also referred to as the third direction, which is parallel to the substrate 330 and perpendicular to the WL direction or the second direction), wherein the second barrier layer 1166 is located in the first region 1272 on the second step rung 762. As a result, the second barrier layer 1166 may be covered from the top and the side by the insulating layer 1480 without being exposed by the GLS opening 1582.

[0124] refer to Figure 4 In process step S450 , the second dielectric layer in the alternating dielectric stack (including the partition walls and the second stepped structure) may be removed through the GLS opening. Figure 16A-16C The lines AA', BB' and CC' according to the process step S450 are shown respectively (see Fig.15A ) is a cross-sectional view of an exemplary 3D memory structure 1600.

[0125] like Figure 16A-16CAs shown, the 3D memory structure 1600 includes a lateral tunnel 1684, wherein the second dielectric layer 454 of the alternating dielectric stack 450 can be selectively removed relative to the first dielectric layer 452 and the first barrier layer 1064. The lateral tunnel 1684 can extend in a lateral direction between adjacent first dielectric layers 452. Note that the term "lateral / laterally" as used herein refers to a plane parallel to the top surface 330f of the substrate 330.

[0126] As previously described, the second dielectric layer 454 (see Fig. 15B ) may also be referred to as a sacrificial layer, and the second dielectric layer 454 may be selectively removed from between the first dielectric layers 452. That is, the etching process of the second dielectric layer 454 may stop on the first dielectric layer 452. The second dielectric layer 454 may be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in the dry / wet etching may travel vertically and laterally from the GLS opening 1582. For example, the plasma and / or chemicals may travel from the GLS opening 1582 toward the second stepped structure 760 along the WL direction and / or the BL direction (see also Fig.15A ). In some embodiments, the second dielectric layer 454 may be silicon nitride and the first dielectric layer 452 may be silicon oxide. In this example, CF 4 , CHF 3 , C 4 F 8 , C 4 F 6 and CH 2 F 2 The second dielectric layer 454 is removed by RIE using one or more etchants such as TECHNOLOGY®, TECHNOLOGY®, and the like. In some embodiments, the second dielectric layer 454 may be removed using a wet etch such as phosphoric acid.

[0127] When the etching process for removing the second dielectric layer 454 (e.g., silicon nitride) is selective to the first barrier layer 1064 (e.g., silicon oxide), the first barrier layer 1064 disposed on the second stepped structure 760 may also be used as an etch stop layer in addition to the first dielectric layer 452 (e.g., silicon oxide). For example, when both the second barrier layer 1166 and the second dielectric layer 454 may be removed during process step S450 (i.e., both include silicon nitride), the first barrier layer 1064 covering the top surface (i.e., lateral surface) and vertical surface (i.e., sidewall) of the second step step 762 may protect the second barrier layer 1166 from being etched by the lateral tunnel 1684 (see FIG. 1 ) from below. Fig. 16C) etching. The portion of the first barrier layer 1064 formed on the lateral surface of the step structure may serve as an etching stop layer for an etching process in the z direction perpendicular to the substrate 330. The portion of the first barrier layer 1064 formed on the vertical sidewall of the step structure 760 may serve as an etching stop layer for an etching process in the WL direction and the BL direction parallel to the front surface 330 f of the substrate 330.

[0128] As previously described, by using the blocking mask 1270 in process steps S430 and S435, the second blocking layer 1166 can be removed from the exposed structure 1276 and thereby away from or away from the GLS opening 1582. The second blocking layer 1166 can be covered and protected by the insulating layer 1480 near the partition wall 865. Therefore, the etching chemical that travels through the GLS opening 1582 does not attack the second blocking layer 1166 (see Fig.16A ) and no additional lateral tunnels are formed on top of the first barrier layer 1064.

[0129] refer to Figure 4 In process step S455, a first conductive material may be disposed inside a lateral tunnel passing through the GLS opening to form a conductive layer between the first dielectric layers. Figure 17A-17C The lines AA', BB' and CC' (see FIG. Fig.15A ) is a cross-sectional view of an exemplary 3D memory structure 1700.

[0130] like Figure 17A-17C As shown, the 3D memory structure 1700 includes a conductive layer 1786 disposed in a lateral tunnel 1684 ( Figure 16A-16C ) inside. The conductive layer 1786 can be disposed between adjacent first dielectric layers 452, wherein the conductive layer 1786 and the first dielectric layer 452 can form a film stack 335 of alternating conductive layers and dielectric layers (eg, Figure 3 middle).

[0131] In some embodiments, the conductive layer 1786 may be formed by filling the lateral tunnel with a first conductive material. The first conductive material for the conductive layer 1786 may include a metal or a metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the first conductive material for the conductive layer 1786 may also include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any other suitable material and / or combination thereof. In some embodiments, the polycrystalline material may be combined with any suitable type of dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the first conductive material may also be an amorphous semiconductor such as amorphous silicon. In some embodiments, the first conductive material may be disposed using a suitable deposition method, such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the conductive layer 1786 (or first conductive material) includes tungsten (W) deposited by CVD.

[0132] In some embodiments, the gate dielectric layer 1785 may be disposed in the lateral tunnel 1684 ( Figure 16A-16C In some embodiments, the gate dielectric layer 1785 surrounds the conductive layer 1786. For example, in the z direction, the gate dielectric layer 1785 is disposed between the first dielectric layer 452 and the conductive layer 1786. In the WL direction or the BL direction, the gate dielectric layer 1785 is disposed between the conductive layer 1786 and the first barrier layer 1064. The gate dielectric layer 1785 may include any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 1785 may also include a high-k dielectric material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer 1785 may be deposited by one or more suitable deposition processes (e.g., CVD, PVD, and / or ALD).

[0133] In some embodiments, an etching and cleaning process can be used to remove excess first conductive material on the sidewalls of GLS opening 1582. Thus, each conductive layer 1786 of film stack 335 can be electrically isolated from each other. In some embodiments, excess first conductive material on top of insulating layer 1480 can also be removed, for example, by CMP.

[0134] After completing process step S455, second dielectric layer 454 can be replaced by conductive layer 1786, and alternating dielectric stack 450 becomes alternating conductive and dielectric layer film stack 335. Thus, second stepped structure 760 becomes third stepped structure 1760, and second stepped rung 762 becomes third stepped rung 1762.

[0135] However, if the blocking mask 1270 is not used and the second blocking layer 1166 is not removed near the GLS opening 1582 (see Figure 21A-Figure 21C ), if the second barrier layer 1166 and the second dielectric layer 454 are made of the same material (e.g., silicon nitride), the second barrier layer 1166 can be removed together with the second dielectric layer 454 in process step S450. An additional tunnel 2184 can be formed under the insulating layer 1480. During process step S455, an additional conductive layer 2186 can also be formed under the insulating layer 1480. The additional conductive layer 2186 may cause circuit shorts and / or increase leakage. In addition, in order to completely fill the additional tunnel 2184, the thickness "t" of the additional conductive layer 2186 needs to be at least the thickness of the second barrier layer 1166. However, if the GLS opening 1582 is not wide enough, for example, having a width w<t, the GLS opening 1582 may be filled and tilted before filling the additional tunnel 2184. The resulting seams in the additional conductive layer 2186 may cause structural problems (e.g., reduced mechanical strength, attraction of defects and chemicals, etc.), and thereby reduce product yield. Therefore, the manufacturing process of the 3D NAND flash memory may be improved by removing the second blocking layer 1166 using the blocking mask 1270 .

[0136] refer to Figure 4 In process step S460 , a GLS filler may be disposed inside the GLS opening to form a GLS. Figure 18A-18B , a top view and a cross-sectional view of an exemplary 3D memory structure 1800 according to process step S460 are shown.

[0137] like Fig.18A and Fig.18B As shown (along line AA'), the 3D memory structure 1800 includes a gate line gap (GLS) 216 (similar to Figure 2-Figure 3 The GLS 216 may be formed in the partition wall 865 in the partition region 863. The GLS 216 extends laterally along the WL direction.

[0138] The GLS 216 penetrates the insulating layer 1480 , the first barrier layer 1064 , and the film stack 335 of alternating conductive and dielectric layers in the z-direction. In some embodiments, the GLS 216 may extend further into the substrate 330 .

[0139] The GLS 216 includes a GLS filler 1888 disposed within the GLS opening 1582 ( Fig.17A ). The GLS fill 1888 may include any suitable insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus doped silicon oxide, carbon doped oxide (CDO or SiOC or SiOC:H), or fluorine doped oxide (SiOF), or any combination thereof. The GLS fill 1888 may be deposited using, for example, ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable film deposition technique.

[0140] In some embodiments, the GLS filler 1888 outside the GLS opening 1582 can be removed by etching (eg, RIE) or CMP. In this way, the GLS 216 can be coplanar with the insulating layer 1480.

[0141] As about Figure 2 and Figure 3 As described above, GLS 216 can divide a memory cell (e.g., memory block 103) into sub-memory cells (e.g., memory fingers 218), wherein the sub-memory cells can independently perform read and / or program operations. Therefore, the read and program speed of the 3D NAND memory can be improved.

[0142] refer to Figure 4 In process step S465, a contact opening may be formed to expose a portion of one of the conductive layers of the third stepped structure. Figure 19A-19B , a top view and a cross-sectional view of an exemplary 3D memory structure 1900 according to process step S465 are shown.

[0143] like Fig.19A As shown, the 3D memory structure 1900 includes a contact opening 1990 in the first region 1272 of the third stepped structure 1760. Fig.19B As shown in the cross-sectional view along line CC' in FIG. 1 , the contact opening 1990 penetrates the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z direction and exposes a portion of the conductive layer 1786. In some embodiments, each contact opening 1990 exposes a portion of one of the conductive layers 1786 of the third stepped structure 1760.

[0144] In some embodiments, forming contact opening 1990 includes selectively etching insulating layer 1480 relative to second barrier layer 1166, wherein second barrier layer 1166 may serve as an etch stop. Then, second barrier layer 1166 and first barrier layer 1064 may be etched to expose a portion of conductive layer 1786 within contact opening 1990.

[0145] In some embodiments, a photoresist or a polymer material may be used as a mask layer for etching the contact openings 1990. Due to the topology of the stepped structure, the depth of the contact openings 1990 depends on the location of the steps of the step. The contact openings 1990 for the lower steps may be much deeper than the contact openings 1990 for the upper steps. Therefore, the contact openings 1990 of the third step steps 1762 closer to the substrate 330 require a longer etching time than the contact openings 1990 farther from the substrate 330. A selective etching process may be used so that the etching rate of the insulating layer 1480 is much higher than the second barrier layer 1166. That is, during the etching process for the contact openings 1990, the second barrier layer 1166 may be used as an etching stop layer and may protect the underlying structure until all of the contact openings 1990 are formed on top of the second barrier layer 1166 of the third stepped structure 1760. Next, the portion of the second barrier layer 1166 and the first barrier layer 1064 inside the contact opening 1990 may be removed.

[0146] In some embodiments, when the gate dielectric layer is provided before the conductive layer 1786 is provided, the etching further includes removing the gate dielectric layer inside the contact opening 1990 .

[0147] The etching process for the contact opening 1990 may include dry etching, wet etching, and / or a combination thereof. When the insulating layer 1480 is silicon oxide and the second barrier layer 1166 is silicon nitride, etching the silicon oxide may use a chemical etchant (e.g., CF 4 , CHF 3 , C 2 F 6 , C 3 F 6 and / or any combination thereof), and etching silicon nitride may be performed using anisotropic RIE using chemical etchants (e.g., O 2 、N 2 CF 4 NF 3 , Cl 2 , HBr, BCl 3 The etching processes and chemistries listed here are examples only and should not be so limited.

[0148] Because the second barrier layer 1166 can be used as an etch stop during the etching process for the contact opening 1990, the second barrier layer 1166 can include a thickness sufficient to protect the underlying structure. For example, the second barrier layer 1166 can include a thickness in a range between 10 nm and 500 nm, more specifically in a range between 50 nm and 500 nm. As previously described with respect to Figure 16A-16C , Figure 17A-17C and Figure 21A-21B As described above, by using the blocking mask 1270, the second barrier layer 1166 can be pulled back from the GLS opening 1582. During the removal of the second dielectric layer 454 and the formation of the lateral tunnel 1684, the second barrier layer 1166 can be surrounded by the insulating layer 1480 and the first barrier layer 1064. Thus, the additional tunnel 2184 and the additional conductive layer 2186 can be avoided. Therefore, the thickness of the second barrier layer 1166 can be optimized for the etching process of the contact opening 1990 without being limited by the additional tunnel 2184 and / or the additional conductive layer 2186. That is, the thickness of the second barrier layer 1166 can be increased to provide a sufficient etching stop function when forming the contact opening 1990 on the third stepped structure 1760.

[0149] refer to Figure 4 , in process step S470 , a second conductive material may be disposed inside the contact opening to form a contact structure for the third stepped structure. Fig. 20A 4 shows a top view of an exemplary 3D memory structure 2000 according to process step S470 . Figure 20B-Figure 20D Shown along Fig. 20A 3D memory structure 2000 cross-sectional view along lines CC′, AA′, and BB′.

[0150] like Fig. 20A and Fig. 20B As shown, the 3D memory structure 2000 includes a contact structure 214 in the first region 1272 of the third stepped structure 1760. The contact structure 214 (similar to Figure 2-Figure 3 The contact structure shown in FIG. 1 includes a contact opening 1990 ( Figure 19A-19B The contact structure 214 penetrates the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z direction. The contact structure 214 can contact one of the conductive layers 1786 of the film stack 335 through the third stepped structure 1760. In some embodiments, when the gate dielectric layer 1785 is provided before the conductive layer 1786 is provided, the contact structure 214 also penetrates the gate dielectric layer 1785.

[0151] In some embodiments, the second conductive material 1992 inside the contact opening 1990 can be in direct contact with the conductive layer 1072. The second conductive material 1992 can include any suitable conductive material, such as a metal or a metal compound, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) and / or any combination thereof. The metal or metal compound can be deposited using a suitable deposition method (e.g., CVD, PVD, ALD, sputtering, evaporation, etc.). The second conductive material 1992 can also be a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The metal silicide material can be formed by directly providing a metal layer on the polysilicon layer inside the contact opening 1990, and then applying a thermal annealing process, followed by removing the unreacted metal. In some embodiments, the second conductive material 1992 includes a combination of TiN / W / TiN deposited by CVD.

[0152] The formation of the contact structure 214 may also include a planarization process, such as CMP, to remove excess second conductive material 1992 on top of the insulating layer 1480. Fig. 20B As shown in , the contact structure 214 can be coplanar with the insulating layer 1480.

[0153] The present disclosure also provides a 3D memory device manufactured using the above method.

[0154] refer to Figures 20A-20D , the 3D memory structure 2000 includes a film stack 335 of alternating conductive layers and dielectric layers. The film stack 335 includes conductive layers 1786 and first dielectric layers 452 alternately disposed on the substrate 330, stacked in the z direction perpendicular to the substrate 330. In some embodiments, the first dielectric layer 452 includes silicon oxide, and the conductive layer includes tungsten.

[0155] A third stepped structure 1760 (also referred to as a stepped structure) may be provided in the film stack 335 in the stepped region 210. The third stepped structure 1760 extends in the WL direction and includes third stepped steps 1762 (also referred to as stepped steps) that rise and fall along the WL direction (i.e., facing the WL direction). The third stepped steps 1762 or "step layers" refer to layer stacks having the same lateral dimensions in a surface parallel to the substrate surface 330f. Each third stepped step terminates at a length shorter than the third stepped step below.

[0156] The film stack 335 further includes a partition wall 865 in the partition region 863. The partition wall 865 extends in parallel to the third stepped structure 1760 in the WL direction. The partition wall 865 is adjacent to the third stepped structure 1760.

[0157] The 3D memory structure 2000 further includes a first barrier layer 1064 and a second barrier layer 1166. The first barrier layer 1064 may be disposed on the third stepped structure 1760, covering the top surface and sidewalls of the third stepped rung 1762. A second barrier layer 1166 different from the first barrier layer 1064 may be disposed on the first barrier layer 1064 in a first region 1272 of the third stepped structure 1760, wherein the first region 1272 is located at the center of the third stepped structure 1760. The first region 1272 extends along the WL direction. That is, the second barrier layer 1166 may be disposed at the center of the third stepped structure 1760, covering the central portion of the third stepped rung 1762. The second barrier layer 1166 may be removed from the second region 1274 of the third stepped structure 1760. The second region 1274 extending along the WL direction is adjacent to the partition wall 865. In some embodiments, the second region 1274 is located on each side of the first region 1272. In some embodiments, the first barrier layer includes silicon oxide and the second barrier layer includes silicon nitride. In some embodiments, the first barrier layer 1064 has a thickness in a range between 10 nm and 100 nm, and the second barrier layer 1166 has a thickness in a range between 50 nm and 500 nm.

[0158] The 3D memory structure 2000 also includes a GLS 216 that vertically penetrates the film stack 335 in the z direction. In some embodiments, the GLS 216 further extends into the substrate 330. The GLS 216 extends parallel to the WL direction and parallel to the third stepped structure 1760. The GLS 216 extends parallel to the first region 1272 and the second region 1274 of the third stepped structure 1760. In some embodiments, the second barrier layer 1166 is away from the GLS 216 in the BL direction. The GLS 216 may include a GLS filler 1888, wherein the GLS filler 1888 may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc.

[0159] The 3D memory structure 2000 further includes an insulating layer 1480 disposed on the first barrier layer 1064 and the second barrier layer 1166 above the third stepped structure 1760 and the partition wall 865 of the film stack 335. In some embodiments, the GLS 216 may be coplanar with the insulating layer 1480. The GLS 216 is configured to divide the memory block into sub-memory units (e.g., memory fingers).

[0160] The 3D memory structure 2000 also includes a contact structure 214 formed on the third step rung 1762 of the third step structure 1760, and the contact structure 214 can provide an electrical connection to the conductive layer 1786 of the film stack 335 of alternating conductive layers and dielectric layers. In some embodiments, the contact structure 214 can be disposed in the first region 1272 of the step structure. The contact structure 214 vertically penetrates the insulating layer, the second dielectric layer, and the first dielectric layer to contact a portion of one of the conductive layers 1786 of the film stack 335.

[0161] In some embodiments, the conductive layer 1786 can be electrically connected to the bottom select gate 332 ( Figure 3 ), a control gate or word line 333 or a top select gate 334. In some embodiments, a 3D memory device may include a memory string 212 (see Figure 2-Figure 3 ), the memory string 212 vertically penetrates the film stack 335 in the z direction, wherein the intersection between the control gate 333 and the memory string 212 can form a memory cell 340, such as Figure 2-Figure 3 As shown in .

[0162] Fig. 22 A block diagram of an exemplary system S1 having a storage system 10 according to some embodiments of the present disclosure is shown. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The storage system 10 (also referred to as a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereinafter referred to as "memory chip") may be a NAND chip (i.e., "flash memory", "NAND flash memory" or "NAND"). The storage system 10 may communicate with a host computer 15 through a memory controller 20, wherein the memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 may be managed by a memory controller 20 via a memory channel 30 .

[0163] In some embodiments, the host computer 15 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host computer 15 sends data to be stored in the NAND storage system or the storage system 10, or retrieves data by reading the storage system 10.

[0164] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and valid storage, and manage the memory chip 25. In order to perform these tasks, the controller runs firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller unit, CPU) inside the controller 20. For example, the controller 20 runs firmware 21 to map logical addresses (i.e., addresses used by the host associated with host data) to physical addresses in the memory chip 25 (i.e., the actual location where the data is stored). The controller 20 also runs firmware 21 to manage defective memory blocks in the memory chip 25, where the firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.), which can be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can also perform error recovery through an error correction code (ECC) engine 29. ECC can be used to detect and correct raw bit errors that occur in each memory chip 25.

[0165] The memory channel 30 may provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 may select one of the memory chips 25 according to a chip enable signal.

[0166] In some embodiments, Fig. 22 Each memory chip 25 in the embodiment may include one or more memory dies 2201, wherein each memory die 2201 may include Figure 1-Figure 3 3D NAND memory 100 shown in FIG. In some embodiments, each of the one or more memory dies 2201 may include Figures 20A-20D The 3D memory device 2000 shown in FIG. 2 may be used to Figure 4In some embodiments, the memory controller 20 may be configured to control the operation of a three-dimensional memory device (eg, the 3D NAND memory 100 ) to which the controller is connected.

[0167] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 10 can be implemented and packaged into different types of terminal electronic products. Fig.23A In one example shown, the memory controller 20 and the single memory chip 25 may be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA (personal computer memory card international association), a CF card, a smart media (SM, smart media) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a processor that connects the memory card 26 to a host (e.g., Fig. 22 The memory card connector 24 is coupled to the host computer 15 in the embodiment. Fig. 23B In another example shown, the memory controller 20 and the plurality of memory chips 25 may be integrated into a solid state drive (SSD) 27. The SSD 27 may also include a processor that connects the SSD 27 to a host (eg, Fig. 22 An SSD connector 28 coupled to a host computer 15).

[0168] Fig.24 A schematic diagram of a memory die 2201 according to some embodiments of the present disclosure is shown. In one example, the memory die 2201 may include Figure 1 The 3D memory device 100 has Figure 3 3D memory array structure 300 shown in FIG. In this example, memory die 2201 may also include Figures 20A-20D3D memory structure 2000 shown in . In some embodiments, memory die 2201 includes one or more memory blocks 103 (e.g., 103-1, 103-2). Each memory block 103 includes a memory string 212. Each memory string 212 includes a memory cell 340. The memory cells 340 sharing the same word line form a memory page 432. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a bottom select gate (BSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the bottom select transistor 332-T may be connected to an array common source (ACS) 430. ACS 430 may be shared by the memory strings 212 in the entire memory block and is also referred to as a common source line.

[0169] The memory die 2201 may also include peripheral circuits 2402, which include many digital, analog and / or mixed signal circuits to support the functions of the memory block 103, such as page buffers / sense amplifiers 50, row decoders / word line drivers 40, column decoders / bit line drivers 52, control circuits 70, voltage generators 65, and input / output buffers 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to one of ordinary skill in the art.

[0170] The memory block 103 may be coupled to the row decoder / word line driver 40 via a word line (“WL”) 333, a bottom select gate (“BSG”) 332, and a top select gate (“TSG”) 334. The memory block 103 may be coupled to the page buffer / sense amplifier 50 via a bit line (“BL”) 341. The row decoder / word line driver 40 may select one of the memory blocks 103 on the memory die 2201 in response to an X-path control signal provided by the control circuit 70. The row decoder / word line driver 40 may pass a voltage provided from the voltage generator 65 to the word line according to the X-path control signal. During read and program operations, the row decoder / word line driver 40 may select a read voltage V read and programming voltage V pgm is passed to the selected word line and will pass the voltage V pass passed to the unselected word lines.

[0171] The column decoder / bit line driver 52 can set the inhibit voltage V inhibitThe bit line 212 is passed to the non-selected bit line and the selected bit line is connected to the ground. That is, the column decoder / bit line driver 52 can be configured to select or deselect one or more memory strings 212 according to the Y path control signal from the control circuit 70. The page buffer / sense amplifier 50 can be configured to read data from the memory block 103 and program (write) data to the memory block 10 according to the Y path control signal from the control circuit 70. For example, the page buffer / sense amplifier 50 can store a page of data to be programmed into a memory page 432. In another example, the page buffer / sense amplifier 50 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sense amplifier 50 can sense the current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340, and amplify the small signal to a measurable amplification rate.

[0172] The input / output buffer 55 can transfer I / O data from / to the page buffer / sense amplifier 50, and transfer an address ADDR or a command CMD to the control circuit 70. In some embodiments, the input / output buffer 55 can be used as a memory controller 20 ( Figure 1 The interface between 2201 and the memory die 2202.

[0173] The control circuit 70 may control the page buffer / sense amplifier 50 and the row decoder / word line driver 40 in response to the command CMD delivered by the input / output buffer 55. During a programming operation, the control circuit 70 may control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to program a selected memory cell. During a read operation, the control circuit 70 may control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR, which may be used to locate a selected memory cell in the memory block 103. The row address X-ADDR may include a page index, a block index, and a plane index to identify the memory page 432, the memory block 103, and the memory plane 101 ( Figure 1 The column address Y-ADDR may identify a byte or word in the data of the memory page 432.

[0174] The voltage generator 65 can generate voltages to be supplied to the word lines and the bit lines under the control of the control circuit 70. The voltages generated by the voltage generator 65 include a read voltage V read , programming voltage V pgm , through the voltage V pass , Prohibited voltage V inhibit wait.

[0175] In summary, the present disclosure provides a method for forming a three-dimensional memory device. The method includes arranging an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a step structure and a partition wall in the alternating dielectric stack. The step structure and the partition wall extend in a second direction parallel to the substrate, and the partition wall is adjacent to the step structure. The method also includes sequentially forming a first barrier layer and a second barrier layer different from the first barrier layer on the step structure. The method also includes forming a gate line gap (GLS) opening in the partition wall. The GLS opening penetrates the alternating dielectric stack in the first direction and is away from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0176] The present disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes: a step structure, the step structure is arranged in the film stack and extends in a second direction parallel to the substrate; and a partition wall, the partition wall extends in the second direction and is positioned adjacent to the step structure. The 3D memory device also includes a gate line gap (GLS), the GLS is arranged in the partition wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction. The 3D memory device also includes: a first barrier layer, the first barrier layer is arranged on the step structure; and a second barrier layer, the second barrier layer is arranged on the first barrier layer in the first region of the step structure, wherein the second barrier layer different from the first barrier layer is away from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0177] The present disclosure also provides a memory storage system, including a three-dimensional memory device. The 3D memory device includes the above features.

[0178] In the present disclosure, a second barrier layer (e.g., silicon nitride) can be used as an etch stop to form a contact opening for a stepped structure. By using a blocking mask, a portion of the second barrier layer located around the gate line gap can be removed before removing the second dielectric layer (e.g., silicon nitride) in the alternating dielectric stack. After the second barrier layer is pulled back from the gate line gap, the second barrier layer will not be replaced by the conductive layer, and thus potential conductive paths can be avoided. The thickness of the second barrier layer is also not limited by the replacement process. Therefore, the performance and reliability of the 3D memory device can be improved.

[0179] The present disclosure also provides a 3D memory die including a three-dimensional (3D) memory device and a peripheral circuit. The 3D memory device includes: a film stack having a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate; a step structure, the step structure is arranged in the film stack and extends in a second direction parallel to the substrate; and a partition wall, the partition wall extends in the second direction and is positioned adjacent to the step structure. The 3D memory device also includes a gate line gap (GLS), the GLS is arranged in the partition wall, wherein the GLS penetrates the film stack in the first direction and extends in the second direction; a first barrier layer, the first barrier layer is arranged on the step structure; and a second barrier layer, the second barrier layer is arranged on the first barrier layer in the first region of the step structure. The second barrier layer, which is different from the first barrier layer, is away from the GLS in a third direction parallel to the substrate and perpendicular to the second direction. The peripheral circuit is coupled to the 3D memory device and is configured to support the operation of the 3D memory device. For example, the peripheral circuits may include functional devices such as page buffers / sense amplifiers 50 , column decoders / bit line drivers 52 , I / O buffers 55 , voltage generators 65 , control circuits 70 , and row decoders 40 .

[0180] The foregoing description of specific embodiments will fully reveal the general nature of the present disclosure so that others can easily modify and / or adjust these specific embodiments for various applications by applying the knowledge within the technology of the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, based on the disclosure and guidance presented herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification are interpreted by the technician based on the disclosure and guidance.

[0181] Embodiments of the present disclosure have been described above by means of functional building blocks that illustrate the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. As long as the specified functions and their relationships are properly performed, the boundaries of the replacements can be defined.

[0182] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0183] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, include: A membrane stack, comprising: Conductive layers and first dielectric layers, the conductive layers and the first dielectric layers are alternately stacked in a first direction; a step structure extending in a second direction intersecting the first direction; and a partition wall extending in the second direction and adjacent to the stepped structure; a gate line slit GLS provided in the partition wall, wherein the gate line slit GLS passes through the film stack in the first direction and extends in the second direction; A first barrier layer comprising: a first portion, the first portion being disposed on the stepped structure; and a second portion disposed on a side wall of the partition wall; and A second barrier layer is disposed on the first portion of the first barrier layer, wherein the second barrier layer is different from the first barrier layer.

2. The memory device according to claim 1, in, The first barrier layer at least covers sidewalls of the step steps of the step structure.

3. The memory device according to claim 2, in, The second barrier layer at least covers the first barrier layer located on the sidewalls of the step steps of the step structure.

4. The memory device according to claim 1, further comprising: include: An insulating layer is disposed on the second barrier layer to cover a top surface and side walls of the second barrier layer.

5. The memory device according to claim 4, further comprising: include: A contact structure passes through the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure contacts one of the conductive layers of the film stack.

6. The memory device according to claim 1, in, In a third direction crossing both the first direction and the second direction, the second barrier layer is spaced apart from the gate line gap GLS.

7. The memory device according to claim 1, in, The first barrier layer includes silicon oxide, and the second barrier layer includes silicon nitride.

8. The memory device according to claim 1, in, The first barrier layer comprises a thickness in a range between 10 nm and 100 nm.

9. The memory device according to claim 1, in, The second barrier layer comprises a thickness in a range between 50 nm and 500 nm.

10. A memory device, include: A membrane stack, comprising: Conductive layers and first dielectric layers, the conductive layers and the first dielectric layers are alternately stacked in a first direction; a step structure extending in a second direction intersecting the first direction; and a partition wall extending in the second direction and adjacent to the stepped structure; a gate line slit GLS provided in the partition wall, wherein the gate line slit GLS passes through the film stack in the first direction and extends in the second direction; a first barrier layer, the first barrier layer being disposed on the stepped structure; a second barrier layer disposed on the first barrier layer, wherein the second barrier layer is different from the first barrier layer; and A contact structure passes through the second barrier layer and the first barrier layer in the first direction, wherein the contact structure is in contact with one of the conductive layers of the film stack.

11. The memory device according to claim 10, in, The first barrier layer at least covers sidewalls of the step steps of the step structure.

12. The memory device according to claim 11, in, The second barrier layer at least covers the first barrier layer located on the sidewalls of the step steps of the step structure.

13. The memory device according to claim 10, further comprising: include: An insulating layer is disposed on the second barrier layer to cover a top surface and sidewalls of the second barrier layer, wherein the contact structure passes through the insulating layer in the first direction.

14. The memory device according to claim 10, in, The first barrier layer is disposed on a side wall of the partition wall.

15. The memory device according to claim 10, in, The first barrier layer includes silicon oxide, and the second barrier layer includes silicon nitride.

16. A memory device, include: A membrane stack, comprising: Conductive layers and first dielectric layers, the conductive layers and the first dielectric layers are alternately stacked in a first direction; a step structure extending in a second direction intersecting the first direction; and a partition wall extending in the second direction and adjacent to the stepped structure; a gate line slit GLS provided in the partition wall, wherein the gate line slit GLS passes through the film stack in the first direction and extends in the second direction; a first barrier layer, the first barrier layer being disposed on the stepped structure; and A second barrier layer is disposed on the first barrier layer, wherein the second barrier layer is different from the first barrier layer, and the first barrier layer and the second barrier layer at least cover side walls of the step steps of the step structure.

17. The memory device according to claim 16, further comprising: include: An insulating layer is disposed on the second barrier layer to cover a top surface and side walls of the second barrier layer.

18. The memory device according to claim 17, further comprising: include: A contact structure passes through the insulating layer, the second barrier layer, and the first barrier layer in the first direction, wherein the contact structure contacts one of the conductive layers of the film stack.

19. The memory device according to claim 16, in, The first barrier layer includes silicon oxide, and the second barrier layer includes silicon nitride.

20. The memory device according to claim 16, in, The first barrier layer is disposed on a side wall of the partition wall.

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