RC-IGBT device and preparation method thereof

Abstract

The invention discloses an RC-IGBT device and a preparation method thereof. The RC-IGBT device is characterized in that an n-fs layer is arranged on a collector side in a local doping mode; the p floating region is arranged above the n + short circuit region on the collector side; the shallow trench medium isolation region is arranged between the p + collector region and the n + short circuit region on the collector side; the emitter trench gate and the embedded trench emitter are arranged on the emitter side; according to the invention, the n-fs layer is introduced to the collector side, and the p floating region is introduced above the n + short circuit region, so that the resistance of the collector side is increased, and the voltage turn-back phenomenon of the device during forward conduction is inhibited; by introducing a shallow trench medium isolation region, it is ensured that when the device is blocked, punch-through breakdown does not occur, and blocking voltage is not reduced; the emitter trench gate and the embedded trench emitter are introduced to the emitter side, so that the short-circuit capability of the trench gate IGBT is improved; and the number of hole flow under the n + emitter region is reduced, so that the device is not easy to latch under high current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an RC-IGBT device and a preparation method thereof. Background Art

[0002] Using RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in the inverter circuit can reduce the parasitic inductance of the circuit and improve the reliability and efficiency of the inverter. + The collector region introduces part n + Short-circuit area, so as to achieve forward and reverse conduction, but n + The introduction of the short-circuit region causes the device to experience snapback (voltage foldback) during forward conduction, which increases the device's turn-on loss. In order to suppress the snapback phenomenon, the chip area is large, which increases the process cost and is not conducive to improving the power density. Figure 1 It is a traditional RC-IGBT structure with a planar gate structure 1 on the emitter side and a p + There is a portion n in the collector region 10 + Short-circuit region 11, when forward conduction occurs, n is injected from the channel - After entering the n-fs layer 8, the electrons in the drift region 7 first flow laterally toward the n + Short-circuit area 11, i.e. the back J of the IGBT at the initial stage of conduction 1 (p + Collector area / n + The short-circuit region) junction is not easy to conduct, and the device works in MOS unipolar conduction mode. As the current density increases, only when the back J 1 After the junction is turned on, p + The collector region 10 will - The drift region 7 injects holes, n - The drift region 7 generates a conductivity modulation effect, so that the IGBT changes from a MOS unipolar conduction mode to an IGBT bipolar conduction mode. Figure 1 The RC-IGBT structure in the + The lateral size of the collector region is used to suppress the snapback phenomenon, which makes the device very large, which is not conducive to improving the power density of the circuit system and also increases the process manufacturing cost.

[0003] In order to reduce the chip area and better suppress the snapback phenomenon, the researchers Figure 1 The traditional RC-IGBT structure proposes the following Figure 2The RC-IGBT structure using dielectric isolation and junction isolation is shown. Figure 2 The collector side of the RC-IGBT structure uses a deep trench isolation region 12 and a junction isolation (p floating region) 9, and a planar gate structure 1 is used on the emitter side. + There is a portion n in the collector region 10 + Short-circuit area 11, and on the back side of the p + Collector region 10 and n + A deep trench isolation region 12 is introduced between the short circuit region 11. + A p-floating region 9 is introduced above the short-circuit region 11 , wherein the depth of the deep trench isolation region 12 is greater than the junction depth of the n-fs layer 8 , and a gap is left between the p-floating region 9 and the right side of the n-fs layer 8 . Figure 2 The RC-IGBT structure in the circuit greatly reduces the chip area and suppresses the snapback phenomenon, but there are also some problems, namely Figure 2 The deep trench dielectric isolation region in the device needs to adopt the process of etching the trench and filling the oxide, which has the process difficulty of deep trench etching and oxide filling, and increases the process cost. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the RC-IGBT structure in the prior art when suppressing the voltage foldback phenomenon, such as large chip area, great process difficulty and high cost, and to provide an RC-IGBT device and a preparation method thereof.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] A first aspect of the present invention provides an RC-IGBT device, the RC-IGBT device comprising:

[0007] The n-fs layer is arranged on the collector side in the form of local doping;

[0008] p floating region, arranged on the collector side of n + Above the short-circuit area;

[0009] A shallow trench dielectric isolation region is provided on the collector side of the p + Collector region and n + Between short-circuit areas;

[0010] An emitter trench gate, arranged on the emitter side;

[0011] The embedded trench emitter is arranged on the emitter side.

[0012] Preferably, the RC-IGBT device further includes:

[0013] An active trench gate, n+ Emitter region, p + Ohmic contact region, p-base region, n-CS layer and anode region of the integrated diode;

[0014] The active trench gate is used to connect polysilicon to the gate;

[0015] There is a p + Ohmic contact region and two n + Emitter regions. The two n + Emitter regions and p + The surfaces of the ohmic contact regions are all provided with aluminum metallized emitters;

[0016] p + The ohmic contact region is connected to the embedded trench emitter to form the anode region of the integrated diode;

[0017] The n-CS layer is located below the p-base region, and the bottom of the n-CS layer is lower than the trench bottoms of the active trench gate and the emitter trench gate, and is formed by an inverted doping process.

[0018] Preferably, the emitter trench gate is used to connect polysilicon to the emitter.

[0019] Preferably, the embedded trench emitter is used to connect the emitter to the n + Emitter region and p + Ohmic contact region respectively.

[0020] Preferably, the p + Collector regions on the collector side are respectively located on both sides of the n - Drift region;

[0021] The n + Short-circuit region on the collector side is located at the middle position of the p - Collector regions on both sides of the n + Drift region.

[0022] Preferably, the n-fs layers are respectively located above the p - Collector regions on both sides of the n + Drift region. The right boundary of the n-fs layer located on the left side of the n - Drift region is connected to the left boundary of the left p floating region, and the right boundary of the n-fs layer is located above the left shallow trench dielectric isolation region; the left boundary of the n-fs layer located on the right side of the n - Drift region is connected to the right boundary of the right p floating region, and the left boundary of the n-fs layer is located above the right shallow trench dielectric isolation region.

[0023] Preferably, the depth of the shallow trench dielectric isolation region is greater than the depth of the p + collector region and the depth of the n + short-circuit region and less than the depth of the n-fs layer.

[0024] A second aspect of the present invention provides a method for manufacturing an RC-IGBT device, the manufacturing method including:

[0025] Forming an implantation window for a locally doped n-fs layer through a photomask, implanting high-energy phosphorus ions and performing high-temperature drive-in to form the n-fs layer;

[0026] Forming an implantation window for a locally doped p floating region through a photomask, implanting boron ions and performing high-temperature drive-in to form the p floating region;

[0027] Forming a p + collector region by boron ion implantation and drive-in;

[0028] Forming an implantation window for the n + short-circuit region through a photomask, implanting high-energy phosphorus ions and performing drive-in to form the n + short-circuit region; then eliminating damage and activating impurities through laser annealing;

[0029] Forming a shallow trench dielectric isolation region through a photomask and oxygen ion implantation.

[0030] Preferably, before the step of forming an implantation window for a locally doped n-fs layer through photolithography to implant high-energy phosphorus ions, the manufacturing method further includes:

[0031] Using the original zone-melted silicon single crystal as the n - drift region and performing a cleaning process;

[0032] Depositing a sacrificial oxide layer on the top silicon surface of the n - drift region after the cleaning process, adopting an inverted doping process, and using the high-energy phosphorus ion implantation, forming an n-CS layer through high-temperature drive-in and annealing;

[0033] Performing boron ion implantation on the surface of the wafer after the above treatment, and performing high-temperature drive-in and annealing to form a p base region;

[0034] Forming a trench on the surface of the wafer after the treatment for forming the p base region through a photomask and plasma etching; forming a sacrificial oxide layer by deposition on the surface of the wafer after the treatment for forming the trench, and then removing the sacrificial oxide layer; growing a gate oxide layer by dry oxidation on the surface of the trench after the above treatment, and then depositing and back-etching polysilicon by low-pressure chemical vapor deposition; forming a p +For the boron ion implantation window in the ohmic contact region, boron ions are implanted; for the upper surface of the wafer after the boron ion implantation process, As + is implanted, and a p + ohmic contact region and an n + emitter region are formed through high-temperature drive and annealing; an embedded emitter trench contact hole is formed through a photomask and etching; a layer of phosphosilicate glass is grown by low-pressure chemical vapor deposition, and a passivation layer is formed by photolithography; on the upper surface of the wafer after the passivation layer is formed, a metal aluminum layer is deposited and etched back, and after alloying, bonding pads for the emitter and gate are formed on the upper surface; after the bonding pads for the emitter and gate are formed, the wafer is flipped, and after back thinning, a sacrificial oxide layer is deposited on its surface.

[0035] Preferably, after the step of forming the shallow trench dielectric isolation region through a photomask and oxygen ion implantation, the preparation method further includes:

[0036] After the shallow trench dielectric isolation region is formed, a metal aluminum layer is first deposited on the back surface, and then titanium, nickel, and silver are sequentially deposited, and after alloying, a bonding pad for the collector is formed on the back surface.

[0037] Based on common knowledge in the art, the above preferred conditions can be combined arbitrarily to obtain various preferred embodiments of the present invention.

[0038] The positive and progressive effects of the present invention are as follows:

[0039] By introducing a locally doped n-fs layer on the collector side and a p floating region above the n + short-circuit region in the present invention, the resistance on the collector side is increased, and the voltage fold-back phenomenon during the forward conduction of the RC-IGBT device is suppressed; and by introducing a shallow trench dielectric isolation region between the p + collector region and the n + short-circuit region, it is ensured that the RC-IGBT device will not experience punch-through breakdown during blocking, resulting in a reduction in the blocking voltage; by introducing an emitter trench gate on the emitter side, the channel density of the trench gate IGBT is reduced, and the short-circuit capability of the trench gate IGBT is improved; by introducing an embedded trench emitter on the emitter side, the number of hole flows under the n + emitter region is reduced, so that the RC-IGBT device is not prone to latch-up even under high current. Description of the Drawings

[0040] Figure 1 FIG. is a first structural schematic diagram of an RC-IGBT device in the prior art.

[0041] Figure 2 FIG. is a second structural schematic diagram of an RC-IGBT device in the prior art.

[0042] Figure 3Schematic diagram of the structure of the RC-IGBT device according to Embodiment 1 of the present invention.

[0043] Figure 4 Schematic diagram of the structural parameters of the RC-IGBT device according to Embodiment 1 of the present invention.

[0044] Figure 5 Flow chart of the manufacturing method of the RC-IGBT device according to Embodiment 2 of the present invention. Detailed implementation manners

[0045] The present invention will be further described below by way of embodiments, but the present invention is not limited to the scope of the described embodiments.

[0046] Embodiment 1

[0047] An RC-IGBT device provided in this embodiment, as Figure 3 shown, the RC-IGBT device includes:

[0048] The n-fs layer 8 is disposed on the collector side in a form of local doping;

[0049] The p floating region 9 is disposed above the n + short-circuit region 11 on the collector side;

[0050] The shallow trench dielectric isolation region 12 is disposed between the p + collector region 10 and the n + short-circuit region 11 on the collector side;

[0051] The emitter trench gate DG is disposed on the emitter side;

[0052] The embedded trench emitter is disposed on the emitter side.

[0053] In this embodiment, as Figure 3 shown, both of the two p floating regions 9 located on the collector side are located above the n + short-circuit region 11; the left boundary of the left p floating region 9 is connected to the right boundary of the left n-fs layer 8, and the left boundary of the left p floating region 9 is located above the left shallow trench dielectric isolation region 12; the right boundary of the right p floating region 9 is connected to the left boundary of the right n-fs layer 8, and the right boundary of the right p floating region 9 is located above the right shallow trench dielectric isolation region 12; the distance between the two p floating regions 9 enables electrons in the n + short-circuit region 11 (the cathode of the diode) to be directly injected into the n - drift region 7 when the integrated diode is turned on, and at the same time provides an additional path for the extraction of electrons in the n - drift region 7 when the IGBT is turned off, accelerating the extraction of electrons when the IGBT is turned off.

[0054] It should be noted that for the p floating region 9, its doping concentration is 8×10 16 cm -3 ~1×10 17 cm -3 , the junction depth is 1.8 μm to 1.9 μm, the distance between two p floating regions 9 is 1.0 μm to 2.0 μm, and the width of the p floating region 9 located above the shallow trench isolation region 12 is 0.5 μm to 1.1 μm.

[0055] In addition, the p + collector region 10 and the n + short-circuit region 11 on the collector side have a width ratio of 3:1 or 4:1, and the junction depth of both is 0.5 μm.

[0056] The RC-IGBT device of this embodiment not only has no voltage snapback phenomenon, low turn-off loss, and good reverse recovery characteristics, but also reduces the process cost.

[0057] In an alternative embodiment, as Figure 3 shown, the RC-IGBT device further includes:

[0058] An active trench gate AG, an n + emitter region 3, a p + ohmic contact region 4, a p base region 5, an n-CS layer 6, and an anode region of an integrated diode, which are arranged on the emitter side;

[0059] The active trench gate AG is used to connect the polysilicon to the gate 1;

[0060] There are a p + ohmic contact region 4 and two n + emitter regions 3 in the p base region 5. Aluminum metallized emitters 2 are arranged on the surfaces of the two n + emitter regions 3 and the p + ohmic contact region 4;

[0061] The p + ohmic contact region 4 is connected to the embedded trench emitter to form the anode region of the integrated diode;

[0062] The n-CS layer 6 is located below the p base region 5, and the bottom of the n-CS layer 6 is lower than the trench bottoms of the active trench gate AG and the emitter trench gate DG, and is formed by an inverted doping process.

[0063] In this embodiment, a p + ohmic contact region 4 (also referred to as the anode region of the diode) and two n + emitter regions 3 (for example, the first n + emitter region, the second n + emitter region) are respectively arranged in the p base region 5 on the emitter side;

[0064] Two n + The emitter region 3 and p + On the surface of the ohmic contact region 4, an aluminum metallized emitter E is provided in common;

[0065] The p + The ohmic contact region 4 on the emitter side is connected to the embedded trench emitter and serves as the anode region of the integrated diode.

[0066] In this embodiment, the RC-IGBT device includes an active trench gate AG, an emitter trench gate DG, an embedded trench emitter, n + Emitter region 3, p + Ohmic contact region 4, p-base region 5, n-CS layer 6, and the anode region of the integrated diode; on the collector side, p + Collector region 10, n + Short-circuit region 11, n-fs layer 8, p-floating region 9, and shallow trench dielectric isolation region 12.

[0067] It should be noted that the n-CS layer 6 on the emitter side is located below the p-base region 5 and the bottom of the n-CS layer 6 is lower than the trench bottoms of the active trench gate AG and the emitter trench gate DG, and is formed by an inverted doping process, with a junction depth of 0.5 μm to 1 μm and a doping concentration of 1×10 16 cm -3 ~2.5×10 16 cm -3 .

[0068] In addition, the ratio of the active trench gate AG to the emitter trench gate DG can be set to 2:6. By adjusting the ratio of the active trench gate AG to the emitter trench gate DG, the contradictory relationship between the saturation voltage and the short-circuit ability of the IGBT can be improved;

[0069] Such as Figure 3 shown, the distribution of the active trench gate AG and the emitter trench gate DG is two active trench gates AG and six emitter trench gates DG, that is, AG-DG-DG-DG-DG-DG-DG-AG, and the two active trench gates AG must be located at the leftmost and rightmost sides of the entire cell respectively, which is beneficial to increasing the path of electrons flowing to the n + short-circuit region, thereby better suppressing the voltage foldback phenomenon.

[0070] In this embodiment, the MOS structure region of the IGBT on the emitter side includes a total of 8 trench gates. In the MOS structure region of the IGBT on the emitter side, the active trench gate (Active Gate, AG) connects the polysilicon to the gate 1, thereby controlling the operation of the IGBT.

[0071] In an alternative embodiment, an emitter trench gate is used to connect the polysilicon to the emitter 2.

[0072] In this embodiment, the emitter trench gate (also known as the dummy gate, DG) in the MOS structure region of the IGBT on the emitter side connects the polysilicon to the emitter 2, reducing the channel density of the trench gate IGBT and improving the short-circuit capability of the RC-IGBT device.

[0073] In an alternative embodiment, an embedded trench emitter is used to connect the emitter 2 to the n + emission region and the p + ohmic contact region respectively.

[0074] In this embodiment, the embedded trench emitter on the emitter side connects the emitter 2 to the n + emission region and the p + ohmic contact region by digging a trench and filling it with aluminum metal, providing an additional flow path for holes and reducing the number of holes flowing under the n + emission region.

[0075] In an alternative embodiment, as Figure 3 shown, the p + collector region 10 on the collector side is located on both sides of the n - drift region 7 respectively;

[0076] The n + short-circuit region 11 on the collector side is located in the middle of the p - collector region 10 on both sides of the n + drift region 7.

[0077] In this embodiment, as Figure 3 shown, the p + collector region 10 on the collector side is located at the leftmost and rightmost sides of the n - drift region 7 respectively. The n + short-circuit region 11 on the collector side is located in the middle of the leftmost and rightmost p + collector region 10.

[0078] In an alternative embodiment, as Figure 3 shown, the n-fs layer 8 is located on both sides of the n - drift region 7. The right boundary of the n-fs layer 8 on the left side of the n - drift region 7 is connected to the left boundary of the left p floating region 9, and the right boundary of the n-fs layer is located above the left shallow trench dielectric isolation region 12; Located on the n -The left boundary of the n-fs layer 8 on the right side of the drift region is connected to the right boundary of the p floating region 9 on the right side, and the left boundary of the n-fs layer 8 is located above the shallow trench dielectric isolation region 12 on the right side.

[0079] In this embodiment, as Figure 3 shown, the n-fs layer 8 on the collector side is formed by a local doping process using a photolithography window, and the n-fs layer 8 is located at the leftmost and rightmost sides of the n - drift region 7 respectively;

[0080] It should be noted that the two p floating regions 9 on the collector side of this embodiment are not located in the n-fs layer 8, and there is no impurity compensation effect between the p floating region 9 and the n-fs layer 8. Moreover, due to the local doping of the n-fs layer 8, the resistance above the n + short-circuit region 11 is further increased, the thickness of the p floating region 9 is reduced, and the energy required for ion implantation is also reduced.

[0081] In an optional embodiment, the depth of the shallow trench dielectric isolation region 12 is greater than the depth of the p + collector region 10 and the depth of the n + short-circuit region 11 and less than the depth of the n-fs layer 8.

[0082] In this embodiment, the two shallow trench dielectric isolation regions 12 on the collector side are both located between the p + collector region 10 and the n + short-circuit region 11; the depth of the two shallow trench dielectric isolation regions 12 is greater than the junction depth of the p + collector region 10 and the junction depth of the n + short-circuit region 11, but much less than the junction depth of the n-fs layer 8; the upper boundary of the left shallow trench dielectric isolation region 12 is connected to the right boundary of the left n-fs layer 8 and the left boundary of the left p floating region 9; the upper boundary of the right shallow trench dielectric isolation region 12 is connected to the left boundary of the right n-fs layer 8 and the right boundary of the right p floating region 9.

[0083] In this embodiment, for the two shallow trench dielectric isolation regions 12, their width can be set to 1.6 μm to 2 μm, and the depth can be set to 0.7 μm to 1 μm.

[0084] For the two shallow trench dielectric isolation regions of this embodiment, their depth is greatly reduced. Therefore, the trench dielectric isolation region can be directly formed by the oxygen implantation isolation process without the processes of etching trenches and depositing oxides, greatly reducing the process difficulty.

[0085] As Figure 3 shown, for the RC-IGBT device of this embodiment, the structure on the emitter side adopts an active trench gate AG and an emitter trench gate DG;

[0086] Among them, the active trench gate AG is connected to the gate 1. When the IGBT is working, the active trench gate AG can generate or turn off the electron channel, thereby controlling the working state of the IGBT; the emitter trench gate DG is connected to the emitter 2. When the IGBT is working, the emitter trench gate DG does not generate an electron channel, reducing the channel density of the trench gate IGBT and improving the short-circuit capability of the trench gate IGBT, which is beneficial to improving the problem of poor short-circuit capability due to the large channel density of the trench gate IGBT.

[0087] Since n + The short-circuit region 11 is located at the middle position between two p + collector regions 10. Therefore, considering the distribution of the active trench gate AG and the emitter trench gate DG as two active trench gates AG and six emitter trench gates DG, that is, AG-DG-DG-DG-DG-DG-DG-AG. When the RC-IGBT conducts forward, the electrons flowing through the channel of the active trench gate AG flow into n - the drift region 7 as far away from n + the short-circuit region 11 as possible, thereby increasing the path for electrons to flow to n + the short-circuit region 11. Most of the electrons flow to p + the collector region 10, enabling the back J 1 (i.e., the p + collector region / n-fs layer) junction to turn on as soon as possible, and the p + collector region 10 injects electrons into n - the drift region 7, realizing the bipolar conduction mode of the IGBT. It should be noted that the trench gate is filled with a gate oxide layer and heavily doped polysilicon in sequence to form the active trench gate AG and the emitter trench gate DG. The active trench gate AG is connected to the gate G, and the emitter trench gate DG is connected to the emitter E to form the emitter trench gate (i.e., the virtual gate);

[0088] See Figure 3 , for the RC-IGBT device of this embodiment, p + ohmic contact regions 4 and two n + emitter regions 3 (such as the first n + emitter region, the second n + emitter region) are respectively provided in the p-base region 5 on the emitter side. The surfaces of the n + emitter region 3 and the p + ohmic contact region 4 are jointly provided with an aluminum metallized emitter, and the connection between the n + emitter region 3 and the p + ohmic contact region 4 and the emitter 2 is connected through a grooved and metal aluminum Al-filled embedded trench emitter; among them, the n + emitter regions 3 on both sides of the emitter trench gate DG are mainly used to reduce p +The lateral dimension of the ohmic contact region 4 (i.e., the anode region of the diode) is reduced, thereby decreasing the anode hole injection efficiency of the diode and improving the reverse recovery characteristics of the diode.

[0089] See Figure 3 , in this embodiment, the structure on the emitter side of the RC-IGBT device adopts an n-CS layer 6. When the IGBT is turned on, the n-CS layer 6 blocks the flow of holes to the emitter 2, and most of the holes accumulate below the n-CS layer 6, causing the n + emitter region 3 to inject more electrons into the n - drift region 7, enhancing the IE effect, reducing the saturation voltage of the IGBT, and not increasing the turn-off loss of the IGBT.

[0090] See Figure 3 , in this embodiment, the p-base region 5 of the structure on the emitter side of the RC-IGBT device adopts an embedded trench emitter, that is, the n + emitter region 3 is connected to the p + ohmic contact region 4 by digging a trench. When the IGBT is operating, the embedded trench emitter structure can provide an additional flow path for holes, that is, the hole current can flow directly from the embedded trench emitter, that is, the p + ohmic contact region 4 without passing under the n + short-circuit region 11, thereby reducing the number of holes flowing under the n + emitter region 3, making it difficult for the chip to latch even under high current, increasing the maximum turn-off current of the device, and increasing the SOA of the RC-IGBT device.

[0091] See Figure 3 , in this embodiment, the structure on the collector side of the RC-IGBT device adopts an n-fs layer 8 formed by a local doping process. Compared with Figure 2 , Figure 3 the n-fs layer 8 formed by the local doping process in + the short-circuit resistance Rcs above the short-circuit region is further increased. When the RC-IGBT device is conducting forward, the resistance of the region directly in contact between the upper part of the n + short-circuit region 11 and the n - drift region 7 is greater than that of the n-fs layer 8, causing most electrons to accumulate in the n-fs layer 8, promoting J 1 (p +The collector region / n-fs layer) junction turns on quickly, and the RC-IGBT device quickly enters the IGBT conduction mode; this structure greatly reduces the chip area and effectively suppresses the voltage snapback phenomenon. The structure on the collector side adopts a shallow trench dielectric isolation region 12 and a p-floating region 9, and the p-floating region 9 is formed by photolithography and ion implantation. The photolithography of the p-floating region 9 is to make the RC-IGBT device conduct as a diode rather than a thyristor during reverse conduction; among them, the depth of the shallow trench dielectric isolation region 12 needs to be greater than the + junction depth of the collector region 10 to ensure that the IGBT does not experience punch-through breakdown during blocking, resulting in p + The connection between the collector region 10 and the p-floating region 9 reduces the blocking voltage, and compared with Figure 2 , Figure 3 in which the depth of the shallow trench dielectric isolation region 12 is reduced, this embodiment can be formed by oxygen implantation isolation process and does not require the Figure 2 deep trench etching and oxide filling process, thus reducing the process difficulty and saving the process manufacturing cost; in addition, the p-floating region 9 increases the resistance of the collector 13. When the RC-IGBT device conducts forward, the p-floating region 9 acts as an electron barrier, causing most electrons to accumulate in the n-fs layer 8, promoting the 1 junction to turn on quickly, and the RC-IGBT device quickly enters the IGBT conduction mode. And compared with Figure 2 , Figure 3 in which the p-floating region 9 is not formed in the n-fs layer 8, there is no impurity compensation effect between the p-floating region 9 and the n-fs layer 8, and due to the local doping of the n-fs layer 8, the resistance above the n + short-circuit region is further increased, so that the thickness of the p-floating region 9 can be reduced compared with Figure 2 , and the energy required for ion implantation can also be reduced.

[0092] Figure 4 This is a schematic diagram of the key structural parameters of the RC-IGBT device in this embodiment. By adjusting the structural parameters of the p-floating region 9, such as the doping concentration N pf of the p-floating region 9, the thickness d pf of the p-floating region 9, the distance L - between the p-floating region 9 and the right side of the n pfgap drift region, and the lateral dimension L pfl of the p-floating region 9 located above the shallow trench isolation region 12, the resistance between the p + collector region 10 and the n + short-circuit region 11 is changed, so as to suppress the voltage snapback phenomenon at the initial stage of forward conduction under a smaller cell size.

[0093] In this embodiment, by introducing a locally doped n-fs layer on the collector side and in the n +A p floating region is introduced above the short - circuit region, increasing the resistance on the collector side and suppressing the voltage fold - back phenomenon of the RC - IGBT device during forward conduction; and by introducing a shallow trench dielectric isolation region between the p + collector region and the n + short - circuit region, it is ensured that the RC - IGBT device will not experience punch - through breakdown during blocking, resulting in a reduction in the blocking voltage; by introducing an emitter trench gate on the emitter side, the channel density of the trench - gate IGBT is reduced, improving the short - circuit ability of the trench - gate IGBT; by introducing an embedded trench emitter on the emitter side, the number of holes flowing under the n + emission region is reduced, making the RC - IGBT device less likely to latch up under high currents. Further, the RC - IGBT device of this embodiment can not only eliminate the voltage fold - back phenomenon during the forward conduction of the device, reduce the switching loss of the trench - gate IGBT, and is beneficial to reducing the reverse recovery peak current density of the integrated diode, but also has a small cell size, reducing the process difficulty of etching deep trenches and oxide filling using dielectric isolation and junction isolation, and reducing the process cost.

[0094] Embodiment 2

[0095] An RC - IGBT device provided in this embodiment, as Figure 5 shown, the manufacturing method includes:

[0096] Step 11: Use the original zone - melted silicon single crystal as the n - drift region and perform a cleaning process;

[0097] Step 12: Deposit a sacrificial oxide layer on the top - silicon surface of the cleaned n - drift region. Adopt the inverted doping process, use high - energy phosphorus ions P + injection, and form the n - CS layer through high - temperature diffusion and annealing;

[0098] Step 13: On the surface of the wafer after the above treatment (i.e., the surface of the wafer after Step 12), perform boron ion B + injection, and perform high - temperature diffusion and annealing to form the p - base region;

[0099] Step 14: On the surface of the wafer after the treatment to form the p - base region (i.e., the surface of the wafer after Step 13), form trenches through a photomask and plasma etching;

[0100] Step 15: On the surface of the wafer after the treatment to form trenches (i.e., the surface of the wafer after Step 14), deposit a sacrificial oxide layer, and then remove the sacrificial oxide layer;

[0101] Step 16: Dry oxidation is used to grow a gate oxide layer on the processed trench surface (i.e., on the wafer surface after Step 15), and then polysilicon is deposited by low-pressure chemical vapor deposition and etched back;

[0102] Step 17: On the upper surface of the processed wafer after depositing polysilicon by low-pressure chemical vapor deposition and etching back (i.e., on the wafer surface after Step 16), a boron ion implantation window for the p + ohmic contact region is formed by photolithography, and boron ion implantation is carried out;

[0103] Step 18: On the upper surface of the processed wafer after boron ion implantation (i.e., on the wafer surface after Step 17), As + implantation is carried out, and a p + ohmic contact region and an n + emitter region are formed through high-temperature drive-in and annealing;

[0104] Step 19: An embedded emitter trench contact hole is formed through a photomask and etching (i.e., on the wafer surface after Step 18, an embedded emitter trench contact hole is formed through photolithography and etching);

[0105] Step 20: A layer of phosphosilicate glass is grown by low-pressure chemical vapor deposition, and a passivation layer is formed by photolithography (i.e., on the wafer surface after Step 19, a layer of phosphosilicate glass is grown by low-pressure chemical vapor deposition, and a passivation layer is formed by photolithography);

[0106] Step 21: On the upper surface of the processed wafer after forming the passivation layer, a metal aluminum layer is deposited and etched back, and after alloying, bonding pads for the emitter and gate are formed on the upper surface (i.e., on the wafer surface after Step 20, a metal aluminum layer is deposited and etched back, and after alloying, bonding pads for the emitter E and gate G are formed on the upper surface);

[0107] Step 22: After forming the bonding pads for the emitter and gate, the wafer is flipped. After back thinning, a sacrificial oxide layer is deposited on its surface;

[0108] In this embodiment, after Step 21 is completed, the wafer is flipped. After back thinning, a sacrificial oxide layer is first deposited on its surface, with a thickness of 10 nm to 40 nm, to reduce the damage (channeling effect) caused to the silicon wafer by subsequent ion implantation processes;

[0109] Step 23: An injection window for the locally doped n-fs layer is formed through a photomask, and high-energy phosphorus ions are injected and driven in at high temperature to form the n-fs layer;

[0110] In this embodiment, after Step 22 is completed, an injection window for the locally doped n-fs layer is formed through a photomask, and P + injection is carried out;

[0111] Step 24: Form an implantation window for the locally doped p floating region through a photomask, implant boron ions, and perform high-temperature drive-in to form the p floating region;

[0112] Step 25: Form the p + collector region through boron ion implantation and drive-in;

[0113] Step 26: Form an implantation window for the n + short-circuit region through a photomask, implant high-energy phosphorus ions, and perform drive-in to form the n + short-circuit region; then eliminate the damage and activate the impurities through laser annealing;

[0114] In this embodiment, after the n-fs layer is completed, form an implantation window for the locally doped p floating region through a photomask, perform B + implantation and high-temperature drive-in to form the p floating region; after the implantation of the p floating region is completed, perform B + implantation and drive-in to form the p + collector region; after the p + collector region is completed, form an implantation window for the n + short-circuit region through a photomask, perform B + implantation and drive-in to form the n + short-circuit region; then eliminate the damage and activate the impurities through laser annealing;

[0115] In this embodiment, form an implantation window for the locally doped p floating region through a photomask and implant boron ions, then perform boron ion implantation to form the p + collector region, and then form an implantation window for the n + short-circuit region through a photomask and implant boron ions; finally, use laser annealing to eliminate the damage and activate the impurities. Laser annealing avoids the influence of the backside thermal process on the front-side structure;

[0116] Step 27: Form a shallow trench isolation region through a photomask and oxygen ion implantation.

[0117] In this embodiment, after Step 26 is completed, use the oxygen implantation isolation technology, that is, form a backside shallow trench isolation region through a photomask and oxygen ion implantation;

[0118] Step 28: After forming the shallow trench isolation region, first deposit a metal aluminum layer on the backside, then deposit titanium, nickel, and silver in sequence, and form a bonding pad for the collector after alloying.

[0119] In this embodiment, after Step 27 is completed, that is, after forming the shallow trench isolation region, first deposit a metal aluminum layer Al on the backside, then deposit titanium Ti, nickel Ni, and silver Ag in sequence, and form a bonding pad for the collector C after alloying.

[0120] In the specific implementation process, when the RC-IGBT device is in the blocking state, the gate-emitter is connected to zero potential (i.e., U GE = 0), and a positive voltage U CE (i.e., U CE > 0) is applied between the collector and emitter. Due to the adoption of the n-fs layer, the electric field distribution during the voltage withstand of the RC-IGBT device is trapezoidal. When the RC-IGBT device is conducting forward, a positive voltage U CE (i.e., U CE > 0) is applied between the collector and emitter, and a positive voltage U GE greater than the threshold voltage U T (i.e., U GE > U T ) is applied between the gate and emitter. At this time, electrons in the n + emission region are injected into the n - drift region through the electron channel on the sidewall of the active trench gate. Since the active gates in the IGBT region on the emitter side are located at the leftmost and rightmost sides respectively, and the n + short-circuit region is located in the middle of the p + collector region, the path for electrons in the n + emission region to enter the n + short-circuit region is increased. Moreover, the region without the n-fs layer above the n + short-circuit region and the p floating region above the n + short-circuit region both block electrons. After entering the n-fs layer, electrons will first accumulate continuously above the p + collector region. When the accumulated electrons turn on the J 1 junction, the p + collector region injects holes into the n - drift region, enabling the RC-IGBT device to quickly enter the IGBT conduction mode, thereby eliminating the voltage foldback phenomenon.

[0121] When the RC-IGBT device is turned off, a negative voltage (i.e., U GE = 0) is applied between the gate and emitter. The electron channel is no longer generated on the sidewall of the active trench gate, and electrons in the n + emission region can no longer be injected into the n - drift region, and the IGBT starts to turn off. At the initial stage of turn-off, due to the presence of a large number of non-equilibrium carriers in the n - drift region, the electron channel above the p floating region is in a low-resistance region. Electrons can flow through the electron channel above the p floating region or through the p floating region to the n + short-circuit region, or directly to the p + transparent collector. At the same time, the p base region quickly extracts holes, enabling the IGBT to turn off quickly and reducing the turn-off loss of the device.

[0122] When a reverse voltage (i.e., U AK <0) is applied between the anode (emitter) and cathode (collector) of the RC-IGBT device, the integrated diode conducts in the reverse direction. The p + Ohmic contact region and the p-base region (i.e., the anode region of the diode) inject holes into the n - drift region, and the n + short-circuit region (i.e., the cathode region of the diode) injects electrons into the n - drift region through the spacing between the two p-floating regions (the electron channel in the cathode region), causing a conductivity modulation effect in the n - drift region. As the reverse voltage increases, non-equilibrium carriers accumulate in the p-floating regions, causing the electron injection in the n + short-circuit region to no longer be affected by the p-floating regions, i.e., the n + short-circuit region can inject electrons into the n - drift region through the spacing between the two p-floating regions and the p-floating regions, then the conductivity modulation effect in the n - drift region is enhanced, and the reverse conduction voltage drop decreases.

[0123] When a forward voltage (i.e., U AK >0) is applied between the anode (emitter) and cathode (collector) of the RC-IGBT device, and a negative voltage (i.e., U GE <0) is applied between the gate and emitter, the IGBT does not conduct, and the diode enters the reverse recovery process from conduction. A large number of non-equilibrium carriers stored in the n - drift region during the diode conduction continuously recombine, and the applied voltage can accelerate the extraction of non-equilibrium carriers, shortening the reverse recovery time of the diode.

[0124] In this embodiment, by introducing a locally doped n-fs layer on the collector side and introducing p-floating regions above the n + short-circuit region, the resistance on the collector side is increased, suppressing the voltage fold-back phenomenon of the RC-IGBT device during forward conduction; and by introducing a shallow trench dielectric isolation region between the p + collector region and the n + short-circuit region, it is ensured that the RC-IGBT device will not experience punch-through breakdown during blocking, resulting in a reduction in the blocking voltage; by introducing an emitter trench gate on the emitter side, the channel density of the trench gate IGBT is reduced, improving the short-circuit capability of the IGBT; by introducing an embedded trench emitter on the emitter side, the n +The number of hole flows under the emitter region enables the RC-IGBT device to be less prone to latch-up even under large currents. Further, the RC-IGBT device of this embodiment can not only eliminate the voltage fold-back phenomenon during the forward conduction of the device, reduce the switching loss of the trench-gate IGBT, and is beneficial to reducing the reverse recovery peak current density of the integrated diode, but also has a small cell size, reducing the process difficulty of etching deep trenches and oxide filling using dielectric isolation and junction isolation, and reducing the process cost.

[0125] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that this is only an example. The protection scope of the present invention is defined by the appended claims. Without departing from the principles and essence of the present invention, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. An RC-IGBT device, characterized in that, the RC-IGBT device includes: an n-fs layer, which is arranged on the collector side in a form of local doping; p floating region, disposed above the n + short-circuit region on the collector side; Shallow trench dielectric isolation region, disposed on the p side of the collector + collector region and the n + short-circuit region; an emitter trench gate, which is arranged on the emitter side; an embedded trench emitter, which is arranged on the emitter side.

2. The RC-IGBT device according to claim 1, characterized in that, the RC-IGBT device further includes: An active trench gate, n, disposed on the emitter side + emission region, p + ohmic contact region, p-base region, n-CS layer, and anode region of the integrated diode; the active trench gate, which is used to connect polysilicon to the gate; The p-type base region is provided with a p + ohmic contact region and two n + emitter regions. Aluminum metallized emitters are provided on the surfaces of both of the two n + emitter regions and the p + ohmic contact region; p + The ohmic contact region is connected to the embedded trench emitter to form the anode region of the integrated diode; the n-CS layer, which is located below the p-base region and the bottom of the n-CS layer is lower than the trench bottoms of the active trench gate and the emitter trench gate, and is formed by an inverted doping process.

3. The RC-IGBT device according to claim 1, characterized in that, the emitter trench gate is used to connect polysilicon to the emitter.

4. The RC-IGBT device according to claim 2, characterized in that, The embedded trench emitter is used to connect the emitter to the n + emission region and the p + ohmic contact region respectively.

5. The RC-IGBT device according to claim 1, characterized in that, The p on the collector side + The collector regions are respectively located on both sides of the n - drift region; The n on the collector side + The short-circuit region is located in the n - The p on both sides of the drift region + At the middle position of the collector region.

6. The RC-IGBT device according to claim 1, characterized in that, The n-fs layers are respectively located at n - above the p + collector regions on both sides of the drift region. The n-fs layer located at the left side of the n - drift region has its right boundary connected to the left boundary of the left p floating region, and the right boundary of the n-fs layer is located above the left shallow trench dielectric isolation region; the n-fs layer located at the right side of the n - drift region has its left boundary connected to the right boundary of the right p floating region, and the left boundary of the n-fs layer is located above the right shallow trench dielectric isolation region.

7. The RC-IGBT device according to claim 1, characterized in that, The depth of the shallow trench dielectric isolation region is greater than that of the p + collector region and that of the n + short-circuit region and less than the depth of the n-fs layer.

8. A manufacturing method of an RC-IGBT device, characterized in that, the manufacturing method includes: forming an implantation window of a locally doped n-fs layer through a photomask, implanting high-energy phosphorus ions and performing high-temperature drive-in to form the n-fs layer; forming an implantation window of a locally doped p-floating region through a photomask, implanting boron ions and performing high-temperature drive-in to form the p-floating region; Form a p collector region by boron ion implantation and drive-in + collector region; Form n through a photomask + The implantation window of the short-circuit region, implant high-energy phosphorus ions and drive them to form n + Short-circuit region; then eliminate damage through laser annealing and activate impurities; forming a shallow trench dielectric isolation region through a photomask and oxygen ion implantation.

9. The manufacturing method of the RC-IGBT device according to claim 8, characterized in that, before the step of forming an implantation window of a locally doped n-fs layer through photolithography to implant high-energy phosphorus ions, the manufacturing method further includes: Using the original float zone silicon single crystal as the n - drift region, perform a cleaning process; After the cleaning process, for n - Deposit a sacrificial oxide layer on the top silicon surface of the drift region. Adopt the reverse doping process, use the high-energy phosphorus ion implantation, and form the n-CS layer through high-temperature drive-in and annealing; performing boron ion implantation on the surface of the wafer after the above treatment, and performing high-temperature drive-in and annealing to form the p-base region; For the processed wafer surface forming the p-base region, trenches are formed through a photomask and plasma etching; for the processed wafer surface with trenches formed, a sacrificial oxide layer is formed by deposition and then the sacrificial oxide layer is removed; on the surface of the trenches after the above processing, a gate oxide layer is grown by dry oxidation, and then polysilicon is deposited by low-pressure chemical vapor deposition and etched back; on the upper surface of the wafer processed by depositing polysilicon by low-pressure chemical vapor deposition and etching back, a boron ion implantation window for the p + ohmic contact region is formed, and boron ion implantation is carried out; on the upper surface of the wafer processed by boron ion implantation, As + implantation is carried out, and the p + ohmic contact region and n + emitter region are formed through high-temperature drive-in and annealing; an embedded emitter trench contact hole is formed through a photomask and etching; a layer of phosphosilicate glass is grown by low-pressure chemical vapor deposition, and a passivation layer is formed by photolithography; on the upper surface of the wafer processed with the passivation layer formed, a metal aluminum layer is deposited and etched back, and after alloying, bonding pads for the emitter and gate are formed on the upper surface; after the bonding pads for the emitter and gate are formed, the wafer is flipped, and after back thinning, a sacrificial oxide layer is deposited on its surface.

10. The manufacturing method of the RC-IGBT device according to claim 9, characterized in that, after the step of forming a shallow trench dielectric isolation region through a photomask and oxygen ion implantation, the manufacturing method further includes: after forming the shallow trench dielectric isolation region, first depositing a metal aluminum layer on the back surface, and then sequentially depositing titanium, nickel, and silver, and forming a pressure welding point of the collector after alloying.

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