Manufacturing method of complementary field effect transistor

Abstract

The invention provides a manufacturing method of a complementary field effect transistor. The method comprises the following steps: providing a substrate; forming a nanowire stack structure on the substrate, wherein the nanowire stack structure comprises a bottom structure located below the middle isolation layer and a top structure located above the middle isolation layer; forming a bottom source electrode and a bottom drain electrode on two sides of the bottom structure; forming a top source electrode and a top drain electrode on two sides of the top structure; the method comprises the following steps: removing a first semiconductor layer in a bottom structure, and forming bottom gates in a plurality of formed bottom to-be-filled gaps; the first semiconductor layer in the top structure is removed, and top gates are formed in the plurality of formed top to-be-filled gaps, that is, channels of the top structure and the bottom structure are released step by step, so that the formation of a work function layer of the top structure and the formation of a work function layer of the bottom structure do not influence each other, and the problem of a channel interface is avoided; and the performance of the manufactured complementary field effect transistor is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductors, and in particular to a method for manufacturing a complementary field effect transistor. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. The traditional three-gate or double-gate Fin Field-Effect Transistor (FinFET) is obviously limited by the short channel effect at nodes below 3 nanometers (nm). Nanosheet-Gate all round Fin Field-Effect Transistor (Nanosheet-GAAFET) has been developed to alleviate the 3nm node limitation. Furthermore, the complementary field-effect transistor (CFET) has received widespread attention and research because it can break through the 1nm node limitation.

[0003] Currently, in the process of manufacturing complementary field effect transistors, after the nanosheets are released, a P-type work function layer is first formed around all the nanosheets, and then a gate is deposited around part of the nanosheets. The P-type work function layer on the surface of the nanosheet not surrounded by the gate is removed, and an N-type work function layer is deposited on the surface of the nanosheet, thereby achieving that the nanosheets are surrounded by different types of work function layers, and finally forming a complementary field effect transistor.

[0004] However, the manufacturing process has high requirements for the removal process of the P-type work function layer, and it is easy to damage the surface of the nanosheet in the process of removing the P-type work function layer, causing channel interface problems. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a method for manufacturing a complementary field effect transistor, which can avoid damage to the nanosheet, avoid channel interface problems, and improve the performance of the manufactured complementary field effect transistor.

[0006] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising:

[0007] providing a substrate;

[0008] forming a nanowire stacking structure on the substrate, wherein the nanowire stacking structure comprises a bottom structure located below an intermediate isolation layer and a top structure located above the intermediate isolation layer, wherein the top structure and the bottom structure are formed by alternately stacking a first semiconductor layer and a second semiconductor layer;

[0009] forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure;

[0010] Removing the first semiconductor layer in the bottom structure, and forming a bottom gate in the formed multiple bottom gaps to be filled;

[0011] The first semiconductor layer in the top structure is removed, and a top gate is formed in the formed multiple top gaps to be filled.

[0012] Optionally, the method further comprises:

[0013] forming a release protection layer on the sidewalls of the top structure;

[0014] The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the formed plurality of bottom gaps to be filled comprises:

[0015] The first semiconductor layer of the bottom structure is removed by using the release protection layer as a mask to form a plurality of bottom gaps to be filled, and a bottom gate is formed in the plurality of bottom gaps to be filled.

[0016] Optionally, before forming bottom gates in the plurality of bottom gaps to be filled, the method further comprises:

[0017] A second type work function layer is formed in the plurality of bottom gaps to be filled.

[0018] Optionally, the method further comprises:

[0019] The release protective layer is removed.

[0020] Optionally, before forming a top gate in the plurality of top gaps to be filled, the method further comprises:

[0021] A first type work function layer is formed in the plurality of top gaps to be filled.

[0022] Optionally, when forming the second type work function layer in the plurality of bottom gaps to be filled, the second type work function layer also covers the top structure;

[0023] Before removing the release protection layer, the method further comprises:

[0024] The second type work function layer covering the top structure is removed.

[0025] Optionally, before forming the second type work function layer in the plurality of bottom gaps to be filled, the method further comprises:

[0026] forming a high-K dielectric layer in the plurality of bottom gaps to be filled and on the surface of the top structure;

[0027] The forming of a second type work function layer in the plurality of bottom gaps to be filled comprises:

[0028] forming a second type work function layer on the surface of the high-K dielectric layer;

[0029] The removing the second type work function layer covering the top structure comprises:

[0030] The high-K dielectric layer and the second type work function layer covering the top structure are removed.

[0031] Optionally, the bottom structure and the top structure have the same first semiconductor layer and the same second semiconductor layer, the first semiconductor layer is made of silicon germanium, and the second semiconductor layer is made of silicon;

[0032] The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the bottom gap to be filled comprises:

[0033] The silicon germanium of the bottom structure is removed, and a bottom gate is formed in the bottom gaps to be filled formed between the plurality of silicons;

[0034] The removing of the first semiconductor layer in the top structure and forming a top gate in the formed top gap to be filled comprises:

[0035] The silicon germanium of the top structure is removed, and a top gate is formed in the top gaps to be filled formed between the plurality of silicons.

[0036] Optionally, the materials of the first semiconductor layer of the bottom structure and the second semiconductor layer of the top structure are different, and the materials of the first semiconductor layer of the bottom structure are different, the material of the first semiconductor layer of the bottom structure is silicon, the material of the second semiconductor layer of the bottom structure is silicon germanium, the material of the first semiconductor layer of the top structure is silicon germanium, and the material of the second semiconductor layer of the top structure is silicon;

[0037] The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the bottom gap to be filled comprises:

[0038] The silicon of the bottom structure is removed, and a bottom gate is formed in the bottom gaps to be filled formed between the plurality of silicon germaniums;

[0039] The removing of the first semiconductor layer in the top structure and forming a top gate in the formed top gap to be filled comprises:

[0040] The silicon germanium of the top structure is removed, and a top gate is formed in the top gaps to be filled formed between the plurality of silicons.

[0041] Optionally, the material of the release protection layer is SiO 2 、SiN x , HfO 2 、AlO x 、LaO x , one or more of SiNO, SiCO, SiCNO and SiCN.

[0042] Optionally, the release protection layer has a thickness ranging from 1 to 100 nm.

[0043] The present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate; forming a nanowire stacking structure on the substrate, the nanowire stacking structure comprising a bottom structure located below an intermediate isolation layer and a top structure located above the intermediate isolation layer, the top structure and the bottom structure being composed of a first semiconductor layer and a second semiconductor layer alternately stacked; forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure; first removing the first semiconductor layer in the bottom structure, and forming a bottom gate in a plurality of bottom gaps to be filled; then removing the first semiconductor layer in the top structure, and forming a top gate in a plurality of top gaps to be filled, that is, releasing the channels of the top structure and the bottom structure in steps, so as to facilitate the formation of a work function layer of the top structure and the work function layer of the bottom structure without affecting each other, thereby avoiding channel interface problems and improving the performance of the complementary field effect transistor manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application is shown;

[0046] Figure 2 A schematic diagram of a three-dimensional structure of a complementary field effect transistor provided in an embodiment of the present application is shown;

[0047] 3 to 20 show schematic structural diagrams of manufacturing complementary field effect transistors according to the method for manufacturing complementary field effect transistors provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0050] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0051] Currently, in the process of manufacturing complementary field effect transistors, after the nanosheets on the top and bottom layers are released at the same time, after the nanosheets are released, a P-type work function layer is first formed around all the nanosheets, and then a gate is deposited around the bottom nanosheet. The P-type work function layer on the surface of the top nanosheet not surrounded by the gate is selectively removed, and an N-type work function layer is deposited on the surface of the top nanosheet, thereby achieving the top nanosheet and the bottom nanosheet being surrounded by different types of work function layers, and finally forming a complementary field effect transistor.

[0052] However, the manufacturing process has high requirements for the removal process of the P-type work function layer, and it is easy to damage the surface of the nanosheet in the process of removing the P-type work function layer, causing channel interface problems.

[0053] Based on this, the present application provides a method for manufacturing a complementary field effect transistor, the method comprising: providing a substrate; forming a nanowire stacking structure on the substrate, the nanowire stacking structure comprising a bottom structure located below an intermediate isolation layer and a top structure located above the intermediate isolation layer, the top structure and the bottom structure being composed of a first semiconductor layer and a second semiconductor layer alternately stacked; forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure; first removing the first semiconductor layer in the bottom structure, and forming a bottom gate in the multiple bottom gaps to be filled formed; then removing the first semiconductor layer in the top structure, and forming a top gate in the multiple top gaps to be filled formed, that is, releasing the channels of the top structure and the bottom structure in steps, so as to facilitate the formation of the work function layer of the top structure and the work function layer of the bottom structure without affecting each other, thereby avoiding channel interface problems and improving the performance of the complementary field effect transistor manufactured.

[0054] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0055] See also Figure 1 , which is a schematic flow chart of a method for manufacturing a complementary field effect transistor provided in an embodiment of the present application.

[0056] Figure 2 The figure shows a three-dimensional structure schematic diagram of a complementary field effect transistor provided in an embodiment of the present application. By making cross sections in the XX and YY directions on the three-dimensional structure schematic diagram, the following are obtained respectively: FIG. 3A to FIG. 20A as well as FIG. 3B to FIG. 20B Schematic diagram of the cross-sectional structure of a complementary field effect transistor.

[0057] The method for manufacturing a semiconductor device provided in an embodiment of the present application comprises the following steps:

[0058] S101, providing a substrate.

[0059] In an embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, and the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0060] As an example, impurities may be injected into the bulk silicon substrate, and a highly doped well region may be formed after annealing to achieve the desired well depth. For different device types, the doping type of the substrate 110 is different, wherein for a P-type semiconductor device, the highly doped well region is an N-well, and the injected impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for an N-type semiconductor device, the highly doped well region is a p-well, and the injected impurities are p-type impurity ions, such as boron (B) ions.

[0061] S102, forming a nanowire stacking structure on a substrate, wherein the nanowire stacking structure includes a bottom structure located below the middle isolation layer and a top structure located above the middle isolation layer, wherein the top structure and the bottom structure are formed by alternatingly stacking a first semiconductor layer and a second semiconductor layer.

[0062] In an embodiment of the present application, a nanowire stacking structure can be formed on a substrate 110, the nanowire stacking structure including a bottom structure 520 located below an intermediate isolation layer 200 and a top structure 510 located above the intermediate isolation layer 200, the top structure 510 and the bottom structure 520 being formed by alternatingly stacking a first semiconductor layer 121 and a second semiconductor layer 122.

[0063] The specific process flow is as follows: First, a stacked structure consisting of a first semiconductor layer 121 and a second semiconductor layer 122 alternately stacked can be formed on one side of the substrate 110. Figure 3A and Figure 3B shown.

[0064] Specifically, for different device types, the material of the first semiconductor layer 121 may be the same, and the material of the second semiconductor layer 122 may be the same. For example, for different device types, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. For different device types, the material of the first semiconductor layer 121 may be different, and the material of the second semiconductor layer 122 may also be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon, and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon.

[0065] Considering that the stacked structure can be used to form two transistors of different device types stacked up and down, when the material is silicon, silicon of different doping types can also be used. For example, the material of the second semiconductor layer 122 located in the top structure 510 is P-type doped silicon, and the material of the second semiconductor layer 122 located in the bottom structure 520 can be N-type doped silicon.

[0066] Along the direction perpendicular to the plane where the substrate 110 is located, the stacked structure includes a buffer layer 123 located in the middle region, and the buffer layer 123 is used to separate two transistors of different doping types stacked up and down to be formed later. The material of the buffer layer 123 can be the same as that of the first semiconductor layer 121, and the thickness of the buffer layer 123 can be slightly greater than the thickness of the first semiconductor layer 121.

[0067] As a possible implementation, along the direction perpendicular to the plane where the substrate 110 is located, for different device types, the material of the first semiconductor layer 121 can be the same, the second semiconductor layer 122 can be the same, if the material of the first semiconductor layer 121 is silicon germanium, the proportion of Ge in the first semiconductor layer 121 in the stacked structure gradually increases and then decreases, wherein the proportion of Ge in the buffer layer 123 is the highest. As an example, the proportion of Ge increases from 30% to 60% and then decreases to 30%.

[0068] In practical applications, silicon oxide may be formed on the substrate 110 . The stacked structure may be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0069] In an embodiment of the present application, the stacked structure and a partially thick substrate 100 may be etched to form a fin structure, wherein the fin structure includes a top structure 510 , a bottom structure 520 and a substrate structure 530 , wherein the top structure 510 and the bottom structure 520 are separated by a buffer layer 123 .

[0070] The process flow of forming the fin structure is introduced in detail below.

[0071] S102a, sidewall transfer process.

[0072] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form a first sidewall, and the material of the first sidewall is silicon nitride. The specific formation process is: a sacrificial layer is covered on the stacked structure, and the material of the sacrificial layer can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer is patterned and etched away by photolithography, and silicon nitride material is deposited. Anisotropic etching is then used to etch away the remaining sacrificial layer, so that only the first sidewall is retained on the stacked structure. The first sidewall acts as a hard mask in the subsequent photolithography for forming the fin.

[0073] S102b, forming a fin structure, reference Figure 4A and Figure 4B shown.

[0074] In the embodiment of the present application, the stacked structure and the substrate 110 with a partial thickness can be etched by an etching process to form a plurality of periodically distributed fins, as shown in FIG. Figure 4A and Figure 4B As shown. The first sidewall is used as a mask for etching to form a fin with a stacked structure. The top of the fin is a top structure 510 and a bottom structure 520 formed by the stacked structure. The top structure 510 and the bottom structure 520 are separated by a buffer layer 123. The top structure 510 and the bottom structure 520 are channel regions. The bottom of the fin is a substrate 110, forming a fin as shown in FIG. Figure 4BThe fin shown in FIG. The fin includes not only a stacked structure but also a single crystal silicon structure that penetrates into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin structure will be used to form a nanosheet of a complementary field effect transistor. Although Figure 4B While one fin is shown, it should be understood that any suitable number and configuration of fins may be used in practical applications.

[0075] In practical applications, after the fin structure is formed, the first sidewall spacer may be removed.

[0076] In an embodiment of the present application, in order to avoid damaging the surface of the nanosheet during the process of removing the P-type work function layer of the top structure after the P-type work function layer is formed on the surface of all the nanosheets after the channel is released, a release protection layer 600 can be formed on the side wall of the top structure along the first direction before the channel is released. The release protection layer 600 is used to realize the channel release of the top structure after the bottom structure. When the P-type work function layer is formed on the surface of the nanosheet of the bottom structure, it will not affect the nanosheet of the top structure, thereby avoiding surface damage to the nanosheet due to removal of the P-type work function layer of the top structure, thereby improving the interface performance of the nanosheet of the top structure.

[0077] Specifically, the first direction is the fin line direction, and the first direction is perpendicular to the connection direction of the top source region and the top drain region, that is, the first direction is the YY direction.

[0078] The process flow of forming the release protection layer is specifically introduced below.

[0079] S102c, forming a first dielectric layer covering the fin structure.

[0080] In the embodiment of the present application, an insulating material is deposited to form a first dielectric layer 410 covering the fin structure, and a selective etching back process is performed on the first dielectric layer 410 to expose the top structure 510. Figure 5A and Figure 5B Specifically, the first dielectric layer 410 is etched until it is flush with the surface of the buffer layer 123 . At this time, the first dielectric layer 410 surrounds the bottom structure 520 and the substrate structure 530 .

[0081] As a possible implementation manner, the first dielectric layer 410 is etched back to the position of 1 / 2 of the buffer layer 123 .

[0082] S102d, forming a release protection layer.

[0083] In the embodiment of the present application, a release protection layer 600 is formed on the sidewall of the top structure 510 along the first direction, referring to Fig. 6A and Figure 6B shown.

[0084] Specifically, the material of the release protection layer 600 is SiO 2 、SiN x , HfO 2 、AlO x 、LaO x The release protection layer 600 may be selected from one of SiNO, SiCO, SiCNO and SiCN. The thickness of the release protection layer 600 is in the range of 1-100 nm.

[0085] S102e, forming shallow trench isolation.

[0086] In the embodiment of the present application, a shallow trench isolation 203 (STI) may be formed between different fins. Fig. 7A and Figure 7B shown.

[0087] Specifically, the first dielectric layer 410 formed in S1031 is selectively etched back to expose the three-dimensional fins. Specifically, the first dielectric layer 410 is etched to be flush with the surface where the bottom structure 520 is located, exposing the top structure 510 and the bottom structure 520, thereby forming a shallow trench isolation 203 adjacent to the fin structure. The surface of the shallow trench isolation 203 on the side away from the substrate 110 can be flush with the surface of the side of the stacked structure in the fin structure close to the substrate 110, and can also be higher or lower than the surface. The shallow trench isolation 203 can be formed by a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fin structures.

[0088] In the embodiments of the present application, considering that two transistors of different doping types need to be stacked up and down subsequently, the source and drain of the two transistors need to be formed separately. First, the source and drain regions of the two transistors need to be formed, and then the inner sidewalls need to be formed. The specific process is described in detail below.

[0089] S102f, forming a false gate and a second spacer, reference Fig. 8A and Figure 8B shown.

[0090] In an embodiment of the present application, a dummy gate stack is formed on the exposed fin structure. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204 and a hard mask layer (not shown). The dummy gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gate stack spans the stacked structure on the upper part of the fin structure, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxide, carbide, organic matter, etc.

[0091] In the embodiment of the present application, second spacers 205 can be respectively provided on both sides of the dummy gate stack, and the second spacers 205 on both sides have the same thickness. The material of the second spacers 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0092] S102g, etching the top structure, the buffer layer and the bottom structure to form a top source region, a top drain region, a bottom source region and a bottom drain region, refer to Fig. 9A and Fig. 9B shown.

[0093] In an embodiment of the present application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process. Specifically, the top structure 510, the buffer layer 123 and the bottom structure 520 are etched in the second direction to form a top source region 1101, a top drain region 1102, a bottom source region 1201 and a bottom drain region 1202. The top source region 1101 and the top drain region 1102 are between the top channel region, and the bottom source region 1201 and the bottom drain region 1202 are between the bottom channel region. The first direction is perpendicular to the second direction, and the second direction is the connection direction of the top source region and the top drain region. Among them, the top source region 1101, the top drain region 1102, the bottom source region 1201 and the bottom drain region 1202 no longer have a stacked structure after being etched. Fig. 9A shown.

[0094] S102h, a concave structure is formed.

[0095] In the embodiment of the present application, the first semiconductor layer 121 located in the top structure 510 and the bottom structure 520 is selectively etched along the second direction, that is, the first semiconductor layer 121 of the sidewall of the top structure 510 and the sidewall of the bottom structure 520 is etched away, and the second semiconductor layer 122 is not damaged. The first semiconductor layer 121 forms a concave structure along the second direction compared to the missing portion of the second semiconductor layer 122. In other words, pull-back etching is performed to etch away a portion of the first semiconductor layer 121 from the bottom source region 1201 and the bottom drain region 1202 to the bottom channel region 1203, and a portion of the first semiconductor layer 121 is etched away from the top source region 1101 and the top drain region 1102 to the top channel region 1103. Fig. 10A and Fig. 10B shown.

[0096] While the first semiconductor layer 121 in the top structure 510 and the bottom structure 520 is selectively etched, the buffer layer 123 is also etched away to form a buffer isolation structure. Fig. 10A and Fig. 10B shown.

[0097] S102i, forming the inner wall, reference Fig.11A and Fig. 11B shown.

[0098] In the embodiment of the present application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the bottom structure 520 in the bottom channel region and the top structure 510 in the top channel region, i.e., the periphery of the fin, and the dielectric material is etched to form an inner sidewall 206, which is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. In other words, the concave structure caused by etching in S1043 is filled by the inner sidewall 206, and the material of the inner sidewall 206 can be silicon nitride or silicon oxide.

[0099] In addition to filling the concave structure, the dielectric material also fills the buffer isolation structure, thereby forming the middle isolation layer 200 .

[0100] At this time, the bottom structure 520 is located below the middle isolation layer 200 , and the top structure 510 is located above the middle isolation layer 200 , thereby forming a nanowire stacking structure including the top structure 510 and the bottom structure 520 .

[0101] S103, forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure.

[0102] In the embodiment of the present application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, a bottom source 131 and a bottom drain 132 can be formed in the bottom source region 1201 and the bottom drain region 1202, respectively, that is, a bottom source 131 and a bottom drain 132 are formed on both sides of the bottom structure 520, referring to Fig. 12A and Fig. 12B The surface of the bottom source 131 and the bottom drain 132 away from the substrate 110 may be flush with the surface of the middle isolation layer 200 close to the substrate 110 .

[0103] Specifically, for different types of semiconductor devices, the source material and the drain material may be different. For P-type semiconductor devices, the source and drain materials are boron-doped silicon germanium, i.e., SiGe:B; for N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0104] In the embodiment of the present application, before forming the bottom source 131 and the bottom drain 132, a target sidewall 320 is formed by deposition and etching, and the target sidewall 320 is at least located on the sidewall of the top channel structure, so as to achieve the isolation of the top channel structure, that is, the target sidewall 320 is respectively arranged on both sides of the top channel structure, and the target sidewall 320 on both sides has the same thickness. The material of the target sidewall 320 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0105] In the embodiment of the present application, after forming the target sidewall 320, a bottom source 131 and a bottom drain 132 may be formed in the bottom source region 1201 and the bottom drain region 1202, respectively, and then a dielectric material is deposited and a planarization process is performed to form a first dielectric layer 420, and the first dielectric layer 420 covers the top structure 510 and the target sidewall 320. The first dielectric layer 420 may be etched back to the surface of the side of the intermediate isolation layer 200 away from the substrate 110, and the target sidewall 320 may be etched back to the surface of the side of the intermediate isolation layer 200 away from the substrate 110, that is, the first dielectric layer 420 and the target sidewall 320 are both etched to the intermediate isolation layer 200, thereby achieving isolation between the source and drain of the upper and lower transistors.

[0106] In the embodiment of the present application, after etching back the first dielectric layer 420 and the target sidewall 320, a top source 133 and a top drain 134 may be further formed on the first dielectric layer 420 and the target sidewall 320, that is, a top source 133 and a top drain 134 are formed on both sides of the top structure 510, so as to form a source and a drain of the transistor located at the upper part of the two transistors stacked up and down, as shown in FIG. Fig. 12A The top source 133 and the top drain 134 may be located on the first dielectric layer 420 .

[0107] S104, removing the first semiconductor layer in the bottom structure, and forming a bottom gate in the formed multiple bottom gaps to be filled.

[0108] In the embodiment of the present application, the bottom structure 520 may be firstly channel-released, that is, the first semiconductor layer 121 in the bottom structure 520 is removed, and a bottom gate 161 is formed in the multiple bottom gaps 402 to be filled.

[0109] Before removing the first semiconductor layer 121 in the bottom channel region, the dummy gate 204 may be removed first. The specific process flow is as follows.

[0110] S104a, remove the false gate 204, refer to Fig.13A and Fig. 13B shown.

[0111] In the embodiment of the present application, an isolation layer 207 may be deposited on the surface of the dummy gate 204, the top source 133 and the top drain 134 to prevent the interconnection short circuit between the dummy gate 204 and the top source 133 or the top drain 1342 in the subsequent steps, and the isolation layer 207 may be subjected to a chemical mechanical polishing process to make it flat. Fig.13A and Fig. 13B As shown, the dummy gate 204 formed of the polysilicon or amorphous silicon is etched or corroded by a selective etching or corrosion process, that is, the dummy gate 204 is removed.

[0112] In the embodiment of the present application, the first semiconductor layer 121 in the bottom channel region can be removed by using the release protection layer 600 as a mask, that is, a nanosheet channel release process in the bottom channel region is performed, so as to form a plurality of bottom gaps 402 to be filled between the second semiconductor layer 122 in the bottom channel region, referring to Fig.14A and Fig. 14B shown.

[0113] Specifically, the first semiconductor layer 121 in the stacked structure in the bottom channel region can be selectively etched with the release protection layer 600 as a mask to release the nanosheet channel in the bottom channel region. In other words, the underlying structure exposed by the fin is processed, the first semiconductor layer 121 of each layer in the bottom channel region is removed, and the first semiconductor layer 121 is a sacrificial layer, and the nanosheet formed by the second semiconductor layer 122 is released. Since the release protection layer 600 covering the top structure 510 is formed in a direction perpendicular to the connection direction of the source and drain, the release protection layer 600 can ensure that the top structure 510 is not affected when the bottom structure 520 is released from the channel.

[0114] In the embodiment of the present application, after forming a plurality of bottom gaps to be filled 402, an interface layer may be formed on the surface of the second semiconductor layer 122 and the interface between the interface layer and the second semiconductor layer 122 may be passivated. Specifically, the material of the interface layer may be silicon oxide.

[0115] In the embodiment of the present application, after the interface layer is formed, a high-k dielectric layer may be formed on the surface of the interface layer, and the high-k dielectric layer surrounds the surface of the interface layer. Specifically, the material of the high-k dielectric layer may be HfO 2 、HfSiO x , HfON, HfSiON, HfAlOx, HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、 2 O 5 or La 2 O3 One or a combination of.

[0116] Considering the formation of different types of transistors above and below, it is necessary to use the intermediate isolation layer 200 to isolate different types of transistors and different types of work function layers to realize different types of transistors, and form a second type of work function layer 710 in the plurality of bottom gaps 402 to be filled in the bottom channel region, and the second type of work function layer 710 surrounds the surface of the high-k dielectric layer. Specifically, the second type of work function layer 710 is a P-type work function layer (P-WFL), referring to Fig.15A and Fig. 15B shown.

[0117] When the interface layer, the high-K dielectric layer, and the second type work function layer 710 are formed in the plurality of bottom gaps to be filled 402 in the bottom channel region, the interface layer, the high-K dielectric layer, and the second type work function layer 710 also cover the surface of the top structure 510 away from the substrate 110, the side wall of the release protection layer 600, and the surface of the middle isolation layer 200 close to the substrate 110, referring to Fig.15A and Fig. 15B shown.

[0118] In the embodiment of the present application, a conductive material may be filled in the plurality of bottom gaps to be filled 402 in the bottom channel region to form a bottom gate 161. Specifically, a conductive material is deposited to cover the fin structure, and then the conductive material is etched to a 1 / 2 position of the middle isolation layer 200 to form the bottom gate 161. Fig.16A and Fig. 16B shown.

[0119] After the bottom nanosheet channel is released, there are multiple bottom gaps 402 to be filled between the multiple second semiconductor layers 122, and the bottom gate 161 can be filled in the multiple bottom gaps 402 to be filled. The bottom gate 161 surrounds the second semiconductor layer 122 to form a ring gate structure. Specifically, the bottom gate 161 surrounds the second type work function layer 710. The stack composed of multiple second semiconductor layers 122 forms a bottom channel structure.

[0120] In the embodiment of the present application, after the bottom gate 161 is formed in the plurality of bottom to-be-filled gaps 402 in the bottom channel region, the channel release process of the bottom structure has been completed, and the channel release process of the top structure can be continued.

[0121] Specifically, the interface layer, the high-K dielectric layer, and the second type work function layer 710 covering the top structure 510 and the sidewall of the release protection layer 600 can be removed first, and then the release protection layer 600 covering the sidewall of the top structure 510 can be removed. Fig.17A and Fig. 17B shown.

[0122] S105, removing the first semiconductor layer in the top structure, and forming a top gate in the formed multiple top gaps to be filled.

[0123] In the embodiment of the present application, the first semiconductor layer 121 in the top channel region can be removed, that is, the nanosheet channel release process in the top channel region is performed, so as to form a plurality of top gaps 403 to be filled between the second semiconductor layer 122 in the top channel region, referring to Fig.18A and Fig.18B shown.

[0124] Specifically, the first semiconductor layer 121 in the stacked structure located in the top channel region can be selectively etched to release the nanosheet channel in the top channel region. That is to say, the top structure exposed by the fin is processed, the first semiconductor layer 121 of each layer in the top channel region is removed, the first semiconductor layer 121 is a sacrificial layer, and the nanosheet formed by the second semiconductor layer 122 is released. Since a release protection layer 600 covering the top structure 510 is formed in a direction perpendicular to the connection direction of the source and drain, the release protection layer 600 can realize the channel release of the top structure 510 after the bottom structure 520, and when the top structure 510 is channel released, the bottom structure 520 has formed the bottom gate 161, so the channel release of the top structure 510 will not affect the bottom structure 520.

[0125] In the embodiment of the present application, after forming a plurality of top gaps to be filled 403, an interface layer may be formed on the surface of the second semiconductor layer 122 and the interface between the interface layer and the second semiconductor layer 122 may be passivated. After forming the interface layer, a high-k dielectric layer may also be formed on the surface of the interface layer.

[0126] Considering the formation of different types of transistors above and below, it is necessary to use the intermediate isolation layer 200 to isolate different types of transistors and different types of work function layers to realize different types of transistors, and form a first type work function layer 720 in the top multiple gaps 403 to be filled in the top channel region, and the first type work function layer 720 surrounds the surface of the high-k dielectric layer. Specifically, the first type work function layer 720 is an N-type work function layer (N-WFL), referring to Fig.19A and Fig.19B shown.

[0127] In an embodiment of the present application, since the complementary field effect transistor includes two transistors of different device types stacked up and down, the materials of the first semiconductor layer 121 of different device types can be the same, and the second semiconductor layer 122 can be the same, or the materials of the first semiconductor layer 121 of different device types can be different, and the materials of the second semiconductor layer 122 can also be different. Therefore, when the channel of the bottom structure 520 and the top structure 510 are released, the materials selectively removed may be different, which is described in detail below.

[0128] As a possible implementation, the materials of the first semiconductor layer 121 in the bottom channel region and the top channel region are the same, and the materials of the second semiconductor layer 122 are the same, the material of the first semiconductor layer 121 is silicon germanium, and the material of the second semiconductor layer 122 is silicon. S106 removes the first semiconductor layer 121 in the bottom channel region to form a plurality of bottom gaps 402 to be filled, which is to selectively remove the silicon germanium in the bottom channel region using the release protection layer 600 as a mask, and a plurality of bottom gaps 402 to be filled are formed between the plurality of silicons. S108 removes the first semiconductor layer 121 in the top channel region to form a plurality of top gaps 403 to be filled, which is to selectively remove the silicon germanium in the top channel region, and a plurality of top gaps 403 to be filled are formed between the plurality of silicons. In other words, a silicon stack nanosheet stack device is formed. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used.

[0129] As another possible implementation, the materials of the first semiconductor layer 121 in the bottom channel region and the top channel region are different, and the materials of the second semiconductor layer 122 are different, the material of the first semiconductor layer 121 in the bottom channel region is silicon, the material of the second semiconductor layer 122 in the bottom channel region is silicon germanium, the material of the first semiconductor layer 121 in the top channel region is silicon germanium, and the material of the second semiconductor layer 122 in the top channel region is silicon. S106 removes the first semiconductor layer 121 in the bottom channel region to form a plurality of bottom gaps 402 to be filled, which is to selectively remove the silicon in the bottom channel region by using the release protection layer 600 as a mask, and a plurality of bottom gaps 402 to be filled are formed between the plurality of silicon germaniums. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon germanium can be used. S108 removes the first semiconductor layer 121 in the top channel region to form a plurality of top gaps 403 to be filled, which is to selectively remove silicon germanium in the top channel region, and form a plurality of top gaps 403 to be filled between the plurality of silicons. In the selective removal process, an etchant that selectively etches silicon germanium at a faster rate than silicon can be used. At this time, a heterogeneous complementary field effect transistor is formed in which the bottom channel structure material is silicon germanium and the top channel structure material is silicon, thereby improving the performance of the bottom transistor.

[0130] That is to say, the channel of the top structure can selectively remove the sacrificial layer material different from that of the bottom structure in the secondary channel release based on the release protection layer, so as to form a heterogeneous channel device in which the top channel and the bottom channel are made of different semiconductor materials.

[0131] In the embodiment of the present application, after the top nanosheet channel is released, there are multiple top gaps 403 to be filled between the multiple second semiconductor layers 122, and the top gate can be filled in the multiple top gaps 403 to be filled, and the top gate surrounds the second semiconductor layer 122 to form a ring gate structure. Specifically, the top gate surrounds the first type work function layer 720. The stack composed of the multiple second semiconductor layers 122 forms a top channel structure and a bottom channel structure, that is, a nanosheet channel of a complementary field effect transistor is formed, refer to Fig. 20A and Fig. 20B shown.

[0132] In practical applications, in addition to forming a top gate at the top gap 403 to be filled, the gate 160 also covers the space after the isolation layer 207 and the dummy gate 204 are removed, and the gate 160 covering the isolation layer 207 can be chemically mechanically polished for planarization. The gate 160 includes a top gate and a bottom gate 161.

[0133] In the embodiment of the present application, after the gate 160 is formed, dielectric deposition can be performed on the top of the complementary field effect transistor away from the substrate 110 to form a top dielectric layer. Contact holes are etched in the top dielectric layer until the surface of the top source or the top drain is reached, and metal materials are deposited in the contact holes to form contact electrodes of the top source or the top drain, and then multi-layer back-end interconnection and passivation protection processes are completed.

[0134] It can be seen that the present application provides a method for manufacturing a complementary field effect transistor, forming a source and a drain in the second direction, forming a release protection layer on the side wall of the top structure in the first direction; removing the first semiconductor layer in the bottom channel region with the release protection layer as a mask to form a plurality of bottom gaps to be filled, forming a second type of work function layer in the plurality of bottom gaps to be filled; filling the bottom gate in the plurality of bottom gaps to be filled; removing the release protection layer; removing the first semiconductor layer in the top channel region to form a plurality of top gaps to be filled, forming a first type of work function layer in the plurality of top gaps to be filled; filling the top gate in the plurality of top gaps to be filled, that is, using the release protection layer to realize the channel separation of the top structure and the bottom structure that is, a release protection layer covering the top structure is formed in a direction perpendicular to the connection direction of the source and the drain, and the release protection layer is used to realize the channel release of the top structure after the bottom structure. Based on the release protection layer, the channel of the top structure will not be covered by the second type work function layer in a channel-surrounding manner, thereby overcoming the difficulty in removing the second type work function layer of the current top structure, and avoiding damage to the channel surface when removing the second type work function layer of the top structure. The work function layers of the top structure and the bottom structure are formed separately and will not affect each other, thereby ensuring that the top structure still has a high-quality channel surface, avoiding channel interface problems, and improving the performance of the complementary field effect transistor manufactured.

[0135] The structural embodiments described above are merely illustrative and can be understood and implemented by a person of ordinary skill in the art without any creative effort.

[0136] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A method for manufacturing a complementary field effect transistor, characterized in that: The method comprises: providing a substrate; Forming a nanowire stacking structure on the substrate, the nanowire stacking structure comprising a bottom structure located below an intermediate isolation layer and a top structure located above the intermediate isolation layer, wherein the top structure and the bottom structure are formed by alternately stacking a first semiconductor layer and a second semiconductor layer; forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure; Removing the first semiconductor layer in the bottom structure, and forming a bottom gate in the formed multiple bottom gaps to be filled; The first semiconductor layer in the top structure is removed, and a top gate is formed in the formed multiple top gaps to be filled.

2. The manufacturing method according to claim 1, characterized in that: The method further comprises: forming a release protection layer on the sidewalls of the top structure; The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the formed plurality of bottom gaps to be filled comprises: The first semiconductor layer of the bottom structure is removed by using the release protection layer as a mask to form a plurality of bottom gaps to be filled, and a bottom gate is formed in the plurality of bottom gaps to be filled.

3. The manufacturing method according to claim 2, characterized in that: Before forming bottom gates in the plurality of bottom gaps to be filled, the method further comprises: A second type work function layer is formed in the plurality of bottom gaps to be filled.

4. The manufacturing method according to claim 2, characterized in that: The method further comprises: The release protective layer is removed.

5. The manufacturing method according to claim 4, characterized in that: Before forming a top gate in the plurality of top gaps to be filled, the method further includes: A first type work function layer is formed in the plurality of top gaps to be filled.

6. The manufacturing method according to claim 4, characterized in that: When forming a second type work function layer in the plurality of bottom gaps to be filled, the second type work function layer also covers the top structure; Before removing the release protection layer, the method further comprises: The second type work function layer covering the top structure is removed.

7. The manufacturing method according to claim 6, characterized in that: Before forming a second type work function layer in the plurality of bottom gaps to be filled, the method further includes: forming a high-K dielectric layer in the plurality of bottom gaps to be filled and on the surface of the top structure; The forming of a second type work function layer in the plurality of bottom gaps to be filled comprises: forming a second type work function layer on the surface of the high-K dielectric layer; The removing the second type work function layer covering the top structure comprises: The high-K dielectric layer and the second type work function layer covering the top structure are removed.

8. The manufacturing method according to claim 1, characterized in that: The bottom structure and the top structure have the same first semiconductor layer and the same second semiconductor layer, the first semiconductor layer is made of silicon germanium, and the second semiconductor layer is made of silicon; The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the bottom gap to be filled comprises: The silicon germanium of the bottom structure is removed, and a bottom gate is formed in the bottom gaps to be filled formed between the plurality of silicons; The removing of the first semiconductor layer in the top structure and forming a top gate in the formed top gap to be filled comprises: The silicon germanium of the top structure is removed, and a top gate is formed in the top gaps to be filled formed between the plurality of silicons.

9. The manufacturing method according to claim 1, characterized in that: The materials of the first semiconductor layer of the bottom structure and the second semiconductor layer of the top structure are different, the material of the first semiconductor layer of the bottom structure is silicon, the material of the second semiconductor layer of the bottom structure is silicon germanium, the material of the first semiconductor layer of the top structure is silicon germanium, and the material of the second semiconductor layer of the top structure is silicon; The removing of the first semiconductor layer in the bottom structure and forming a bottom gate in the bottom gap to be filled comprises: The silicon of the bottom structure is removed, and a bottom gate is formed in the bottom gaps to be filled formed between the plurality of silicon germaniums; The removing of the first semiconductor layer in the top structure and forming a top gate in the formed top gap to be filled comprises: The silicon germanium of the top structure is removed, and a top gate is formed in the top gaps to be filled formed between the plurality of silicons.

10. The manufacturing method according to any one of claims 2 to 9, characterized in that: The material of the release protection layer is SiO2, SiN x 、HfO2、AlO x 、LaO x , one or more of SiNO, SiCO, SiCNO and SiCN.

11. The manufacturing method according to any one of claims 2 to 9, characterized in that: The thickness of the release protection layer is in the range of 1-100 nm.

Images