Mosfet device with single crystal substrate as epitaxial region and manufacturing method of mosfet device

Abstract

The invention discloses a mosfet device with a single crystal substrate as an epitaxial region and a manufacturing method. The manufacturing method comprises the following steps: manufacturing a gate interconnection structure, a trench gate and a voltage-withstanding ring on a high-resistivity substrate; forming a body region and a source region through ion implantation and high-temperature activation; depositing an isolation layer, and manufacturing a grid interconnection contact, a source region contact and a cut-off ring contact; gate metal, source metal and cut-off ring metal are manufactured; and thinning the back surface of the substrate and forming drain metal. In the invention, the high-resistivity substrate is adopted to replace a low-resistivity substrate, and the original trapezoidal doping concentration of the substrate can be diffused to realize the doping concentration redistribution through a high-temperature step in the manufacturing process, so that the doping concentration equivalent to that of a voltage-withstanding layer is obtained on the substrate, and the required voltage-withstanding specification of the mosfet device is realized; and an epitaxial layer does not need to be grown, so that the manufacturing process is simplified, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductor devices, and particularly relates to a MOSFET device with a single crystal substrate as an epitaxial region and a manufacturing method thereof. Background Art

[0002] The Bi-directional MOSFET device of CSP (Chip Scale Package) is mainly used in charge and discharge protection circuits. The conduction current between its substrate and backside metal is in the horizontal direction. Its resistance is composed of the epitaxial layer resistance, substrate resistance, and backside metal resistance, among which the epitaxial layer resistance and substrate resistance are significantly higher than the metal resistance. The above structure requires growing a relatively thick epitaxial layer, and the growth of the epitaxial layer increases the process steps and manufacturing costs. Summary of the Invention

[0003] Aiming at the deficiencies of the above prior art, the technical problem to be solved by the present invention is: to provide a MOSFET device with a single crystal substrate as an epitaxial region and a manufacturing method thereof.

[0004] To solve the above technical problem, the present invention provides the following technical solutions:

[0005] A manufacturing method of a MOSFET device with a single crystal substrate as an epitaxial region, comprising the following steps:

[0006] S110. Take a high-resistivity substrate;

[0007] S120. Form trenches on the substrate through photolithography and etching; the trenches include a plurality of gate interconnection trenches, a plurality of active region gate trenches, and a plurality of breakdown voltage ring trenches;

[0008] S130. Form a gate interconnection structure in the gate interconnection trenches, form trench gates in the active region gate trenches, and form breakdown voltage rings in the breakdown voltage ring trenches;

[0009] S140. Perform ion implantation and high-temperature activation of the body region, and ion implantation and high-temperature activation of the source region;

[0010] S150. Deposit an isolation layer, and fabricate gate interconnection contacts, source contacts, and cutoff ring contacts penetrating the isolation layer; the gate interconnection contacts are connected to the gate interconnection structure, the source contacts are connected to the source regions, and the cutoff ring contacts are connected to the outermost breakdown voltage rings;

[0011] S160. Deposit metal on the isolation layer and form pads through photolithography and etching. The pads include gate metal connected to the gate interconnection contact, source metal connected to the source region, and cutoff ring metal connected to the cutoff ring. The gate metal, source metal, and cutoff ring metal are isolated from each other.

[0012] S180. Thinning the back of the substrate, and then forming drain metal on the back of the substrate.

[0013] Further, the average doping concentration of the substrate is E16 cm -3 ~E17 cm -3 ; the thickness of the substrate is 700 μm to 800 μm.

[0014] Further, the step S130 includes the following sub-steps:

[0015] S131. Grow a sacrificial oxide layer in the trench and remove the sacrificial oxide layer by chemical etching.

[0016] S132. Grow a gate oxide layer in the trench.

[0017] S133. Deposit polysilicon, and remove the polysilicon outside the trench by chemical mechanical polishing planarization and etching to form a gate interconnection structure in the gate interconnection trench, a trench gate in the active region gate trench, and a breakdown voltage ring in the breakdown voltage ring trench.

[0018] Further, by controlling the temperature during the processes of growing the sacrificial oxide layer, growing the gate oxide layer, high-temperature activation after ion implantation in the body region, and high-temperature activation after source region ion implantation, the trapezoidal doping concentration of the substrate is redistributed through diffusion to obtain a doping concentration equivalent to that of the breakdown voltage layer on the substrate.

[0019] Further, the step S150 includes the following sub-steps:

[0020] S151. Deposit silicon dioxide on the substrate to form an isolation layer.

[0021] S152. Form a through contact hole in the isolation layer. The contact hole includes a gate interconnection contact hole extending into the gate interconnection structure, an active region contact hole extending into the source region, and a cutoff ring contact hole extending into the outer breakdown voltage ring.

[0022] S153. Form a gate interconnection contact in the gate interconnection contact hole, a source contact in the active region contact hole, and a cutoff ring contact in the cutoff ring contact hole by depositing metal.

[0023] Further, after performing the step S160, the following steps are also performed:

[0024] S170. Deposit a passivation layer and form a protective layer through photolithography and etching. The protective layer includes a first protective layer formed between the gate metal and the source metal, and a second protective layer formed on the upper end and its periphery of the cutoff ring metal.

[0025] Further, before performing the step S120, the following steps are first performed:

[0026] S111. Grow a thin epitaxial layer doped with undoped impurities or extremely low-concentration impurities on the substrate.

[0027] Further, the impurity doping concentration of the thin epitaxial layer doped with extremely low-concentration impurities is E12 cm -3 ~E13 cm -3 .

[0028] Further, the thickness of the thin epitaxial layer is determined according to different breakdown voltage specifications, and the thickness of the thin epitaxial layer is 3 μm to 20 μm.

[0029] A MOSFET device using a single-crystal substrate as an epitaxial region is fabricated by using the MOSFET device manufacturing method using any one of the above single-crystal substrates as an epitaxial region.

[0030] In the present invention, the resistivity of the substrate is adjusted by thermal operation in cooperation with the high-temperature process during the manufacturing process. A high-resistivity substrate meeting the resistivity requirements of the breakdown voltage layer of the MOSFET device is used to replace the low-resistivity substrate. By controlling the temperature in the high-temperature process, the original trapezoidal doping concentration of the substrate can be redistributed through diffusion, so as to obtain a doping concentration equivalent to that of the breakdown voltage layer on the substrate, enabling the MOSFET device to achieve the required breakdown voltage specification. Since the present invention does not require growing an epitaxial layer, the manufacturing process of the MOSFET device is simplified, and the manufacturing cost of the MOSFET device is reduced. Description of the Drawings

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0032] Figure 1 is a schematic structural diagram of a MOSFET device in the prior art.

[0033] Figure 2 is a flowchart of an embodiment of the MOSFET device manufacturing method using a single-crystal substrate as an epitaxial region of the present invention.

[0034] Figure 3 is a schematic structural diagram after forming the trench.

[0035] Figure 4 It is a schematic diagram of the structure after growing the gate oxide layer.

[0036] Figure 5 It is a schematic diagram of the structure after forming the gate interconnection structure, trench gate, and breakdown voltage ring.

[0037] Figure 6 It is a schematic diagram of the structure after forming the body region and source region.

[0038] Figure 7 It is a schematic diagram of the structure after depositing the isolation layer and fabricating the gate interconnection contact, source region contact, and cutoff ring contact.

[0039] Figure 8 It is a schematic diagram of the structure after forming the gate metal, source metal, and cutoff ring metal.

[0040] Figure 9 It is a schematic diagram of the structure after forming the protective layer and fabricating the drain metal.

[0041] Figure 10 It is a flowchart of another embodiment of the method for manufacturing a MOSFET device with the single crystal substrate of the present invention as the epitaxial region.

[0042] Figure 11 It is a schematic diagram of the structure after growing a thin epitaxial layer.

[0043] Figure 12 It is a schematic diagram of the structure after completion of another embodiment.

[0044] The reference numerals in the specification are as follows:

[0045] Substrate - 100; Gate contact region - 101; Active region - 102; Terminal region - 103; Epitaxial layer - 110; Thin epitaxial layer - 111; Body region - 120; Source region - 130; Isolation layer - 140; Drain metal - 150; Gate metal - 161; Source metal - 162; Cutoff ring metal - 163; First protective layer - 171; Second protective layer - 172; Gate oxide layer - 201; Gate interconnection trench - 210; Gate interconnection structure - 211; Active region gate trench - 220; Trench gate - 221; Breakdown voltage ring trench - 230; Breakdown voltage ring - 231; Gate interconnection contact hole - 310; Gate interconnection contact - 311; Active region contact hole - 320; Source region contact - 321; Cutoff ring contact hole - 330; Cutoff ring contact - 331; First sub - chip - 910; Second sub - chip - 920. Detailed implementation manners

[0046] The following describes the implementation manners of the present invention through specific specific examples. The diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0047] Please refer to Figure 1 , in the existing MOSFET device structure, it is necessary to grow a relatively thick epitaxial layer 110, and growing the epitaxial layer 110 increases the process steps and manufacturing costs of manufacturing the MOSFET device.

[0048] Embodiment 1

[0049] Please refer to Figure 2 , Figure 2 is a flowchart of an embodiment of a method for manufacturing a MOSFET device with a single-crystal substrate as an epitaxial region according to the present invention. Hereinafter, taking each group of chips including two sub-chips (i.e., the first sub-chip 910 and the second sub-chip 920) as an example to illustrate this embodiment. Of course, when each group of chips only includes one sub-chip, the manufacturing method of this embodiment can also be adopted. The method for manufacturing a MOSFET device with a single-crystal substrate as an epitaxial region in this embodiment includes the following steps:

[0050] S110. Take a high-resistivity substrate 100. Conventional MOSFET devices generally use low-resistivity substrates, and their doping concentrations are relatively high (the higher the doping concentration of the substrate 100, the lower the resistivity). In order to omit the step of growing the epitaxial layer in this embodiment, a high-resistivity substrate 100 (i.e., a substrate 100 with a lower doping concentration) is used to replace the low-resistivity substrate in the manufacturing process of conventional MOSFET devices (the specific resistivity value of the substrate 100 can be adjusted in combination with the thermal calculation of subsequent high-temperature processes to enable the MOSFET device to achieve the required breakdown voltage specification). In this embodiment, the average doping concentration of the substrate 100 is E16cm -3 ~E17cm -3 , so that the substrate 100 has a relatively high resistivity. The thickness of the substrate 100 is generally 700 μm to 800 μm, preferably 775 μm.

[0051] S120. Please refer to Figure 3 , and form trenches on the substrate 100 through photolithography and etching. The trenches include a plurality of gate interconnection trenches 210 for forming a gate contact region 101, a plurality of active region gate trenches 220 formed in the active region 102, and a plurality of breakdown voltage ring trenches 230 formed in the terminal region 103.

[0052] S130. Form a gate interconnection structure 211 in the gate interconnection trenches 210, form a trench gate 221 in the active region gate trenches 220, and form a breakdown voltage ring 231 in the breakdown voltage ring trenches 230. This step may include the following sub-steps:

[0053] S131. Grow a sacrificial oxide layer in the trenches (i.e., the gate interconnect trench 210, the active region gate trench 220, and the breakdown voltage ring trench 230), and remove the sacrificial oxide layer by chemical etching.

[0054] S132. Refer to Figure 4 , and grow a gate oxide layer 201 in the trenches.

[0055] In the above steps S131 and S132, the high-temperature processes in the two processes of growing oxide layers (i.e., growing the sacrificial oxide layer and growing the gate oxide layer 201) will cause a preliminary redistribution of the impurity doping concentration in the substrate 100.

[0056] S133. Refer to Figure 5 , deposit polysilicon, and remove the polysilicon outside the trenches by chemical mechanical polishing planarization and etching. Thus, a gate interconnect structure 211 is formed in the gate interconnect trench 210, a trench gate 221 is formed in the active region gate trench 220, and a breakdown voltage ring 231 is formed in the breakdown voltage ring trench 230.

[0057] S140. Refer to Figure 6 , perform ion implantation and high-temperature activation of the body region 120 and ion implantation and high-temperature activation of the source region 130. Through the two high-temperature activation steps of the body region 120 and the source region 130 (especially the high-temperature activation of the body region 120), the redistribution of the impurity doping concentration in the substrate 100 can be continued on the basis of the previous two high-temperature steps of growing oxide layers, so as to finally achieve the desired doping concentration distribution in the device design on the substrate 100.

[0058] In the foregoing four high-temperature steps, by adjusting the doping concentration of the substrate 100, through the concentration gradient existing in the substrate 100 itself and the high-temperature thermal budget of the subsequent main process (the temperature is between 90 °C and 1200 °C, and the main step time is between 30 min and 60 min), the doping concentration of the substrate 100 is redistributed to obtain a doping concentration similar to that of the breakdown voltage layer (the doping concentration is between E14cm -3 ~E16cm -3 ), so that the mosfet device can achieve the corresponding breakdown voltage specification. Of course, in addition to selecting the initial doping concentration of the substrate 100 according to the change of the doping concentration distribution in the four high-temperature steps, the temperature in the four high-temperature steps can also be finely adjusted so that the doping concentration of the substrate 100 can more accurately reach the designed desired doping concentration distribution after redistribution.

[0059] S150. Refer to Figure 7, deposit the isolation layer 140, and fabricate the gate interconnection contact 311, source region contact 321, and cutoff ring contact 331 that penetrate the isolation layer 140. Among them, the gate interconnection contact 311 is connected to the gate interconnection structure 211, the source region contact 321 is connected to the source region 130, and the cutoff ring contact 331 is connected to the outermost (i.e., the side of the breakdown voltage ring 231 away from the active region 130) breakdown voltage ring 231. This step may include the following sub-steps:

[0060] S151: Deposit silicon dioxide on the substrate 100 to form the isolation layer 140.

[0061] S152: Form penetrating contact holes on the isolation layer 140. The contact holes include the gate interconnection contact hole 310 extending into the gate interconnection structure 211, the active region contact hole 320 extending into the source region 130, and the cutoff ring contact hole 330 extending into the outermost breakdown voltage ring 231.

[0062] S153: Form the gate interconnection contact 311 in the gate interconnection contact hole 310, the source region contact 321 in the active region contact hole 320, and the cutoff ring contact 331 in the cutoff ring contact hole 330 by depositing metal.

[0063] S160: Please refer to Figure 8 , perform metallization deposition on the isolation layer 140, and form pads through photolithography and etching. The pads include the gate metal 161 connected to the gate interconnection contact 311, the source metal 162 connected to the source region contact 321, and the cutoff ring metal 163 connected to the cutoff ring contact 331; the gate metal 161, source metal 162, and cutoff ring metal 163 are isolated from each other.

[0064] S170: Please refer to Figure 9 , deposit a passivation layer, and form a protective layer through photolithography and etching. The protective layer includes the first protective layer 171 formed between the gate metal 161 and the source metal 162, and the second protective layer 172 formed on the upper end and its periphery of the cutoff ring metal 163.

[0065] S180: Please continue to refer to Figure 9 , perform back thinning on the substrate 100, and then form the drain metal 150 on the back surface of the substrate 100.

[0066] In this embodiment, a substrate 100 with a high resistivity is used to replace the low-resistance substrate. According to the resistivity requirements of the voltage-bearing layer of the MOSFET device, the resistivity of the substrate 100 is adjusted in coordination with the thermal operation of the subsequent high-temperature process. By controlling the temperature during the processes of growing the sacrificial oxide layer, growing the gate oxide layer 201, high-temperature activation after ion implantation in the body region 120, and high-temperature activation after ion implantation in the source region 130, the original trapezoidal doping concentration of the substrate 100 is redistributed through diffusion, so as to obtain a doping concentration equivalent to that of the voltage-bearing layer on the substrate 100, enabling the MOSFET device to achieve the corresponding voltage withstand specification. Since no epitaxial layer needs to be grown in this embodiment, the manufacturing process of the MOSFET device is simplified, and the manufacturing cost of the MOSFET device is reduced.

[0067] Embodiment 2

[0068] Please refer to Figure 10 , Figure 10 , which is a flowchart of an embodiment of a method for manufacturing a MOSFET device with a single-crystal substrate as an epitaxial region according to the present invention. In this embodiment, it is still assumed that each group of chips includes two sub-chips (i.e., the first sub-chip 910 and the second sub-chip 920) for illustration.

[0069] By comparing Figure 10 and Figure 2 , it can be seen that the difference between this embodiment and Embodiment 1 is that before performing the step S120, the following steps are first performed:

[0070] S111. Please refer to Figure 11 , and grow a thin epitaxial layer 111 doped with no impurities or extremely low-concentration impurities on the substrate 100. When growing a thin epitaxial layer 111 doped with extremely low-concentration impurities on the substrate 100, the impurity doping concentration of the thin epitaxial layer 111 is E12cm -3 ~E13cm -3 (the impurity doping concentration of the epitaxial layer 110 grown during the manufacturing process of traditional MOSFET devices is generally E18cm -3 ~E19cm -3 ). The thickness of the thin epitaxial layer 111 is determined according to different voltage withstand specifications of the MOSFET device. The thickness range of the thin epitaxial layer 111 is generally 3μm to 20μm, which is much smaller than the thickness of the epitaxial layer in conventional MOSFET devices. For example, when V ds = 30V, the thickness of the thin epitaxial layer 111 is generally 3μm to 5μm. When V ds = 100V, the thickness of the thin epitaxial layer 111 is generally 8μm to 10μm. Among them, V ds represents the voltage withstand specification of the MOSFET device.

[0071] Please refer toFigure 12 The MOSFET device with the single-crystal substrate fabricated by the method of this embodiment as the epitaxial region has a thin epitaxial layer 111 with a thickness much smaller than that of the epitaxial layer 110 in the traditional MOSFET device compared with Embodiment 1. In this embodiment, by adding a thin epitaxial layer 111 doped with undoped impurities or extremely low-concentration impurities, a higher concentration of the substrate 100 can be achieved, thereby reducing the resistivity of the substrate 100 in the finished MOSFET device.

[0072] Embodiment 3

[0073] The present invention also discloses a MOSFET device with a single-crystal substrate as the epitaxial region, and the MOSFET device can be fabricated by using the method for fabricating a MOSFET device with a single-crystal substrate as the epitaxial region in any of the above embodiments.

[0074] The MOSFET device in this embodiment simplifies the manufacturing process, reduces the manufacturing cost, and can achieve the required breakdown voltage specification.

[0075] The above embodiments only represent the preferred embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region, characterized in that: The following steps are involved: S110, obtaining a high resistivity substrate; S120, forming grooves on the substrate by photolithography and etching; the grooves include a plurality of gate interconnection grooves, a plurality of active region gate grooves and a plurality of voltage-resistant ring grooves; S130, forming a gate interconnect structure in the gate interconnect trench, forming a trench gate in the active region gate trench, and forming a voltage-resistant ring in the voltage-resistant ring trench; S140, performing ion implantation and high temperature activation in the body region and ion implantation and high temperature activation in the source region; S150, depositing an isolation layer, and manufacturing a gate interconnection contact, a source region contact, and a cutoff ring contact penetrating the isolation layer; the gate interconnection contact is connected to the gate interconnection structure, the source region contact is connected to the source region, and the cutoff ring contact is connected to the outer voltage-resistant ring; S160, performing metallization deposition on the isolation layer, and forming a pad by photolithography and etching, wherein the pad includes a gate metal connected to the gate interconnect, a source metal connected to the source region, and a stop ring metal connected to the stop ring; the gate metal, the source metal, and the stop ring metal are isolated from each other; S180, thinning the back side of the substrate, and then forming a drain metal on the back side of the substrate.

2. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 1, characterized in that: The average doping concentration of the substrate is E16cm -3 ~E17cm -3 ; The thickness of the substrate is 700μm to 800μm.

3. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 1, characterized in that: The step S130 includes the following sub-steps: S131, growing a sacrificial oxide layer in the groove, and removing the sacrificial oxide layer by chemical etching; S132, growing a gate oxide layer in the trench; S133, depositing polysilicon, and removing the polysilicon outside the groove by chemical mechanical polishing and etching, forming a gate interconnection structure in the gate interconnection groove, forming a trench gate in the active area gate groove, and forming a voltage-resistant ring in the voltage-resistant ring groove.

4. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 3, characterized in that: By controlling the temperature during the growth of the sacrificial oxide layer, the growth of the gate oxide layer, the high-temperature activation of the body region after ion implantation, and the high-temperature activation of the source region after ion implantation, the trapezoidal doping concentration of the substrate is redistributed through diffusion, thereby obtaining a doping concentration on the substrate equivalent to that of the voltage-resistant layer.

5. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 1, characterized in that: The step S150 includes the following sub-steps: S151, depositing silicon dioxide on the substrate to form an isolation layer; S152, forming penetrating contact holes on the isolation layer; the contact holes include a gate interconnection contact hole extending into the gate interconnection structure, an active region contact hole extending into the source region, and a stop ring contact hole extending into the outer voltage-resistant ring; S153, forming a gate interconnect contact in the gate interconnect contact hole, forming a source region contact in the active region contact hole, and forming a stop ring contact in the stop ring contact hole by depositing metal.

6. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 1, characterized in that: After executing the step S160, the following steps are further performed: S170, depositing a passivation layer, and forming a protection layer by photolithography and etching, wherein the protection layer includes a first protection layer formed between the gate metal and the source metal, and a second protection layer formed on the upper end of the stop ring metal and its periphery.

7. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to any one of claims 1 to 6, characterized in that: Before executing the step S120, the following steps are performed: S111 , growing a thin epitaxial layer that is not doped with impurities or is doped with impurities at a very low concentration on the substrate.

8. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 7, characterized in that: The impurity doping concentration of the extremely low-concentration impurity-doped thin epitaxial layer is E12cm -3 ~E13cm -3 .

9. The method for manufacturing a MOSFET device using a single crystal substrate as an epitaxial region according to claim 7, characterized in that: The thickness of the thin epitaxial layer is determined according to different withstand voltage specifications, and the thickness of the thin epitaxial layer is 3 μm to 20 μm.

10. A MOSFET device with a single crystal substrate as an epitaxial region, characterized in that: The MOSFET device is manufactured by the method for manufacturing a MOSFET device using the single crystal substrate as described in any one of claims 1 to 9 as the epitaxial region.

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