PN Shallow Junction Composite Terminal of SiC VDMOS and Preparation Method

Abstract

The present invention provides a PN shallow junction composite terminal and a preparation method thereof for a silicon carbide VDMOS. The method includes: epitaxially growing on a silicon carbide substrate to form a drift layer; forming a blocking layer above the drift layer, etching, and ion implanting to form a first P+ doped region, a P+ well region, a cut-off ring contact region, a second P+ doped region, and an N-doped region. The PN shallow junction includes the second P+ doped region and the N-doped region; reforming the blocking layer, etching, and depositing to form an insulating dielectric region; reforming the blocking layer, etching, and depositing to form an insulating layer; reforming the blocking layer, etching, and depositing to form a capacitive metal layer; reforming the blocking layer, etching, and depositing to form a high-resistivity conductor layer; reforming the blocking layer, etching, and depositing to form a source metal layer and a cut-off ring metal layer, removing the blocking layer, and laterally expanding the electric field at the main junction of the device towards the cut-off ring metal direction to reduce the electric field intensity and improve the device reliability.

Description

Technical Field

[0001] The present invention relates to a PN shallow junction composite terminal of a silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion.

[0003] Based on the device structure design, due to the transverse distribution of the electric field at the edge of the repeating cell, electric field concentration occurs in the transverse direction, resulting in breakdown at the device edge. The traditional cell uses a field limiting ring structure with the same doping concentration to suppress electric field concentration. Since the doping concentration and spacing distribution of the field limiting ring are equal, the electric field intensity distribution gradually decreases, and there are still high and low differences in the electric field distribution. The breakdown risk in the area near the P+ well region is still relatively high, and a relatively large number of field limiting rings are required to achieve the breakdown voltage of the device terminal, and area needs to be sacrificed to obtain the breakdown voltage. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a PN shallow junction composite terminal of a silicon carbide VDMOS and a preparation method thereof, which avoids the problem of high process difficulty in realizing a deep trench terminal, and saves the width of the terminal structure while ensuring the breakdown voltage capability of the terminal.

[0005] In a first aspect, the present invention provides a preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS, including the following steps:

[0006] Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer;

[0007] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a first P+ doping region;

[0008] Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to respectively form a P+ well region and a cutoff ring contact region;

[0009] Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a second P+ doping region;

[0010] Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N- doping region. The PN shallow junction includes the second P+ doping region and the N- doping region;

[0011] Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the first P+ doping region to form a groove, and deposit an insulating medium to form an insulating medium region;

[0012] Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, deposit, and form an insulating layer;

[0013] Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and etch the insulating layer to form at least three trenches, deposit metal, and form a capacitor metal layer;

[0014] Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, deposit, and form a high-resistivity conductor layer;

[0015] Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal, form a source metal layer and a cutoff ring metal layer, and remove the blocking layer.

[0016] In a second aspect, the present invention provides a PN shallow junction composite terminal of a silicon carbide VDMOS, and the silicon carbide VDMOS is prepared by using the preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS described in the first aspect.

[0017] The advantages of the present invention are as follows:

[0018] 1. By constructing a first P+ doped region beside the P+ well region in the present invention, the first P+ doped region wraps the insulating dielectric region, and pushes the electric field of the main junction towards the inside of the device, so that the concentration of the electric field of the main junction of the device is alleviated;

[0019] 2. The present invention constructs a PN shallow junction, and the PN shallow junction includes a second P+ doped region and an N- doped region. The shallow junction formed by the second P+ doped region and the drift layer can prevent the field limiting ring from being depleted in advance, and provide more negative charges after depletion, sharing the electric fields of the main junction and the previous PN shallow junction. The N- doped region reduces the doping concentration on the right side of the field limiting ring, thereby reducing the peak value of the surface electric field on the right side of the PN shallow junction and avoiding being broken down in advance;

[0020] 3. The present invention constructs a high-resistivity conductor layer and a capacitor metal layer. The high-resistivity conductor layer realizes the uniform distribution of voltage from the source metal layer to the cutoff ring metal layer, thereby realizing the uniform distribution of electric field between the PN shallow junctions. The capacitor metal layer and the insulating layer can increase the capacitance effect through a thinner insulating layer, and improve the capacitance effect of the N- doped region. Description of the Drawings

[0021] The following further describes the present invention with reference to the accompanying drawings in conjunction with embodiments.

[0022] Figure 1 It is a schematic diagram of a PN shallow junction composite terminal of a silicon carbide VDMOS of the present invention.

[0023] Figure 2Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 1 。

[0024] Figure 3 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 2 。

[0025] Figure 4 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 3 。

[0026] Figure 5 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 4 。

[0027] Figure 6 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 5 。

[0028] Figure 7 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 6 。

[0029] Figure 8 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 7 。

[0030] Figure 9 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 8 。

[0031] Figure 10 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 9 。

[0032] Figure 11 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 10 。

[0033] Figure 12 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 10 I.

[0034] Figure 13 Process cross-section of the PN shallow junction composite terminal of a silicon carbide VDMOS according to the present invention Figure 10 II. Detailed implementation mode

[0035] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, a first element, component, region, layer, doping type or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0038] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0039] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0040] As Figures 1 to 13 shown, an embodiment of the present application provides a method for preparing a PN shallow junction composite terminal of a silicon carbide VDMOS, including the following steps:

[0041] Step 1: Epitaxially grow on a silicon carbide substrate 1 to form a drift layer 2;

[0042] Step 2: Form a blocking layer 9 above the drift layer 2, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a first P+ doped region 22;

[0043] Step 3: Remove the blocking layer 9 in Step 2, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to respectively form a P+ well region 21 and a cutoff ring contact region 24;

[0044] Step 4: Remove the blocking layer 9 in Step 3, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a second P+ doped region 231;

[0045] Step 5: Remove the blocking layer 9 in Step 4, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form an N- doped region 232. The PN shallow junction 23 includes the second P+ doped region 231 and the N- doped region 232;

[0046] Step 6: Remove the blocking layer 9 in Step 5, reform the blocking layer 9, etch the blocking layer to form a through hole, and etch the first P+ doped region 22 to form a groove 222, and deposit an insulating medium to form an insulating medium region 221;

[0047] Step 7: Remove the blocking layer 9 in Step 6, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit to form an insulating layer 3;

[0048] Step 8: Remove the blocking layer 9 in Step 7, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and etch the insulating layer 3 to form at least three trenches 31, and deposit metal to form a capacitive metal layer 4;

[0049] Step 9: Remove the barrier layer 9 of Step 8, reform the barrier layer 9, etch the barrier layer 9 to form a via hole, deposit, and form a high-resistivity conductor layer 7;

[0050] Step 10: Remove the barrier layer 9 of Step 9, reform the barrier layer 9, etch the barrier layer 9 to form a via hole, deposit metal, form a source metal layer 5 and a cutoff ring metal layer 6, and remove the barrier layer 9.

[0051] In this embodiment, preferably, the left side surface of the second P+ doped region 231 of the leftmost PN shallow junction 23 is connected to the right side surface of the first P+ doped region 22, and the right side surface of the N- doped region 232 of the rightmost PN shallow junction 23 is connected to the left side surface of the cutoff ring contact region 24, and the second P+ doped region 231 and the N- doped region 232 do not contact; the capacitor metal layer 4 is located directly above the N- doped region 232.

[0052] In this embodiment, preferably, the widths of both the second P+ doped region 231 and the N- doped region 232 are equal.

[0053] In this embodiment, preferably, the doping concentration of the first P+ doped region 22 is greater than the doping concentration of the second P+ doped region 231, and the doping concentration of the second P+ doped region 231 is greater than the doping concentration of the N- doped region 232.

[0054] In this embodiment, preferably, the thickness of the PN shallow junction 23 is greater than the thickness of the P+ well region 21, and the thickness of the PN shallow junction 23 is less than the thickness of the first P+ doped region 22.

[0055] In this embodiment, preferably, the thickness of the first P+ doped region 22 is greater than the thickness of the P+ well region 21.

[0056] As Figure 1 shown, the terminal obtained by the above manufacturing method includes:

[0057] A silicon carbide substrate 1,

[0058] A drift layer 2, the lower side surface of the drift layer 2 is connected to the upper side surface of the silicon carbide substrate 1; the drift layer 2 is provided with a P+ well region 21, a first P+ doped region 22, at least three PN shallow junctions 23, and a cutoff ring contact region 24, the PN shallow junctions 23 are provided between the first P+ doped region 22 and the cutoff ring contact region 24, and the left PN shallow junction 23 is connected to the right side surface of the first P+ doped region 22, and the right PN shallow junction 23 is connected to the left side surface of the cutoff ring contact region 24, the left side surface of the first P+ doped region 22 is connected to the right side surface of the P+ well region 21; an insulating dielectric region 221 is provided in the first P+ doped region 22; the PN shallow junction 23 includes a second P+ doped region 231 and an N- doped region 232;

[0059] An insulating layer 3, the lower side of the insulating layer 3 is respectively connected to the insulating dielectric region 221, the first P+ doped region 22, and the PN shallow junction 23, and at least three trenches 31 are provided on the insulating layer;

[0060] A capacitive metal layer 4, the capacitive metal layer 4 is disposed in the trench 31, and the capacitive metal layer 4 is located directly above the PN shallow junction 23;

[0061] A source metal layer 5, the source metal layer 5 is respectively connected to the P+ well region 21 and the first P+ doped region 22;

[0062] A cutoff ring metal layer 6, the cutoff ring metal layer 6 is connected to the cutoff ring contact region 24;

[0063] A high resistivity conductor layer 7, the high resistivity conductor layer 7 is respectively connected to the insulating layer 3, the capacitive metal layer 4, the source metal layer 5, and the cutoff ring metal layer 6;

[0064] A drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0065] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 5 - 9e16 cm -3 , the doping concentration of the first P+ doped region 22 is 1 - 5e18 cm -3 , the doping concentration of the P+ well region 21 is 5 - 8e18 cm -3 , the doping concentration of the cutoff ring contact region 24 is 5 - 8e18 cm -3 , the doping concentration of the second P+ doped region 231 is 1 - 5e17 cm -3 , the doping concentration of the N- doped region 232 is 1 - 5e15 cm -3 , the material of the insulating layer 3 can be silicon dioxide, the material of the insulating dielectric region 221 can be silicon dioxide or a certain insulating material with a dielectric constant less than that of silicon dioxide, the material of the high resistivity conductor layer 7 can be a SIPOS material or lightly doped polysilicon, and the materials of the source metal layer 5, the cutoff ring metal layer 6, and the capacitive metal layer 4 can be one metal among Al, Cu, Ni or an alloy of several metals;

[0066] Among them, the doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are considered in the traditional design structure of the planar-gate silicon carbide VDMOS device. The doping concentrations of the second P+ doping region 231 and the N- doping region 232 are the basis for realizing the voltage-dividing standard cell. The doping concentration of the first P+ doping region 22 is to ensure that the main junction is not broken down and to avoid defects in etching and depositing the insulating medium, which may lead to device reliability.

[0067] In the terminal structure, the width (d1 + w1) of the first P+ doping region 22 is 5 μm, the maximum depth of the P+ well region 21 is 600 nm, and the depth of the first P+ doping region 22 is 2 μm, where w1 is 500 nm, to avoid separation of the two regions due to process errors and affect the terminal breakdown voltage characteristics of the device. The widths of the first P+ doping regions 22 on both sides of the insulating dielectric region 221 are equal because the electric field concentration at the main junction is the most severe and the risk of being broken down first is the highest. The electric field intensity of the main junction needs to be laterally extended through the first P+ doping region 22. The width of the insulating dielectric region 221 is 4 μm and the thickness is 1.5 μm. The widths w of the second P+ doping region 231 and the N- doping region 232 are both 1 μm and the depth is 800 nm. The distance w2 from the second P+ doping region 231 to the N- doping region 232 (equal distance from the N- doping region 232 to the second P+ doping region 231) is 500 nm - 1 μm. The widths of the second P+ doping region 231, the N- doping region 232, and the distance between them are to ensure a voltage division and breakdown voltage characteristic of at least 200 V. The maximum thickness of the insulating layer 3 is 200 nm, and the thickness of the insulating layer 3 under the capacitive metal layer 4 is 100 nm. This is to achieve a large capacitive effect on the basis of ensuring the breakdown voltage characteristic of the insulating layer. The thickness of the capacitive metal layer 4 is 100 nm and the width is 1.1 μm, and it is distributed directly above the N- doping region 232. This is to improve the capacitive effect of the N- doping region 232 and reduce the electric field concentration in the N- doping region 232. According to different breakdown voltage requirements, the voltage-dividing standard cells can be increased or decreased. Increasing the voltage-dividing standard cells can improve the breakdown voltage, but changes in the breakdown voltage requirements need to be simulated and designed according to the overall structure of the device terminal.

[0068] The thicknesses of the source metal layer 5 and the cutoff ring metal layer 6 are both 800 nm, and the thickness of the high-resistivity conductor layer 7 is 300 nm.

[0069] In this embodiment, by constructing the first P+ doping region 22 beside the P+ well region 21, the first P+ doping region 22 wraps the insulating dielectric region 221, and pushes the electric field of the main junction into the device, so that the electric field concentration of the main junction of the device is alleviated.

[0070] In this embodiment, a PN shallow junction 23 is formed. The PN shallow junction 23 includes a second P+ doped region 231 and an N- doped region 232. The shallow junction formed by the second P+ doped region 231 and the drift layer 2 can prevent the field limiting ring from being depleted prematurely, and provide more negative charges after depletion to share the electric field of the main junction and the previous PN shallow junction 23. The N- doped region 232 reduces the doping concentration on the right side of the field limiting ring, thereby reducing the peak value of the surface electric field on the right side of the PN shallow junction 23 and avoiding premature breakdown.

[0071] In this embodiment, a high resistivity conductor layer 7 and a capacitive metal layer 4 are formed. The high resistivity conductor layer 7 realizes uniform voltage distribution from the source metal layer 5 to the cutoff ring metal layer 6, thereby realizing uniform distribution of the electric field between the PN shallow junctions 23. The capacitive metal layer 4 and the insulating layer 3 can increase the capacitive effect through a thinner insulating layer 3, and improve the capacitive effect of the N- doped region 232.

[0072] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than limiting the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A preparation method for a PN shallow junction composite terminal of a silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a first P+ doped region; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to respectively form a P+ well region and a cutoff ring contact region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form a second P+ doped region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form an N- doped region, and the PN shallow junction includes the second P+ doped region and the N- doped region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and etch the first P+ doped region to form a groove, deposit an insulating medium to form an insulating medium region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form an insulating layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and etch the insulating layer to form at least three trenches, deposit metal to form a capacitor metal layer; the capacitor metal layer is located directly above the N- doped region; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a high-resistivity conductor layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal to form a source metal layer and a cutoff ring metal layer, and remove the blocking layer.

2. The preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS according to claim 1, characterized in that: The left side of the second P+ doped region of the leftmost PN shallow junction is connected to the right side of the first P+ doped region, and the right side of the N- doped region of the rightmost PN shallow junction is connected to the left side of the cutoff ring contact region, and the second P+ doped region and the N- doped region do not contact.

3. The preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS as claimed in claim 1, characterized in that: The widths of the second P+ doped region and the N- doped region are equal.

4. The preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first P+ doped region is greater than that of the second P+ doped region, and the doping concentration of the second P+ doped region is greater than that of the N- doped region.

5. The preparation method of a PN shallow junction composite terminal of a silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the PN shallow junction is greater than the thickness of the P+ well region and less than the thickness of the first P+ doped region.

6. A PN shallow junction composite terminal of a silicon carbide VDMOS, characterized in that, The terminal is obtained by the preparation method described in any one of claims 1 to 5.

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