A potential balance terminal structure and preparation method for a silicon carbide VDMOS device

Abstract

The present invention provides a potential balance terminal structure and a preparation method for a silicon carbide VDMOS device. The method includes: epitaxially growing on a silicon carbide substrate to form a drift layer; forming a blocking layer, etching, ion implanting to form a P+ doped region; reforming the blocking layer, etching, ion implanting to respectively form a P+ well region and a cutoff ring contact region; reforming the blocking layer, etching, etching the drift layer to form at least three trenches, depositing to form an insulating dielectric region; reforming the blocking layer, etching, and depositing to form an insulating layer; reforming the blocking layer, etching, etching the insulating layer to form at least two perforations, and depositing metal to form a potential transfer metal layer; reforming the blocking layer, etching, depositing to form a high resistivity conductor layer; reforming the blocking layer, etching, depositing to form a source metal layer and a cutoff ring metal layer, saving the width of the terminal structure while ensuring the terminal breakdown voltage capability.

Description

Technical Field

[0001] The present invention relates to a potential balance terminal structure and a preparation method of a silicon carbide VDMOS device. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. Based on the device structure design, due to the transverse distribution of the electric field at the edge of the repeating cell, electric field concentration occurs transversely, resulting in breakdown at the edge of the device. The traditional cell uses a field limiting ring structure with the same doping concentration to suppress electric field concentration. Since the doping concentration and spacing distribution of the field limiting ring are equal, the electric field intensity distribution gradually decreases, and there are still high and low differences in the electric field distribution. The risk of breakdown is still relatively high in the area near the P+ well region, and a relatively large number of field limiting rings are required to achieve the breakdown voltage of the device terminal. It is necessary to sacrifice area to obtain breakdown voltage, and the process implementation is difficult. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a potential balance terminal structure and a preparation method of a silicon carbide VDMOS device, which improve the breakdown voltage of the average unit width terminal, that is, save the width of the terminal structure while ensuring the breakdown voltage of the terminal.

[0004] In a first aspect, the present invention provides a preparation method of a potential balance terminal structure of a silicon carbide VDMOS device, including the following steps:

[0005] Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a blocking layer on the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P+ doped region;

[0007] Step 3: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P+ well region and a cut-off ring contact region respectively;

[0008] Step 4: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the drift layer to form at least three grooves, and deposit to form an insulating dielectric region;

[0009] Step 5: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating layer;

[0010] Step 6: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the insulating layer to form at least two perforations, and deposit metal to form a potential transfer metal layer;

[0011] Step 7: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, deposit, and form a high-resistivity conductor layer;

[0012] Step 8: Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, deposit, and form a source metal layer and a cutoff ring metal layer.

[0013] In a second aspect, the present invention provides a potential balance terminal structure for a silicon carbide VDMOS device, and the silicon carbide VDMOS is prepared by using the preparation method of the potential balance terminal structure for a silicon carbide VDMOS device described in the first aspect.

[0014] The advantages of the present invention are as follows:

[0015] 1. By constructing a P+ doped region beside the P+ well region of the device, the present invention diffuses the electric field of the main junction towards the cutoff ring direction, avoiding the concentration of the electric field at the main junction. A high-resistivity conductor layer is constructed and connected between the source metal layer and the cutoff ring metal layer 5 to achieve uniform distribution of the potential between the source metal layer and the cutoff ring metal layer. The potential of the high-resistivity conductor layer is transferred equidistantly to the drift layer through the potential transfer metal layer, realizing the lateral uniform transfer of the potential in the drift layer;

[0016] 2. By constructing an insulating dielectric region beside the potential transfer metal layer, the present invention improves the electric field strength of the insulating dielectric region through a low-dielectric-constant insulating dielectric, gradually distributes the high potential from the main junction towards the cutoff ring metal layer direction, realizes an approximately uniform distribution of the electric field strength laterally, and improves the breakdown voltage of the terminal structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0018] Figure 1 It is a schematic diagram of a potential balance terminal structure for a silicon carbide VDMOS device of the present invention.

[0019] Figure 2 It is a process cross-section of a potential balance terminal structure for a silicon carbide VDMOS device of the present invention Figure 1 。

[0020] Figure 3 It is a process cross-section of a potential balance terminal structure for a silicon carbide VDMOS device of the present invention Figure 2 。

[0021] Figure 4 It is a process cross-section of a potential balance terminal structure for a silicon carbide VDMOS device of the present invention Figure 3 。

[0022] Figure 5 It is a process cross-section of a potential balance terminal structure for a silicon carbide VDMOS device of the present inventionFigure 4 。

[0023] Figure 6 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 5 。

[0024] Figure 7 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 6 。

[0025] Figure 8 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 7 。

[0026] Figure 9 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 8 。

[0027] Figure 10 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 9 。

[0028] Figure 11 Process cross-section of a potential balance terminal structure of a silicon carbide VDMOS device according to the present invention Figure 10 。 Detailed implementation manners

[0029] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion.

[0032] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0033] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0034] As Figures 1 to 11 shown, an embodiment of the present application provides a method for preparing a potential balance terminal structure of a silicon carbide VDMOS device, including the following steps:

[0035] Step 1: Epitaxially grow on a silicon carbide substrate 1 to form a drift layer 2;

[0036] Step 2: Form a blocking layer 9 on the drift layer 2, etch the blocking layer 9 to form a through hole, perform ion implantation to form a P+ doped region 22;

[0037] Step 3: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, perform ion implantation to respectively form a P+ well region 21 and a cutoff ring contact region 24;

[0038] Step 4: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, etch the drift layer 2 to form at least three trenches 25, deposit to form an insulating dielectric region 23;

[0039] Step 5: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit to form an insulating layer 3;

[0040] Step 6: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, etch the insulating layer 3 to form at least two perforations 31, and deposit metal to form a potential transfer metal layer 4;

[0041] Step 7: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, deposit to form a high resistivity conductor layer 7;

[0042] Step 8: Remove the blocking layer 9, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, deposit to form a source metal layer 6 and a cutoff ring metal layer 5.

[0043] In this embodiment, preferably, the doping concentration of the P+ doped region 22 is less than the doping concentration of the P+ well region 21.

[0044] In this embodiment, preferably, the thickness of the P+ doped region 22 is greater than the thickness of the P+ well region 21.

[0045] In this embodiment, preferably, the thickness of the insulating dielectric region 23 is greater than the thickness of the P+ well region 21.

[0046] In this embodiment, preferably, the width of the insulating dielectric region 23 is equal to the distance between the leftmost insulating dielectric region 23 and the P+ doped region 22, and the width of the insulating dielectric region 23 is equal to the distance between two adjacent insulating dielectric regions 23.

[0047] As Figure 1 shown, a potential balance terminal structure of a silicon carbide VDMOS device obtained by the above manufacturing method includes:

[0048] A silicon carbide substrate 1,

[0049] The drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and the drift layer 2 is provided with a P+ well region 21, a P+ doped region 22, at least three insulating dielectric regions 23 and a cutoff ring contact region 24;

[0050] The insulating layer 3, the insulating layer 3 is respectively connected to the upper side of the P+ doped region 22, the upper side of the drift layer 2 and the upper side of the insulating dielectric region 23; at least two through holes 31 are provided on the insulating layer 3;

[0051] At least two potential transfer metal layers 4, the potential transfer metal layers 4 are arranged in the through holes 31, and the lower side of the potential transfer metal layers 4 is connected to the upper side of the drift layer 2;

[0052] The cutoff ring metal layer 5, the lower side of the cutoff ring metal layer 5 is connected to the cutoff ring contact region 24;

[0053] The source metal layer 6, the lower side of the source metal layer 6 is connected to the P+ well region 21 and the P+ doped region 22;

[0054] The high resistivity conductor layer 7, the lower side of the high resistivity conductor layer 7 is connected to the insulating layer 3 and the potential transfer metal layer 4;

[0055] The drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0056] In another embodiment of the present invention, the terminal structure is applied to the terminal of a planar gate silicon carbide VDMOS device. Since it is a terminal structure design, the device cell structure will not be described again. Taking the terminal structure on one side of the device as an example, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 5 - 9e16 cm -3 , the doping concentration of the P+ doped region 22 is 1 - 5e18 cm -3 , the doping concentration of the P+ well region 21 is 5 - 8e18 cm -3 , the doping concentration of the cutoff ring contact region 24 is 5 - 8e18 cm -3 , the material of the insulating layer 3 can be silicon dioxide, the material of the insulating dielectric region 23 can be silicon dioxide or an insulating material with a dielectric constant less than that of silicon dioxide, the high resistivity conductor layer 7 is a SIPOS material or lightly doped polysilicon, and the source metal layer 6, the cutoff ring metal layer 5 and the potential transfer metal layer 4 are one of the metals Al, Cu, Ni or an alloy of several metals; the doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are considered in the traditional design structure of the planar gate silicon carbide VDMOS device, and the electric field of the device is laterally extended towards the cutoff ring metal layer 5 to reduce the electric field strength and improve the reliability of the device;

[0057] The width d1 of the P+ doping region 22 in the terminal structure is 5μm, the maximum depth of the P+ well region 21 is 600nm, and the depth of the P+ doping region 22 is 1.5μm; the width w1 of the overlapping area of ​​the P+ well region 21 and the P+ doping region 22 is 200nm to avoid separation of the two regions due to process errors, which affects the terminal withstand voltage characteristics of the device. This is because the electric field concentration at the main junction is the most serious and the risk of being broken down first is the highest. The main junction electric field strength needs to be expanded laterally through the P+ doping region 22. The width w of the insulating dielectric region 23 is 2μm and the thickness is 800μm. The distance w from the P+ doping region 22 to the nearest insulating dielectric region 23 is 2μm, and the potential transmission The metal layer 4 is distributed between the insulating dielectric regions 23, and its width is equal to the distance between two adjacent insulating dielectric regions 23, which is 2μm. The width w of the insulating dielectric region 23 is 2μm. The lateral voltage division adopts a standard unit structure. This is because the lateral electric field distribution can be relatively uniform through the high resistivity material and the potential transfer metal structure after the main junction. The thickness of the insulating layer 3 is 800nm, which is a compromise design between the comprehensive preparation process speed and the withstand voltage capability. The voltage division standard unit can be increased or decreased according to different withstand voltage requirements. The increase of the voltage division standard unit can improve the withstand voltage. The thickness of the high resistivity conductor layer 7 is 100nm, which is to improve the voltage division effect.

[0058] By constructing a P+ doping region 22 next to the device P+ well region 21, the electric field of the main junction is diffused toward the cutoff ring direction to avoid electric field concentration at the main junction, and a high resistivity conductor layer 7 is constructed between the device source metal layer 6 and the cutoff ring metal layer 5 for connection to achieve uniform distribution of potential from the source metal layer 6 to the cutoff ring metal layer 5, and the potential of the high resistivity conductor layer 7 is equidistantly transferred to the N-type drift layer 2 through the potential transfer metal layer 4 to achieve lateral uniform transfer of potential in the N-type drift layer 2;

[0059] An insulating dielectric region 23 is constructed next to the potential transfer metal layer 4. The electric field strength of the insulating dielectric region 23 is increased by using a low dielectric constant insulating medium, and the high potential from the main junction is gradually distributed toward the cutoff ring metal layer 5, thereby achieving approximately uniform distribution of the electric field strength in the lateral direction and improving the withstand voltage of the terminal structure.

[0060] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A preparation method of a potential balance terminal structure for a silicon carbide VDMOS device, characterized in that: It includes the following steps: Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer on the drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a P+ doped region; Step 3: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to respectively form a P+ well region and a cutoff ring contact region; Step 4: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the drift layer to form at least three trenches, deposit to form an insulating dielectric region; Step 5: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating layer; Step 6: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the insulating layer to form at least two perforations, and deposit metal to form a potential transfer metal layer; Step 7: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a high resistivity conductor layer; Step 8: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a source metal layer and a cutoff ring metal layer; The insulating layer is respectively connected to the upper side of the P+ doped region, the upper side of the drift layer, and the upper side of the insulating dielectric region; the lower side of the potential transfer metal layer is connected to the upper side of the drift layer; The lower side of the cutoff ring metal layer is connected to the cutoff ring contact region; the lower side of the source metal layer is connected to the P+ well region and the P+ doped region; the lower side of the high resistivity conductor layer is connected to the insulating layer and the potential transfer metal layer.

2. The manufacturing method of a potential balance terminal structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The doping concentration of the P+ doped region is less than the doping concentration of the P+ well region.

3. The preparation method of a potential balance terminal structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The thickness of the P+ doped region is greater than the thickness of the P+ well region.

4. The preparation method of a potential balance terminal structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The thickness of the insulating dielectric region is greater than the thickness of the P+ well region.

5. The preparation method of a potential balance terminal structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The width of the insulating dielectric region is equal to the distance between the leftmost insulating dielectric region and the P+ doped region, and the width of the insulating dielectric region is equal to the distance between two adjacent insulating dielectric regions.

6. A potential balance terminal structure of a silicon carbide VDMOS device, characterized in that, The terminal structure is obtained by the preparation method described in any one of claims 1 to 5.

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