Image sensing device and manufacturing method thereof

Abstract

The invention relates to an image sensing device and a manufacturing method thereof. An image sensing apparatus is disclosed. In an embodiment, an image sensing device may include: a substrate; a photodiode formed in the substrate; a transfer transistor formed on the substrate; and an oxide transistor formed over the transfer transistor, the oxide transistor may include: a gate electrode formed over the transfer transistor; a gate isolation layer formed on the gate electrode; an oxide layer formed on the gate isolation layer; a first electrode formed on one side of the oxide layer; and a second electrode formed on the other side of the oxide layer.

Description

Technical Field

[0001] Various embodiments of the disclosed technology relate to an image sensing device and a method of manufacturing the same. Background Art

[0002] Image sensing devices refer to semiconductor devices that capture optical images and convert them into electrical signals. With the development of the automotive, medical, computer and telecommunication industries, the demand for high-performance image sensing devices is increasing in various devices such as smartphones, digital cameras, gaming devices, IoT, robots, security cameras and medical miniature cameras.

[0003] The most common types of image sensing devices are charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. Summary of the invention

[0004] The disclosed technology may be implemented in some embodiments to provide an image sensing device that may exhibit high thermal process margin while minimizing degradation.

[0005] In an embodiment, an image sensing device may include: a substrate; a photodiode formed in the substrate; a transfer transistor formed on the substrate; and an oxide transistor formed above the transfer transistor, and the oxide transistor may include: a gate electrode formed above the transfer transistor; a gate isolation layer formed on the gate electrode; an oxide layer formed on the gate isolation layer; a first electrode formed on one side of the oxide layer; and a second electrode formed on the other side of the oxide layer. In one example, the transfer transistor is configured to transfer charge generated by the photodiode. In one example, the oxide transistor is configured to reset the photodiode.

[0006] The image sensing device may further include a floating diffusion region formed above the photodiode and below the transfer transistor.

[0007] The image sensing device may further include: a conductive path configured to electrically connect the oxide transistor and the floating diffusion region to each other.

[0008] The gate electrode may include doped polysilicon.

[0009] The gate isolation layer may include silicon oxide.

[0010] The oxide layer may include an oxide-based thin film transistor (TFT) material.

[0011] In another embodiment, a method for manufacturing an image sensing device may include the following steps: forming a photodiode in a substrate; forming a transfer transistor above the substrate; forming a photoresist layer above the transfer transistor; forming a channel region for forming a stacked transistor in a region of the photoresist layer; and forming an oxide transistor in the channel region of the photoresist layer, and the step of forming the oxide transistor may include stacking a gate electrode, a gate isolation layer, and an oxide layer in the channel region of the photoresist layer. In one example, the transfer transistor is configured to transfer charge generated by the photodiode. In one example, the oxide transistor is configured to reset the photodiode.

[0012] The step of stacking a gate electrode, a gate isolation layer and an oxide layer may include the following steps: forming a gate electrode on a first isolation layer on which a transfer transistor is formed; forming a gate isolation layer on the gate electrode; forming an oxide layer on the gate isolation layer; forming a first electrode on one side of the oxide layer; and forming a second electrode on the other side of the oxide layer.

[0013] The gate electrode may include doped polysilicon.

[0014] The gate isolation layer may include silicon oxide.

[0015] The oxide layer may include an oxide-based thin film transistor (TFT) material.

[0016] The method for manufacturing the image sensing device may further include forming an interconnection configured to connect the oxide transistor and the floating diffusion region to each other after forming the oxide transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram of an image sensing device according to an embodiment.

[0018] Figure 2 An example structure of a unit pixel of an image sensing device according to an embodiment is shown.

[0019] Figure 3 An example structure of an oxide transistor according to an embodiment is shown.

[0020] Figures 4 to 9 An example method for manufacturing an image sensing device based on an embodiment is shown. DETAILED DESCRIPTION

[0021] Features and specific advantages related to specific implementations of the disclosed technology disclosed in this patent document are described by way of example embodiments with reference to the accompanying drawings.

[0022] The disclosed technology may be implemented in some embodiments to provide an image sensing device including a transistor formed using an oxide-based thin film transistor (TFT) material and a method of manufacturing the same.

[0023] The smaller the pixel size of the CMOS image sensing device is, the more pixels can be provided per unit area, which improves image resolution, and thus the performance of the CMOS image sensing device can be improved.

[0024] In some implementations, the image sensing pixels in the image sensing device can be highly integrated by placing pixel transistors in a stacked structure. However, in the case of a stacked pixel structure, the silicon (Si)-based pixel transistor process requires a wafer bonding process during the stacking process, which reduces process reliability and increases process costs. In addition, during the silicon (Si)-based pixel transistor process, the high-temperature thermal process degrades the characteristics of the image sensor. The disclosed technology can be implemented in some embodiments to solve these problems by forming transistors without wafer bonding. In this way, a high thermal process margin can be achieved, and there may be structural advantages over silicon (Si)-based pixel transistors when manufacturing a stacked structure. The image sensing device implemented based on some embodiments may exhibit better electrical characteristics than silicon (Si)-based pixel transistors, and the degradation during the annealing process may be minimized. In some implementations, the dark noise caused by the charge transfer mechanism of the oxide TFT (oxide-based TFT) can be reduced, and the noise can be reduced by EHP (electron-hole pair) suppression.

[0025] Figure 1 is a block diagram of an image sensing device according to an embodiment.

[0026] Reference Figure 1 , an image sensing device based on an embodiment may include a pixel array 1100, a row driver 1200, a correlated double sampler (CDS) 1300, an analog-to-digital converter (ADC) 1400, an output buffer 1500, a column driver 1600, a timing controller 1700, and a bias generator 1800. The components of the image sensing device shown are discussed only as examples, and this patent document covers adding or omitting components as needed.

[0027] The pixel array 1100 may include a plurality of pixels arranged in a plurality of rows and columns. In one embodiment, the plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, a plurality of unit imaging pixels may be arranged in a three-dimensional pixel array. A plurality of pixels may convert an optical signal into an electrical signal based on a unit pixel or based on a pixel group, and the pixels in the pixel group at least share a specific internal circuit. The pixel array 1100 may receive a drive signal including a row selection signal, a pixel reset signal, and a transmission signal from a row driver 1200. Upon receiving the drive signal, the corresponding pixel in the pixel array 1100 may be enabled to perform operations corresponding to the row selection signal, the pixel reset signal, and the transmission signal.

[0028] The row driver 1200 may enable the pixel array 1100 based on the command and control signal provided by the timing controller 1700 to perform a specific operation on the pixels in the corresponding row. In one embodiment, the row driver 1200 may select at least one pixel arranged in at least one row of the pixel array 1100. The row driver 1200 may generate a row selection signal to select at least one row among the multiple rows. The row driver 1200 may sequentially enable the pixel reset signal and the transmission signal of the pixel corresponding to at least one selected row. Therefore, as analog signals generated by each pixel of the selected row, the reference signal and the image signal may be sequentially transmitted to the CDS1300. At this time, the reference signal may be an electrical signal provided to the CDS1300 when the sensing node (e.g., floating diffusion node) of the pixel is reset, and the image signal may be an electrical signal provided to the CDS1300 when the photocharge generated by the pixel is accumulated in the sensing node. The reference signal representing the reset noise inherent in the pixel and the image signal representing the intensity of the incident light may be collectively referred to as a pixel signal.

[0029] The CMOS image sensor may use correlated double sampling (CDS) to remove the undesired offset value of the pixel (referred to as fixed pattern noise) by sampling the pixel signal twice to remove the difference between the two samples. In some embodiments, correlated double sampling (CDS) may remove the undesired offset value of the pixel by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the sensing node, so that only the pixel output voltage based on the incident light can be measured. In one embodiment, the CDS 1300 may sequentially sample and hold the reference signal and the image signal provided to each of the plurality of column lines from the pixel array 1100. That is, the CDS 1300 may sample and hold the reference signal and the image signal corresponding to each column of the pixel array 1100.

[0030] The CDS 1300 may transmit the reference signal and the image signal of each column as a correlated double sampling signal to the ADC 1400 based on a control signal from the timing controller 1700 .

[0031] ADC 1400 is used to convert the CDS signal into a digital signal for each column and output the digital signal. In one embodiment, ADC 1400 can be implemented as a ramp comparison ADC. The ramp comparison ADC may include a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down over time and a counter that counts until the ramp signal matches the analog pixel signal. In one embodiment, ADC 1400 can convert the correlated double sampling signal generated by CDS 1300 for each column into a digital signal and output the digital signal.

[0032] The ADC 1400 may include a plurality of column counters corresponding to the columns of the pixel array 1100. Each column of the pixel array 1100 is connected to the column counter, and image data may be generated by converting a correlated double sampling signal corresponding to each column into a digital signal using the column counter. In another embodiment, the ADC 1400 may include a global counter to convert a correlated double sampling signal corresponding to each column into a digital signal using a global code provided from the global counter.

[0033] The output buffer 1500 may temporarily hold the column-based image data provided from the ADC 1400 to output the image data. The output buffer 1500 may temporarily store the image data output from the ADC 1400 based on a control signal of the timing controller 1700. The output buffer 1500 may be used as an interface to compensate for a data rate difference or a transmission (or processing) rate difference between the image sensing device and other devices.

[0034] The column driver 1600 may select a column of the output buffer 1500 based on a control signal from the timing controller 1700, and sequentially output image data temporarily stored in the selected column of the output buffer 1500. In one embodiment, upon receiving an address signal from the timing controller 1700, the column driver 1600 may generate a column selection signal based on the address signal and select a column of the output buffer 1500, thereby outputting the image data as an output signal from the selected column of the output buffer 1500.

[0035] The timing controller 1700 may control at least one of the row driver 1200 , the CDS 1300 , the ADC 1400 , the output buffer 1500 , the column driver 1600 , or the bias generator 1800 .

[0036] The timing controller 1700 may provide at least one of the row driver 1200, the CDS 1300, the ADC 1400, the output buffer 1500, the column driver 1600, or the bias generator 1800 with a clock signal required for the operation of each component of the image sensing device, a control signal for timing control and an address signal for selecting a row or column, a signal for controlling the level of a bias voltage applied to the pixel array 1100, etc. In an embodiment of the disclosed technology, the timing controller 1700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0037] The bias voltage generator 1800 may generate a bias voltage for suppressing a dark current generated in a pixel of the pixel array 1100 and supply the generated bias voltage to the pixel array 1100 .

[0038] The bias voltage may be determined during wafer probe testing of the image sensing device and stored in a one-time programmable (OTP) memory. For example, the bias voltage may be experimentally determined to be a value capable of maximizing the dark current suppression effect while minimizing unnecessary power consumption without impairing the performance of the image sensing device.

[0039] The bias voltage generator 1800 may generate a voltage corresponding to a bias voltage stored in the OTP memory. In an embodiment, the OTP memory may be included in the image sensing device, and in particular, may be included in the bias voltage generator 1800.

[0040] In an embodiment, the bias voltage may have a plurality of values. In one example, at a specific timing, the bias voltage may have one of the plurality of values.

[0041] In some implementations, the plurality of values ​​may correspond to a plurality of operating modes of the image sensing device, respectively. The dark current generated at a low light level and the dark current generated at a high light level may be different from each other, and in order to effectively suppress the dark current by the bias generator 1800 under various environments, the bias voltage may vary according to the mode.

[0042] In some implementations, the plurality of values ​​may respectively correspond to a plurality of regions of the pixel array 1100. Dark currents generated at different locations of a pixel in the pixel array 1100 may be different from each other, and in order for the bias voltage generator 1800 to effectively suppress the dark current regardless of the location of the pixel, the bias voltage may vary according to the region.

[0043] In one example, the bias voltage may be a negative voltage having a negative sign, but the disclosed technology is not limited thereto.

[0044] Figure 2 An example structure of a unit pixel of an image sensing device according to an embodiment is shown. Figure 3 An example structure of an oxide transistor according to an embodiment is shown.

[0045] Reference Figure 2 , based on the embodiment, the image sensing device may include a substrate 110, a photodetector 20 (e.g., a photodiode) for detecting incident light to generate a photocharge or charge representing the detected incident light, a transfer transistor Tx, a floating diffusion region FD, an oxide transistor 130, a first isolation layer 140, and a second isolation layer 160. In some embodiments, the oxide transistor 130 may be an oxide thin film transistor (oxide TFT). In one example, the oxide TFT may be a thin film transistor in which the semiconductor of the thin film transistor is a metal oxide compound. In some implementations, the oxide transistor 130 may be a reset transistor that can reset the photodiode 120. In one example, the reset transistor may remove the photocharge accumulated during the previous exposure and define the start of the subsequent exposure.

[0046] In some implementations, the substrate 110 may include a single crystalline silicon (Si) material.

[0047] The photodiode 120 may be formed in an inner region of the substrate 110. An n-type impurity region and a p-type impurity region may be vertically stacked in the photodiode 120. The n-type impurity region and the p-type impurity region may be formed through an ion implantation process.

[0048] The transfer transistor Tx may be formed on the substrate 110 , and may transfer charges (photocharges) generated in the photodiode 120 from the photodiode 120 to the floating diffusion region FD.

[0049] A floating diffusion region FD may be formed above the photodiode 120 and below the transfer transistor Tx to hold charges transferred from the photodiode 120. In one example, the floating diffusion region FD is at a lower height (or a deeper depth) than the transfer transistor Tx.

[0050] The floating diffusion region FD may store photo charges and may be formed to overlap the photodiode 120 and the transfer transistor Tx. The floating diffusion region FD may be formed to vertically overlap a central portion of the photodiode 120.

[0051] The floating diffusion region FD may be an n-type impurity region.

[0052] The oxide transistor 130 may be formed over the transfer transistor Tx. In an implementation, the oxide transistor 130 may be one of a reset transistor, a drive transistor, or a select transistor.

[0053] Reference Figure 2 and Figure 3 In an implementation, the oxide transistor 130 may include a gate electrode 131 , a gate isolation layer 132 , an oxide layer 133 , a first electrode 134 , and a second electrode 135 .

[0054] A gate electrode 131 may be formed over the transfer transistor Tx.

[0055] In an implementation, the gate electrode 131 may include doped polysilicon.

[0056] A gate isolation layer 132 may be formed on the gate electrode 131 .

[0057] In an implementation, the gate isolation layer 132 may include silicon oxide.

[0058] An oxide layer 133 may be formed on the gate isolation layer 132 .

[0059] In an implementation, the oxide layer 133 may include an oxide-based thin film transistor (TFT) material, such as indium gallium zinc oxide (IGZO) and zinc oxide (ZnO).

[0060] Since the oxide layer 133 may allow transistors to be formed without wafer bonding, subsequent thermal processes may be efficiently performed and have structural advantages over silicon (Si) based pixel transistors when a stacked structure is manufactured.

[0061] In addition, the oxide layer 133 including an oxide-based thin film transistor (TFT) material may exhibit excellent electrical characteristics compared to a silicon (Si)-based pixel transistor, and may prevent or minimize degradation that may occur during an annealing process.

[0062] In addition, noise characteristics may be improved by the oxide layer 133 including an oxide-based thin film transistor (TFT) material, compared to a silicon (Si)-based pixel transistor.

[0063] The first electrode 134 may be formed on one side of the oxide layer 133. The first electrode 134 may include a metal material.

[0064] The second electrode 135 may be formed on the other side of the oxide layer 133. The second electrode 135 may include a metal material.

[0065] The first isolation layer 140 may be formed on the substrate 110. The first isolation layer 140 may include at least one of oxide, nitride, or oxynitride. The transfer transistor Tx may be formed inside the first isolation layer 140.

[0066] The second isolation layer 160 may be formed on the first isolation layer 140. The second isolation layer 160 may include at least one of oxide, nitride, or oxynitride. The oxide transistor 130 may be formed in the second isolation layer 160.

[0067] Figures 4 to 9 An example method for manufacturing an image sensing device based on an embodiment is shown. The method for manufacturing an image sensing device based on an embodiment may include the following steps: forming a photodiode 120 in a substrate 110; forming a transfer transistor Tx on the substrate 110; forming a photoresist layer 150 above the transfer transistor Tx; forming a channel region for forming a stacked transistor in one region of the photoresist layer 150; and forming an oxide transistor 130 in the channel region of the photoresist layer 150. The step of forming the oxide transistor 130 may include the following steps: stacking a gate electrode 131, a gate isolation layer 132, and an oxide layer 133 in the channel region of the photoresist layer 150. The step of stacking the gate electrode 131, the gate isolation layer 132, and the oxide layer 133 may include the following steps: forming the gate electrode 131 on the first isolation layer 140 where the transfer transistor Tx is formed; forming the gate isolation layer 132 on the gate electrode 131; forming the oxide layer 133 on the gate isolation layer 132; forming the first electrode 134 on one side of the oxide layer 133; and forming the second electrode 135 on the other side of the oxide layer 133. After forming the oxide transistor 130, the method for manufacturing the image sensing device may include the following steps: forming a conductive path 170 (e.g., a metal wiring) as an interconnection for connecting the oxide transistor 130 and the floating diffusion region FD to each other. In some implementations, the term "metal wiring" may be used to indicate a conductive path or an electrical conductor as an interconnection, which is a current-carrying line connecting devices and structures within a semiconductor device such as an image sensing device.

[0068] Reference Figure 4 After the photodiode 120 is formed in the substrate 110 , a transfer transistor Tx may be formed on the substrate 110 .

[0069] After forming the transfer transistor Tx, the first isolation layer 140 may be formed through an oxide deposition process and a chemical mechanical polishing (CMP) process.

[0070] The first isolation layer 140 may include at least one of oxide, nitride, or oxynitride.

[0071] Reference Figure 5A photoresist layer 150 may be formed on the first isolation layer 140. The photoresist layer 150 defining regions for stacked transistors such as a reset transistor, a drive transistor, a select transistor, etc. may be formed using a photolithography process. A channel region of the stacked transistor may be formed using a photolithography process.

[0072] Reference Figure 6 , an oxide transistor 130 may be formed on the transfer transistor Tx. The oxide transistor 130 may be formed in a channel region of a stacked transistor formed in a photoresist layer 150 on the first isolation layer 140.

[0073] In some implementations, the gate electrode 131 may be formed in a channel region of the photoresist layer 150 where a region for stacking transistors is located through a deposition process, and a gate isolation layer 132 may be formed on the gate electrode 131 .

[0074] The gate electrode 131 may include doped polysilicon.

[0075] The gate isolation layer 132 may include silicon oxide.

[0076] Reference Figure 7 , an oxide layer 133 may be formed on the gate isolation layer 132 through an oxide-based thin film transistor (TFT) material deposition process and an oxide activation annealing process.

[0077] Reference Figure 8 The first electrode 134 and the second electrode 135 may be formed on one side and the other side of the oxide layer 133, respectively, by depositing a metal (eg, aluminum (Al) and platinum (Pt)) capable of making ohmic contact with the oxide.

[0078] In an implementation, the first electrode 134 may be a source electrode.

[0079] In an implementation, the second electrode 135 may be a drain electrode.

[0080] After forming the first electrode 134 and the second electrode 135 , the second isolation layer 160 may be formed through an oxide deposition process and a chemical mechanical polishing (CMP) process.

[0081] The second isolation layer 160 may include at least one of oxide, nitride, or oxynitride.

[0082] Reference Fig. 9 After the oxide transistor 130 is formed, a metal wiring 170 connecting the oxide transistor 130 and the floating diffusion region FD to each other may be formed.

[0083] Although this patent document contains many details, these should not be interpreted as limitations on the scope of any subject matter or content that may be claimed, but rather as descriptions of features specific to specific embodiments of specific technologies. Specific features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the above features may be described as working in a particular combination, even initially claimed as such, one or more features in the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a sub-combination or a variation of a sub-combination.

[0084] Only a few implementations and examples of the disclosed technology are described, and other implementations, enhancements, and variations may be made based on what is described and illustrated in this patent document.

[0085] Cross-references to related applications and priority claims

[0086] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0164617, filed on November 23, 2023, which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: substrate; a photodiode formed in the substrate; a transfer transistor formed on the substrate; as well as an oxide transistor formed above the transfer transistor, Wherein, the oxide transistor comprises: a gate electrode formed above the transfer transistor; a gate isolation layer formed on the gate electrode; an oxide layer formed on the gate isolation layer; a first electrode formed on one side of the oxide layer; and A second electrode is formed on the other side of the oxide layer.

2. The image sensing device according to claim 1, further comprising: A floating diffusion region is formed above the photodiode and below the transfer transistor.

3. The image sensing device according to claim 2, further comprising: A conductive path electrically connects the oxide transistor and the floating diffusion region to each other.

4. The image sensing device according to claim 1, in, The gate electrode includes doped polysilicon.

5. The image sensing device according to claim 1, in, The gate isolation layer includes silicon oxide.

6. The image sensing device according to claim 1, in, The oxide layer includes an oxide-based thin film transistor (TFT) material.

7. A method for manufacturing an image sensing device, the method comprising the steps of: forming a photodiode in a substrate; forming a transfer transistor over the substrate; forming a photoresist layer over the transfer transistor; forming a channel region for forming a stacked transistor in a region of the photoresist layer; as well as forming an oxide transistor in the channel region of the photoresist layer, The step of forming the oxide transistor includes stacking a gate electrode, a gate isolation layer and an oxide layer in the channel region of the photoresist layer.

8. The method according to claim 7, in, The step of stacking the gate electrode, the gate isolation layer and the oxide layer comprises the following steps: forming the gate electrode on the first isolation layer on which the transfer transistor is formed; forming the gate isolation layer on the gate electrode; forming the oxide layer on the gate isolation layer; forming a first electrode on one side of the oxide layer; and A second electrode is formed on the other side of the oxide layer.

9. The method according to claim 8, in, The gate electrode includes doped polysilicon.

10. The method according to claim 8, in, The gate isolation layer includes silicon oxide.

11. The method according to claim 8, in, The oxide layer includes an oxide-based thin film transistor (TFT) material.

12. The method according to claim 8, further comprising the steps of: After forming the oxide transistor, an interconnection connecting the oxide transistor and a floating diffusion region to each other is formed.

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