LED wafer bonding method capable of reducing warpage

Abstract

The invention relates to an LED wafer bonding method capable of reducing warpage. The method comprises the following steps: (1) coarsening a P-type layer of an epitaxial wafer; (2) preparing a film on the surface; (3) manufacturing a metal layer; (4) coating photoresist on the surface of the substrate; (5) evaporating a metal material on the substrate; (6) removing the photoresist; (7) manufacturing silicon oxide on the substrate; (8) planarizing the surface of the silicon oxide by using CMP (chemical mechanical polishing) to expose the metal material; (9) bonding the epitaxial wafer with the substrate; (10) removing the GaAs substrate of the epitaxial wafer, and corroding the cut-off layer; (11) removing a part of the N-type ohmic contact layer, and performing roughening treatment; (12) etching and penetrating the current epitaxial layer, and removing the thin film in the step (2) to form a cutting channel; and (13) manufacturing an N electrode in the N-type ohmic contact layer region, and cutting along the cutting channel to obtain an independent chip. According to the invention, the contact area is reduced, the bonding contact area is optimized on the basis of meeting the use requirement, and the stress is reduced.

Description

Technical Field

[0001] The present invention relates to a method for bonding an LED wafer to reduce warpage, and belongs to the field of optoelectronic technology. Background Art

[0002] At present, reverse-polarity AlGaInP quaternary LED chips are widely used in the field of high-power red LED displays. Reverse-polarity means replacing the substrate. The light-absorbing GaAs substrate is replaced with a single-crystal conductive Si substrate or a sapphire substrate, etc., which can improve the light efficiency by more than 20%. During the substrate replacement process, the original wafer needs to be transferred to the support substrate through a bonding process. The bonding material used in this step can be materials such as metals, oxides, and organic adhesives. During the bonding process, by applying temperature, pressure, and electric fields, the bonding strength can be increased, that is, the firmness between the wafers is increased. Due to the different thermal expansion coefficients of different materials, when the temperature and pressure return to room temperature or the operating temperature, stress differences between the wafers will be caused, resulting in wafer warpage. The entire process flow is relatively long, and the warpage of the wafer after the substrate replacement process is large. During the subsequent wafer processing, it is extremely easy to generate broken wafers, which affects the wafer processing efficiency and has a great impact on the production, sales, and profits of reverse-polarity chips. At present, how to effectively reduce warpage, reduce the breakage rate, and improve the output of reverse-polarity chips has become the main research direction.

[0003] Chinese Patent Document CN104518056A discloses a method for preparing a reverse-polarity AlGaInP red LED chip, including the following steps: (1) bonding a wafer of a GaAs substrate light-emitting diode to a silicon wafer; (2) etching the GaAs substrate, rotating the wafer 180 degrees in the vertical direction, and continuing to etch; (3) after the GaAs substrate etching is completed, scraping off the residual metal film layer at the edge of the wafer; (4) rinsing the wafer surface clean; etching the barrier layer on the wafer surface with a sulfuric acid solution; (5) pasting a high-temperature resistant tape strip with an area larger than the alignment mark on the alignment mark of the wafer; (6) then depositing an N-type metal electrode, and etching a window with a window etching solution; after etching, a clear alignment mark pattern is obtained. In this method, operations are carried out after confirming relevant dimensions. Due to the relatively long manufacturing process of reverse-polarity AlGaInP quaternary LED chips, the possibility of process instability is greater, and the final output alignment rate is low. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention provides a method for bonding an LED wafer to reduce warpage. By using patterned materials of metals and oxides for bonding, it is equivalent to having metal in some areas and no metal in some areas, reducing the contact area. On the basis of meeting the use requirements, the bonding contact area is optimized to reduce stress. The metal has the linear thermal expansion coefficient of some materials, with a unit of 10^-6 / °C.

[0005] The technical solution of the present invention is as follows:

[0006] A method for bonding an LED wafer to reduce warpage, the steps are as follows:

[0007] (1) Roughen the P-type layer of the epitaxial wafer;

[0008] (2) Prepare a thin film on the surface of the roughened P-type layer;

[0009] (3) Fabricate a metal layer on the surface of the thin film;

[0010] (4) Coat a photoresist on the surface of the substrate to form a periodic photoresist pattern;

[0011] (5) Evaporate a metal material on the substrate with the completed pattern;

[0012] (6) Use the lift off process to remove the photoresist and complete the fabrication of the periodic metal pattern;

[0013] (7) Fabricate silicon oxide on the substrate with the metal pattern;

[0014] (8) Use CMP to planarize the surface of the silicon oxide to expose the metal material and thin the metal material;

[0015] (9) Bond the P side of the epitaxial wafer in step (3) to the metal side of the substrate in step (8);

[0016] (10) Remove the GaAs substrate and the etch stop layer of the epitaxial wafer;

[0017] (11) Remove part of the N-type ohmic contact layer and roughen the removed part of the ohmic contact layer;

[0018] (12) Etch through the current epitaxial layer and remove the thin film in step (2) to form a dicing channel;

[0019] (13) Fabricate an N electrode in the N-type ohmic contact layer region;

[0020] (14) Use laser cutting or dicing wheel cutting to cut according to the dicing channel formed in step (6) to obtain independent chips.

[0021] Preferably according to the present invention, in step (1), the roughening uses a mixed solution of HF, HNO 3 and CH 3 COOH, and the volume ratio of HF, HNO 3 and CH 3 COOH is 3:2:4, the temperature of the mixed solution is 25-35 °C, and the soaking time is 30-120 seconds.

[0022] Preferably according to the present invention, in step (2), the thin film is a transparent conductive thin film ITO, a transparent conductive thin film ZnO or SiO 2 \TCF composite thin film, and the thickness of the thin film is 300 - 1200 angstroms.

[0023] Preferably according to the present invention, in step (3), the metal layer material is gold, silver or copper, etc., and the manufacturing method is electron beam evaporation or sputtering, and the thickness of the metal layer is 0.1 μm.

[0024] Preferably according to the present invention, in step (4), the substrate is a silicon wafer, sapphire or ceramic.

[0025] Preferably according to the present invention, in step (5), the metal material is gold, silver or copper, etc., and the thickness is 0.5 - 1 μm.

[0026] Preferably according to the present invention, in step (7), the thickness of the silicon oxide is 1 - 2 μm.

[0027] Preferably according to the present invention, in step (8), the metal material is thinned to 0.8 - 0.9 μm.

[0028] Preferably according to the present invention, in step (10), the removal method is etching, and the etching solution used is a mixed solution of ammonia water, hydrogen peroxide and water, and the volume ratio of ammonia water: hydrogen peroxide: water in the mixed solution is 1:2:6.

[0029] Preferably according to the present invention, in step (12), the epitaxial layer etching utilizes a wet etching or dry etching process.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention uses patterned materials of metals and oxides for bonding. It is equivalent to having metal in some areas and no metal in some areas, reducing the contact area. On the basis of meeting the use requirements, the bonding contact area is optimized and the stress is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a cross-sectional view of a quaternary chip made in step (1) of the present invention;

[0033] Figure 2 It is a cross-sectional view of a quaternary chip made in step (2) of the present invention;

[0034] Figure 3 It is a cross-sectional view of a quaternary chip made in step (3) of the present invention;

[0035] Figure 4 It is a cross-sectional view of a quaternary chip made in step (6) of the present invention;

[0036] Figure 5Cross-sectional view of the quaternary chip made in step (7) of the present invention;

[0037] Figure 6 Cross-sectional view of the quaternary chip made in step (8) of the present invention;

[0038] Figure 7 Cross-sectional view of the quaternary chip made in step (9) of the present invention;

[0039] Figure 8 Cross-sectional view of a single chip made in step (11) of the present invention;

[0040] Figure 9 Cross-sectional view of a single chip made in step (12) of the present invention;

[0041] Figure 10 Cross-sectional view of a single chip made in step (13) of the present invention;

[0042] Figure 11 Cross-sectional view of a single chip made in step (14) of the present invention;

[0043] In the figure, 1, GaAs substrate; 2, etching stop layer; 3, ohmic contact layer; 4, P-type layer; 5, metal layer; 6, thin film; 7, metal material; 8, silicon oxide; 9, substrate; 10, roughened area; 11, N electrode. Detailed implementation mode

[0044] The present invention will be further described below through examples in conjunction with the accompanying drawings, but is not limited thereto.

[0045] Example 1:

[0046] This example provides a preparation method for an AlGaInP quaternary vertical LED chip, and the steps are as follows:

[0047] (1) Roughening the P-type layer 4 of the epitaxial wafer: The roughening uses a mixed solution of HF, HNO3 and CH3COOH, and the volume ratio of HF, HNO3 and CH3COOH is 3:2:4. The temperature of the mixed solution is 25°C, and the soaking time is 30 seconds;

[0048] (2) Prepare an ITO thin film on the surface of the roughened P-type layer, and the thickness of the thin film 6 is 300 Å;

[0049] (3) Use electron beam evaporation to make a metal layer 5 on the surface of the ITO thin film, with a thickness of 0.1 μm;

[0050] (4) Coating a photoresist on the surface of the substrate 9 made of silicon wafer to form a periodic photoresist pattern;

[0051] (5) Evaporating the metal material 7 on the substrate with the completed pattern, and the process is the same as that in step (3), with a thickness of 1 μm;

[0052] (6) Use the lift off process to remove the photoresist and complete the fabrication of periodic metal patterns. As shown in Figure 4 , a plurality of columnar metals are juxtaposed to form a periodic metal pattern;

[0053] (7) Deposit silicon oxide 8 on the surface of the substrate with the metal pattern fabricated in step (6). The thickness of the silicon oxide is 1.5 μm;

[0054] (8) Use CMP to planarize the surface of the silicon oxide. After planarization, the metal is exposed, and the metal thickness is reduced from 1 μm in step (5) to 0.9 μm;

[0055] (9) Bond the P side of the epitaxial wafer in step (3) to the metal side of the substrate in step (8);

[0056] (10) Use an etching solution to remove the GaAs substrate 1 and the etch stop layer 2. The etching solution is a mixed solution of ammonia water, hydrogen peroxide, and water. The volume ratio of ammonia water: hydrogen peroxide: water in the mixed solution is 1:2:6;

[0057] (11) Use a wet etching or dry etching process, in conjunction with a photoresist mask, to selectively etch the N-type ohmic contact layer 3 (only a part needs to be retained to achieve ohmic contact, and specific values are not limited). At the same time, roughen the removed part. The roughening solution is composed of 96% phosphoric acid, hydrochloric acid with a mass concentration of 36.5%, and pure water, configured in a volume ratio of 1:3:5 or 2:5:10. The roughening time is 30 seconds;

[0058] (12) Use a wet etching or dry etching process to etch through the current epitaxial layer and remove the thin film in step (2) to form a chip dicing channel;

[0059] (13) Use a lithography process to prepare an electrode pattern on the N-type surface, and use methods such as electron beam evaporation and sputtering to prepare the N electrode 11;

[0060] (14) Along the dicing channel in step (13), use a 355 nm laser for surface cutting, and then obtain independent chips by means of die separation.

[0061] Example 2:

[0062] This example provides a method for fabricating an AlGaInP quaternary vertical LED chip, including:

[0063] (1) Roughening the P-type layer of the epitaxial wafer: The roughening uses a mixed solution of HF, HNO3, and CH3COOH. The volume ratio of HF, HNO3, and CH3COOH is 3:2:4. The temperature of the mixed solution is 35 °C, and the soaking time is 120 seconds;

[0064] (2) preparing an ITO film on the roughened surface of the P-type layer, the film thickness being 1200 angstroms;

[0065] (3) using electron beam evaporation to form a metal layer on the surface of the ITO film with a thickness of 0.1 μm;

[0066] (4) applying photoresist on the sapphire surface to form a periodic photoresist pattern;

[0067] (5) Vapor-depositing metal material on the patterned substrate, using the same process as step (3) with a thickness of 1 μm;

[0068] (6) Use the lift-off process to remove the photoresist and complete the periodic metal pattern production, such as Figure 4 As shown, a plurality of columnar metals are arranged side by side to form a periodic metal pattern;

[0069] (7) forming silicon oxide on the surface of the substrate with the metal pattern formed in step (6), the thickness of the silicon oxide being 1.5 μm;

[0070] (8) using CMP to planarize the silicon oxide surface, exposing the metal after planarization, and reducing the metal thickness from 1 um in step (5) to 0.9 um;

[0071] (9) bonding the P surface of the epitaxial wafer in step (3) to the metal side of the substrate in step (8);

[0072] (10) removing the GaAs substrate and etching the stop layer using an etching solution, wherein the etching solution is a mixture of ammonia water, hydrogen peroxide, and water, wherein the volume ratio of ammonia water: hydrogen peroxide: water in the mixture is 1:2:6;

[0073] (11) selectively etching the N-type ohmic contact layer using a wet etching or dry etching process in conjunction with a photoresist mask, and roughening the removed portion at the same time, wherein the roughening solution comprises 96% phosphoric acid, 36.5% hydrochloric acid, and pure water in a volume ratio of 1:3:5 or 2:5:10, and the roughening time is 60 seconds;

[0074] (12) using a wet etching or dry etching process to etch the current epitaxial layer through to the metal layer described in step (3);

[0075] (13) Using wet etching or dry etching process again, continue etching to the sapphire surface to form a cutting path;

[0076] (14) Prepare an electrode pattern on the surface in step (14) using a lithography process, and prepare P\N electrodes by means of electron beam evaporation, sputtering, etc. Here, sapphire is used as the bonding substrate. Since sapphire is non-conductive, it is necessary to etch from the epitaxial layer to the bonding metal layer to achieve the conduction of the P electrode. The P\N electrodes can be made simultaneously here;

[0077] (15) Along the dicing lane in step (14), perform surface cutting using a 355 nm laser, and then obtain independent chips by means of die separation.

Claims

1. A method for bonding LED wafers with reduced warpage, characterized in that: Here are the steps: (1) Roughening the P-type layer of the epitaxial wafer; (2) preparing a thin film on the roughened surface of the P-type layer; (3) forming a metal layer on the surface of the film; (4) applying photoresist on the surface of the substrate to form a periodic photoresist pattern; (5) evaporating metal material on the substrate with the completed pattern; (6) Using the lift-off process to remove the photoresist and complete the periodic metal pattern production; (7) Fabricating silicon oxide on a substrate with a metal pattern; (8) Using CMP to flatten the silicon oxide surface, exposing the metal material, and thinning the metal material; (9) bonding the P surface of the epitaxial wafer in step (3) to the metal side of the substrate in step (8); (10) Removing the GaAs substrate of the epitaxial wafer and etching the stop layer; (11) removing a portion of the N-type ohmic contact layer and roughening the removed portion of the ohmic contact layer; (12) etching through the current epitaxial layer and removing the thin film in step (2) to form a cutting path; (13) forming an N electrode in the N-type ohmic contact layer region; (14) Cutting is performed according to the cutting paths formed in step (6) to obtain independent chips.

2. The LED wafer bonding method for reducing warpage according to claim 1, characterized in that: In step (1), a mixed solution of HF, HNO3 and CH3COOH is used for roughening, the volume ratio of HF, HNO3 and CH3COOH is 3:2:4, the temperature of the mixed solution is 25-35°C, and the immersion time is 30-120 seconds.

3. The LED wafer bonding method for reducing warpage according to claim 2, characterized in that: In step (2), the film is a transparent conductive film ITO, a transparent conductive film ZNO or a SiO2\TCF composite film, and the film thickness is 300-1200 angstroms.

4. The LED wafer bonding method for reducing warpage according to claim 3, characterized in that: In step (3), the metal layer material is gold, silver or copper, the manufacturing method is electron beam evaporation or sputtering, and the thickness of the metal layer is 0.1 μm.

5. The LED wafer bonding method for reducing warpage according to claim 4, characterized in that: In step (4), the substrate is a silicon wafer, sapphire or ceramic.

6. The LED wafer bonding method for reducing warpage according to claim 5, characterized in that: In step (5), the metal material is gold, silver or copper, etc., and has a thickness of 0.5-1 μm.

7. The LED wafer bonding method for reducing warpage according to claim 6, characterized in that: In step (7), the thickness of silicon oxide is 1-2 um.

8. The LED wafer bonding method for reducing warpage according to claim 7, characterized in that: In step (8), the metal material is thinned to 0.8-0.9 um.

9. The LED wafer bonding method for reducing warpage according to claim 8, characterized in that: In step (10), the removal method is corrosion, and the corrosion liquid used is a mixture of ammonia water, hydrogen peroxide and water, and the volume ratio of ammonia water: hydrogen peroxide: water in the mixture is 1:2:

6.

10. The LED wafer bonding method for reducing warpage according to claim 9, characterized in that: In step (12), the epitaxial layer is etched using a wet etching process or a dry etching process.

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