Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for solving the problem of poor fingerprint identification performance caused by incapability of ensuring the accuracy of fingerprint identification when a display product with a fingerprint identification function in related technologies performs fingerprint identification. The display panel comprises a second initialization signal transmission layer; the second initialization signal transmission layer comprises a plurality of second initialization signal lines and a plurality of second initialization compensation lines; the second initialization signal line comprises a second main body part and a second extension part, the second main body part extends along the first direction, the second extension part extends along the second direction, and the second initialization compensation line extends along the second direction; the second main body part is coupled with the first pole of the corresponding second reset transistor; the second extension part comprises an extension connecting part and an extension compensation part, the first end of the extension connecting part is coupled with the second main body part, and the second end of the extension connecting part is respectively coupled with the extension compensation part and the corresponding second initialization compensation line.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, display products with fingerprint recognition functions are widely used in various fields. Such display products utilize the light emitted by pixels, which is reflected by a finger and then forms an image through a small hole onto a sensor, to achieve the function of under-screen fingerprint recognition. However, in such display products, due to the limited layout space in the driving backplane, light-leakage slits are formed between metal layers, resulting in the acquisition of periodic interference stripes during fingerprint recognition. The width of the interference stripes is close to the width of normal fingerprint stripes, and the period of the interference stripes is approximately the same as that of the fingerprint stripes, and they cannot be filtered out by algorithms. Therefore, in related technologies, when a display product with a fingerprint recognition function performs fingerprint recognition, the accuracy of fingerprint recognition cannot be guaranteed, resulting in poor fingerprint recognition performance. Summary of the Invention

[0003] The purpose of the present invention is to provide a display panel and a display device, which are used to solve the problem that in related technologies, when a display product with a fingerprint recognition function performs fingerprint recognition, the accuracy of fingerprint recognition cannot be guaranteed, resulting in poor fingerprint recognition performance.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display panel, including a second initialization signal transmission layer and a plurality of sub-pixels; wherein,

[0006] The sub-pixels include a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit includes a second reset transistor, and a second pole of the second reset transistor is coupled to an anode of the light-emitting element;

[0007] The second initialization signal transmission layer includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines; the second initialization signal lines include a second main portion and a second extension portion, the second main portion extends along a first direction, the second extension portion extends along a second direction, the second initialization compensation lines extend along the second direction, and the first direction intersects with the second direction;

[0008] The second main portion is coupled to a first pole of a corresponding second reset transistor; the second extension portion includes an extended connection portion and an extended compensation portion, a first end of the extended connection portion is coupled to the second main portion, and a second end of the extended connection portion is respectively coupled to the extended compensation portion and a corresponding second initialization compensation line.

[0009] Optionally, the extended connection portion includes an intermediate portion between its first end and second end, the intermediate portion having a first width in a first direction, and the width of the extended compensation portion in the first direction being greater than the first width.

[0010] Optionally, in the second direction, the width of the extended compensation portion is less than the width of the second end of the extended connection portion.

[0011] Optionally, the minimum width d1 of the extended compensation portion in the first direction satisfies: 2.8 μm ≤ d1 ≤ 3.2 μm;

[0012] The maximum width d2 of the extended compensation portion in the first direction satisfies: 5.3 μm ≤ d2 ≤ 5.7 μm;

[0013] The minimum width d3 of the extended compensation portion in the second direction satisfies: 2.1 μm ≤ d3 ≤ 2.5 μm;

[0014] The maximum width d4 of the extended compensation portion in the second direction satisfies: 3.4 μm ≤ d3 ≤ 3.8 μm.

[0015] Optionally, the display panel further includes a first source-drain metal layer, and the extended compensation portion is provided on the same layer and made of the same material as the first source-drain metal layer.

[0016] Optionally, the positive projection of the second initialization compensation line on the substrate of the display panel at least partially overlaps with the positive projection of the extended compensation portion on the substrate.

[0017] Optionally, the second initialization compensation line includes a plurality of first portions, a plurality of second portions, and a plurality of third portions, the first portions and the second portions being alternately arranged, and there being one third portion between the first portions and the second portions;

[0018] The first portion includes a connection pattern and a compensation pattern; the connection pattern is coupled to the second end of the extended connection portion, and the positive projection of the compensation pattern on the substrate at least partially overlaps with the positive projection of the extended compensation portion on the substrate; the width of the compensation pattern in the first direction is greater than the width of the third portion in the first direction.

[0019] Optionally, the maximum width of the compensation pattern in the first direction is the same as the maximum width of the extended compensation portion in the first direction, and the positive projection of the extended compensation portion on the substrate of the display panel is located inside the positive projection of the compensation pattern on the substrate.

[0020] Optionally, the minimum width d5 of the compensation pattern along the first direction satisfies: 1.9 μm ≤ d5 ≤ 2.3 μm;

[0021] The maximum width d6 of the compensation pattern along the first direction satisfies: 5.2 μm ≤ d6 ≤ 5.6 μm;

[0022] The minimum width d7 of the compensation pattern along the second direction satisfies: 3.4 μm ≤ d7 ≤ 3.8 μm;

[0023] The maximum width d8 of the compensation pattern along the second direction satisfies: 6 μm ≤ d8 ≤ 6.4 μm.

[0024] Optionally, the display panel further includes a second source-drain metal layer, and the compensation pattern is provided on the same layer and made of the same material as the second source-drain metal layer.

[0025] Optionally, the display panel further includes:

[0026] A first initialization signal transmission layer, which includes a plurality of first initialization signal lines, and at least a part of the first initialization signal lines extends along the first direction;

[0027] The sub-pixel driving circuit further includes a driving transistor, a first reset transistor, and a first conductive connection part, and the second pole of the first reset transistor is coupled to the gate of the driving transistor;

[0028] The first conductive connection part includes a first main body part, and the first main body part is respectively coupled to the first pole of the corresponding first reset transistor and the corresponding first initialization signal line;

[0029] Part of the first conductive connection part further includes a first compensation part coupled to the first main body part. In the layout area of the sub-pixel driving circuits arranged in the first direction, the first compensation part and the extended compensation part are alternately arranged along the first direction.

[0030] Optionally, the first initialization signal transmission layer further includes: a plurality of first initialization compensation lines, the first initialization compensation lines extend along the second direction, and the first initialization compensation lines are coupled to the corresponding first compensation parts.

[0031] Optionally, the width of the first compensation part along the first direction is substantially the same as the width of the extended compensation part along the first direction.

[0032] Optionally, the display panel further includes a first source-drain metal layer, and the first compensation part is provided on the same layer and made of the same material as the first source-drain metal layer.

[0033] Based on the technical solution of the above display panel, the second aspect of the present invention provides a display device, including the above display panel.

[0034] In the technical solution provided by the present invention, it is set that the second initialization signal transmission layer includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines. The second initialization signal lines include a second main body portion and a second extension portion. The second main body portion is coupled to the first pole of the corresponding second reset transistor. The second extension portion includes an extended connection portion and an extended compensation portion. The first end of the extended connection portion is coupled to the second main body portion, and the second end of the extended connection portion is respectively coupled to the extended compensation portion and the corresponding second initialization compensation line. This setting manner enables the second initialization signal transmission layer to form a grid-like structure, which is beneficial to better reducing the Loading when the second initialization signal transmission layer transmits the second initialization signal; at the same time, it ensures good connection performance between the second initialization signal transmission layer and the first pole of the second reset transistor.

[0035] Moreover, in the technical solution provided by the present invention, it is set that the second extension portion includes an extended connection portion and an extended compensation portion, so that the extended compensation portion can further block the light-transmitting area of the display panel, optimize the arrangement of the light-transmitting holes during the pixel layout period, effectively weaken the periodic interference fringes collected during fingerprint recognition, and through algorithm optimization in the later stage, it can not affect the accuracy of fingerprint recognition. Therefore, the technical solution provided by the present invention realizes the uniform arrangement of the light-transmitting holes formed by various functional patterns with light-shielding properties within the period, and can achieve that the difference in the distribution consistency of the light-transmitting hole shape in the horizontal and vertical directions is less than 5%, thereby eliminating the periodic interference fringes collected during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0037] Figure 1 is a schematic circuit structure diagram of a sub-pixel driving circuit in the display panel provided by an embodiment of the present invention;

[0038] Figure 2 is a schematic cross-sectional view of the display panel provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic layout diagram of the active layer and the first gate metal layer in the display panel provided by an embodiment of the present invention;

[0040] Figure 4Schematic layout diagram of the second gate metal layer in the display panel provided by the embodiment of the present invention;

[0041] Figure 5 For adding on the basis of Figure 3 the schematic layout diagram of the second gate metal layer shown in Figure 4 ;

[0042] Figure 6 Schematic layout diagram of the first source / drain metal layer in the display panel provided by the embodiment of the present invention;

[0043] Figure 7 Schematic diagram of the vias included in the interlayer insulating layer in the display panel provided by the embodiment of the present invention;

[0044] Figure 8 For adding on the basis of Figure 5 the schematic layout diagram of the first source / drain metal layer shown in Figure 6 and the vias shown in Figure 7 ;

[0045] Figure 9 Schematic layout diagram of the second source / drain metal layer in the display panel provided by the embodiment of the present invention;

[0046] Figure 10 Schematic diagram of the vias included in the first planarization layer in the display panel provided by the embodiment of the present invention;

[0047] Figure 11 Schematic layout diagram of the vias included in the interlayer insulating layer, the first source / drain metal layer, the vias included in the first planarization layer, and the second source / drain metal layer in the display panel provided by the embodiment of the present invention;

[0048] Figure 12 For adding on the basis of Figure 8 the schematic layout diagram of the second source / drain metal layer shown in Figure 9 and the vias shown in Figure 10 ;

[0049] Figure 13 Schematic distribution diagram of the light-transmitting holes formed after the active layer, the first source / drain metal layer, and the second source / drain metal layer are stacked in the display panel provided by the embodiment of the present invention;

[0050] Figure 14 Schematic distribution diagram of the light-transmitting holes formed after the active layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer are stacked in the display panel provided by the embodiment of the present invention;

[0051] Figure 15 Schematic layout diagram of the anode layer in the display panel provided by the embodiment of the present invention;

[0052] Figure 16Based on Figure 12 to add Figure 15 Schematic diagram of the layout of the vias included in the anode layer and the second flat layer shown in

[0053] Figure 17 Schematic diagram of the distribution of the light-transmitting holes formed after the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the anode layer in the display panel provided by the embodiment of the present invention are stacked

[0054] Figure 18 Schematic diagram of the size of the extended compensation part provided by the embodiment of the present invention

[0055] Figure 19 Schematic diagram of the size of the compensation pattern provided by the embodiment of the present invention

[0056] Figure 20 Schematic diagram of the periodic interference fringes collected in the related art

[0057] Figure 21 Schematic diagram of the fingerprint stripes collected in the display panel provided by the embodiment of the present invention Detailed implementation manners

[0058] In order to further illustrate the display panel and the display device provided by the embodiment of the present invention, the following will be described in detail with reference to the accompanying drawings of the specification.

[0059] Please refer to Figure 1 , Figures 3 to 12 , Figure 15 and Figure 16 , the embodiment of the present invention provides a display panel, including a second initialization signal transmission layer and a plurality of sub-pixels; wherein,

[0060] The sub-pixel includes a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit includes a second reset transistor T7, and the second pole of the second reset transistor T7 is coupled to the anode of the light-emitting element;

[0061] The second initialization signal transmission layer includes a plurality of second initialization signal lines Vinit2 and a plurality of second initialization compensation lines Vinit2'; the second initialization signal line Vinit2 includes a second main body 31 and a second extension 32, the second main body 31 extends along a first direction, the second extension 32 extends along a second direction, the second initialization compensation line Vinit2' extends along the second direction, and the first direction intersects with the second direction;

[0062] The second main body portion 31 is coupled to a first pole of a corresponding second reset transistor T7; the second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. A first end 320a of the extension connection portion 320 is coupled to the second main body portion 31, and a second end 320b of the extension connection portion 320 is respectively coupled to the extension compensation portion 321 and a corresponding second initialization compensation line Vinit2'.

[0063] Exemplarily, the display panel includes a plurality of sub-pixels, and a plurality of sub-pixel driving circuits included in the plurality of sub-pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example: the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0064] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light. The structure of the sub-pixel driving circuit is diverse. For example: the sub-pixel driving circuit includes: a 7T1C (i.e., 7 transistors and 1 capacitor) circuit structure, an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, a 9T1C (i.e., 9 transistors and 1 capacitor) circuit structure, etc., but is not limited thereto.

[0065] Taking the sub-pixel driving circuit adopting an 8T1C circuit structure as an example below, the specific structure of the sub-pixel driving circuit will be described in detail.

[0066] As Figure 1 shown, the sub-pixel driving circuit includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a power control transistor T5, a light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.

[0067] A gate of the first reset transistor T1 is coupled to a corresponding first reset signal line Rst1, a first pole of the first reset transistor T1 is coupled to a first initialization signal line Vinit1, and a second pole of the first reset transistor T1 is coupled to a gate T3-g of the driving transistor T3.

[0068] The gate of the compensation transistor T2 is coupled to the corresponding first scan line G1, the first pole of the compensation transistor T2 is coupled to the second pole of the driving transistor T3, and the second pole of the compensation transistor T2 is coupled to the gate of the driving transistor T3. For example, the second pole of the first reset transistor T1 and the second pole of the compensation transistor T2 are formed as an integral structure and are coupled to the fourth conductive connection portion 24 through the sixth via Via6, and the fourth conductive connection portion 24 is further coupled to the gate of the driving transistor T3 through the seventh via Via7.

[0069] The gate of the data writing transistor T4 is coupled to the corresponding first scan line G1, the first pole of the data writing transistor T4 is coupled to the corresponding data line DA, and the second pole of the data writing transistor T4 is coupled to the first pole of the driving transistor T3.

[0070] The gate of the power control transistor T5 is coupled to the corresponding light emission control signal line EM, the first pole of the power control transistor T5 is coupled to the power signal line VDD, and the second pole of the power control transistor T5 is coupled to the first pole of the driving transistor.

[0071] The gate of the light emission control transistor T6 is coupled to the corresponding light emission control signal line EM, the first pole of the light emission control transistor T6 is coupled to the second pole of the driving transistor T3, the second pole of the light emission control transistor T6 is coupled to the anode Ano of the light emitting element, and the cathode of the light emitting element receives the negative power signal VSS.

[0072] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, the first pole of the second reset transistor T7 is coupled to the second initialization signal line Vinit2, and the second pole of the second reset transistor T7 is coupled to the anode of the light emitting element. For example, the second pole of the light emission control transistor T6 and the second pole of the second reset transistor T7 are formed as an integral structure and are coupled to the sixth conductive connection portion 26 through the tenth via Via10, and the sixth conductive connection portion 26 is further coupled to the eighth conductive connection portion 28 through the eleventh via Via11, and the eighth conductive connection portion 28 is coupled to the anode Ano of the corresponding light emitting element through the nineteenth via Via19.

[0073] The gate of the third reset transistor T8 is coupled to the corresponding second reset signal line Rst2, the first pole of the third reset transistor T8 is coupled to the third initialization signal line Vinit3, and the second pole of the third reset transistor T8 is coupled to the first pole of the driving transistor T3. For example, the second pole of the third reset transistor T8 is coupled to the fifth conductive connection portion 25 through the eighth via Via8, and the fifth conductive connection portion 25 is further coupled to the first pole of the driving transistor T3 through the ninth via Via9.

[0074] The first electrode Cst1 of the storage capacitor Cst is multiplexed as the gate T3-g of the driving transistor T3, and the second electrode Cst2 of the storage capacitor Cst is coupled to the power supply signal line VDD.

[0075] It should be noted that the display panel includes a plurality of first reset signal lines Rst1, the plurality of first reset signal lines Rst1 correspond to the plurality of rows of sub-pixel driving circuits one by one, and the first reset signal line Rst1 is respectively coupled to the gates of the first reset transistors T1 in the corresponding row of sub-pixel driving circuits.

[0076] The display panel includes a plurality of second reset signal lines Rst2, the plurality of second reset signal lines Rst2 correspond to the plurality of rows of sub-pixel driving circuits one by one, and the second reset signal line Rst2 is respectively coupled to the gates of the second reset transistors T7 and the gates of the third reset transistors T8 in the corresponding row of sub-pixel driving circuits.

[0077] The display panel includes a plurality of first scan lines G1, the plurality of first scan lines G1 correspond to the plurality of rows of sub-pixel driving circuits one by one, and the first scan line G1 is respectively coupled to the gates of the compensation transistors T2 and the gates of the data writing transistors T4 in the corresponding row of sub-pixel driving circuits.

[0078] The display panel includes a plurality of light emission control signal lines EM, the plurality of light emission control signal lines EM correspond to the plurality of rows of sub-pixel driving circuits one by one, and the light emission control signal line EM is respectively coupled to the gates of the power supply control transistors T5 and the gates of the light emission control transistors T6 in the corresponding row of sub-pixel driving circuits.

[0079] The display panel includes a plurality of data lines DA, the plurality of data lines DA correspond to the plurality of columns of sub-pixel driving circuits one by one, and the data line DA is respectively coupled to the first electrodes of the data writing transistors T4 in the corresponding column of sub-pixel driving circuits. For example: the data line DA is coupled to the corresponding second conductive connection portion 22 through the first via Via1, and the second conductive connection portion 22 is coupled to the first electrode of the corresponding data writing transistor T4 through the second via Via2.

[0080] The display panel includes a plurality of power supply lines VDD, and the plurality of power supply lines VDD correspond to the multiple columns of sub-pixel driving circuits one by one. The power supply line VDD is respectively coupled to the first pole of each power control transistor T5 and the second electrode plate Cst2 of each storage capacitor Cst in a corresponding column of sub-pixel driving circuits. For example, the power supply line VDD is coupled to a corresponding third conductive connection portion 23 through a third via Via3, the third conductive connection portion 23 is coupled to the first pole of a corresponding power control transistor T5 through a fourth via Via4, and the third conductive connection portion 23 is further coupled to the second electrode plate Cst2 of a corresponding storage capacitor Cst through a fifth via Via5. The sub-pixel driving circuits included in the same row of sub-pixel driving circuits are divided into multiple circuit groups, and each circuit group includes two adjacent sub-pixel driving circuits. Two third conductive connection portions in the same circuit group are formed into an integral structure.

[0081] As Figure 2 shown, exemplarily, the display panel includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel definition layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc., which are sequentially stacked in a direction away from the substrate 70. The display substrate may further include a passivation layer PVX, but is not limited thereto.

[0082] Exemplarily, the second initialization signal transmission layer includes a plurality of second initialization signal lines Vinit2 and a plurality of second initialization compensation lines Vinit2'; the plurality of second initialization signal lines Vinit2 are arranged in sequence along the second direction, and each second initialization signal line Vinit2 includes at least a part extending along the first direction, and the second initialization signal line Vinit2 is provided with the same layer and the same material as the first source-drain metal layer; the plurality of second initialization compensation lines Vinit2' are arranged in sequence along the first direction, and each second initialization compensation line Vinit2' includes at least a part extending along the second direction, and the second initialization compensation line Vinit2' is provided with the same layer and the same material as the second source-drain metal layer.

[0083] Exemplarily, the second initialization signal line Vinit2 includes a second main body portion 31 and a second extension portion 32 of an integral structure. The second main body portion 31 is coupled to a first pole of a corresponding second reset transistor T7 through a twelfth via Via12. The second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. A first end 320a of the extension connection portion 320 is formed as an integral structure with the second main body portion 31, and a second end 320b of the extension connection portion 320 is formed as an integral structure with the extension compensation portion 321. The extension connection portion is coupled to a corresponding second initialization compensation line Vinit2' through a thirteenth via Via13.

[0084] Exemplarily, a plurality of second initialization signal lines Vinit2 and a plurality of second initialization compensation lines Vinit2' included in the second initialization signal transmission layer together form a grid-like structure for transmitting a second initialization signal. The second reset transistor T7 uses the second initialization signal to reset an anode of a light-emitting element.

[0085] According to the specific structure of the above display panel, in the display panel provided by an embodiment of the present invention, it is provided that the second initialization signal transmission layer includes a plurality of second initialization signal lines Vinit2 and a plurality of second initialization compensation lines Vinit2'. The second initialization signal line Vinit2 includes a second main body portion 31 and a second extension portion 32. The second main body portion 31 is coupled to a first pole of a corresponding second reset transistor T7. The second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. A first end 320a of the extension connection portion 320 is coupled to the second main body portion 31, and a second end 320b of the extension connection portion 320 is respectively coupled to the extension compensation portion 321 and a corresponding second initialization compensation line Vinit2'. This setting manner enables the second initialization signal transmission layer to form a grid-like structure, which is beneficial to better reducing the Loading when the second initialization signal transmission layer transmits the second initialization signal. At the same time, good connection performance between the second initialization signal transmission layer and the first pole of the second reset transistor T7 is ensured.

[0086] Moreover, in the display panel provided by the embodiments of the present invention, the second extension part 32 is provided to include an extension connection part 320 and an extension compensation part 321, so that the extension compensation part 321 can further block the light-transmitting area of the display panel, optimize the arrangement of the light-transmitting holes during the pixel layout period, effectively weaken the periodic interference stripes collected during fingerprint recognition, and through algorithm optimization in the later stage, the accuracy of fingerprint recognition can be ensured. Therefore, the display panel provided by the embodiments of the present invention realizes the uniform arrangement of the light-transmitting holes formed by various functional patterns with light-shielding properties within the period, and can achieve that the difference in the distribution consistency of the light-transmitting hole shapes in the horizontal and vertical directions is less than 5%, thereby eliminating the periodic interference stripes collected during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0087] As Figure 6 shown, in some embodiments, the extension connection part 320 includes an intermediate part 320c located between its first end and second end, the intermediate part 320c has a first width along a first direction, and the width of the extension compensation part 321 along the first direction is greater than the first width.

[0088] The above setting that the width of the extension compensation part 321 along the first direction is greater than the first width enables the extension compensation part 321 to achieve a larger shielding area relative to the intermediate part 320c along the first direction, thereby further optimizing the arrangement of the light-transmitting holes during the pixel layout period, effectively weakening the periodic interference stripes collected during fingerprint recognition, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0089] As Figure 6 shown, in some embodiments, it is set that along the second direction, the width of the extension compensation part 321 is smaller than the width of the second end 320b of the extension connection part 320.

[0090] The above setting method enables the extension compensation part 321 to effectively avoid other functional patterns adjacent to it in the second direction, while ensuring a larger shielding area, avoiding short circuits with other functional patterns, and ensuring the manufacturing yield of the display panel.

[0091] As Figure 18 shown, in some embodiments, the minimum width d1 of the extension compensation part 321 along the first direction satisfies: 2.8μm ≤ d1 ≤ 3.2μm;

[0092] The maximum width d2 of the extension compensation part 321 along the first direction satisfies: 5.3μm ≤ d2 ≤ 5.7μm;

[0093] The minimum width d3 of the extension compensation portion 321 along the second direction satisfies: 2.1 μm ≤ d3 ≤ 2.5 μm;

[0094] The maximum width d4 of the extension compensation portion 321 along the second direction satisfies: 3.4 μm ≤ d3 ≤ 3.8 μm.

[0095] By setting the dimensions of the extension compensation portion 321 in the first and second directions within the above ranges, not only is the light-shielding area of the extension compensation portion 321 increased, the arrangement of the light-transmitting holes within the pixel layout period is further optimized, but also the extension compensation portion 321 can effectively avoid other functional patterns adjacent to its periphery. While ensuring a larger shielding area is achieved, short circuits with other functional patterns are avoided, ensuring the production yield of the display panel.

[0096] As Figure 6 、 Figure 9 and Figure 11 shown, in some embodiments, the positive projection of the second initialization compensation line Vinit2' on the substrate of the display panel at least partially overlaps with the positive projection of the extension compensation portion 321 on the substrate.

[0097] As Figure 6 、 Figure 9 and Figure 11 shown, in some embodiments, the second initialization compensation line Vinit2' includes a plurality of first portions 41, a plurality of second portions 42, and a plurality of third portions 43. The first portions 41 and the second portions 42 are alternately arranged, and there is one third portion 43 between the first portions 41 and the second portions 42; the first portion 41 includes a connection pattern 41a and a compensation pattern 41b; the connection pattern 41a is coupled to the second end 320b of the extension connection portion 320, and the positive projection of the compensation pattern 41b on the substrate at least partially overlaps with the positive projection of the extension compensation portion 321 on the substrate; the width of the compensation pattern 41b along the first direction is greater than the width of the third portion 43 along the first direction.

[0098] Exemplarily, the first portion 41, the second portion 42, and the third portion 43 are formed as an integral structure.

[0099] Exemplarily, the width of the connection pattern 41a along the first direction is greater than the width of the third portion 43 along the first direction. The width of the second portion 42 along the first direction is greater than the width of the third portion 43 along the first direction.

[0100] Exemplarily, the connection pattern 41a is coupled to the second end 320b of the extended connection portion 320 through the thirteenth via Via13.

[0101] Exemplarily, the maximum width of the compensation pattern 41b along the first direction is the same as the maximum width of the extended compensation portion 321 along the first direction, and the orthographic projection of the extended compensation portion 321 on the substrate of the display panel is located inside the orthographic projection of the compensation pattern 41b on the substrate.

[0102] The above arrangement enables the extended compensation portion 321 and the compensation pattern 41b arranged on different layers to jointly block the light-transmitting area of the display panel, better ensuring the light-shielding effect and optimizing the arrangement of the light-transmitting holes during the pixel layout period, thereby effectively reducing the periodic interference fringes collected during fingerprint recognition.

[0103] As Figure 19 shown, in some embodiments, the minimum width d5 of the compensation pattern 41b along the first direction satisfies: 1.9 μm ≤ d5 ≤ 2.3 μm;

[0104] The maximum width d6 of the compensation pattern 41b along the first direction satisfies: 5.2 μm ≤ d6 ≤ 5.6 μm;

[0105] The minimum width d7 of the compensation pattern 41b along the second direction satisfies: 3.4 μm ≤ d7 ≤ 3.8 μm;

[0106] The maximum width d8 of the compensation pattern 41b along the second direction satisfies: 6 μm ≤ d8 ≤ 6.4 μm.

[0107] Setting the dimensions of the compensation pattern 41b in the first direction and the second direction within the above ranges not only increases the light-shielding area of the compensation pattern 41b, further optimizes the arrangement of the light-transmitting holes during the pixel layout period, but also enables the compensation pattern 41b to effectively avoid other adjacent functional patterns around it, ensuring a larger shielding area while avoiding short circuits with other functional patterns and guaranteeing the production yield of the display panel.

[0108] As Figure 1 、 Figures 3 to 12 shown, in some embodiments, the display panel further includes: a first initialization signal transmission layer, the first initialization signal transmission layer includes a plurality of first initialization signal lines Vinit1, and at least a part of the first initialization signal lines Vinit1 extends along the first direction;

[0109] The sub-pixel driving circuit further includes a driving transistor T3, a first reset transistor T1, and a first conductive connection portion 21. A second pole of the first reset transistor T1 is coupled to a gate of the driving transistor T3;

[0110] The first conductive connection portion 21 includes a first main portion 51. The first main portion 51 is respectively coupled to a first pole of the corresponding first reset transistor T1 and a corresponding first initialization signal line Vinit1;

[0111] As Figure 6 shown, a part of the first conductive connection portion 21 further includes a first compensation portion 52 coupled to the first main portion 51. In a layout area of the sub-pixel driving circuits in the same row arranged in a first direction, the first compensation portion 52 and the extended compensation portion 321 are alternately arranged in the first direction.

[0112] Exemplarily, the first initialization signal transmission layer includes a plurality of first initialization signal lines Vinit1 and a plurality of first initialization compensation lines Vinit1'. The plurality of first initialization signal lines Vinit1 are sequentially arranged in the second direction. Each first initialization signal line Vinit1 includes at least a part extending in the first direction. The first initialization signal line Vinit1 is provided with the same layer and the same material as the second gate metal layer. The plurality of first initialization compensation lines Vinit1' are sequentially arranged in the first direction. Each first initialization compensation line Vinit1' includes at least a part extending in the second direction. The first initialization compensation line Vinit1' is provided with the same layer and the same material as the second source-drain metal layer.

[0113] Exemplarily, the first main portion 51 is coupled to the first pole of the corresponding first reset transistor T1 through a fourteenth via Via14, and the first main portion 51 is coupled to the corresponding first initialization signal line Vinit1 through a fifteenth via Via15.

[0114] Exemplarily, a part of the first conductive connection portion 21 further includes a first compensation portion 52 formed as an integral structure with the first main portion 51. A part of the first compensation portion 52 is coupled to the corresponding first initialization compensation line Vinit1' through a sixteenth via Via16, and another part of the first compensation portion 52 is not coupled to the corresponding first initialization compensation line Vinit1' through the sixteenth via Via16.

[0115] Exemplarily, a plurality of first initialization signal lines Vinit1 and a plurality of first initialization compensation lines Vinit1' included in the first initialization signal transmission layer together form a grid-like structure for transmitting a first initialization signal, and the first reset transistor T1 uses the first initialization signal to reset the gate of the driving transistor T3.

[0116] It should be noted that the layout area of the sub-pixel driving circuits in the same row arranged along the first direction refers to the layout area occupied by all the sub-pixel driving circuits in the same row arranged along the first direction. The layout area occupied by each sub-pixel driving circuit can be an area capable of accommodating the sub-pixel driving circuit. Exemplarily, this area can be selected as a rectangular area, but is not limited thereto.

[0117] In the display panel provided in the above embodiment, the first initialization signal transmission layer is provided with a plurality of first initialization signal lines Vinit1 and a plurality of first initialization compensation lines Vinit1', so that the first initialization signal transmission layer forms a grid-like structure, which is beneficial to better reducing the Loading when the first initialization signal transmission layer transmits the first initialization signal.

[0118] Moreover, in the display panel provided in the above embodiment, in the layout area of the sub-pixel driving circuits in the same row arranged along the first direction, the first compensation part 52 and the extended compensation part 321 are alternately arranged along the first direction, so that the first compensation part 52 and the extended compensation part 321 can alternately block the light-transmitting area of the display panel along the first direction, optimizing the arrangement of the light-transmitting holes within the pixel layout period, realizing the uniform arrangement of the light-transmitting holes formed by various functional patterns with light-shielding properties in the display panel within the period, being able to achieve that the difference in the distribution consistency of the light-transmitting hole shape in the horizontal and vertical directions is less than 5%, thereby eliminating the periodic interference stripes collected during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0119] More specifically, Figure 13 It is a schematic diagram of the distribution of the light-transmitting holes formed after the active layer, the first source-drain metal layer, and the second source-drain metal layer of the display panel provided in the embodiment of the present invention are stacked; Figure 14 It is a schematic diagram of the distribution of the light-transmitting holes formed after the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer of the display panel provided in the embodiment of the present invention are stacked; Figure 17Schematic diagram of the distribution of light-transmitting holes formed after the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the anode layer in the display panel provided by the embodiment of the present invention are stacked; it can be seen from the above drawings that the light-transmitting holes formed by various functional patterns with light-shielding properties in the display panel are evenly arranged within a period, and the difference in the distribution consistency of the shapes of the light-transmitting holes in the horizontal and vertical directions within the period can be less than 5%.

[0120] Figure 20 Schematic diagram of periodically collected interference fringes in the related art; Figure 21 Schematic diagram of fingerprint stripes collected in the display panel provided by the embodiment of the present invention; comparison Figure 20 and Figure 21 It can be seen that the periodically collected interference fringes in the fingerprint stripes collected by the display panel provided by the embodiment of the present invention are eliminated.

[0121] Such as Figure 6 shown, in some embodiments, the width of the first compensation part 52 along the first direction is set to be substantially the same as the width of the extended compensation part 321 along the first direction.

[0122] The above setting method improves the consistency of the shielding widths of the first compensation part 52 and the extended compensation part 321 in the first direction, further optimizes the arrangement of the light-transmitting holes within the pixel layout period, realizes the uniform arrangement of the light-transmitting holes formed by various functional patterns with light-shielding properties in the display panel within the period, and can achieve a difference in the distribution consistency of the light-transmitting hole shapes in the horizontal and vertical directions of less than 5%, thereby eliminating the periodically collected interference fringes during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively improving the performance of fingerprint recognition.

[0123] Such as Figures 3 to 16 shown, in some embodiments, the display panel further includes a third initialization signal layer, and the third initialization signal transmission layer includes a plurality of third initialization signal lines Vinit3 and a plurality of third initialization compensation lines; the plurality of third initialization signal lines Vinit3 are arranged in sequence along the second direction, each third initialization signal line Vinit3 includes at least a part extending along the first direction, and the third initialization signal line Vinit3 is arranged on the same layer and made of the same material as the second gate metal layer; the plurality of third initialization compensation lines are arranged in sequence along the first direction, each third initialization compensation line includes at least a part extending along the second direction, and the third initialization compensation line is arranged on the same layer and made of the same material as the second source-drain metal layer.

[0124] Exemplarily, the sub-pixel driving circuit further includes a seventh conductive connection portion 27. The seventh conductive connection portion 27 is coupled to a first pole of a third reset transistor T8 through a seventeenth via Via17, and the seventh conductive connection portion 27 is coupled to a third initialization signal line Vinit3 through an eighteenth via Via18. A part of the seventh conductive connection portion 27 is coupled to a third initialization compensation line through a nineteenth via.

[0125] Exemplarily, multiple first initialization compensation lines Vinit1’, multiple second initialization compensation lines Vinit2’, and multiple third initialization compensation lines in the display panel form multiple groups of signal line groups arranged in sequence along a first direction. Each group of signal line groups includes a first initialization compensation line Vinit1’, a first second initialization compensation line Vinit2’, a third initialization compensation line, and a second second initialization compensation line Vinit2’ arranged in sequence along the first direction.

[0126] Exemplarily, multiple third initialization signal lines Vinit3 and multiple third initialization compensation lines included in the third initialization signal transmission layer jointly form a grid-like structure for transmitting a third initialization signal. The third reset transistor T8 uses the third initialization signal to reset a first pole of a driving transistor T3.

[0127] Exemplarily, the third initialization compensation line has the same structure as the first initialization compensation line Vinit1’, and is only connected to the corresponding initialization signal line through different vias.

[0128] In the display panel provided in the above embodiment, the third initialization signal transmission layer is provided to include multiple third initialization signal lines Vinit3 and multiple third initialization compensation lines, so that the third initialization signal transmission layer forms a grid-like structure, which is beneficial to better reducing the Loading when the third initialization signal transmission layer transmits the third initialization signal.

[0129] Moreover, by arranging the first initialization compensation line Vinit1’, the second initialization compensation line Vinit2’, and the third initialization compensation line in the above manner, the first initialization compensation line Vinit1’, the second initialization compensation line Vinit2’, and the third initialization compensation line can periodically block the light-transmitting area of the display panel along the first direction, optimizing the arrangement of the light-transmitting holes within the pixel layout period, and enabling the distribution consistency difference of the light-transmitting hole shape in the horizontal and vertical directions to be less than 5%, thereby eliminating the periodic interference stripes collected during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0130] In some embodiments, the display panel further includes a first source-drain metal layer and a second source-drain metal layer. The first compensation portion 52 is provided on the same layer and made of the same material as the first source-drain metal layer; the extended compensation portion 321 is provided on the same layer and made of the same material as the first source-drain metal layer; the compensation pattern 41b is provided on the same layer and made of the same material as the second source-drain metal layer.

[0131] The above arrangement enables the fabrication of the first compensation portion 52, the extended compensation portion 321, and the compensation pattern 41b without introducing additional processes, that is, it can be compatible with the existing processes in the display panel. The above arrangement enables the display panel to improve the light-shielding area and optimize the arrangement of the light-transmitting holes within the pixel layout period by designing the first source-drain metal layer and the second source-drain metal layer.

[0132] An embodiment of the present invention further provides a display device, including the display panel provided in the above embodiment.

[0133] It should be noted that the display device may be: a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, or any other product or component with a display function. Among them, the display device further includes a flexible circuit board, a printed circuit board, a backplane, etc.

[0134] Exemplarily, the display panel includes an OLED flexible display panel, and the display device includes an OLED flexible display device, but is not limited thereto.

[0135] In the display panel provided in the above embodiment, it is set that the second initialization signal transmission layer includes a plurality of second initialization signal lines Vinit2 and a plurality of second initialization compensation lines Vinit2'. The second initialization signal line Vinit2 includes a second main portion 31 and a second extended portion 32. The second main portion 31 is coupled to the first pole of the corresponding second reset transistor T7. The second extended portion 32 includes an extended connection portion 320 and an extended compensation portion 321. The first end 320a of the extended connection portion 320 is coupled to the second main portion 31, and the second end 320b of the extended connection portion 320 is respectively coupled to the extended compensation portion 321 and the corresponding second initialization compensation line Vinit2'. This arrangement enables the second initialization signal transmission layer to form a grid-like structure, which is beneficial to better reducing the Loading when the second initialization signal transmission layer transmits the second initialization signal; at the same time, it ensures good connection performance between the second initialization signal transmission layer and the first pole of the second reset transistor T7.

[0136] Moreover, in the display panel provided in the above embodiments, the second extension portion 32 is provided to include an extended connection portion 320 and an extended compensation portion 321, such that the extended compensation portion 321 can further block the light-transmitting area of the display panel, optimize the arrangement of the light-transmitting holes within the pixel layout period, effectively reduce the periodic interference fringes collected during fingerprint recognition, and through algorithm optimization in the later stage, the accuracy of fingerprint recognition can be not affected. Therefore, the display panel provided by the embodiments of the present invention realizes the uniform arrangement of the light-transmitting holes formed with various functional patterns having light-shielding properties within the period, and can achieve that the difference in the distribution consistency of the light-transmitting hole shape in the horizontal and vertical directions is less than 5%, thereby eliminating the periodic interference fringes collected during fingerprint recognition of the display product, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0137] Therefore, when the display device provided by the embodiments of the present invention includes the above display panel, it also has the above beneficial effects, which will not be elaborated herein.

[0138] It should be noted that the signal line extending in a certain direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is in the shape of a line, a line segment or a strip, the main portion extends in a certain direction, and the length of the main portion extending in a certain direction is greater than the length of the secondary portion extending in other directions.

[0139] It should be noted that the "same layer" in the embodiments of the present invention may refer to the film layers on the same structural layer. Or for example, the film layers in the same layer may be the film layers formed by the same film-forming process for forming a specific pattern, and then the layer structure formed by patterning the film layer by using the same mask through a single patterning process. According to the different specific patterns, the single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0140] In the method embodiments of the present invention, the sequence numbers of the steps cannot be used to limit the order of the steps. For those of ordinary skill in the art, without creative efforts, the changes in the order of the steps are also within the protection scope of the present invention.

[0141] It should be noted that the embodiments in this specification are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0142] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this invention belongs. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0143] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or intervening elements may be present.

[0144] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0145] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that: It includes a second initialization signal transmission layer and a plurality of sub-pixels; wherein, The sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprises a second reset transistor, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; The second initialization signal transmission layer includes a plurality of second initialization signal lines and a plurality of second initialization compensation lines; the second initialization signal line includes a second main body portion and a second extension portion, the second main body portion extends along a first direction, the second extension portion extends along a second direction, the second initialization compensation line extends along the second direction, and the first direction intersects with the second direction; The second main body is coupled to the first electrode of the corresponding second reset transistor; the second extension portion includes an extended connection portion and an extended compensation portion, the first end of the extended connection portion is coupled to the second main body, and the second end of the extended connection portion is respectively coupled to the extended compensation portion and the corresponding second initialization compensation line.

2. The display panel according to claim 1, characterized in that: The extending connecting portion includes a middle portion between a first end and a second end thereof, the middle portion has a first width along a first direction, and the width of the extending compensating portion along the first direction is greater than the first width.

3. The display panel according to claim 2, characterized in that: Along the second direction, a width of the extending compensating portion is smaller than a width of the second end of the extending connecting portion.

4. The display panel according to any one of claims 1 to 3, characterized in that: The minimum width d1 of the extended compensation portion along the first direction satisfies: 2.8 μm≤d1≤3.2 μm; The maximum width d2 of the extended compensation portion along the first direction satisfies: 5.3 μm≤d2≤5.7 μm; The minimum width d3 of the extended compensation portion along the second direction satisfies: 2.1 μm≤d3≤2.5 μm; A maximum width d4 of the extended compensating portion along the second direction satisfies: 3.4 μm≤d3≤3.8 μm.

5. The display panel according to any one of claims 1 to 3, characterized in that: The display panel further includes a first source-drain metal layer, and the extended compensation portion is provided in the same layer and with the same material as the first source-drain metal layer.

6. The display panel according to claim 1, characterized in that: An orthographic projection of the second initialization compensation line on the base substrate of the display panel at least partially overlaps with an orthographic projection of the extended compensation portion on the base substrate.

7. The display panel according to claim 6, characterized in that: The second initialization compensation line includes a plurality of first portions, a plurality of second portions, and a plurality of third portions, wherein the first portions and the second portions are alternately arranged, and a third portion is provided between the first portions and the second portions; The first portion includes a connection pattern and a compensation pattern; the connection pattern is coupled to the second end of the extended connection portion, and the orthographic projection of the compensation pattern on the substrate substrate at least partially overlaps with the orthographic projection of the extended compensation portion on the substrate substrate; A width of the compensation pattern along the first direction is greater than a width of the third portion along the first direction.

8. The display panel according to claim 7, characterized in that: The maximum width of the compensation pattern along the first direction is the same as the maximum width of the extended compensation portion along the first direction, and the orthographic projection of the extended compensation portion on the base substrate of the display panel is located inside the orthographic projection of the compensation pattern on the base substrate.

9. The display panel according to any one of claims 7 or 8, characterized in that: The minimum width d5 ​​of the compensation pattern along the first direction satisfies: 1.9 μm≤d5≤2.3 μm; The maximum width d6 of the compensation pattern along the first direction satisfies: 5.2 μm≤d6≤5.6 μm; The minimum width d7 of the compensation pattern along the second direction satisfies: 3.4 μm≤d7≤3.8 μm; A maximum width d8 of the compensation pattern along the second direction satisfies: 6 μm≤d8≤6.4 μm.

10. The display panel according to claim 7 or 8, characterized in that: The display panel further includes a second source-drain metal layer, and the compensation pattern and the second source-drain metal layer are provided in the same layer and with the same material.

11. The display panel according to claim 1, characterized in that: The display panel further includes: a first initialization signal transmission layer, the first initialization signal transmission layer comprising a plurality of first initialization signal lines, the first initialization signal lines comprising at least a portion extending along the first direction; The sub-pixel driving circuit further includes a driving transistor, a first reset transistor and a first conductive connection portion, wherein a second electrode of the first reset transistor is coupled to a gate of the driving transistor; The first conductive connection portion includes a first main body portion, and the first main body portion is respectively coupled to the first electrode of the corresponding first reset transistor and the corresponding first initialization signal line; Part of the first conductive connection portion also includes a first compensation portion coupled to the first main portion, and in a layout area of ​​sub-pixel driving circuits in the same row arranged along the first direction, the first compensation portion and the extended compensation portion are alternately arranged along the first direction.

12. The display panel according to claim 11, characterized in that: The first initialization signal transmission layer further includes: a plurality of first initialization compensation lines, the first initialization compensation lines extending along the second direction, and the first initialization compensation lines coupled to corresponding first compensation parts.

13. The display panel according to claim 12, characterized in that: A width of the first compensating portion along the first direction is substantially the same as a width of the extending compensating portion along the first direction.

14. The display panel according to any one of claims 11 to 13, characterized in that: The display panel further includes a first source-drain metal layer, and the first compensation portion is provided in the same layer and with the same material as the first source-drain metal layer.

15. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 14.

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