Array substrate and display panel

Abstract

The invention relates to an array substrate and a display panel. The array substrate comprises a substrate body and a plurality of pixel circuit layers arranged on one side of the substrate body, each pixel circuit layer comprises a pixel electrode, a first transistor and a second transistor, and the first transistor and the second transistor are connected with the pixel electrode; the first transistor comprises a first grid electrode, a first source electrode and a first drain electrode; the second transistor comprises a second grid electrode, a second source electrode and a second drain electrode; wherein the second source electrode or the second drain electrode and the first grid electrode are the same electrode. According to the scheme, the damage risk resistance of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] With the development of science and technology, electronic devices such as mobile phones, tablets, and TVs are widely used in people's daily lives. The display screens of such electronic devices all rely on the support of display panels, and the core component of the display panel is the array substrate.

[0003] However, the current array substrate still needs to be further improved in terms of structural design to reduce the risk of easy damage to the display panel. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide an array substrate and a display panel that can improve the anti-damage risk ability of the display panel.

[0005] In a first aspect, the present application provides an array substrate, which includes a substrate and a plurality of pixel circuit layers disposed on one side of the substrate. Each pixel circuit layer includes a pixel electrode, a first transistor, and a second transistor connected to the pixel electrode.

[0006] The first transistor includes a first gate, a first source, and a first drain; the second transistor includes a second gate, a second source, and a second drain.

[0007] Wherein, the second source or the second drain is the same electrode as the first gate.

[0008] In one embodiment, the first source or the first drain is connected to the pixel electrode, and the second source or the second drain is connected to the pixel electrode; the pixel circuit layer further includes a first insulating layer, a second insulating layer, a third insulating layer, a first active layer, and a second active layer.

[0009] The first active layer is disposed on one side of the substrate and isolates the first source and the first drain.

[0010] The first insulating layer covers the first active layer, the first source, and the first drain.

[0011] The second active layer is disposed on the side of the first insulating layer away from the substrate and isolates the second source and the second drain.

[0012] The second insulating layer covers the second active layer, the second source, and the second drain.

[0013] The second gate is disposed on the side of the second insulating layer away from the substrate.

[0014] The third insulating layer covers the second gate.

[0015] The pixel electrode is disposed on a side of the third insulating layer away from the substrate.

[0016] In one embodiment, the first source electrode and the first drain electrode are disposed on the same layer as the first active layer; or,

[0017] The first electrode portion of the first source electrode and the first electrode portion of the first drain electrode are disposed on a side of the first active layer away from the substrate, and the second electrode portion of the first source electrode and the second electrode portion of the first drain electrode are disposed on the same layer as the first active layer; or,

[0018] The first electrode portion of the first active layer is disposed on a side of the first source electrode and the first drain electrode away from the substrate, and the second electrode portion of the first active layer is disposed on the same layer as the first source electrode and the first drain electrode.

[0019] In one embodiment, the second source electrode and the second drain electrode are disposed on the same layer as the second active layer; or,

[0020] The first electrode portion of the second source electrode and the first electrode portion of the second drain electrode are disposed on a side of the second active layer away from the substrate, and the second electrode portion of the second source electrode and the second electrode portion of the second drain electrode are disposed on the same layer as the first active layer; or,

[0021] The first electrode portion of the second active layer is disposed on a side of the second source electrode and the second drain electrode away from the substrate, and the second electrode portion of the second active layer is disposed on the same layer as the second source electrode and the second drain electrode.

[0022] In one embodiment, the first active layer and the second active layer are made of the same material.

[0023] In one embodiment, the materials of the first active layer and the second active layer both include polysilicon, amorphous silicon, or metal oxide.

[0024] In one embodiment, a first via hole extending from the third insulating layer to the first source electrode or the first drain electrode is provided in the array substrate to connect the first source electrode or the first drain electrode to the pixel electrode; and

[0025] A second via hole extending from the third insulating layer to the second source electrode or the second drain electrode is provided in the array substrate to connect the second source electrode or the second drain electrode to the pixel electrode.

[0026] In one embodiment, the third insulating layer is a planar layer.

[0027] In one embodiment, the array substrate further includes signal lines; the signal lines are connected to the first transistor, the second transistor, and the controller.

[0028] In a second aspect, the present application further provides a display panel, and the display panel includes the array substrate according to any one of the above first aspects.

[0029] The above-mentioned array substrate includes a substrate and a plurality of pixel circuit layers disposed on one side of the substrate. Among them, each pixel circuit layer includes a pixel electrode, a first transistor, and a second transistor connected to the pixel electrode; the first transistor includes a first gate, a first source, and a first drain; the second transistor includes a second gate, a second source, and a second drain; wherein, the second source or the second drain is the same electrode as the first gate. In this way, the multiplexing of the gate and the source, or the multiplexing of the gate and the drain is realized. A pixel electrode is connected to two transistors. Therefore, when one of the transistors fails or its characteristics shift, another transistor can be activated, thereby reducing the damage risk of the array substrate and further enhancing the anti-damage risk ability of the display panel. Description of the Drawings

[0030] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0031] Figure 1 Schematic diagram of the structure of the array circuit in the related technology;

[0032] Figure 2 Schematic cross-sectional view of the array substrate in one embodiment;

[0033] Figure 3 Schematic diagram of the structure of the pixel circuit layer in one embodiment;

[0034] Figure 4 Schematic cross-sectional view of the first type of first transistor in one embodiment;

[0035] Figure 5 Schematic cross-sectional view of the second type of first transistor in one embodiment;

[0036] Figure 6 Schematic cross-sectional view of the third type of first transistor in one embodiment;

[0037] Figure 7 Schematic diagram of the structure of the array circuit corresponding to the array substrate in one embodiment;

[0038] Figure 8 Layout of the array substrate in one embodiment;

[0039] Figure 9 Schematic diagram of the structure of a display panel in one embodiment. Detailed Embodiments

[0040] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure content of the present application more thorough and comprehensive.

[0042] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0043] In this document, spatially relative terms such as "upper" and "lower" are defined with reference to the accompanying drawings. Therefore, it will be understood that "upper" and "lower" can be used interchangeably. It will be understood that when a layer is referred to as being "on" another layer, it can be directly formed on the other layer or there can also be an intermediate layer. Therefore, it will be understood that when a layer is referred to as being "directly on" another layer, no intermediate layer is inserted therebetween.

[0044] In the accompanying drawings, in order to clearly illustrate, the dimensions of layers and regions can be exaggerated. It can be understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element can be directly on the other layer or substrate, or there can also be an intermediate layer. Additionally, it can also be understood that when a layer is referred to as being "between" two layers, the layer can be the only layer between the two layers, or there can also be one or more intermediate layers. Additionally, the same reference numerals always represent the same elements.

[0045] Hereinafter, although terms such as "first", "second", etc. can be used to describe various components, these components do not necessarily have to be limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form of the expression has a significantly different meaning in the context. Furthermore, in the following embodiments, it will also be understood that the terms "comprising" and / or "having" used herein indicate the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0046] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements disposed therebetween. For example, when a layer, region, element, etc. are described as being connected or electrically connected, the layer, region, element, etc. can not only be directly connected or directly electrically connected, but also be connected or electrically connected through another layer, region, element, etc. disposed therebetween.

[0047] As used in the application documents, the term "and / or" includes any combination and all combinations of one or more of the related listed items. When an expression such as "at least one of..." is located after a list of elements, it modifies the entire list of elements rather than an individual element in the list.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0049] It should also be understood that terms such as "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0050] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, and this error range should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately", or "substantially" can mean within one or more standard deviations, which is not limited herein.

[0051] In addition, in the specification, the phrase "schematic diagram of planar distribution" refers to the drawing when observing the target part from above, and the phrase "schematic cross-sectional view" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0052] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0053] Refer to Figure 1As shown, the array circuit in the related art includes a plurality of pixel circuits, and each pixel circuit includes a transistor. When one or several transistors fail or their characteristics shift, the entire display panel will be irreversibly affected, resulting in the scrapping of the terminal or the screen body.

[0054] Based on this, it is necessary to propose effective technical means to solve the above problems. The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0055] Refer to Figure 2 As shown, a cross-sectional schematic diagram of an array substrate is provided. Figure 3 It is a schematic structural diagram of a pixel circuit layer provided by an embodiment of the present application. Combining Figure 2 and Figure 3 , the array substrate includes: a substrate 100 and a plurality of pixel circuit layers 200 disposed on one side of the substrate 100. Among them, each pixel circuit layer 200 includes a pixel electrode 201, a first transistor 202, and a second transistor 203 connected to the pixel electrode 201; the first transistor 202 includes a first gate M11, a first source M12, and a first drain M13; the second transistor 203 includes a second gate M21, a second source M22, and a second drain M23; among them, the second source M22 or the second drain M23 and the first gate M11 are the same electrode.

[0056] Specifically, the substrate 100 can provide functions such as protection and support for the array substrate. The substrate 100 can be a flexible substrate, and the material of the flexible substrate can be polyimide (PI), polyethylene naphthalate-2,6-dicarboxylate (PEN), polyethylene terephthalate (PET), etc., or a mixed material of the above-mentioned multiple materials. The substrate 100 can also be a hard substrate formed of materials such as glass.

[0057] The pixel electrode (Pixel Electrode, PIX) 201, the material can be a transparent conductive material, such as indium tin oxide (ITO).

[0058] Both the first transistor 202 and the second transistor 203 can be thin film transistors (TFTs). The first transistor 202 and the second transistor 203 do not work simultaneously. When the first transistor 202 is in the on state, the second transistor 203 is in the off state. Correspondingly, when the first transistor 202 is in the off state, the second transistor 203 is in the on state, where:

[0059] The materials of the first source M12, the first drain M13, the second gate M21, the second source M22, and the second drain M23 all include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0060] The first source M12 and the first drain M13 are arranged on the same layer and are disposed on one side of the substrate 100; the second source M22 and the second drain M23 are arranged on the same layer and are disposed on the side of the first source M12 and the first drain M13 away from the substrate 100, and the second gate M21 is disposed on the side of the second source M22 and the second drain M23 away from the substrate 100; using the second source M22 or the second drain M23 as the first gate M11 realizes the multiplexing of the gate and the source, or the multiplexing of the gate and the drain.

[0061] The above array substrate includes: a substrate 100 and a plurality of pixel circuit layers 200 disposed on one side of the substrate 100. Each pixel circuit layer 200 includes a pixel electrode 201, a first transistor 202, and a second transistor 203 connected to the pixel electrode 201; the first transistor 202 includes a first gate M11, a first source M12, and a first drain M13; the second transistor 203 includes a second gate M21, a second source M22, and a second drain M23; where the second source M22 or the second drain M23 and the first gate M11 are the same electrode. In this way, the multiplexing of the gate and the source, or the multiplexing of the gate and the drain is realized. One pixel electrode is connected to two transistors. Therefore, when one of the transistors fails or its characteristics shift, the other transistor can be activated, thereby reducing the damage risk of the array substrate and further enhancing the anti-damage risk ability of the display panel.

[0062] In an exemplary embodiment, continue to refer to Figure 2 As shown, the first source M12 or the first drain M13 is connected to the pixel electrode 201, and the second source M22 or the second drain M23 is connected to the pixel electrode 201. It should be noted that Figure 2 In the example where the second source M22 and the first gate M11 are the same electrode, the first drain M13 is connected to the pixel electrode 201, and the second drain M23 is connected to the pixel electrode 201, the pixel circuit layer 200 further includes a first insulating layer 204, a second insulating layer 205, a third insulating layer 206, a first active layer A1, and a second active layer A2.

[0063] In other words, the pixel circuit layer 200 includes a pixel electrode 201, a third insulating layer 205, a first transistor 202 and a second transistor 203 connected to the pixel electrode 201; the first transistor 202 includes a first gate M11, a first source M12, a first drain M13, a first active layer A1 and a first insulating layer 204; the second transistor 203 includes a second gate M21, a second source M22, a second drain M23, a second active layer A2 and a second insulating layer 205.

[0064] The first source M12 or the first drain M13 is connected to the pixel electrode 201, and the second source M22 or the second drain M23 is connected to the pixel electrode 201, realizing that one pixel electrode 201 is connected to two transistors, that is, the first transistor 202 and the second transistor 203. In this way, when one of the transistors fails or its characteristics shift, the other transistor can be activated to provide current for the pixel electrode 201, ensuring the normal operation of the array substrate.

[0065] The first active layer A1 is disposed on one side of the substrate 100 and isolates the first source M12 and the first drain M13; the first insulating layer 204 covers the first active layer A1, the first source M12 and the first drain M13.

[0066] The second active layer A2 is disposed on the side of the first insulating layer 204 away from the substrate 100 and isolates the second source M22 and the second drain M23; the second insulating layer 205 covers the second active layer A2, the second source M22 and the second drain M23.

[0067] The second gate M21 is disposed on the side of the second insulating layer 205 away from the substrate 100; the third insulating layer 206 covers the second gate M21.

[0068] The pixel electrode 201 is disposed on the side of the third insulating layer 206 away from the substrate 100.

[0069] Among them, the materials of the first insulating layer 204, the second insulating layer 205, and the third insulating layer 206 may all include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0070] The first insulating layer 204 is a gate insulating layer (Gate Insulator, GI) for isolating the first gate M11, the first source M12, the first drain M13, and the first active layer A1 in the first transistor 202, ensuring effective electrical isolation between the first gate M11 and the first active layer A1, the first gate M11 and the first source M12, the first gate M11 and the first drain M13, and between the first source M12 and the first drain M13.

[0071] The second insulating layer 205 is an Inter-Layer Dielectric (ILD), which is used to isolate the second gate M21, the second source M22, the second drain M23, and the second active layer A2 in the first transistor 203, ensuring effective electrical isolation between the second gate M21 and the second active layer A2, between the second gate M21 and the second source M22, between the second gate M21 and the second drain M23, and between the second source M22 and the second drain M23.

[0072] The third insulating layer 206 is a Planarization Layer (PLN), and its material can also be a resin material such as photoresist to achieve planarization, and it is used to isolate the pixel electrode 201 and the second gate M21, ensuring effective electrical isolation between the pixel electrode 201 and the second gate M21.

[0073] Optionally, the positive projection of the first active layer A1 on the substrate 100 overlaps with the positive projection of the second source M22 on the substrate 100, or the positive projection of the first active layer A1 on the substrate 100 overlaps with the positive projection of the second drain M23 on the substrate 100, so as to use the second source M22 or the second drain M23 as the top gate of the first active layer A1.

[0074] The positive projection of the second active layer A2 on the substrate 100 overlaps with the positive projection of the second gate M21 on the substrate 100, so as to use the second gate M21 as the top gate of the second active layer A2.

[0075] Herein, the overlap of A and B means that the positive projections of A and B on the substrate overlap at least partially, that is, partially overlap or completely overlap.

[0076] In an exemplary embodiment, the positional relationship among the first source M12, the first drain M13, and the first active layer A1 in the first transistor 202 can be as follows:

[0077] Referring to Figure 4 As shown, the first source M12 and the first drain M13 are arranged on the same layer as the first active layer A1. That is, on the substrate 100, in the first direction, the first source M12, the first active layer A1, and the first drain M13 are arranged in sequence.

[0078] In addition, the surfaces of the first source M12 and the first active layer A1 that are in contact with each other are both inclined planes or arc surfaces with a certain angle, which can reduce the risk of gaps between the first source M12 and the first active layer A1 during the manufacturing process, and avoid the risk of breakage of the first insulating layer 204 formed on the first active layer A1.

[0079] Referring to Figure 5As shown, the first electrode portion M121 of the first source electrode M12 and the first electrode portion M131 of the first drain electrode M13 are disposed on the side of the first active layer A1 away from the substrate 100, and the second electrode portion M122 of the first source electrode M12 and the second electrode portion M132 of the first drain electrode M13 are disposed on the same layer as the first active layer A1.

[0080] Among them, the first electrode portion M121 of the first source electrode M12 covers a part of the first active layer A1, the first electrode portion M131 of the first drain electrode M13 covers a part of the first active layer A1, and there is a gap between the first electrode portion M121 of the first source electrode M12 and the first electrode portion M131 of the first drain electrode M13.

[0081] Refer to Figure 6 As shown, the first electrode portion A11 of the first active layer A1 is disposed on the side of the first source electrode M12 and the first drain electrode M13 away from the substrate 100, and the second electrode portion A12 of the first active layer A1 is disposed on the same layer as the first source electrode M12 and the first drain electrode M13.

[0082] Among them, the first electrode portion A11 of the first active layer A1 covers a part of the first source electrode M12, and the second electrode portion A12 of the first active layer A1 covers a part of the first source electrode M12.

[0083] In an exemplary embodiment, the positional relationship among the second source electrode M22, the second drain electrode M23, and the second active layer A2 in the second transistor 203 may be as follows:

[0084] The second source electrode M22 and the second drain electrode M23 are disposed on the same layer as the second active layer A2; or,

[0085] The first electrode portion of the second source electrode M22 and the first electrode portion of the second drain electrode M23 are disposed on the side of the second active layer A2 away from the substrate 100, and the second electrode portion of the second source electrode M22 and the second electrode portion of the second drain electrode M23 are disposed on the same layer as the first active layer A2; or,

[0086] The first electrode portion of the second active layer A2 is disposed on the side of the second source electrode M22 and the second drain electrode M23 away from the substrate 100, and the second electrode portion of the second active layer A2 is disposed on the same layer as the second source electrode M22 and the second drain electrode M23.

[0087] The various positional relationships among the second source electrode M22, the second drain electrode M23, and the second active layer A2 in the second transistor 203 in this embodiment are similar to the positional relationships among the first source electrode M12, the first drain electrode M13, and the first active layer A1 in the first transistor 202 above. Therefore, the various positional relationships among the second source electrode M22, the second drain electrode M23, and the second active layer A2 in the second transistor 203 may refer to Figures 4 - 6 , which will not be elaborated here.

[0088] In an exemplary embodiment, the materials of the first active layer A1 and the second active layer A2 are the same. The materials of the first active layer and the second active layer may both include polysilicon, amorphous silicon, or metal oxide.

[0089] Among them, according to different classifications of polysilicon, polysilicon may include P-type polysilicon or N-type polysilicon, and polysilicon may also include low-temperature polysilicon or high-temperature polysilicon.

[0090] Amorphous silicon may include hydrogenated amorphous silicon, etc. Metal oxide may include indium tin zinc oxide, indium gallium zinc oxide, etc.

[0091] In this embodiment, the materials of the first active layer A1 and the second active layer A2 are the same. Thus, the threshold voltages of the first transistor 202 and the second transistor 203 are the same or similar, thereby avoiding color disorder in pixel display caused by mischarging.

[0092] In an exemplary embodiment, continue to refer to Figure 2 As shown, a first via hole H1 extending from the third insulating layer 206 to the first source electrode M12 or the first drain electrode M13 is provided in the array substrate to connect the first source electrode M12 or the first drain electrode M13 to the pixel electrode 201; and a second via hole H2 extending from the third insulating layer 206 to the second source electrode M22 or the second drain electrode M23 is provided in the array substrate to connect the second source electrode M22 or the second drain electrode M23 to the pixel electrode 201.

[0093] Among them, a conductive layer covers the wall of the first via hole H1 and the wall of the second via hole H2. In this way, taking the first active layer A1 and the second active layer A2 as P-type polysilicon as an example, when the first transistor 202 is turned on, current can flow out from the first drain electrode M13 of the first transistor 202 and reach the pixel electrode 201 through the conductive layer on the wall of the first via hole H1; when the second transistor 203 is turned on, current can flow out from the second drain electrode M23 of the second transistor 203 and reach the pixel electrode 201 through the conductive layer on the wall of the second via hole H2.

[0094] In an exemplary embodiment, continue to refer to Figure 7 As shown, a schematic structural diagram of an array circuit corresponding to the array substrate is provided. The array substrate further includes signal lines; the signal lines are connected to the first transistor 202, the second transistor 203, and the controller.

[0095] Among them, the controller may be an integrated circuit chip (IC). The controller can realize the switching control of the first transistor 202 and the second transistor 203 through the signal lines.

[0096] In the array substrate, both the first transistor 202 and the second transistor 203 in each pixel circuit layer are connected to the controller through signal lines. Additionally, the controller is redundantly configured, for example, two controllers are set up. In this way, when one of the controllers is damaged, the other controller can be activated, thereby enhancing the anti-damage risk ability of the display panel.

[0097] In summary, referring to Figure 8 As shown, a layout of an array substrate is provided. The pixel electrode 201 is connected to a first pole and a second pole. The first pole is one of the first source M12 and the first drain M13, and the second pole is one of the second source M22 and the second drain M23. Whether the first pole and the second pole specifically act as a source or a drain depends on the materials of the first active layer A1 and the second active layer A2. Figure 8 In [reference], the first pole is taken as the first drain M13 and the second pole is taken as the second drain M23 as an example.

[0098] The first active layer A1 is connected to the first source M12 and the first drain M13, and the second active layer A2 is connected to the second source M22 and the second drain M23.

[0099] The second source M22 or the second drain M23 serves as the top gate of the first active layer A1 and covers the first active layer A1. Figure 8 In [reference], the second source M22 is taken as the top gate of the first active layer A1 as an example; the second gate M21 serves as the top gate of the second active layer A2 and covers the second active layer A2.

[0100] In one embodiment, referring to Figure 9 As shown, the present application further provides a display panel, and the display panel includes the array substrate described in any one of the above array substrate embodiments.

[0101] The display panel provided by the embodiments of the present application includes the array substrate in the above embodiments. Therefore, the display panel provided by the embodiments of the present application also has the beneficial effects described in the above embodiments, which will not be elaborated here. It should be noted that the display panel provided by the embodiments of the present application can be an organic light-emitting display panel or a liquid crystal display panel. Exemplarily, the display panel can be any product or component with a display function, such as a laptop computer, a tablet computer, or a monitor.

[0102] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0103] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a substrate and a plurality of pixel circuit layers arranged on one side of the substrate, wherein each of the pixel circuit layers comprises a pixel electrode and a first transistor and a second transistor connected to the pixel electrode; The first transistor includes a first gate, a first source and a first drain; the second transistor includes a second gate, a second source and a second drain; Wherein, the second source or the second drain and the first gate are the same electrode.

2. The array substrate according to claim 1, characterized in that: The first source electrode or the first drain electrode is connected to the pixel electrode, and the second source electrode or the second drain electrode is connected to the pixel electrode; the pixel circuit layer further includes a first insulating layer, a second insulating layer, a third insulating layer, a first active layer and a second active layer; The first active layer is disposed on one side of the substrate and isolates the first source and the first drain; The first insulating layer covers the first active layer, the first source electrode and the first drain electrode; The second active layer is disposed on a side of the first insulating layer away from the substrate and isolates the second source electrode and the second drain electrode; The second insulating layer covers the second active layer, the second source electrode and the second drain electrode; The second gate is arranged on a side of the second insulating layer away from the substrate; The third insulating layer covers the second gate; The pixel electrode is arranged on a side of the third insulating layer away from the substrate.

3. The array substrate according to claim 2, characterized in that: The first source electrode and the first drain electrode are arranged in the same layer as the first active layer; or, The first electrode portion of the first source electrode and the first electrode portion of the first drain electrode are arranged on a side of the first active layer away from the substrate, and the second electrode portion of the first source electrode and the second electrode portion of the first drain electrode are arranged in the same layer as the first active layer; or, The first electrode portion of the first active layer is arranged on a side of the first source and the first drain away from the substrate, and the second electrode portion of the first active layer is arranged in the same layer as the first source and the first drain.

4. The array substrate according to claim 2, characterized in that: The second source electrode and the second drain electrode are arranged in the same layer as the second active layer; or, The first electrode portion of the second source and the first electrode portion of the second drain are arranged on a side of the second active layer away from the substrate, and the second electrode portion of the second source and the second electrode portion of the second drain are arranged in the same layer as the first active layer; or, The first electrode portion of the second active layer is arranged on a side of the second source and the second drain away from the substrate, and the second electrode portion of the second active layer is arranged on the same layer as the second source and the second drain.

5. The array substrate according to claim 2, characterized in that: The first active layer and the second active layer are made of the same material.

6. The array substrate according to claim 2, characterized in that: Materials of the first active layer and the second active layer both include polysilicon, amorphous silicon or metal oxide.

7. The array substrate according to claim 2, characterized in that: The array substrate is provided with a first via hole extending from the third insulating layer to the first source electrode or the first drain electrode, so that the first source electrode or the first drain electrode is connected to the pixel electrode; as well as The array substrate is provided with a second via hole extending from the third insulating layer to the second source electrode or the second drain electrode, so as to connect the second source electrode or the second drain electrode with the pixel electrode.

8. The array substrate according to claim 2, characterized in that: The third insulating layer is a planar layer.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The array substrate further includes a signal line; The signal line is connected to the first transistor, the second transistor, and a controller.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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