Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.A pixel circuit column group of the display panel comprises a first pixel circuit column, a second pixel circuit column, a third pixel circuit column and a fourth pixel circuit column; the channel width of the first transistor of the first pixel circuit of the first pixel circuit column is different from the channel width of the first transistor of the second pixel circuit of the second pixel circuit column. A channel width of a first transistor of a third pixel circuit of the third pixel circuit column is different from a channel width of a first transistor of a fourth pixel circuit of the fourth pixel circuit column, the first pixel circuit drives a first color light emitting device or a third color light emitting device, and the second pixel circuit drives a second color light emitting device. The third pixel circuit drives the second color light-emitting device, and the fourth pixel circuit drives the third color light-emitting device or the first color light-emitting device. The display device comprises the display panel. Color cast can be improved, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed, and has become the focus of current research in the display field. When applied in a display panel, a pixel circuit is generally designed to provide a driving current for the OLED to drive the OLED to emit light, and the change in the magnitude of the driving current has an obvious influence on the emission brightness of the OLED.

[0003] However, in the pixel circuit of the existing OLED display panel, due to the fluctuation error of the pixel circuit process, there will be a situation where the magnitudes of the driving currents of different pixels are different. When the difference is serious, it is easy to cause display color deviation and display mura.

[0004] Therefore, providing a display panel and a display device that can improve color deviation, weaken the mura visual effect, and is beneficial to improving the display effect is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem that the existing display device is prone to color deviation during display, which affects the display quality.

[0006] The present disclosure provides a display panel, including a plurality of pixel circuits, and the pixel circuit includes a driving transistor and a first transistor that are electrically connected;

[0007] The plurality of pixel circuits at least include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit;

[0008] The display panel includes a plurality of pixel circuit column groups arranged in sequence along a first direction, and one pixel circuit column group includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column;

[0009] The first pixel circuit column includes a plurality of first pixel circuits, the second pixel circuit column includes a plurality of second pixel circuits, the third pixel circuit column includes a plurality of third pixel circuits, and the fourth pixel circuit column includes a plurality of fourth pixel circuits;

[0010] The channel width of the first transistor of the first pixel circuit is different from the channel width of the first transistor of the second pixel circuit. The channel width of the first transistor of the third pixel circuit is different from the channel width of the first transistor of the fourth pixel circuit. The channel width of the first transistor of the first pixel circuit is equal to the channel width of the first transistor of the third pixel circuit. The channel width of the first transistor of the second pixel circuit is equal to the channel width of the first transistor of the fourth pixel circuit;

[0011] The display panel includes a plurality of light-emitting devices, and the plurality of light-emitting devices include a first-color light-emitting device, a second-color light-emitting device, and a third-color light-emitting device;

[0012] The first pixel circuit drives the first-color light-emitting device or the third-color light-emitting device, the second pixel circuit drives the second-color light-emitting device, the third pixel circuit drives the second-color light-emitting device, and the fourth pixel circuit drives the third-color light-emitting device or the first-color light-emitting device.

[0013] Based on the same inventive concept, the present disclosure also provides a display device, and the display device includes the above-mentioned display panel.

[0014] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0015] The present disclosure provides a plurality of first pixel circuits to form a first pixel circuit column, and a plurality of second pixel circuits to form a second pixel circuit column. The channel width of the first transistor of the first pixel circuit is different from that of the first transistor of the second pixel circuit. The first pixel circuit drives a first color light-emitting device or a third color light-emitting device, and the second pixel circuit drives a second color light-emitting device. A plurality of third pixel circuits form a third pixel circuit column, and a plurality of fourth pixel circuits form a fourth pixel circuit column. The channel width of the first transistor of the third pixel circuit is different from that of the first transistor of the fourth pixel circuit. The channel width of the first transistor of the third pixel circuit is the same as that of the first transistor of the first pixel circuit, and the channel width of the first transistor of the fourth pixel circuit is the same as that of the first transistor of the second pixel circuit. At this time, the color of the light-emitting device driven by the third pixel circuit is different from the color of the light-emitting device driven by the first pixel circuit. The third pixel circuit drives the second color light-emitting device, and the color of the light-emitting device driven by the fourth pixel circuit is different from the color of the light-emitting device driven by the second pixel circuit. The fourth pixel circuit drives the third color light-emitting device or the first color light-emitting device. Thus, the color deviation colors of the light-emitting regions corresponding to the third pixel circuit and the fourth pixel circuit are neutralized with the color deviation colors of the light-emitting regions corresponding to the first pixel circuit and the second pixel circuit. Furthermore, the color deviation problem can be improved in the overall visual effect, and the display quality can be enhanced. The present disclosure makes a relatively small change to the layout structure of the display panel, without changing the layout structures of the pixel circuits and the light-emitting devices, and without adopting a complex brightness compensation method. It only needs to make the first pixel circuit drive the first color light-emitting device or the third color light-emitting device, the second pixel circuit drive the second color light-emitting device, the third pixel circuit drive the second color light-emitting device, and the fourth pixel circuit drive the third color light-emitting device or the first color light-emitting device in a pixel circuit column group formed by four adjacent pixel circuit columns in the first direction, that is, change the color of the light-emitting device driven by the third pixel circuit and change the color of the light-emitting device driven by the fourth pixel circuit, then the display color deviation problem can be improved. The structure and the manufacturing process are relatively simple, which is beneficial to improving the manufacturing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are incorporated herein and form a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0018] Figure 1It is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 2 It is Figure 1 a schematic electrical connection structure diagram of a pixel circuit in

[0020] Figure 3 It is Figure 1 a partial enlarged schematic view of a pixel circuit in the J1 region of

[0021] Figure 4 a schematic layout structure diagram of a pixel circuit and a light-emitting device provided in the prior art;

[0022] Figure 5 It is Figure 4 a schematic curve diagram of color shift to pink or green caused by different driving current magnitudes of corresponding pixel circuits in

[0023] Figure 6 It is Figure 1 a partial enlarged schematic view of the layout of a pixel circuit and a light-emitting device in the J1 region of

[0024] Figure 7 It is Figure 1 another schematic electrical connection structure diagram of a pixel circuit in

[0025] Figure 8 It is Figure 7 a working timing diagram of a pixel circuit in

[0026] Figure 9 It is Figure 1 a partial enlarged schematic view of the arrangement of light-emitting devices in a partial region of

[0027] Figure 10 It is Figure 3 the pixel circuit of Figure 9 combined with the light-emitting device of

[0028] Figure 11 It is Figure 3 the pixel circuit of Figure 9 combined with another light-emitting device of

[0029] Figure 12 It is Figure 11 a partial enlarged schematic view of the J2 region in

[0030] Figure 13 It is Figure 12 a schematic cross-sectional structure diagram in the A-A' direction of

[0031] Figure 14 It is Figure 12A schematic cross-sectional structure diagram in the B-B' direction;

[0032] Figure 15 is Figure 12 A schematic cross-sectional structure diagram in the C-C' direction;

[0033] Figure 16 is Figure 12 A schematic cross-sectional structure diagram in the D-D' direction;

[0034] Figure 17 Another schematic plan view of the display panel provided by the embodiment of the present disclosure;

[0035] Figure 18 is Figure 17 A partial enlarged schematic view of the J3 area of;

[0036] Figure 19 is Figure 17 Another partial enlarged schematic view of the J3 area of;

[0037] Figure 20 Another schematic plan view of the display panel provided by the embodiment of the present disclosure;

[0038] Figure 21 Another schematic plan view of the display panel provided by the embodiment of the present disclosure;

[0039] Figure 22 is Figure 21 A partial enlarged schematic view of the J4 area of;

[0040] Figure 23 is Figure 22 A schematic layout diagram of the pixel circuit and the data line in;

[0041] Figure 24 is Figure 21 A partial enlarged schematic view of the corresponding area of multiple pixel circuit column groups in;

[0042] Figure 25 is Figure 24 A schematic layout diagram of the pixel circuit and the data line in;

[0043] Figure 26 A schematic plan view of the display device provided by the embodiment of the present disclosure. Detailed implementation manners

[0044] In order to more clearly understand the above objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0045] In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.

[0046] Please refer to Figures 1 - 3 , Figure 1 which is a schematic plan view of a display panel provided by an embodiment of the present disclosure, Figure 2 and Figure 1 is a schematic electrical connection structure diagram of the pixel circuit in Figure 3 and Figure 1 is a partial enlarged schematic diagram of the pixel circuit in the J1 region of Figure 1 (it can be understood that in order to clearly illustrate the structure of this embodiment,

[0047] the pixel circuit is represented by a frame diagram in

[0048] ). This embodiment provides a display panel 000, including a plurality of pixel circuits 10, and the pixel circuit 10 includes a driving transistor DT and a first transistor T1 that are electrically connected;

[0049] The plurality of pixel circuits 10 at least include a first pixel circuit 101, a second pixel circuit 102, a third pixel circuit 103, and a fourth pixel circuit 104;

[0050] The display panel 000 includes a plurality of pixel circuit column groups 10A arranged in sequence along a first direction X, and one pixel circuit column group 10A includes a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4;

[0051] The display panel 000 includes a plurality of light-emitting devices 20, and the plurality of light-emitting devices 20 include a first-color light-emitting device 201, a second-color light-emitting device 202, and a third-color light-emitting device 203;

[0052] The first pixel circuit 101 drives the first-color light-emitting device 201 or the third-color light-emitting device 203, the second pixel circuit 102 drives the second-color light-emitting device 202, the third pixel circuit 103 drives the second-color light-emitting device 202, and the fourth pixel circuit 104 drives the third-color light-emitting device 203 or the first-color light-emitting device 201.

[0053] Specifically, the display panel 000 provided in this embodiment may be an organic light-emitting diode display panel. The display panel 000 may include a substrate, which is used as a carrier substrate for arranging pixel circuits, light-emitting devices, and other structures of the display panel 000. It can be understood that the film layer structure of the display panel 000 will not be elaborated in this embodiment. When the display panel 000 is an OLED display panel, the pixel circuit 10 included in the display panel 000 may be fabricated by a driving array layer on the substrate. The thin-film transistor structure, capacitor structure, driving traces, etc. of the pixel circuit 10 or other driving circuits are set through a plurality of conductive layers and insulating layers included in the driving array layer. The light-emitting device 20 may be disposed on a side of the driving array layer away from the substrate. An anode, etc. may also be disposed between the light-emitting device and the driving array layer. This will not be elaborated in this embodiment, and specific understanding can be made with reference to the film layer structure of an OLED display panel in related technologies.

[0054] As Figure 2 shown, the pixel circuit 10 of this embodiment at least includes a driving transistor DT and a first transistor T1 that are electrically connected. The driving transistor DT and the first transistor T1 are used to generate a driving current and supply it to the light-emitting device 20 electrically connected to the pixel circuit 10, so that the light-emitting device 20 emits light for display. It can be understood that the first transistor T1 of this embodiment may be any transistor electrically connected to one pole of the driving transistor DT. For example, in the structure where the pixel circuit 10 in related technologies includes 7 transistors and 1 capacitor, the first transistor T1 can be understood as any one of the 7 transistors that satisfies being electrically connected to one pole (gate, source, or drain) of the driving transistor DT.

[0055] As Figure 3As shown, along the first direction X, the first direction X can be understood as the direction from one edge of the display panel 000 to the opposite edge. The display panel 000 includes a plurality of pixel circuit column groups 10A arranged in sequence along the first direction X. A pixel circuit column group 10A includes a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4. That is, a pixel circuit column group 10A includes the first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 arranged in sequence along the first direction X. The first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 can be understood as four adjacent pixel circuit columns in the first direction X, thus constituting a pixel circuit column group 10A. Among the plurality of pixel circuits 10 included in the display panel 000, there are at least a first pixel circuit 101, a second pixel circuit 102, a third pixel circuit 103, and a fourth pixel circuit 104. The first pixel circuit column 10A1 includes a plurality of first pixel circuits 101, the second pixel circuit column 10A2 includes a plurality of second pixel circuits 102, the third pixel circuit column 10A3 includes a plurality of third pixel circuits 103, and the fourth pixel circuit column 10A4 includes a plurality of fourth pixel circuits 104. That is, a plurality of first pixel circuits 101 constitute the first pixel circuit column 10A1, a plurality of second pixel circuits 102 constitute the second pixel circuit column 10A2, a plurality of third pixel circuits 103 constitute the third pixel circuit column 10A3, and a plurality of fourth pixel circuits 104 constitute the fourth pixel circuit column 10A4.

[0056] During the manufacturing process of the display panel, especially during the manufacturing process of the pixel circuit, errors are often easily generated due to process fluctuations. For example, in a pixel circuit column group 10A composed of four adjacent pixel circuit columns in the first direction X, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102, the channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is equal to the channel width W3 of the first transistor T1 of the third pixel circuit 103, and the channel width W2 of the first transistor T1 of the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. It can be understood that, as Figure 3 shown, for the purpose of clearly showing the channel region of the first transistor T1, Figure 3Other film layers of the pixel circuit are briefly arranged and not shown. In actual implementation, the pixel circuit may further include other conductive film layers, which are not elaborated in this embodiment; the gate T1G and the semiconductor part T1P of the first transistor T1 overlap to form a channel region. The entire scanning line G1 corresponding to the gate T1G is regarded as extending along the first direction X, and the entire semiconductor part T1P of the first transistor T1 is regarded as extending along the second direction Y. The first direction X and the second direction Y intersect or are perpendicular to each other. For example, if the first direction X is Figure 3 the horizontal direction in Figure 3 , then the second direction Y is

[0057] the vertical direction in Figure 3 . The channel width of the first transistor T1 is the width of the semiconductor part T1P of the first transistor T1 in the first direction X. The first direction X and the overall extension direction of the scanning line G1 corresponding to the gate T1G of the first transistor T1 are the same.

[0058] For example, as Figure 4 shown, Figure 4It is a schematic diagram of the layout structure of a pixel circuit and a light-emitting device provided in the prior art. Under the interference of process fluctuations in the prior art, in multiple repeated pixel circuit column groups 10A', the channel width W1' of the first transistor T1' of the first pixel circuit 101' is different from the channel width W2' of the first transistor T1' of the second pixel circuit 102', and the channel width W3' of the first transistor T1' of the third pixel circuit 103' is different from the channel width W4' of the first transistor T1' of the fourth pixel circuit 104'. The driving transistor DT' is used to generate a driving current. The difference in the channel width of the first transistor T1' electrically connected to the driving transistor DT' will cause different coupling capacitances, and thus cause differences in the driving current. For example, the channel width W1' of the first transistor T1' of the first pixel circuit 101' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B', the channel width W2' of the first transistor T1' of the second pixel circuit 102' is large and always corresponds to driving the green light-emitting device G', the channel width W3' of the first transistor T1' of the third pixel circuit 103' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B', and the channel width W4' of the first transistor T1' of the fourth pixel circuit 104' is large and always corresponds to driving the green light-emitting device G'. Then, the coupling capacitances in the second pixel circuit 102' and the fourth pixel circuit 104' with the large channel width W1' of the first transistor T1' are large, and the generated driving current is large, that is, the driving current obtained by the green light-emitting device G' is large, the brightness of the green light-emitting device G' is brighter, and the color is greener, resulting in a greenish color under high-brightness display and a color deviation problem.

[0059] Similarly, for example, the channel width of the first transistor of the first pixel circuit is large and always corresponds to driving the red light-emitting device or the blue light-emitting device, the channel width of the first transistor of the second pixel circuit is small and always corresponds to driving the green light-emitting device, the channel width of the first transistor of the third pixel circuit is large and always corresponds to driving the red light-emitting device or the blue light-emitting device, and the channel width of the first transistor of the fourth pixel circuit is small and always corresponds to driving the green light-emitting device. Then, the coupling capacitances in the first pixel circuit and the third pixel circuit with the large channel width of the first transistor are large, and the generated driving current is large, that is, the driving current obtained by the red light-emitting device or the blue light-emitting device is large, and the color is pinker, resulting in a pinkish color under high-brightness display and a color deviation problem.

[0060] As Figure 5 and Table 1 show, Figure 5 is Figure 4 a schematic curve diagram of pink or green deviation caused by different driving current magnitudes corresponding to different pixel circuits in Figure 4In the display panel, the CIEy value is too small and the color is pinkish, or the CIEy value is too large and the color is greenish due to the difference in the channel width of the first transistor in different pixel circuits. (It can be understood that CIEy refers to the Y coordinate value in the color space, which is usually used to represent the brightness or lightness of a color. In the CIE XYZ color space, the Y coordinate represents the luminance component of light, while the X and Z coordinates represent the red and blue color components respectively.)

[0061] Table 1:

[0062]

[0063] Specifically, from Figure 5 and Table 1, it can be seen that Figure 4 In the multiple repeated pixel circuit column groups 10A’ shown in the figure, if the channel width W1’ of the first transistor T1’ in the first pixel circuit 101’ is large and always corresponds to driving the red light-emitting device R’ or the blue light-emitting device B’, the channel width W2’ of the first transistor T1’ in the second pixel circuit 102’ is small and always corresponds to driving the green light-emitting device G’, the channel width W3’ of the first transistor T1’ in the third pixel circuit 103’ is large and always corresponds to driving the red light-emitting device R’ or the blue light-emitting device B’, and the channel width W4’ of the first transistor T1’ in the fourth pixel circuit 104’ is small and always corresponds to driving the green light-emitting device G’, then the coupling capacitors in the first pixel circuit 101’ and the third pixel circuit 103’ with a large channel width of the first transistor T1’ are large, and the generated driving current is large, that is, the driving current obtained by the red light-emitting device R’ or the blue light-emitting device B’ is large, and the driving current obtained by the green light-emitting device G’ is small, and the color is more pinkish (such as Figure 5 the schematic diagram of the driving current size shown in the pinkish color). The CIEy value is negative and too small, that is, it is more pinkish (as shown in the brightness and chromaticity values in the row with color deviation being pinkish in Table 1); that is, the light-emitting device areas corresponding to the first pixel circuit 101’ and the second pixel circuit 102’ are always pinkish, and the light-emitting device areas corresponding to the third pixel circuit 103’ and the fourth pixel circuit 104’ are also always pinkish, thereby resulting in the color deviation problem that the entire display panel is pinkish. Similarly, if Figure 4In the schematic repeated multiple pixel circuit column groups 10A', the channel width W1' of the first transistor T1' of the first pixel circuit 101' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B'. The channel width W2' of the first transistor T1' of the second pixel circuit 102' is large and always corresponds to driving the green light-emitting device G'. The channel width W3' of the first transistor T1' of the third pixel circuit 103' is small and always corresponds to driving the red light-emitting device R' or the blue light-emitting device B'. The channel width W4' of the first transistor T1' of the fourth pixel circuit 104' is large and always corresponds to driving the green light-emitting device G'. Then, the coupling capacitors in the second pixel circuit 102' and the fourth pixel circuit 104' with a large channel width of the first transistor T1' are large, and the generated driving current is large. That is, the driving current obtained by the red light-emitting device R' or the blue light-emitting device B' is small, and the driving current obtained by the green light-emitting device G' is large, and the color is greener (such as Figure 5 shown in the schematic diagram of the driving current magnitude for green emission in the middle). The CIEy value is positive, and a larger value means a greener color (as shown in the brightness and chromaticity values in the row indicating green color deviation in Table 1). That is, the light-emitting device regions corresponding to the first pixel circuit 101' and the second pixel circuit 102' are always greenish, and the light-emitting device regions corresponding to the third pixel circuit 103' and the fourth pixel circuit 104' are also always greenish, thus resulting in a color deviation problem where the entire display panel is greenish.

[0064] To solve the above problem, as Figures 1 - 3 、 Figure 6 shown, Figure 6 is Figure 1 a partial enlarged schematic diagram of the layout of the pixel circuit and the light-emitting device in the J1 region of Figure 6(differently indicated by different filling patterns for different colors), the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201. That is, multiple first pixel circuits 101 form the first pixel circuit column 10A1, multiple second pixel circuits 102 form the second pixel circuit column 10A2. The channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102. The first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, and the second pixel circuit 102 drives the second color light-emitting device 202. Multiple third pixel circuits 103 form the third pixel circuit column 10A3, and multiple fourth pixel circuits 104 form the fourth pixel circuit column 10A4. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is the same as the channel width W1 of the first transistor T1 of the first pixel circuit 101, and the channel width W4 of the first transistor T1 of the fourth pixel circuit 104 is the same as the channel width W2 of the first transistor T1 of the second pixel circuit 102. At this time, the color of the light-emitting device driven by the third pixel circuit 103 is different from the color of the light-emitting device driven by the first pixel circuit 101. The third pixel circuit 103 drives the second color light-emitting device 202, and the color of the light-emitting device driven by the fourth pixel circuit 104 is different from the color of the light-emitting device driven by the second pixel circuit 102. The fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201.

[0065] Therefore, if the channel width W1 of the first transistor T1 of the first pixel circuit 101 is greater than the channel width W2 of the first transistor T1 of the second pixel circuit 102, the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is large, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is small. The light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased toward the color of the first color light-emitting device 201 or the third color light-emitting device 203. If the channel width W3 of the first transistor T1 of the third pixel circuit 103 is greater than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is large, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is small. The light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased toward the color of the second color light-emitting device 202. Therefore, in the light-emitting region corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the color shift colors of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralize the color shift colors of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102. Furthermore, the color shift problem can be improved and the display quality can be enhanced in the overall visual effect.

[0066] Similarly, if the channel width W1 of the first transistor T1 of the first pixel circuit 101 is smaller than the channel width W2 of the first transistor T1 of the second pixel circuit 102, the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased toward the color of the second color light-emitting device 202. If the channel width W3 of the first transistor T1 of the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased toward the color of the first color light-emitting device 201 or the third color light-emitting device 203. Therefore, in the light-emitting region corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the color shift colors of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 are neutralized with the color shift colors of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102. Furthermore, the color shift problem can be improved, the mura problem can be improved, and the display quality can be improved in terms of the overall visual effect.

[0067] The structure for improving the display color shift in this embodiment has a small change to the layout structure of the display panel 000. There is no need to change the layout structure of the pixel circuit and the layout structure of the light-emitting device, nor to adopt a complex brightness compensation method. Only in a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, that is, changing the color of the light-emitting device driven by the third pixel circuit 103 and changing the color of the light-emitting device driven by the fourth pixel circuit 104 can improve the display color shift problem. The structure and the manufacturing process are relatively simple, which is beneficial to improving the manufacturing efficiency.

[0068] It can be understood that in this embodiment, the first pixel circuit 101 driving the first-color light-emitting device 201 or the third-color light-emitting device 203 means that the first pixel circuits 101 located in different rows can drive light-emitting devices of different colors. For example, the first pixel circuit 101 in the first row drives the first-color light-emitting device 201, and the first pixel circuit 101 in the second row drives the third-color light-emitting device 203. The fourth pixel circuit 104 driving the third-color light-emitting device 203 or the first-color light-emitting device 201 means that the fourth pixel circuits 104 located in different rows can drive light-emitting devices of different colors. For example, the fourth pixel circuit 104 in the first row drives the third-color light-emitting device 203, and the fourth pixel circuit 104 in the second row drives the first-color light-emitting device 201. And the first pixel circuit 101 and the fourth pixel circuit 104 in the same row drive light-emitting devices of different colors. For example, if the first pixel circuit 101 in the first row drives the first-color light-emitting device 201, then the fourth pixel circuit 104 in the first row drives the third-color light-emitting device 203; if the first pixel circuit 101 in the second row drives the third-color light-emitting device 203, then the fourth pixel circuit 104 in the second row drives the first-color light-emitting device 201.

[0069] It can be understood that the arrangement manner of the multiple light-emitting devices 20 included in the display panel 000 in this embodiment can adopt the arrangement manner in the prior art. This embodiment Figure 6 is only an example. In specific implementation, other known arrangement manners can be adopted.

[0070] Optionally, in this embodiment, it is shown that the first pixel circuit 101 drives the first-color light-emitting device 201 or the third-color light-emitting device 203, the second pixel circuit 102 drives the second-color light-emitting device 202, the third pixel circuit 103 drives the second-color light-emitting device 202, and the fourth pixel circuit 104 drives the third-color light-emitting device 203 or the first-color light-emitting device 201. The driving can be realized through connection lines, such as Figure 6As shown, the first pixel circuit 101 is electrically connected to and drives the first color light-emitting device 201 or the third color light-emitting device 203 through the connection line L1, the second pixel circuit 102 is electrically connected to and drives the second color light-emitting device 202 through the connection line L2, the third pixel circuit 103 is electrically connected to and drives the second color light-emitting device 202 through the connection line L3, and the fourth pixel circuit 104 is electrically connected to and drives the third color light-emitting device 203 or the first color light-emitting device 201 through the connection line L4. Furthermore, the color of the light-emitting device driven by the third pixel circuit 103 is different from the color of the light-emitting device driven by the first pixel circuit 101, the color of the light-emitting device driven by the third pixel circuit 103 is the same as the color of the light-emitting device driven by the second pixel circuit 102, the color of the light-emitting device driven by the fourth pixel circuit 104 is different from the color of the light-emitting device driven by the second pixel circuit 102, and the color of the light-emitting device driven by the fourth pixel circuit 104 is the same as the color of the light-emitting device driven by the first pixel circuit 101. In the light-emitting area corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the color shift colors of the light-emitting areas corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 are neutralized with the color shift colors of the light-emitting areas corresponding to the first pixel circuit 101 and the second pixel circuit 102. Therefore, the color shift problem can be improved in the overall visual effect, and the display quality can be improved.

[0071] It should be noted that Figures 1 - 3 、 Figure 6 only the structure of the display panel 000 is exemplarily drawn. In specific implementation, the structure of the display panel includes but is not limited to this. The structure of the display panel in the figure of this embodiment is also only an example. In specific implementation, the structure of the display panel does not represent the shape, quantity, or area shown in the figure. For example, Figure 6 the shape of the light-emitting device 20 shown is only an example, and the shape layout of the pixel circuit 10 is also only an example. In specific implementation, it can be designed according to actual requirements.

[0072] Optionally, as Figure 6 shown, the first color light-emitting device 201 is one of a red light-emitting device or a blue light-emitting device, and the third color light-emitting device 203 is the other of a red light-emitting device or a blue light-emitting device; the second color light-emitting device 202 is a green light-emitting device. Taking the first color light-emitting device 201 as a red light-emitting device, the second color light-emitting device 202 as a green light-emitting device, and the third color light-emitting device 203 as a blue light-emitting device as an example.

[0073] If the channel width W1 of the first transistor T1 of the first pixel circuit 101 is greater than the channel width W2 of the first transistor T1 of the second pixel circuit 102, the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is large, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is small. The light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102 (such as Figure 6 the K1 region shown) may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, that is, biased towards pink. If the channel width W3 of the first transistor T1 of the third pixel circuit 103 is greater than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is large, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is small. The light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 (such as Figure 6 the K2 region shown) may be biased towards the color of the second color light-emitting device 202, that is, biased towards green. Therefore, in the light-emitting region corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the green bias of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the pink bias of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102. Furthermore, the color deviation problem can be improved and the display quality can be enhanced in terms of the overall visual effect.

[0074] Similarly, if the channel width W1 of the first transistor T1 in the first pixel circuit 101 is less than the channel width W2 of the first transistor T1 in the second pixel circuit 102, the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the second color light-emitting device 202, that is, towards green. If the channel width W3 of the first transistor T1 in the third pixel circuit 103 is less than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, that is, towards pink. Therefore, in the light-emitting region corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the pink bias of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the green bias of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102. Furthermore, the color deviation problem can be improved and the display quality can be enhanced in terms of the overall visual effect.

[0075] Optionally, as Figure 3 and Figure 6As shown, in this embodiment, during the manufacturing process of the display panel 000, especially during the manufacturing process of the pixel circuit 10, errors are often easily generated due to manufacturing process fluctuations. As a result, in a pixel circuit column group 10A composed of four adjacent pixel circuit columns in the first direction X, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102, and the channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. Moreover, the channel width W1 of the first transistor T1 of the first pixel circuit 101 is equal to the channel width W3 of the first transistor T1 of the third pixel circuit 103, and the channel width W2 of the first transistor T1 of the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. This is an inevitable difference caused by manufacturing process fluctuations. However, through the adjustment of the manufacturing process, the process fluctuations can be made as small as possible. For example, it can be achieved that the difference range between the channel width W1 of the first transistor T1 of the first pixel circuit 101 and the channel width W2 of the first transistor T1 of the second pixel circuit 102 is ∣W1 - W2∣ ≤ 0.1μm, and the difference range between the channel width W3 of the first transistor T1 of the third pixel circuit 103 and the channel width W4 of the first transistor T1 of the fourth pixel circuit 104 is ∣W3 - W4∣ ≤ 0.1μm. Thus, within the process adjustable range, the difference between the driving currents of different pixel circuits 10 caused by process fluctuations is minimized as much as possible, which is beneficial to improving color deviation, enhancing visual effects, and improving the display effect.

[0076] It can be understood that in this embodiment and subsequent embodiments, an example is given where the channel width W1 of the first transistor T1 of the first pixel circuit 10 is less than the channel width W2 of the first transistor T1 of the second pixel circuit 102, and the channel width W3 of the first transistor T1 of the third pixel circuit 103 is less than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. In specific implementation, the channel width W1 of the first transistor T1 of the first pixel circuit 10 can also be greater than the channel width W2 of the first transistor T1 of the second pixel circuit 102, and the channel width W3 of the first transistor T1 of the third pixel circuit 103 can also be greater than the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. This embodiment does not make any limitations.

[0077] In some alternative embodiments, please refer to Figure 1 、 Figure 3 、 Figure 6 and Figure 7 , Figure 7 is Figure 1Another schematic diagram of the electrical connection structure of the pixel circuit. In this embodiment, the first transistor T1 is electrically connected between the gate and the first pole of the driving transistor DT, and the first transistor T1 is an N-type transistor. Optionally, the first transistor T1 can be an N-type metal oxide transistor, while the other transistors in the pixel circuit 10 can be P-type low-temperature polysilicon transistors. As Figure 7 shown, taking the pixel circuit 10 of this embodiment including 8 transistors and 1 storage capacitor Cst as an example, the first transistor T1 can be Figure 7 the transistor that is electrically connected between the gate (the first node N1) and the first pole (the third node N3) of the driving transistor DT and plays a threshold compensation role; or in some other alternative embodiments, the first transistor T1 can also be Figure 7 the transistor that is electrically connected between the gate (the first node N1) of the driving transistor DT and the first reference voltage signal terminal REF1 and plays a role in resetting the gate of the driving transistor DT. It should be noted that in this embodiment, the first transistor T1 is electrically connected between the gate and the first pole of the driving transistor DT. The first pole of the driving transistor DT can be one of the drain or the source, and the second pole of the driving transistor DT can be the other of the drain or the source. This embodiment does not limit this, and only the case where the first pole is the drain is taken as an example for illustration in the figure.

[0078] This embodiment takes Figure 7Taking the pixel circuit 10 shown as an example, in different pixel circuits 10, there are slight differences in the channel width of the first transistor T1 that plays a threshold compensation role and is electrically connected between the gate (the first node N1) and the first pole (the third node N3) of the driving transistor DT due to process fluctuations. For example, the channel width W1 of the first transistor T1 in the first pixel circuit 10 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 102, and the channel width W3 of the first transistor T1 in the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104. Moreover, the channel width W1 of the first transistor T1 in the first pixel circuit 10 is equal to the channel width W3 of the first transistor T1 in the third pixel circuit 103, and the channel width W2 of the first transistor T1 in the second pixel circuit 102 is equal to the channel width W4 of the first transistor T1 in the fourth pixel circuit 104. Then, during the light-emitting stage of the driving process of the display panel, the first transistor T1 is turned off. Since the first transistor T1 is an N-type transistor, the gate of the first transistor T1 is at a low potential. The potentials of the first node N1 and the third node N3 are both pulled down following due to the coupling of the gate potential of the first transistor T1 (there is a coupling capacitor C' between the first node N1 and the gate of the first transistor T1, and the coupling relationship is represented by a dotted line). The parasitic capacitance of the third node N3 is very small, that is, the potential of the third node N3 will be pulled very low. However, during the pulling-down process, the charge balance between the first node N1 and the third node N3 still needs to be maintained. Therefore, the potential of the first node N1 will also be pulled very low following the third node N3. If the channel width W2 of the first transistor T1 in the second pixel circuit 102 is larger, then compared with the potential of the first node N1 in the first pixel circuit 101, the potential of the first node N1 in the second pixel circuit 102 will be pulled lower. Then, the driving current on the driving transistor DT in the second pixel circuit 102 will be larger, and the light-emitting brightness will be brighter. That is, the second color light-emitting device 202 driven by the second pixel circuit 102 will be brighter. Then, it will cause the light-emitting area driven by the second pixel circuit 102 to be more biased towards the color of the second color light-emitting device 202, such as emitting green light.

[0079] In some other alternative embodiments, if the first transistor T1 is Figure 7 a transistor that is electrically connected between the gate (the first node N1) of the driving transistor DT and the first reference voltage signal terminal REF1 and plays a role in resetting the gate of the driving transistor DT, the principle of the color shift problem caused by the driving current difference is the same as above, and this embodiment will not be elaborated here.

[0080] Taking Figure 7 the pixel circuit 10 shown as an example, combined with Figure 8 , Figure 8 is Figure 7A timing diagram of the operation of the middle pixel circuit. When the display panel 000 of this embodiment performs driving operations, it may include a first bias adjustment stage tj1, a reset stage tj2, a threshold compensation and data writing stage tj3, a second bias adjustment stage tj4, and a light emitting stage tj5;

[0081] In the first bias adjustment stage tj1, that is, before resetting the gate of the driving transistor DT, the bias control signal terminal SCP* inputs a low-level bias control signal to control the fourth transistor T4 to conduct, and the second scan signal terminal SCN2 inputs a high-level second scan signal to control the first transistor T1 to conduct. Then, the bias adjustment signal provided by the bias adjustment signal terminal DVH is transmitted to the gate of the driving transistor DT (i.e., the first node N1) through the fourth transistor T4 and the first transistor T1, adjusting the bias state of the driving transistor DT for the first time, making the driving transistor DT reverse-biased, reversing the source and drain of the driving transistor DT, weakening the degree of ion polarization inside the driving transistor DT, reducing the threshold voltage of the driving transistor DT, and adjusting the threshold voltage of the driving transistor DT by biasing the driving transistor DT to compensate for the threshold voltage drift problem caused by the hysteresis effect of the driving transistor due to its forward-biased state. And at this time, the bias control signal terminal SCP* inputting a low-level bias control signal can also control the fifth transistor T5 to conduct, and the second reference voltage signal terminal REF2 resets the anode of the light emitting device 20 (i.e., the fourth node N4) through the fifth transistor T5, initializing the anode of the light emitting element 20, thereby improving the residue of the data signal of the previous frame and the ghosting phenomenon, and enhancing the display effect of the display panel 000.

[0082] In the reset stage tj2, the first scan signal terminal SCN1 inputs a high-level first scan signal to control the second transistor T2 to conduct, and the second reference voltage signal terminal REF2 resets the gate of the driving transistor DT (i.e., the first node N1), refreshing the gate potential of the driving transistor DT of the previous frame.

[0083] In the threshold compensation and data writing stage tj3, the third scan signal terminal SCP inputs a low-level third scan signal to control the third transistor T3 to conduct, and the second scan signal terminal SCN2 inputs a high-level second scan signal to control the first transistor T1 to conduct. The data voltage VDATA provided by the data line of the display panel is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1 to perform threshold compensation on the driving transistor DT and self-compensate for the deviation of the threshold voltage of the driving transistor DT.

[0084] In the second bias adjustment stage tj4, a low-level bias control signal is input to the bias control signal terminal SCP* to control the fourth transistor T4 to conduct. The bias adjustment signal provided by the bias adjustment signal terminal DVH is transmitted to the source of the driving transistor DT (i.e., the second node N2) through the fourth transistor T4, and the bias state of the driving transistor DT is adjusted for the second time.

[0085] In the light-emitting stage tj5, a low-level light-emitting control signal is input to the light-emitting control signal terminal EM to control the sixth transistor T6 and the seventh transistor T7 to conduct. The driving transistor DT generates a driving current under the control of its gate voltage. A conductive path is formed among the first power signal terminal PVDD, the sixth transistor T6, the driving transistor DT, the seventh transistor T7, the light-emitting device 20, and the second power signal terminal PVEE, and the driving current is supplied to the light-emitting device 20 to control the light-emitting device 20 to emit light.

[0086] Optionally, in this embodiment, the transistor in the pixel circuit 10 that is electrically connected to the anode of the light-emitting device 20 and drives it to emit light is the seventh transistor T7. The fifth transistor T5 is also electrically connected to the anode of the light-emitting device 20 and is used for resetting.

[0087] It can be understood that the Figure 7 electrical connection structure of the pixel circuit 10 provided in this embodiment is only an example. In specific implementation, the electrical connection structure of the pixel circuit 10 includes but is not limited to this, and can also be other circuit structures.

[0088] In some alternative embodiments, please continue to refer to Figure 1 、 Figure 3 and Figure 6 . In this embodiment, in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 is mirror-symmetrical to the second pixel circuit 102 of the second pixel circuit column 10A2, and the third pixel circuit 103 of the third pixel circuit column 10A3 is mirror-symmetrical to the fourth pixel circuit 104 of the fourth pixel circuit column 10A4.

[0089] This embodiment explains that the layout structure of the pixel circuit 10 of the display panel 000 can be a structure in which two adjacent pixel circuits 10 are mirror-symmetrical. For example, in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 is mirror-symmetrical with the second pixel circuit 102 of the second pixel circuit column 10A2, and the third pixel circuit 103 of the third pixel circuit column 10A3 is mirror-symmetrical with the fourth pixel circuit 104 of the fourth pixel circuit column 10A4, which is beneficial to saving layout space of the panel. It can be understood that the mirror symmetry in this embodiment is not completely consistent in the strict sense. It can be understood that in the first direction X, the first pixel circuit 101 of the first pixel circuit column 10A1 and the second pixel circuit 102 of the second pixel circuit column 10A2 are approximately mirror symmetric, and the third pixel circuit 103 of the third pixel circuit column 10A3 and the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 are approximately mirror symmetric, that is, in actual production, due to process fluctuations, the size, width and other structures of each film layer structure may not be strictly symmetrical and consistent, but in the first direction X, the corresponding transistor structure and capacitor structure in the first pixel circuit 101 of the first pixel circuit column 10A1 and the corresponding transistor structure and capacitor structure in the second pixel circuit 102 of the second pixel circuit column 10A2 are symmetrical to each other. For example, in actual production, the width of the semiconductor layer of the semiconductor part of the thin film transistor used to make the pixel circuit may be different due to process fluctuations, which is prone to the color deviation problem caused by the difference in driving current of different pixel circuits to be solved in this embodiment.

[0090] In some optional embodiments, please refer to Figure 1 , Figure 3 , Figure 9 and Figure 10 , Figure 9 yes Figure 1 A partially enlarged schematic diagram of the arrangement of light-emitting devices in a partial area, Figure 10 yes Figure 3 The pixel circuit and Figure 9 A schematic diagram of a layout structure of a light emitting device combined with (it can be understood that, in order to clearly illustrate the structure of this embodiment, Figure 10 In the embodiment, the display panel 000 includes a plurality of light emitting device column groups 20A sequentially arranged along the first direction X; one light emitting device column group 20A includes a first light emitting device column 20A1, a second light emitting device column 20A2, a third light emitting device column 20A3 and a fourth light emitting device column 20A4 sequentially arranged along the first direction X;

[0091] Along the second direction Y, the first light-emitting device column 20A1 includes a plurality of first-color light-emitting devices 201 and third-color light-emitting devices 203 arranged alternately, the second light-emitting device column 20A2 includes a plurality of second-color light-emitting devices 202, the third light-emitting device column 20A3 includes a plurality of third-color light-emitting devices 203 and first-color light-emitting devices 201 arranged alternately, and the fourth light-emitting device column 20A4 includes a plurality of second-color light-emitting devices 202; wherein, the first direction X and the second direction Y intersect on a plane parallel to the plane where the display panel 000 is located. In this embodiment, it is schematically illustrated by taking the first direction X and the second direction Y as perpendicular to each other on a plane parallel to the plane where the display panel 000 is located as an example.

[0092] A plurality of pixel circuits 10 are arranged along the first direction X to form a pixel circuit row 10H.

[0093] Along the second direction Y, in the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the third-color light-emitting device 203 of the third light-emitting device column 20A3; where i is a positive integer.

[0094] Optionally, along the second direction Y, in the (i + 1)-th pixel circuit row 10H(i + 1), the first pixel circuit 101 is electrically connected to the third-color light-emitting device 203 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the first-color light-emitting device 201 of the third light-emitting device column 20A3.

[0095] This embodiment explains that when the display panel 000 includes a plurality of light-emitting devices 20, and the plurality of light-emitting devices 20 include a first-color light-emitting device 201, a second-color light-emitting device 202, and a third-color light-emitting device 203 ( Figure 9(differently filled patterns are used to distinguish different colors), the arrangement structure of multiple light-emitting devices 20 can be a first light-emitting device column 20A1, a second light-emitting device column 20A2, a third light-emitting device column 20A3, and a fourth light-emitting device column 20A4 arranged in sequence along the first direction X to form a light-emitting device column group 20A, and one light-emitting device column group 20A is correspondingly driven to emit light by one pixel circuit column group 10A. Along the second direction Y, the first light-emitting device column 20A1 includes multiple alternately arranged first-color light-emitting devices 201 and third-color light-emitting devices 203, the second light-emitting device column 20A2 includes multiple second-color light-emitting devices 202, the third light-emitting device column 20A3 includes multiple alternately arranged third-color light-emitting devices 203 and first-color light-emitting devices 201, and the fourth light-emitting device column 20A4 includes multiple second-color light-emitting devices 202, that is, the arrangement manner of the light-emitting devices 20 is a commonly used arrangement manner in the related art. The first-color light-emitting device 201 and the third-color light-emitting device 203 can be a red light-emitting device and a blue light-emitting device respectively, and the third-color light-emitting device 203 can be a green light-emitting device. Therefore, if the Figure 4 shown pixel circuit and the driving structure of the light-emitting device are adopted, once process fluctuations occur in the pixel circuit and cause differences in the driving current, the first light-emitting device column 20A1 and the second light-emitting device column 20A2 will be biased pink as a whole, and the third light-emitting device column 20A3 and the fourth light-emitting device column 20A4 will also be biased pink as a whole. By analogy, the overall visual effect of the display panel will have a color shift and a mura visual effect problem caused by being biased pink; or, if the Figure 4 shown pixel circuit and the driving structure of the light-emitting device are adopted, once process fluctuations occur in the pixel circuit and cause differences in the driving current, the first light-emitting device column 20A1 and the second light-emitting device column 20A2 will be biased green as a whole, and the third light-emitting device column 20A3 and the fourth light-emitting device column 20A4 will also be biased green as a whole. By analogy, the overall visual effect of the display panel will have a color shift and a mura visual effect problem caused by being biased green.

[0096] In the design structure of this embodiment, when the pixel circuit 10 and the light-emitting device 20 are combined and arranged, the arrangement structure of the two remains unchanged. By improving, in the i-th pixel circuit row 10H(i) in the second direction Y, the first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 in the first light-emitting device column 20A1, so as to realize that the first pixel circuit 101 drives the first-color light-emitting device 201; the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 in the second light-emitting device column 20A2, so as to realize that the second pixel circuit 102 drives the second-color light-emitting device 202; the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 in the fourth light-emitting device column 20A4, so as to realize that the third pixel circuit 103 also drives the second-color light-emitting device 202; the fourth pixel circuit 104 is electrically connected to the third-color light-emitting device 203 in the third light-emitting device column 20A3, so as to realize that the fourth pixel circuit 104 drives the third-color light-emitting device 203; moreover, in the (i + 1)-th pixel circuit row 10H(i + 1) adjacent to the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the third-color light-emitting device 203 in the first light-emitting device column 20A1, so as to realize that the first pixel circuit 101 drives the third-color light-emitting device 203; the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 in the second light-emitting device column 20A2, so as to realize that the second pixel circuit 102 drives the second-color light-emitting device 202; the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 in the fourth light-emitting device column 20A4, so as to realize that the third pixel circuit 103 also drives the second-color light-emitting device 202; the fourth pixel circuit 104 is electrically connected to the first-color light-emitting device 201 in the third light-emitting device column 20A3, so as to realize that the fourth pixel circuit 104 drives the first-color light-emitting device 201.That is, multiple first pixel circuits 101 form a first pixel circuit column 10A1, and multiple second pixel circuits 102 form a second pixel circuit column 10A2. The channel width W1 of the first transistor T1 of the first pixel circuit 101 is different from the channel width W2 of the first transistor T1 of the second pixel circuit 102. The first pixel circuit 101 drives a first color light-emitting device 201 or a third color light-emitting device 203, and the second pixel circuit 102 drives a second color light-emitting device 202. Multiple third pixel circuits 103 form a third pixel circuit column 10A3, and multiple fourth pixel circuits 104 form a fourth pixel circuit column 10A4. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is different from the channel width W4 of the first transistor T1 of the fourth pixel circuit 104. The channel width W3 of the first transistor T1 of the third pixel circuit 103 is the same as the channel width W1 of the first transistor T1 of the first pixel circuit 101, and the channel width W4 of the first transistor T1 of the fourth pixel circuit 104 is the same as the channel width W2 of the first transistor T1 of the second pixel circuit 102. At this time, the color of the light-emitting device driven by the third pixel circuit 103 is different from the color of the light-emitting device driven by the first pixel circuit 101, and the color of the light-emitting device driven by the third pixel circuit 103 is the same as the color of the light-emitting device driven by the second pixel circuit 102. The third pixel circuit 103 drives the second color light-emitting device 202. The color of the light-emitting device driven by the fourth pixel circuit 104 is different from the color of the light-emitting device driven by the second pixel circuit 102, and the color of the light-emitting device driven by the fourth pixel circuit 104 is the same as the color of the light-emitting device driven by the first pixel circuit 101. The fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201.

[0097] If the channel width W1 of the first transistor T1 in the first pixel circuit 101 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 102, the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the first pixel circuit 101 is small, and the driving current of the second color light-emitting device 202 driven by the second pixel circuit 102 is large. The light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102 may be biased towards the color of the second color light-emitting device 202, that is, towards green. If the channel width W3 of the first transistor T1 in the third pixel circuit 103 is smaller than the channel width W4 of the first transistor T1 in the fourth pixel circuit 104, the driving current of the second color light-emitting device 202 driven by the third pixel circuit 103 is small, and the driving current of the first color light-emitting device 201 or the third color light-emitting device 203 driven by the fourth pixel circuit 104 is large. The light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 may be biased towards the color of the first color light-emitting device 201 or the third color light-emitting device 203, that is, towards pink. Therefore, in the light-emitting region corresponding to a pixel circuit column group 10A formed by four adjacent pixel circuit columns in the first direction X, the pink bias of the light-emitting regions corresponding to the third pixel circuit 103 and the fourth pixel circuit 104 neutralizes the green bias of the light-emitting regions corresponding to the first pixel circuit 101 and the second pixel circuit 102. Furthermore, the color deviation problem can be improved and the display quality can be enhanced in the overall visual effect.

[0098] In some alternative embodiments, please refer to Figure 1 、 Figure 3 、 Figures 9 - 10 、 Figure 11 , Figure 11 is Figure 3 a schematic diagram of another layout structure of the pixel circuit combined with Figure 9 the light-emitting device (it can be understood that, for clearly showing the structure of this embodiment, Figure 11 the light-emitting device and the connecting lines are filled with transparency). In this embodiment, the first pixel circuit 101 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 through the first connecting line LJ1;

[0099] The second pixel circuit 102 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2 through the second connecting line LJ2;

[0100] The third pixel circuit 103 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4 through the third connecting line LJ3;

[0101] The fourth pixel circuit 104 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3 through the fourth connecting line LJ4.

[0102] In this embodiment, it is explained that in the first direction X, a first light-emitting device column 20A1, a second light-emitting device column 20A2, a third light-emitting device column 20A3, and a fourth light-emitting device column 20A4 are arranged in sequence in a light-emitting device column group 20A. A light-emitting device column group 20A is correspondingly driven to emit light by a pixel circuit column group 10A, and a first pixel circuit column 10A1, a second pixel circuit column 10A2, a third pixel circuit column 10A3, and a fourth pixel circuit column 10A4 are arranged in sequence in a pixel circuit column group 10A. In order to realize that in the i-th pixel circuit row 10H(i), the first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the third-color light-emitting device 203 of the third light-emitting device column 20A3, connection lines can be made of a conductive film layer. For example, the first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 of the first light-emitting device column 20A1 through a first connection line LJ1, the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2 through a second connection line LJ2, the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 of the fourth light-emitting device column 20A4 through a third connection line LJ3, and the fourth pixel circuit 104 is electrically connected to the third-color light-emitting device 203 of the third light-emitting device column 20A3 through a fourth connection line LJ4. Optionally, the first connection line LJ1 and the second connection line LJ1 can be anode signal lines, that is, the first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 of the first light-emitting device column 20A1 and the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2 through anode signal lines on the same layer as the anode. The third connection line LJ3 and the fourth connection line LJ4 can be a connection structure connected through vias with different layers (or when there is enough panel space, they can also be signal lines on the same film layer, such as anode signal lines on the same layer as the anode) as the third connection line LJ3 and the fourth connection line LJ4 to realize the electrical connection between the third pixel circuit 103 and the second-color light-emitting device 202 of the fourth light-emitting device column 20A4 and the electrical connection between the fourth pixel circuit 104 and the third-color light-emitting device 203 of the third light-emitting device column 20A3.

[0103] Optionally, as Figure 1 , Figure 3 , Figures 9 - 10 , Figure 11 and Figure 12 shown, Figure 12 is Figure 11Partial enlarged schematic diagram of the J2 region. Since the first pixel circuit 101 of the first pixel circuit column 10A1 is electrically connected to the first color light-emitting device 201 of the first light-emitting device column 20A1 through the first connection line LJ1, and the second pixel circuit 102 of the second pixel circuit column 10A2 is electrically connected to the second color light-emitting device 202 of the second light-emitting device column 20A2 through the second connection line LJ2. Along the first direction X, the first light-emitting device column 20A1, the second light-emitting device column 20A2, the third light-emitting device column 20A3, and the fourth light-emitting device column 20A4 are arranged in sequence in a group of light-emitting device columns 20A. A group of light-emitting device columns 20A is correspondingly driven to emit light by a group of pixel circuit columns 10A. The first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 are arranged in sequence in a group of pixel circuit columns 10A. Therefore, the lengths of the first connection line LJ1 and the second connection line LJ2 are generally short. The third pixel circuit 103 of the third pixel circuit column 10A3 is electrically connected to the second color light-emitting device 202 of the fourth light-emitting device column 20A4 through the third connection line LJ3, and the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 is electrically connected to the third color light-emitting device 203 of the third light-emitting device column 20A3 through the fourth connection line LJ4. Therefore, the lengths of the third connection line LJ3 and the fourth connection line LJ4 are generally long. That is, the length of at least one of the first connection line LJ1 and the second connection line LJ2 is less than the length of at least one of the third connection line LJ3 and the fourth connection line LJ4. The first connection line LJ1 and the second connection line LJ1 are short and can be directly made of a film layer on the same layer as the anode, that is, the anode signal line, to directly electrically connect the first pixel circuit 101 of the first pixel circuit column 10A1 to the first color light-emitting device 201 of the first light-emitting device column 20A1, and the second pixel circuit 102 of the second pixel circuit column 10A2 to the second color light-emitting device 202 of the second light-emitting device column 20A2. The third connection line LJ3 and the fourth connection line LJ4 can be a connection line structure in which multiple film layers are connected through vias and are arranged in different layers (or when there is enough panel space, it can also be an anode signal line on the same film layer as the anode as the third connection line LJ3 and the fourth connection line LJ4) to realize the electrical connection between the third pixel circuit 103 of the third pixel circuit column 10A3 and the second color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 of the fourth pixel circuit column 10A4 and the third color light-emitting device 203 of the third light-emitting device column 20A3.

[0104] It should be noted that in this embodiment Figure 11 is only for indicating that each connection line is connected to the pixel circuit, Figure 11The connection positions of the middle pixel circuit and each connection line do not represent the actual connection positions. In specific implementation, the connection positions where the light-emitting devices are connected to the transistors in the pixel circuit can be set according to the actual layout structure of the pixel circuit. The shape and structure of the pixel circuit in this embodiment are only schematic and do not represent the actual complete layout structure of the pixel circuit.

[0105] It can be understood that Figure 11 and Figure 12 the layout shapes and routing manners of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 in

[0106] are only examples. In specific implementation, they can be set according to the actual film layer space of the panel, as long as it is satisfied that one light-emitting device column group 20A is driven to emit light by one pixel circuit column group 10A. The first pixel circuit 101 is electrically connected to the first-color light-emitting device 201 of the first light-emitting device column 20A1, the second pixel circuit 102 is electrically connected to the second-color light-emitting device 202 of the second light-emitting device column 20A2, the third pixel circuit 103 is electrically connected to the second-color light-emitting device 202 of the fourth light-emitting device column 20A4, and the fourth pixel circuit 104 is electrically connected to the third-color light-emitting device 203 of the third light-emitting device column 20A3. Figure 1 、 Figure 3 、 Figures 9 - 12 、 Figures 13 - 16 、 Figure 13 is Figure 12 a schematic cross-sectional structure diagram in the A-A' direction in Figure 14 is Figure 12 a schematic cross-sectional structure diagram in the B-B' direction in Figure 15 is Figure 12 a schematic cross-sectional structure diagram in the C-C' direction in Figure 16 is Figure 12 a schematic cross-sectional structure diagram in the D-D' direction in. In this embodiment, the display panel 000 includes a substrate 01, a driving array layer 02, and an anode layer 03. The anode layer 03 is located on the side of the driving array layer 02 away from the substrate 01.

[0107] The driving array layer 02 includes pixel circuits 10. The anode layer 03 includes a plurality of anodes 031. The light-emitting devices 20 are electrically connected to the pixel circuits 10 through the anodes 031. Further optionally, the light-emitting devices 20 are electrically connected to the transistors in the pixel circuits 10. At least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the anode layer 03; or at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the driving array layer 02.

[0108] In this embodiment, it is explained that the film layer structure of the display panel 000 may include a substrate 01, a driving array layer 02, and an anode layer 03 that are sequentially located on one side of the substrate 01. The substrate 01 is used as a carrier substrate for setting other film layer structures of the display panel 000. Optionally, in this embodiment, the substrate 01 of the display panel 000 may be made of a hard material such as glass or ceramic, or may be a flexible material, such as a polymer material formed by polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc. The substrate 01 may be any one of a transparent substrate, a semi-transparent substrate, or an opaque substrate, which is not limited in this embodiment. The driving array layer 02 may be provided with transistors, capacitors, etc. of the pixel circuit 10 through a plurality of conductive film layers, or may be provided with other driving traces and driving circuits. The layout structure of the driving array layer 02 in this embodiment will not be elaborated, and specific understanding can be referred to the film layer structure of the OLED display panel in the related art. The anode layer 03 is used to set an anode 031 that is electrically connected to the light-emitting device 20 correspondingly. The anode layer 03 may be formed of various conductive materials. For example, the anode layer 03 may be formed as a transparent anode or a reflective anode according to its own use. When the anode layer 03 is formed as a transparent anode, the material of the anode layer 03 may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.; when the anode layer 03 is formed as a reflective anode, the material of the anode layer 03 may include silver, magnesium, aluminum, etc. or other metal mixtures, which are not specifically limited in this embodiment. The anode 031 corresponding to the light-emitting device 20 may be electrically connected to at least one transistor in the pixel circuit 10, and is used to transmit the driving signal of the pixel circuit 10 to the anode 031 to achieve the driving and light-emitting effect of the light-emitting device 20.

[0109] It can be understood that the film layer structure of the display panel 000 shown in the figure of this embodiment is only an example. In specific implementation, the film layer structure of the display panel 000 includes but is not limited to this, and may further include a cathode layer, a packaging layer, etc. on the side of the light-emitting device 20 away from the substrate 01, which will not be elaborated in this embodiment.

[0110] In this embodiment, at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the anode layer 03. For example, Figures 13 - 14 as shown, the first connection line LJ1 and the second connection line LJ2 may be located in the anode layer 03, and a certain transistor in the first pixel circuit 101 (such as Figure 7The seventh transistor T7) in is electrically connected to the anode 031 corresponding to the first color light-emitting device 201. The anode 031 corresponding to the first color light-emitting device 201 in the first light-emitting device column 20A1 is directly electrically connected to the first pixel circuit 101 in the first pixel circuit column 10A1 through the first connection line LJ1 located in the anode layer 03; a certain transistor in the second pixel circuit 102 (such as Figure 7 The seventh transistor T7) in is electrically connected to the anode 031 corresponding to the second color light-emitting device 202. The anode 031 corresponding to the second color light-emitting device 202 in the second light-emitting device column 20A2 is directly electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the second connection line LJ2 located in the anode layer 03. As Figures 15 - 16 shown, the third connection line LJ3 and the fourth connection line LJ4 can be located in a certain conductive film layer of the driving array layer 02. A certain transistor in the third pixel circuit 103 (such as Figure 7 The seventh transistor T7) in is electrically connected to the anode 031 corresponding to the second color light-emitting device 202. The anode 031 corresponding to the second color light-emitting device 202 in the fourth light-emitting device column 20A4 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the third connection line LJ3 located in a certain conductive film layer of the driving array layer 02; a certain transistor in the fourth pixel circuit 104 (such as Figure 7 The seventh transistor T7) in is electrically connected to the anode 031 corresponding to the third color light-emitting device 203. The anode 031 corresponding to the third color light-emitting device 203 in the third light-emitting device column 20A3 is electrically connected to the fourth pixel circuit 104 in the fourth pixel circuit column 10A4 through the fourth connection line LJ4 located in a certain conductive film layer of the driving array layer 02;

[0111] In this embodiment, at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the anode layer 03, or at least one of the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 is located in the driving array layer 02. The first connection line LJ1 and the second connection line LJ2 can be directly set in the anode layer 03, which simplifies the manufacturing process. When the layout space in the anode layer 03 is insufficient, the third connection line LJ3 and the fourth connection line LJ4 can be arranged in the driving array layer 02 close to the anode layer 03, thereby avoiding the short-circuit problem of more connection lines in the anode layer 03 and facilitating the realization of the normal driving and display function of the display panel.

[0112] Optionally, in the same third connection line LJ3 in this embodiment, at least a part of the line segment can be located in the anode layer 03, and at least a part of the line segment can be located in the driving array layer 02. Or among multiple third connection lines LJ3, at least a part of the third connection lines LJ3 can be located in the anode layer 03, and at least a part of the third connection lines LJ3 can be located in the driving array layer 02. In the same fourth connection line LJ4, at least a part of the line segment can be located in the anode layer 03, and at least a part of the line segment can be located in the driving array layer 02. Or among multiple fourth connection lines LJ4, at least a part of the fourth connection lines LJ4 can be located in the anode layer 03, and at least a part of the fourth connection lines LJ4 can be located in the driving array layer 02. It only needs to satisfy that short - circuit problems are avoided between different connection lines in the film layer where the connection lines are located. In this embodiment, there are no restrictions on the specific film layer where the first connection line LJ1, the second connection line LJ2, the third connection line LJ3, and the fourth connection line LJ4 are arranged and their routing shapes. During specific implementation, the remaining space of the film layer can be fully utilized for layout.

[0113] Optionally, as Figures 13 - 16 shown, the driving array layer 02 of the display panel 000 can include a first metal layer M1, and there is no other conductive layer between the first metal layer M1 and the anode layer 03; that is, the first metal layer M1 is the conductive film layer closest to the anode layer 03 in the driving array layer 02. At least a part of the third connection line LJ3 can be arranged in the first metal layer M1; or at least a part of the fourth connection line LJ4 can be arranged in the first metal layer M1. Furthermore, when the transistors of the pixel circuit 10 are connected to the third connection line LJ3 or the fourth connection line LJ4 through vias, and the third connection line LJ3 or the fourth connection line LJ4 is then electrically connected to the anode 031 of the anode layer 03 through vias, the vias will not be too deep, that is, it is possible to avoid the problem that too - deep vias affect the manufacturing process and signal transmission performance, which is beneficial to ensuring the signal transmission stability of the third connection line LJ3 and the fourth connection line LJ4 and improving the display quality.

[0114] In some alternative embodiments, please refer to Figure 7 、 Figure 17 and Figure 18 , Figure 17 which is another schematic plan view of the display panel provided by the embodiment of the present disclosure, Figure 18 is Figure 17 a partial enlarged view of the J3 area of Figure 17 (it can be understood that for clearly showing the structure of this embodiment, Figure 18After transparency filling is performed, in this embodiment, the display panel 000 includes multiple data lines S. The multiple data lines S include a first data line S1, a second data line S2, a third data line S3, and a fourth data line S4 arranged along the first direction X. Among them, the first data line S1 is electrically connected to the first pixel circuit 101, the second data line S2 is electrically connected to the second pixel circuit 102, the third data line S3 is electrically connected to the third pixel circuit 103, and the fourth data line S4 is electrically connected to the fourth pixel circuit 104;

[0115] Along the first direction X, the second data line S2 and the third data line S3 are adjacent to each other with a spacing of D1, the first data line S1 and the second data line S2 are adjacent to each other with a spacing of D2, and the third data line S3 and the fourth data line S4 are adjacent to each other with a spacing of D3. Among them, D2 > D1 and D3 > D1.

[0116] Optionally, in the pixel circuit 10, the transistor electrically connected to the data line S can be Figure 7 One pole of the third transistor T3 as shown. During the threshold compensation and data writing stages when driving the display panel 000, the third scan signal terminal SCP inputs a low-level third scan signal to control the third transistor T3 to conduct, and the second scan signal terminal SCN2 inputs a high-level second scan signal to control the first transistor T1 to conduct. The data voltage VDATA provided by the data line S of the display panel 000 is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1.

[0117] This embodiment explains that multiple data lines S can be provided in the display panel 000. The data lines S are used to provide data voltage signals for the pixel circuit 10. Among the multiple data lines S, at least the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 are arranged along the first direction X. It can be understood that the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 can be understood as being used to provide data voltage signals for the first pixel circuit column 10A1, the second pixel circuit column 10A2, the third pixel circuit column 10A3, and the fourth pixel circuit column 10A4 included in a pixel circuit column group 10A.

[0118] Optionally, if the first data line S1 is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, then the first data line S1 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light respectively; the second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202, then the second data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light; the third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202, then the third data line S2 is used to provide the data voltage signal when the second color light-emitting device 202 emits light; the fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, then the fourth data line S4 is used to provide the data voltage signal when the first color light-emitting device 201 emits light or the data voltage signal when the third color light-emitting device 203 emits light respectively. Since the first data line S1 and the fourth data line S4 are both for providing the data voltage signal for the third color light-emitting device 203 or the first color light-emitting device 201 compared with the second data line S2 and the third data line S3, and the second data line S2 and the third data line S3 are both for providing the data voltage signal for the second color light-emitting device 202, in this embodiment, along the first direction X, that is, along the direction in which the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 are arranged in sequence, the distance D1 between the adjacent second data line S2 and the third data line S3 is set to be smaller, and the distances D2 between the adjacent first data line S1 and the second data line S2 and D3 between the adjacent third data line S3 and the fourth data line S4 are set to be larger, that is, the distance D1 between the second data line S2 and the third data line S3 is less than the distance D2 between the first data line S1 and the second data line S2, and the distance D1 between the second data line S2 and the third data line S3 is less than the distance D3 between the third data line S3 and the fourth data line S4, that is, the first data line S1 and the fourth data line S4 can both be farther away from the second data line S2 and the third data line S3, so that the two data lines for transmitting different data voltage signals to different color light-emitting devices can be spaced farther apart, which is beneficial to avoiding the mutual interference between the data voltage signals of different color light-emitting devices, and thus beneficial to ensuring the display quality.

[0119] Optionally, if the first data line S1 is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, then the first data line S1 is used to provide a data voltage signal when the first color light-emitting device 201 emits light or a data voltage signal when the third color light-emitting device 203 emits light; that is, when the first color light-emitting device 201 and the third color light-emitting device 203 in the first light-emitting device column 20A1 emit light, the first data line S1 needs to jump and switch the data voltage signal (such as jumping between the data voltage signals required by the R / B light-emitting devices) to enable the first pixel circuit 101 to drive the first color light-emitting device 201 and the third color light-emitting device 203 in the first light-emitting device column 20A1 to emit light respectively.

[0120] The second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202, then the second data line S2 is used to provide a data voltage signal when the second color light-emitting device 202 emits light; that is, when the second color light-emitting device 202 in the second light-emitting device column 20A2 emits light, the second data line S2 does not need to jump and switch the data voltage signal (such as the data voltage signal required by the G light-emitting device) to enable the second pixel circuit 102 to drive the second color light-emitting device 202 in the second light-emitting device column 20A2 to emit light.

[0121] The third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202, then the third data line S2 is used to provide a data voltage signal when the second color light-emitting device 202 emits light; that is, when the second color light-emitting device 202 in the fourth light-emitting device column 20A4 emits light, the third data line S3 does not need to jump and switch the data voltage signal (such as the data voltage signal required by the G light-emitting device) to enable the third pixel circuit 103 to drive the second color light-emitting device 202 in the fourth light-emitting device column 20A4 to emit light.

[0122] The fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, then the fourth data line S4 is used to provide a data voltage signal when the first color light-emitting device 201 emits light or a data voltage signal when the third color light-emitting device 203 emits light; that is, when the first color light-emitting device 201 and the third color light-emitting device 203 in the third light-emitting device column 20A3 emit light, the fourth data line S4 needs to jump and switch the data voltage signal (such as jumping between the data voltage signals required by the R / B light-emitting devices) to enable the fourth pixel circuit 104 to drive the first color light-emitting device 201 and the third color light-emitting device 203 in the third light-emitting device column 20A3 to emit light respectively.

[0123] As described above, during the driving process of the display panel 000, both the first data line S1 and the fourth data line S4 need to jump and switch the data voltage signal to drive the light emission of different color light-emitting devices by the same data line. While the second data line S2 and the third data line S3 can drive the light emission of the same color light-emitting devices without jumping and switching the data voltage signal. Therefore, in this embodiment, it can be set that along the first direction X, that is, along the direction in which the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4 are arranged in sequence, the adjacent spacing D1 between the second data line S2 and the third data line S3 is smaller, and the adjacent spacing D2 between the first data line S1 and the second data line S2 and the adjacent spacing D3 between the third data line S3 and the fourth data line S4 are larger. That is, the spacing D1 between the second data line S2 and the third data line S3 is less than the spacing D2 between the first data line S1 and the second data line S2, and the spacing D1 between the second data line S2 and the third data line S3 is less than the spacing D3 between the third data line S3 and the fourth data line S4. In this way, the first data line S1 that needs to switch the data voltage signal can be farther away from the second data line S2, and the fourth data line S4 that needs to switch the data voltage signal can be farther away from the third data line S3, avoiding the data voltage signals jumped by the first data line S1 and the fourth data line S4 from being coupled to the second data line S2 and the third data line S3, which affects the signal transmission performance of the second data line S2 and the third data line S3 itself, and thus is beneficial to improving the display quality. And the second data line S2 and the third data line S3 that do not need to switch the data voltage signal are closer to each other. Even if the first data line S1 is farther away from the second data line S2 and the fourth data line S4 is farther away from the third data line S3, it will not affect the space occupied by the four data lines S, namely the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4, in the first direction X. Therefore, it is beneficial to ensure that the panel has enough space to arrange multiple data lines, which is convenient for simplifying the wiring process.

[0124] It can be understood that the data line S in this embodiment can be arranged in one or two film layers in the driving array layer. Multiple data lines S can be arranged in different layers or in the same layer. This embodiment will not elaborate on this, and specifically, it can be set with reference to the film layer arrangement method of the data line in the related technology.

[0125] It should be noted that the Figure 17 and Figure 18 data line S in is only for illustration. In actual implementation, the arrangement of the data line S can be slightly adjusted in shape according to the actual space of the panel, and only needs to meet that the overall extension direction of the data line S is the vertical direction in the figure, which is convenient for electrical connection with the driving chip subsequently bound to the display panel 000.

[0126] Optionally, such as Figure 7 、Figure 17 , Figure 18 and Figure 19 As shown, Figure 19 yes Figure 17 Another partial enlarged schematic diagram of the J3 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 19 In this embodiment, the first data line S1 can be electrically connected to the transistor in the first pixel circuit 101 through the fifth connection line LJ5. Figure 7 The second data line S2 can be electrically connected to the transistor T3 in the second pixel circuit 102 through the sixth connection line LJ6. Figure 7 The third data line S3 can be electrically connected to the transistor T3 in the third pixel circuit 103 through the seventh connection line LJ7. Figure 7 The fourth data line S4 can be electrically connected to the transistor T3 in the fourth pixel circuit 104 through the eighth connection line LJ8. Figure 7 One end of the third transistor T3 is connected to the pixel circuit 10, thereby realizing the transmission of the data voltage signal between the pixel circuit 10 and the data line S.

[0127] Further optionally, the film layer of the fifth connecting line LJ5, the sixth connecting line LJ6, the seventh connecting line LJ7, and the eighth connecting line LJ8 can be set according to the actual space of the panel. For example, at least one of the fifth connecting line LJ5, the sixth connecting line LJ6, the seventh connecting line LJ7, and the eighth connecting line LJ8 can be in the same layer as the data line S, or can be at least partially in a different layer from the data line S. This embodiment is not limited to this, and it only needs to be able to achieve the electrical connection effect between the pixel circuit and the data line to avoid a short circuit.

[0128] In some optional embodiments, please refer to Figure 7 , Figures 17 - 19 and Figure 20 , Figure 20 000 is another schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure. In this embodiment, a non-display area NA of a display panel 000 includes a plurality of first binding pads 301, a plurality of second binding pads 302, a plurality of third binding pads 303, and a plurality of fourth binding pads 304. The first binding pads 301, the second binding pads 302, the third binding pads 303, and the fourth binding pads 304 are sequentially arranged along a first direction X.

[0129] The first data line S1 is electrically connected to the first binding pad 301 through the first fan-out line LS1, the second data line S2 is electrically connected to the second binding pad 302 through the second fan-out line LS2, the third data line S3 is electrically connected to the fourth binding pad 304 through the third fan-out line LS3, and the fourth data line S4 is electrically connected to the third binding pad 303 through the fourth fan-out line LS4;

[0130] The third outgoing line LS3 and the fourth outgoing line LS4 are arranged on different layers, and the orthographic projection of the third outgoing line LS3 on the plane where the display panel 000 is located overlaps with the orthographic projection of the fourth outgoing line LS4 on the plane where the display panel 000 is located.

[0131] This embodiment explains that when the display panel 000 is subsequently bonded to a driving chip or a flexible circuit board and the driving chip or the flexible circuit board provides a driving signal for the display panel 000, bonding pads can be arranged in the non-display area NA of the display panel 000, generally in the non-display area NA at the lower border of the display panel 000, and the bonding with the driving chip or the flexible circuit board is realized through the bonding pads. Specifically, the non-display area NA of the display panel 000 includes a plurality of first bonding pads 301, a plurality of second bonding pads 302, a plurality of third bonding pads 303, and a plurality of fourth bonding pads 304, which are used to provide data voltage signals for a plurality of data lines S. The first bonding pads 301, the second bonding pads 302, the third bonding pads 303, and the fourth bonding pads 304 are arranged in sequence along the first direction X. Among them, the first bonding pads 301, the second bonding pads 302, the third bonding pads 303, and the fourth bonding pads 304 correspond to the first data line S1, the second data line S2, the third data line S3, and the fourth data line S4. The first data line S1 is electrically connected to the first bonding pad 301 through the first fan-out line LS1, the second data line S2 is electrically connected to the second bonding pad 302 through the second fan-out line LS2, the third data line S3 is electrically connected to the fourth bonding pad 304 through the third fan-out line LS3, and the fourth data line S4 is electrically connected to the third bonding pad 303 through the fourth fan-out line LS4. In related technologies, the pins that provide data voltage signals in a developed and mature driving chip or flexible circuit board are generally sorted as follows: the R / B pins that provide jumping data voltage signals to drive red light-emitting devices or blue light-emitting devices, the G pins that provide non-jumping data voltage signals to drive green light-emitting devices, the R / B pins that provide jumping data voltage signals to drive red light-emitting devices or blue light-emitting devices, the G pins that provide non-jumping data voltage signals to drive green light-emitting devices... and so on in sequence.Therefore, when the first data line S1 of this embodiment is electrically connected to the first pixel circuit 101, and the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, that is, the first data line S1 needs to jump and switch the data voltage signal; the second data line S2 is electrically connected to the second pixel circuit 102, and the second pixel circuit 102 drives the second color light-emitting device 202, that is, the second data line S2 does not need to jump and switch the data voltage signal; the third data line S3 is electrically connected to the third pixel circuit 103, and the third pixel circuit 103 drives the second color light-emitting device 202, that is, the third data line S3 does not need to jump and switch the data voltage signal; the fourth data line S4 is electrically connected to the fourth pixel circuit 104, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, that is, when the fourth data line S4 needs to jump and switch the data voltage signal, a driving chip or a flexible circuit board that has been developed and used in the related art and has a relatively mature technology can still be used. The third fan-out line LS3 and the fourth fan-out line LS4 are arranged in different layers, and the orthographic projection of the third fan-out line LS3 on the plane where the display panel 000 is located overlaps with the orthographic projection of the fourth fan-out line LS4 on the plane where the display panel 000 is located. Furthermore, it is not necessary to re-develop and design the driving chip or the flexible circuit board. It is only necessary to make the third fan-out line LS3 and the fourth fan-out line LS4 overlap in the direction perpendicular to the plane where the display panel is located, that is, by crossing the third fan-out line LS3 and the fourth fan-out line LS4 in different layers, the corresponding electrical connections can be achieved without changing the order of the pins on the driving chip or the flexible circuit board, which is beneficial to reducing the development and design costs.

[0132] It can be understood that the third fan-out line LS3 and the fourth fan-out line LS4 in this embodiment are arranged in different layers. The third fan-out line LS3 and the fourth fan-out line LS4 can be arranged in two different conductive layers in the driving array layer, such as the gate metal layer where the gate of the thin-film transistor is located and the capacitor metal layer where one pole of the capacitor is located, etc., or they can also be arranged in different layers in other two different conductive layers. This embodiment does not make any limitations in this regard.

[0133] It should be noted that in this embodiment of Figure 20 , the arrangement structure of the multiple bonding pads is only an example. In actual implementation, the multiple bonding pads may not be arranged straight along the first direction X in the non-display area NA, and may be arranged in a undulating shape according to the space of the non-display area NA. This embodiment does not make any limitations in this regard, and it only needs to satisfy that the overall multiple bonding pads are arranged along the first direction X. For details, reference can be made to the design of the pads when the driving chip or the flexible circuit board is bonded to the display panel in the related art.

[0134] In some alternative embodiments, please refer to Figure 7 、 Figure 21 and Figure 22 ,Figure 21 It is another schematic plan view of the display panel provided by an embodiment of the present disclosure. Figure 22 It is Figure 21 A partial enlarged schematic view of the J4 area of Figure 21 (It can be understood that in order to clearly illustrate the structure of this embodiment, Figure 22 the pixel circuit is represented by a block diagram in Figure 7 and transparency filling is performed). In this embodiment, the display panel 000 includes a plurality of data lines S, and the data lines S are electrically connected to the pixel circuit 10; optionally, in the pixel circuit 10, the transistor electrically connected to the data line S can be Figure 7 one pole of the third transistor T3 shown in

[0135] During the threshold compensation and data writing stages when driving the display panel 000, the third scan signal terminal SCP inputs a low-level third scan signal to control the third transistor T3 to conduct, and the second scan signal terminal SCN2 inputs a high-level second scan signal to control the first transistor T1 to conduct. The data voltage VDATA provided by the data line S of the display panel 000 is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1.

[0135] In this embodiment, the light-emitting devices 20 driven by a plurality of pixel circuits 10 electrically connected to the same data line S are set to have the same color. That is, only the data voltage signal required by the light-emitting device 20 of the corresponding color can be transmitted on one data line S of this embodiment, and the data voltage signal on the same data line S does not need to jump, so that a stable data voltage signal can be transmitted on each data line S, thereby reducing the power consumption of the driving chip or flexible circuit board subsequently bonded to the display panel and the display panel, and further saving the overall driving power consumption.

[0136] Optionally, the plurality of data lines S include a fifth data line S5, a sixth data line S6, a seventh data line S7, and an eighth data line S8 arranged along the first direction X;

[0137] The fifth data line S5 is used to provide a data voltage signal VDATA-R for the pixel circuit 10 electrically connected to the first color light-emitting device 201, the sixth data line S6 is used to provide a data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second color light-emitting device 202, the seventh data line S7 is used to provide a data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second color light-emitting device 202, and the eighth data line S8 is used to provide a data voltage signal VDATA-B for the pixel circuit 10 electrically connected to the third color light-emitting device 203;

[0138] The multiple first pixel circuits 101 in the first pixel circuit column 10A1 include a first sub-pixel circuit 1011 and a second sub-pixel circuit 1012. The first sub-pixel circuit 1011 is electrically connected to the first color light-emitting device 201 in the first light-emitting device column 20A1, and the second sub-pixel circuit 1012 is electrically connected to the third color light-emitting device 203 in the first light-emitting device column 20A1. The fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1;

[0139] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2. The second pixel circuit 102 in the second pixel circuit column 10A2 is electrically connected to the second color light-emitting device 202 in the second light-emitting device column 20A2;

[0140] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3. The third pixel circuit 103 in the third pixel circuit column 10A3 is electrically connected to the second color light-emitting device 202 in the fourth light-emitting device column 20A4;

[0141] The multiple fourth pixel circuits 104 in the fourth pixel circuit column 10A4 include a third sub-pixel circuit 1041 and a fourth sub-pixel circuit 1042. The third sub-pixel circuit 1041 is electrically connected to the first color light-emitting device 201 in the third light-emitting device column 20A3, and the fourth sub-pixel circuit 1042 is electrically connected to the third color light-emitting device 203 in the third light-emitting device column 20A3. The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4.

[0142] This embodiment explains that when setting a pixel circuit column group 10A composed of four adjacent pixel circuit columns in the first direction X, the first pixel circuit 101 drives the first color light-emitting device 201 or the third color light-emitting device 203, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203 or the first color light-emitting device 201, that is, changing the color of the light-emitting device driven by the third pixel circuit 103 and changing the color of the light-emitting device driven by the fourth pixel circuit 104 to achieve the effect of improving display color deviation. It is also possible to combine the layout structure of the data lines S to make the colors of the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S the same, avoiding the problem of increased power consumption caused by signal jumps on the data line S, and thus saving the overall driving power consumption.

[0143] Moreover, since the fifth data line S5 is only used to provide the data voltage signal VDATA-R for the pixel circuit 10 electrically connected to the first color light-emitting device 201, the sixth data line S6 is only used to provide the data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second color light-emitting device 202, the seventh data line S7 is only used to provide the data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second color light-emitting device 202, and the eighth data line S8 is only used to provide the data voltage signal VDATA-B for the pixel circuit 10 electrically connected to the third color light-emitting device 203, the fifth data line S5, the sixth data line S6, the seventh data line S7, and the eighth data line S8 are arranged in sequence along the first direction X, and the first pixel circuit 101, the second pixel circuit 102, the third pixel circuit 103, and the fourth pixel circuit 104 are arranged in sequence along the first direction X. In the same pixel circuit row, the first pixel circuit 101 drives the first color light-emitting device 201, the second pixel circuit 102 drives the second color light-emitting device 202, the third pixel circuit 103 drives the second color light-emitting device 202, and the fourth pixel circuit 104 drives the third color light-emitting device 203. Therefore, the connection sub-line when the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 can be set to be shorter, and its connection sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The connection sub-line when the sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 can be set to be shorter, and its connection sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The connection sub-line when the seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 can be set to be shorter, and its connection sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The connection sub-line when the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 can also be set to be shorter, and its connection sub-line does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The data line in the current column is electrically connected to the pixel circuit in the current column. It is very likely that the electrical connection between the data line in the current column and the pixel circuit in the current column can be achieved by directly drilling holes in the direction perpendicular to the plane where the display panel is located, which can greatly optimize and reduce the parasitic capacitance on the data line S and is beneficial to improving the display effect.

[0144] Optionally, in this embodiment, the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S have the same color. The fifth data line S5 is used to provide a data voltage signal VDATA-R to the pixel circuit 10 electrically connected to the first-color light-emitting device 201. The sixth data line S6 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202. The seventh data line S7 is used to provide a data voltage signal VDATA-G to the pixel circuit 10 electrically connected to the second-color light-emitting device 202. The eighth data line S8 is used to provide a data voltage signal VDATA-B to the pixel circuit 10 electrically connected to the third-color light-emitting device 203. Since the fifth data line S5 and the eighth data line S8 are different from the sixth data line S6 and the seventh data line S7 in that the sixth data line S6 and the seventh data line S7 both provide data voltage signals for the second-color light-emitting device 202, while the fifth data line S5 provides a data voltage signal for the first-color light-emitting device 201 and the eighth data line S8 provides a data voltage signal for the third-color light-emitting device 203, in this embodiment, along the first direction X, that is, along the direction in which the fifth data line S5, the sixth data line S6, the seventh data line S7, and the eighth data line S8 are arranged in sequence, the adjacent spacing between the sixth data line S6 and the seventh data line S7 is set to be smaller, and the adjacent spacing between the fifth data line S5 and the sixth data line S6 and the adjacent spacing between the seventh data line S7 and the eighth data line S8 are set to be larger (as Figure 22 and Figure 23 shown), that is, the spacing between the sixth data line S6 and the seventh data line S7 is less than the spacing between the fifth data line S5 and the sixth data line S6, and the spacing between the sixth data line S6 and the seventh data line S7 is less than the spacing between the seventh data line S7 and the eighth data line S8. That is, the sixth data line S6 and the seventh data line S7 can both be farther away from the fifth data line S5 and the eighth data line S8, so that two data lines for transmitting different data voltage signals to different-color light-emitting devices can be spaced farther apart, which is beneficial to avoiding mutual interference between the data voltage signals of different-color light-emitting devices, and thus is beneficial to ensuring the display quality.

[0145] Optionally, in this embodiment, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the first connection portion; the sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the second connection portion; the seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the third connection portion; and the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 through the fourth connection portion. The first connection portion, the second connection portion, the third connection portion, and the fourth connection portion may be connection sub-lines provided in the conductive film layer of the display panel, or may be directly via holes opened between different conductive layers, or may be a combination of connection sub-lines and via holes.

[0146] Optionally, taking the first connection portion, the second connection portion, the third connection portion, and the fourth connection portion as an example, the connection sub-wires are Figure 21 , Figure 22 and Figure 23 As shown, Figure 23 yes Figure 22 Schematic diagram of the corresponding layout of the pixel circuit and the data line (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 23 The light emitting devices are omitted for illustration. Figure 23 Transparency filling is performed), in this embodiment, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the first sub-line LZ1;

[0147] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the second sub-line LZ2;

[0148] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the third sub-line LZ3;

[0149] The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 through the fourth sub-line LZ4.

[0150] In this embodiment, it is explained that since the data lines of the current column are electrically connected to the corresponding pixel circuits of the current column, the first sub-line LZ1 when the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 can be set shorter, and the first sub-line LZ1 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The second sub-line LZ2 when the sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 can be set shorter, and the second sub-line LZ2 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The third sub-line LZ3 when the seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 can be set shorter, and the third sub-line LZ3 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. The fourth sub-line LZ4 when the eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 can also be set shorter, and the fourth sub-line LZ4 does not need to extend to the positions of other pixel circuits in adjacent or other pixel circuit columns. In this way, the electrical connection between the data lines of the current column and the corresponding pixel circuits of the current column can be achieved, which can greatly save the layout space of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4, optimize and reduce the parasitic capacitance on the data line S, and is beneficial to improving the display effect.

[0151] Optionally, since the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are all shorter, at least one of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 can be on the same layer as the data line S, that is, the sub-line is directly pulled out from the data line S to achieve the electrical connection effect with the pixel circuit 10. Furthermore, the number of vias when the sub-line and the data line S are on different layers can be reduced, and thus the display quality can be optimized.

[0152] It can be understood that when the film layer space where the data line S is located is insufficient, some of the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 can also be arranged on different layers from the data line S. In this embodiment, the film layers for arranging the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are not specifically limited, and only need to satisfy that there is enough spacing between the wiring structures to avoid short circuits.

[0153] Optionally, taking the first connection part, the second connection part, the third connection part, and the fourth connection part as vias (not shown in the figure), when the distance between the fifth data line S5 and the transistor required to be connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 is relatively close, a hole can be directly drilled in the direction perpendicular to the plane of the display panel below the fifth data line S5. The fifth data line S5 can be electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the via, and there is no need to connect the sub-line;

[0154] When the distance between the sixth data line S6 and the transistor required to be connected to the second pixel circuit 102 in the second pixel circuit column 10A2 is relatively close, a hole can be directly drilled in the direction perpendicular to the plane of the display panel below the sixth data line S6. The sixth data line S6 can be electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the via, and there is no need to connect the sub-line;

[0155] When the distance between the seventh data line S7 and the transistor required to be connected to the third pixel circuit 103 in the third pixel circuit column 10A3 is relatively close, a hole can be directly drilled in the direction perpendicular to the plane of the display panel below the seventh data line S7. The seventh data line S7 can be electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the via, and there is no need to connect the sub-line;

[0156] When the distance between the eighth data line S8 and the transistor required to be connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 is relatively close, a hole can be directly drilled in the direction perpendicular to the plane of the display panel below the eighth data line S8. The eighth data line S8 can be electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 through the via, and there is no need to connect the sub-line.

[0157] That is, in the display panel of this embodiment, a hole can also be directly drilled in the direction perpendicular to the plane of the display panel to realize the electrical connection between the data line of the current column and the pixel circuit of the current column, which is beneficial to reducing the number of signal traces in the panel, simplifying the manufacturing process, and at the same time, beneficial to improving the pixel arrangement density and the display quality.

[0158] In some alternative embodiments, please refer to Figures 21 - 23 and Figures 24 - 25 as shown. Figure 24 It is Figure 21 a partial enlarged schematic diagram of the corresponding areas of multiple pixel circuit column groups in Figure 25 It is Figure 24 a corresponding layout schematic diagram of the pixel circuit and the data line in Figure 25 (It can be understood that for the sake of clearly showing the structure of this embodiment, Figure 24 the light-emitting devices inFigure 25 After transparency filling, in this embodiment, along the first direction X, the display panel includes the (N - 1)-th pixel circuit column group 10A(N - 1), the N-th pixel circuit column group 10A(N), and the (N + 1)-th pixel circuit column group 10A(N + 1); where N is a positive integer greater than or equal to 2;

[0159] The fifth data line S5 corresponding to the N-th pixel circuit column group 10A(N) is also electrically connected to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the (N - 1)-th pixel circuit column group 10A(N - 1);

[0160] The eighth data line S8 corresponding to the N-th pixel circuit column group 10A(N) is also electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the (N + 1)-th pixel circuit column group 10A(N + 1).

[0161] Optionally, the fifth data line S5 is electrically connected to the first sub-pixel circuit 1011 in the first pixel circuit column 10A1 through the first sub-line LZ1;

[0162] The sixth data line S6 is electrically connected to the second pixel circuit 102 in the second pixel circuit column 10A2 through the second sub-line LZ2;

[0163] The seventh data line S7 is electrically connected to the third pixel circuit 103 in the third pixel circuit column 10A3 through the third sub-line LZ3;

[0164] The eighth data line S8 is electrically connected to the fourth sub-pixel circuit 1042 in the fourth pixel circuit column 10A4 through the fourth sub-line LZ4;

[0165] The fifth data line S5 corresponding to the N-th pixel circuit column group 10A(N) is electrically connected to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the (N - 1)-th pixel circuit column group 10A(N - 1) through the fifth sub-line LZ5;

[0166] The eighth data line S8 corresponding to the N-th pixel circuit column group 10A(N) is electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the (N + 1)-th pixel circuit column group 10A(N + 1) through the sixth sub-line LZ6;

[0167] The length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1; and / or, the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4.

[0168] This embodiment explains that the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S have the same color. Since the fifth data line S5 is only used to provide the data voltage signal VDATA-R for the pixel circuit 10 electrically connected to the first-color light-emitting device 201, the sixth data line S6 is only used to provide the data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second-color light-emitting device 202, the seventh data line S7 is only used to provide the data voltage signal VDATA-G for the pixel circuit 10 electrically connected to the second-color light-emitting device 202, and the eighth data line S8 is only used to provide the data voltage signal VDATA-B for the pixel circuit 10 electrically connected to the third-color light-emitting device 203. Therefore, the fifth data line S5 corresponding to the Nth pixel circuit column group 10A(N) also needs to be electrically connected to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the previous (N-1)th pixel circuit column group 10A(N-1) adjacent to it, and the eighth data line S8 corresponding to the Nth pixel circuit column group 10A(N) also needs to be electrically connected to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the next (N+1)th pixel circuit column group 10A(N+1) adjacent to it. Thus, the second sub-pixel circuit 1012 and the first sub-pixel circuit 1011 of the first pixel circuit column 10A1 drive light-emitting devices of different colors and are connected to different data lines S, and the third sub-pixel circuit 1041 and the fourth sub-pixel circuit 1042 of the fourth pixel circuit column 10A4 drive light-emitting devices of different colors and are connected to different data lines S. While improving the color shift problem, it is ensured that the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S have the same color, saving driving power consumption.

[0169] Optionally, as Figure 24 and Figure 25As shown, the length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1; and / or, the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4. Since the fifth sub-line LZ5 needs to be pulled from the fifth data line S5 corresponding to the Nth pixel circuit column group 10A(N) to the third sub-pixel circuit 1041 of the fourth pixel circuit column 10A4 in the adjacent (N-1)th pixel circuit column group 10A(N-1), while the first sub-line LZ1 only connects the data line of the current column to the pixel circuit of the current column, the pulling length of the fifth sub-line LZ5 is relatively long, and the length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1. Similarly, the sixth sub-line LZ6 needs to be pulled from the eighth data line S8 corresponding to the Nth pixel circuit column group 10A(N) to the second sub-pixel circuit 1012 of the first pixel circuit column 10A1 in the adjacent (N+1)th pixel circuit column group 10A(N+1), while the fourth sub-line LZ4 only connects the data line of the current column to the pixel circuit of the current column, so the pulling length of the sixth sub-line LZ6 is relatively long, and the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4. By increasing the pulling length of the sub-line, the electrical connection between different pixel circuit columns 10A and the data line S not corresponding to the current column is realized, so that the light-emitting devices 20 driven by multiple pixel circuits 10 electrically connected to the same data line S have the same color, saving the driving power consumption.

[0170] Optionally, although the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are all relatively short and can be on the same layer as the data line S, that is, the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are directly pulled out from the data line S to achieve the electrical connection effect with the pixel circuit 10, reducing the number of vias when the first sub-line LZ1, the second sub-line LZ2, the third sub-line LZ3, and the fourth sub-line LZ4 are on different layers from the data line S respectively, thereby improving the display quality. However, since the pulling length of the fifth sub-line LZ5 is relatively long, the length of the fifth sub-line LZ5 is greater than the length of the first sub-line LZ1, and the pulling length of the sixth sub-line LZ6 is relatively long, the length of the sixth sub-line LZ6 is greater than the length of the fourth sub-line LZ4. Therefore, at least part of the fifth sub-line LZ5 is on a different layer from the data line S; or, at least part of the sixth sub-line LZ6 is on a different layer from the data line S, so that the conductive film layer other than the data line S can be used for via routing, avoiding the problem of short circuit between different lines caused by too much wiring in the film layer where the data line S is located, which is beneficial to improving the product yield.

[0171] In some alternative embodiments, please refer to Figure 26 , Figure 26 is a schematic plan view of a display device provided by an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 26The embodiments are described by taking a mobile phone as an example for the display device 111. It can be understood that the display device 111 provided by the embodiments of the present invention can be other display devices 111 with a display function, such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations thereto. The display device 111 provided by the embodiments of the present invention has the beneficial effects of the display panel 000 provided by the embodiments of the present invention. For specific descriptions of the display panel 000, reference can be made to the above embodiments, and details are not described herein again.

[0172] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0173] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: comprising a plurality of pixel circuits, the pixel circuit comprising a driving transistor and a first transistor electrically connected; The plurality of pixel circuits at least include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit; The display panel comprises a plurality of pixel circuit column groups sequentially arranged along a first direction, wherein one pixel circuit column group comprises a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column; The first pixel circuit column includes a plurality of the first pixel circuits, the second pixel circuit column includes a plurality of the second pixel circuits, the third pixel circuit column includes a plurality of the third pixel circuits, and the fourth pixel circuit column includes a plurality of the fourth pixel circuits; The channel width of the first transistor of the first pixel circuit is different from the channel width of the first transistor of the second pixel circuit, the channel width of the first transistor of the third pixel circuit is different from the channel width of the first transistor of the fourth pixel circuit, the channel width of the first transistor of the first pixel circuit is equal to the channel width of the first transistor of the third pixel circuit, and the channel width of the first transistor of the second pixel circuit is equal to the channel width of the first transistor of the fourth pixel circuit; The display panel includes a plurality of light emitting devices, wherein the plurality of light emitting devices include a first color light emitting device, a second color light emitting device and a third color light emitting device; The first pixel circuit drives the first color light-emitting device or the third color light-emitting device, the second pixel circuit drives the second color light-emitting device, the third pixel circuit drives the second color light-emitting device, and the fourth pixel circuit drives the third color light-emitting device or the first color light-emitting device.

2. The display panel according to claim 1, characterized in that: The channel width of the first transistor of the first pixel circuit is W1, and the channel width of the first transistor of the second pixel circuit is W2; |W1-W2|≤0.1 μm; The channel width of the first transistor of the third pixel circuit is W3, and the channel width of the first transistor of the fourth pixel circuit is W4; |W3-W4|≤0.1 μm.

3. The display panel according to claim 1, characterized in that: The channel width of the first transistor of the first pixel circuit is smaller than the channel width of the first transistor of the second pixel circuit, and the channel width of the first transistor of the third pixel circuit is smaller than the channel width of the first transistor of the fourth pixel circuit.

4. The display panel according to claim 1, characterized in that: The first color light emitting device is one of a red light emitting device or a blue light emitting device, and the third color light emitting device is the other of the red light emitting device or the blue light emitting device; The second color light emitting device is a green light emitting device.

5. The display panel according to claim 1, characterized in that: The first transistor is electrically connected between the gate and the first electrode of the driving transistor, and the first transistor is an N-type transistor.

6. The display panel according to claim 1, characterized in that: In the first direction, the first pixel circuit of the first pixel circuit column is mirror-symmetrical to the second pixel circuit of the second pixel circuit column, and the third pixel circuit of the third pixel circuit column is mirror-symmetrical to the fourth pixel circuit of the fourth pixel circuit column.

7. The display panel according to claim 1, characterized in that: The display panel comprises a plurality of light emitting device column groups sequentially arranged along the first direction; one of the light emitting device column groups comprises a first light emitting device column, a second light emitting device column, a third light emitting device column and a fourth light emitting device column sequentially arranged along the first direction; Along the second direction, the first light emitting device column includes a plurality of the first color light emitting devices and the third color light emitting devices arranged alternately, the second light emitting device column includes a plurality of the second color light emitting devices, the third light emitting device column includes a plurality of the third color light emitting devices and the first color light emitting devices arranged alternately, and the fourth light emitting device column includes a plurality of the second color light emitting devices; wherein the first direction and the second direction intersect on a plane parallel to the display panel; A plurality of the pixel circuits are arranged along the first direction to form a pixel circuit row; In the i-th row of pixel circuits, the first pixel circuit is electrically connected to the first color light-emitting device of the first light-emitting device column, the second pixel circuit is electrically connected to the second color light-emitting device of the second light-emitting device column, the third pixel circuit is electrically connected to the second color light-emitting device of the fourth light-emitting device column, and the fourth pixel circuit is electrically connected to the third color light-emitting device of the third light-emitting device column; wherein i is a positive integer.

8. The display panel according to claim 7, characterized in that: Along the second direction, in the i+1th pixel circuit row, the first pixel circuit is electrically connected to the third color light-emitting device of the first light-emitting device column, the second pixel circuit is electrically connected to the second color light-emitting device of the second light-emitting device column, the third pixel circuit is electrically connected to the second color light-emitting device of the fourth light-emitting device column, and the fourth pixel circuit is electrically connected to the first color light-emitting device of the third light-emitting device column.

9. The display panel according to claim 7, characterized in that: The first pixel circuit is electrically connected to the first color light emitting device of the first light emitting device column through a first connecting line; The second pixel circuit is electrically connected to the second color light emitting device of the second light emitting device column through a second connecting line; The third pixel circuit is electrically connected to the second color light emitting device of the fourth light emitting device column through a third connecting line; The fourth pixel circuit is electrically connected to the third color light emitting device of the third light emitting device column through a fourth connecting line.

10. The display panel according to claim 9, characterized in that: A length of at least one of the first connection line and the second connection line is smaller than a length of at least one of the third connection line and the fourth connection line.

11. The display panel according to claim 9, characterized in that: The display panel includes a substrate, a drive array layer, and an anode layer, wherein the anode layer is located on a side of the drive array layer away from the substrate. The driving array layer includes the pixel circuit, the anode layer includes a plurality of anodes, and the light-emitting device is electrically connected to the pixel circuit through the anode; at least one of the first connecting wire, the second connecting wire, the third connecting wire, and the fourth connecting wire is located in the anode layer; or, at least one of the first connecting wire, the second connecting wire, the third connecting wire, and the fourth connecting wire is located in the driving array layer.

12. The display panel according to claim 11, characterized in that: The driving array layer includes a first metal layer, and no other conductive layer is included between the first metal layer and the anode layer; At least part of the third connection line is located in the first metal layer; or at least part of the fourth connection line is located in the first metal layer.

13. The display panel according to claim 7, characterized in that: The display panel includes a plurality of data lines, and the plurality of data lines include a first data line, a second data line, a third data line, and a fourth data line arranged along the first direction; wherein the first data line is electrically connected to the first pixel circuit, the second data line is electrically connected to the second pixel circuit, the third data line is electrically connected to the third pixel circuit, and the fourth data line is electrically connected to the fourth pixel circuit; Along the first direction, the second data line and the third data line are adjacently arranged with a spacing of D1, the first data line and the second data line are adjacently arranged with a spacing of D2, and the third data line and the fourth data line are adjacently arranged with a spacing of D3; D2>D1, D3>D1.

14. The display panel according to claim 13, characterized in that: The non-display area of ​​the display panel includes a plurality of first binding pads, a plurality of second binding pads, a plurality of third binding pads, and a plurality of fourth binding pads, wherein the first binding pads, the second binding pads, the third binding pads, and the fourth binding pads are sequentially arranged along the first direction; The first data line is electrically connected to the first binding pad through a first fan-out line, the second data line is electrically connected to the second binding pad through a second fan-out line, the third data line is electrically connected to the fourth binding pad through a third fan-out line, and the fourth data line is electrically connected to the third binding pad through a fourth fan-out line; The third fan-out line and the fourth fan-out line are arranged in different layers, and the orthographic projection of the third fan-out line on the plane where the display panel is located overlaps with the orthographic projection of the fourth fan-out line on the plane where the display panel is located.

15. The display panel according to claim 7, characterized in that: The display panel includes a plurality of data lines, and the data lines are electrically connected to the pixel circuit; The light-emitting devices driven by the plurality of pixel circuits electrically connected to the same data line have the same color.

16. The display panel according to claim 15, characterized in that: The plurality of data lines include a fifth data line, a sixth data line, a seventh data line and an eighth data line arranged along the first direction; The fifth data line is used to provide a data voltage signal for the pixel circuit electrically connected to the first color light emitting device, the sixth data line is used to provide a data voltage signal for the pixel circuit electrically connected to the second color light emitting device, the seventh data line is used to provide a data voltage signal for the pixel circuit electrically connected to the second color light emitting device, and the eighth data line is used to provide a data voltage signal for the pixel circuit electrically connected to the third color light emitting device; The plurality of first pixel circuits of the first pixel circuit column include a first sub-pixel circuit and a second sub-pixel circuit, the first sub-pixel circuit is electrically connected to the first color light emitting device of the first light emitting device column, and the second sub-pixel circuit is electrically connected to the third color light emitting device of the first light emitting device column; the fifth data line is electrically connected to the first sub-pixel circuits in the first pixel circuit column; The sixth data line is electrically connected to the second pixel circuit in the second pixel circuit column; The seventh data line is electrically connected to the third pixel circuit in the third pixel circuit column; The multiple fourth pixel circuits of the fourth pixel circuit column include a third sub-pixel circuit and a fourth sub-pixel circuit, the third sub-pixel circuit is electrically connected to the first color light-emitting device of the third light-emitting device column, and the fourth sub-pixel circuit is electrically connected to the third color light-emitting device of the third light-emitting device column; the eighth data line is electrically connected to the fourth sub-pixel circuit in the fourth pixel circuit column.

17. The display panel according to claim 16, characterized in that: The fifth data line is electrically connected to the first sub-pixel circuit in the first pixel circuit column through the first sub-line; The sixth data line is electrically connected to the second pixel circuit in the second pixel circuit column through a second sub-line; The seventh data line is electrically connected to the third pixel circuit in the third pixel circuit column through a third sub-line; The eighth data line is electrically connected to the fourth sub-pixel circuit in the fourth pixel circuit column through a fourth sub-line; At least one of the first sub-line, the second sub-line, the third sub-line, and the fourth sub-line is in the same layer as the data line.

18. The display panel according to claim 16, characterized in that: Along the first direction, the display panel includes the N-1th pixel circuit column group, the Nth pixel circuit column group, and the N+1th pixel circuit column group; wherein N is a positive integer and is greater than or equal to 2; The fifth data line corresponding to the Nth pixel circuit column group is also electrically connected to the third sub-pixel circuit of the fourth pixel circuit column in the N-1th pixel circuit column group; The eighth data line corresponding to the Nth pixel circuit column group is also electrically connected to the second sub-pixel circuit of the first pixel circuit column in the N+1th pixel circuit column group.

19. The display panel according to claim 18, characterized in that: The fifth data line is electrically connected to the first sub-pixel circuit in the first pixel circuit column through the first sub-line; The sixth data line is electrically connected to the second pixel circuit in the second pixel circuit column through a second sub-line; The seventh data line is electrically connected to the third pixel circuit in the third pixel circuit column through a third sub-line; The eighth data line is electrically connected to the fourth sub-pixel circuit in the fourth pixel circuit column through a fourth sub-line; The fifth data line corresponding to the Nth pixel circuit column group is electrically connected to the third sub-pixel circuit of the fourth pixel circuit column in the N-1th pixel circuit column group through a fifth sub-line; The eighth data line corresponding to the Nth pixel circuit column group is electrically connected to the second sub-pixel circuit of the first pixel circuit column in the N+1th pixel circuit column group through the sixth sub-line; The length of the fifth sub-line is greater than the length of the first sub-line; and / or the length of the sixth sub-line is greater than the length of the fourth sub-line.

20. The display panel according to claim 19, characterized in that: At least part of the fifth sub-line and the data line are in a different layer; or at least part of the sixth sub-line and the data line are in a different layer.

21. A display device, characterized in that: A display panel comprising any one of claims 1-20.

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