Quadrature error detection device and method, rotary digital converter and medium

Abstract

The invention discloses a quadrature error detection device and method, a rotary digital converter and a medium, and relates to the technical field of rotary digital converters, and the method comprises the steps: carrying out the processing of a rotation phase and an excitation phase outputted by an excitation phase correction module through a frequency synthesis module, and obtaining a first excitation signal and a second excitation signal; processing the resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal through a demodulation module to obtain a demodulation signal and a detection signal; the demodulation signal is controlled to output a rotation phase through a rotation phase extraction module; the detection signal is controlled to pass through the filter module to output the output signal, and then the output signal is controlled to pass through the orthogonality error detection module to obtain the orthogonality error signal, so that the filter module and the orthogonality error detection module are added on the basis of the main body demodulation device, and the hardware cost is very low; therefore, the orthogonality error detection function is considered on the basis of the main body demodulation function.

Description

Technical Field

[0001] This application relates to the technical field of rotary digital converters, and particularly to an orthogonal error detection device, method, rotary digital converter, and medium. Background Art

[0002] A rotary digital converter realizes an interface between a resolver and a system microprocessor, and decodes the angular position and rotational speed of a motor shaft through a resolver input signal.

[0003] The orthogonality error of the rotary digital converter will cause amplitude mismatch and phase mismatch in the decoded data. Therefore, detecting the orthogonality error can determine whether there are situations such as amplitude mismatch and phase mismatch. So currently, a hardware structure for detecting orthogonality error is additionally provided in the rotary digital converter. Through this hardware structure, orthogonality error detection is performed and the corresponding orthogonality detection result is output for calibration to ensure the accuracy of amplitude and phase. However, the additional hardware architecture will not only increase the additional hardware overhead, but also require the rotary digital converter to reserve a certain space for the addition of this hardware architecture. At the same time, when the quantizer uses a Delta Sigma modulator, there will be a problem of quantization noise aliasing, and it will also increase the circuit area and hardware cost. Summary of the Invention

[0004] The main purpose of this application is to provide an orthogonal error detection device, method, rotary digital converter, and medium, aiming to solve the technical problems of quantization noise aliasing, increased circuit area, and increased hardware cost existing in the solution of the additional hardware structure for detecting orthogonality error in order to ensure the accuracy of demodulation.

[0005] To achieve the above object, this application proposes an orthogonal error detection device. The orthogonal error detection device is applied to a rotary digital converter, and the orthogonal error detection device includes an excitation phase correction module, a frequency synthesis module, a demodulation module, a rotation phase extraction module, and an orthogonality error detection module; The frequency synthesis module processes the rotation phase and the excitation phase output by the excitation phase correction module to obtain a first excitation signal and a second excitation signal; The demodulation module processes the resolver sine signal, resolver cosine signal, first excitation signal, and second excitation signal to obtain a demodulation signal and a detection signal; Control the demodulation signal to output the rotation phase through the rotation phase extraction module; and, Control the detection signal to output an output signal through the filter module, and then control the output signal to pass through the orthogonality error detection module to obtain an orthogonal error signal.

[0006] In one embodiment, the frequency synthesis module includes a first adder and a second adder; The input terminals of the first adder are respectively connected to the rotation phase and the excitation phase for addition, and the first target input signal is output; The input terminals of the second adder are respectively connected to the rotation phase and the excitation phase for subtraction, and the second target input signal is output; The frequency synthesis module further includes a lookup combination unit, a third adder, and a fourth adder; The input terminal of the lookup combination unit is connected to the output terminal of the first adder and the output terminal of the second adder, and is used to look up the corresponding sine value and cosine value according to the accessed first target input signal and second target input signal, and output a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal; The input terminal of the third adder is connected to the cosine output terminal of the lookup combination unit, and is used to perform operations on the first cosine signal and the second cosine signal output by the cosine output terminal, and output a first excitation signal; The input terminal of the fourth adder is connected to the sine output terminal of the lookup combination unit, and is used to perform operations on the first sine signal and the second sine signal output by the sine output terminal, and output a second excitation signal.

[0007] In one embodiment, the demodulation module includes a first multiplier, a second multiplier, and a fifth adder; The input terminals of the first multiplier are respectively connected to the output terminal of the fourth adder and the modulator in the rotation digital converter, and are used to multiply the accessed second excitation signal and the resolver sine signal in the modulation signal, and output a first output signal; The input terminals of the second multiplier are respectively connected to the output terminal of the third adder and the modulator, and are used to multiply the accessed first excitation signal and the resolver cosine signal in the modulation signal, and output a second output signal; The input terminals of the fifth adder are respectively connected to the output terminal of the first multiplier and the output terminal of the second multiplier, and are used to subtract the accessed first output signal and the second output signal, and output a demodulation signal.

[0008] In one embodiment, the orthogonality error detection module includes a third multiplier, a fourth multiplier, and a sixth adder; The input terminals of the third multiplier are respectively connected to the output terminal of the third adder and the modulator, and are used to multiply the accessed first excitation signal and the resolver sine signal, and output a third output signal; The input terminals of the fourth multiplier are respectively connected to the output terminal of the fourth adder and the modulator, and are used to multiply the accessed second excitation signal and the resolver cosine signal, and output a fourth output signal; The input terminals of the sixth adder are respectively connected to the output terminal of the third multiplier and the output terminal of the fourth multiplier, and are used to add the accessed third output signal and the fourth output signal, and output a detection signal.

[0009] In addition, to achieve the above object, the present application also proposes an orthogonality error detection method, which is applied to the above orthogonality error detection device. The orthogonality error detection method includes: Processing the excitation phase output by the rotation phase and excitation phase correction module through the frequency synthesis module to obtain a first excitation signal and a second excitation signal; Processing the resolver sine signal, resolver cosine signal, first excitation signal, and second excitation signal through the demodulation module to obtain a demodulation signal and a detection signal; Suppressing quantization noise in the detection signal through a filter; Suppressing double excitation frequency interference in the detection signal through a filter; Judging the detection signal after the suppression operation and outputting an orthogonality error result.

[0010] In an embodiment, before the step of performing an operation with the received modulation signal and outputting a detection signal, it further includes: Adding an excitation phase correction coefficient to the excitation phase.

[0011] In an embodiment, the step of processing the resolver sine signal, resolver cosine signal, first excitation signal, and second excitation signal through the demodulation module to obtain a demodulation signal and a detection signal includes: Performing a multiplication operation on the second excitation signal and the resolver sine signal in the modulation signal to output a first output signal, and performing a multiplication operation on the first excitation signal and the resolver cosine signal in the modulation signal to output a second output signal; Subtracting the first output signal from the second output signal to output a demodulation signal; and Performing a multiplication operation on the first excitation signal and the resolver sine signal to output a third output signal, and performing a multiplication operation on the second excitation signal and the resolver cosine signal to output a fourth output signal; Adding the third output signal and the fourth output signal to output a detection signal.

[0012] In an embodiment, the step of suppressing double excitation frequency interference in the detection signal through a filter includes: In the case where the filter includes a digital integrator, based on the digital integrator, controlling the subtraction of the integration of each quarter excitation frequency period to suppress double excitation frequency interference; or In the case where the filter includes a notch filter or a half-band notch filter, suppressing double excitation frequency interference based on the notch filter or the half-band notch filter.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a rotation digital converter, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the orthogonality error detection method as described above.

[0014] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the orthogonality error detection method described above are implemented.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: An orthogonal error detection device is proposed. The orthogonal error detection device is applied to a rotary digital converter and can be well adapted to the main demodulation device of the rotary digital converter system, including: processing the rotation phase and the excitation phase through a frequency synthesis module (the excitation phase can be the original signal or the signal processed by the excitation phase correction module) to obtain a first excitation signal and a second excitation signal; processing the resolver sine signal, the resolver cosine signal and the first excitation signal and the second excitation signal through a demodulation module to obtain a demodulation signal and a detection signal; the demodulation signal obtains the rotation phase through a rotation phase extraction module (the rotation phase will be used as the input signal of the frequency synthesis module); the detection signal passes through the output signal of the filter module, and then passes through the orthogonality error detection module to obtain an orthogonal error signal. The technical solution of this application aims to solve the problem of large circuit area in the existing orthogonal error detection technology; it can also avoid the quantization noise aliasing problem when the quantizer uses a Delta Sigma modulator; at the same time, the technical solution only adds a filter module and an orthogonality error detection module on the basis of the main demodulation device, and with very little hardware expenditure, the orthogonality error detection function can be taken into account on the basis of the main demodulation function. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic diagram of the system architecture of the orthogonal error detection device of the present application; Figure 2 Schematic diagram of an embodiment of the frequency synthesis module and the demodulation module of the orthogonal error detection device of the present application; Figure 3 Schematic diagram of the structure of the filter module of the present application; Figure 4 Schematic diagram of the structure of a conventional orthogonality error detection device; Figure 5 Schematic flowchart provided by an embodiment of the orthogonality error detection method of the present application; Figure 6 Another schematic diagram of the structure of the filter module of the present application; Figure 7 Schematic diagram of the structure of a traditional orthogonality error detection implemented by the sum of squares detection method; Figure 8 The input signal of the present application passes through Figure 7 Schematic diagram of the waveform obtained by the sum of squares operation; Figure 9 The present application performs Figure 8 Schematic diagram of the waveform obtained by periodic area integration; Figure 10 The present application performs Figure 8 Schematic diagram of the waveform obtained by envelope extraction; Figure 11 Output of DSM ADC Spectrum diagram of the signal after noise shaping; Figure 12 For The signal generated after the sum of squares operation of the signal Spectrum diagram of the signal; Figure 13 For Signal, Signal and Spectrum diagram of the signal; Figure 14 Schematic diagram of the device structure of the hardware operating environment involved in the orthogonality error detection method in the embodiment of the present application.

[0019] Explanation of the reference numerals in the drawings: 10. Frequency synthesis module; a. First adder; b. Second adder; c. Third adder; d. Fourth adder; LUT. Lookup combination unit; 20. Rotating phase extraction module; 30. Orthogonality error detection module; m1. First multiplier; m2. Second multiplier; e. Fifth adder; m3. Third multiplier; m4. Fourth multiplier; f. Sixth adder; 301. Filter module.

[0020] The implementation, functional features, and advantages of this application will be further described in conjunction with embodiments and with reference to the accompanying drawings. Detailed implementation manners

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not used to limit this application.

[0022] To better understand the technical solutions of this application, the following will be described in detail in conjunction with the accompanying drawings of the specification and specific implementation manners.

[0023] The main solution of the embodiment of this application is as follows: The excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain a first excitation signal and a second excitation signal; the resolver sine signal, resolver cosine signal, first excitation signal, and second excitation signal are processed by the demodulation module to obtain a demodulation signal and a detection signal; the demodulation signal is controlled to output a rotation phase through the rotation phase extraction module; and, the detection signal is controlled to output an output signal through the filter module, and then the output signal is controlled to pass through the orthogonality error detection module to obtain an orthogonality error signal.

[0024] Since the orthogonality error of the rotary digital converter is an important factor affecting the accuracy of amplitude and phase, in order to reduce the influence of the orthogonality error, it is necessary to detect the orthogonality error to determine whether there are situations such as amplitude mismatch and phase mismatch. Therefore, it is currently proposed to additionally set up a hardware structure for orthogonality error detection in the rotary digital converter, and the orthogonality error is detected through this hardware structure and the corresponding orthogonality detection result is output for calibration to ensure the accuracy of amplitude and phase. However, the additional hardware architecture will not only increase the additional hardware cost, but also require the rotary digital converter to reserve a certain space for the addition of this hardware architecture. At the same time, when the quantizer uses a Delta Sigma modulator, there will be a problem of quantization noise aliasing, and it will also increase the circuit area and hardware cost.

[0025] The present application provides a solution. By proposing an orthogonal error detection device, which is applied to a rotary digital converter, it includes processing the rotary phase and the excitation phase through a frequency synthesis module (the excitation phase can be the original signal or the signal processed by the excitation phase correction module) to obtain a first excitation signal and a second excitation signal; processing the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal through a demodulation module to obtain a demodulation signal and a detection signal; obtaining the rotary phase from the demodulation signal through a rotary phase extraction module (the rotary phase will be used as the input signal of the frequency synthesis module); obtaining the output signal of the detection signal through the filter module, and then obtaining the orthogonal error signal through the orthogonality error detection module. The technical solution of the present application aims to solve the problem of large circuit area in the existing orthogonal error detection technology; it can also avoid the quantization noise aliasing problem when the quantizer uses a Delta Sigma modulator; at the same time, this technical solution only adds a filter module and an orthogonality error detection module on the basis of the main demodulation device, and with a very small hardware cost, it can take into account the orthogonality error detection function on the basis of the main demodulation function.

[0026] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of implementing the above functions. Hereinafter, a rotary digital converter will be taken as an example to illustrate this embodiment and the following embodiments.

[0027] Based on this, an embodiment of the present application provides an orthogonal error detection device, referring to Figure 1 , Figure 1 which is a module schematic diagram of the orthogonal error detection device of the present application.

[0028] In this embodiment, the orthogonal error detection device includes an excitation phase correction module, a frequency synthesis module 10, a demodulation module, a rotary phase extraction module 20, and an orthogonality error detection module 30; The frequency synthesis module 10 processes the rotary phase and the excitation phase output by the excitation phase correction module to obtain a first excitation signal and a second excitation signal; The demodulation module processes the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal to obtain a demodulation signal and a detection signal; Control the demodulation signal to output the rotary phase through the rotary phase extraction module 20; and, control the detection signal to output the output signal through the filter module, and then control the output signal to pass through the orthogonality error detection module 30 to obtain the orthogonal error signal.

[0029] In this embodiment, based on the similarities between the deformation formula of the current demodulation signal and the deformation formula of the detection signal, a frequency synthesis module 10 is set up to generate a first excitation signal for demodulation and a second excitation signal for error detection simultaneously. The demodulation module not only outputs the demodulation signal but also outputs the detection signal. The detection signal is then passed through the filter module and the orthogonality error detection module 30 to obtain the orthogonality error signal. In this way, the functions of realizing the demodulation operation and the function of realizing the orthogonality error detection are set in the same device circuit board, avoiding the increase in hardware cost and the increase in the required circuit area caused by separately setting the demodulation module and the orthogonality error detection module.

[0030] At the same time, a rotation phase extraction module 20 is also set on the circuit board to extract the rotation phase returned to the frequency synthesis module 10 from the demodulation signal output by the demodulation module. Further, an excitation phase can be connected to the frequency synthesis module 10. In order to increase the sensitivity of the inspection, the excitation phase is corrected by adding an excitation phase correction coefficient, where the excitation phase correction coefficient can be a fixed constant.

[0031] It should be noted that, referring to Figure 1 it can be seen that the excitation phase input to the frequency synthesis module 10 is the phase corrected by the excitation phase correction module, and the output signal output by the demodulation module to the orthogonality error detection module 30 needs to be filtered by the filter module to eliminate errors.

[0032] In a feasible implementation manner, referring to Figure 2 as shown, the frequency synthesis module 10 includes a first adder a and a second adder b; The input terminals of the first adder a are respectively connected to the output terminal of the clock module and the output terminal of the demodulation module, and are used to perform addition according to the accessed excitation phase and rotation phase, and output a first target input signal; the input terminals of the second adder b are respectively connected to the output terminal of the clock module and the output terminal of the demodulation module, and are used to perform subtraction according to the accessed excitation phase and rotation phase, and output a second target input signal.

[0033] Specifically, in combination with Figure 2 for explanation. The first adder a accesses the excitation phase and the rotation phase output by the demodulation module , and adds the accessed excitation phase and the rotation phase to perform addition processing, and outputs the first target input signal . At the same time, the second adder b also accesses the excitation phase and the rotation phase output by the demodulation module . The difference is that the second adder b will access the excitation phase and the rotation phase perform subtraction processing to output a second target input signal .

[0034] The frequency synthesis module 10 further includes a lookup combination unit LUT, a third adder c, and a fourth adder d; The input end of the lookup combination unit LUT is connected to the output ends of the first adder a and the second adder b, and is used to look up corresponding sine values and cosine values according to the accessed first target input signal and the second target input signal, and output a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal; the input end of the third adder c is connected to the cosine output end of the lookup combination unit LUT, and is used to perform operations on the first cosine signal and the second cosine signal output by the cosine output end to output the first excitation signal; the input end of the fourth adder d is connected to the sine output end of the lookup combination unit LUT, and is used to perform operations on the first sine signal and the second sine signal output by the sine output end to output the second excitation signal.

[0035] After obtaining the first target input signal and the second target input signal through the first adder a and the second adder b, the first target input signal and the second target input signal are input into the lookup combination unit LUT. According to Figure 2 it can be known that there are two sine values and two cosine values in the lookup combination unit LUT in this embodiment. According to the lookup relationship between the first adder a and the second adder b and the sine values and the cosine values respectively (i.e., the connection relationship in Figure 2 ), the sine values and the cosine values are combined to output the first sine signal , the second sine signal and the first cosine signal , the second cosine signal .

[0036] In the third adder c, the third adder c performs a subtraction operation according to the cosine output end of the lookup combination unit LUT accessed at its input end, accessing the first cosine signal and the second cosine signal output by the cosine output end, and outputs the first excitation signal .

[0037] In the fourth adder d, the fourth adder d accesses the sine output terminal of the lookup combination unit LUT connected to its input terminal, and accesses the first sine signal output from the sine output terminal and the second sine signal to perform subtraction processing, and outputs a second excitation signal .

[0038] It should be noted that in this embodiment, the rotation phase extracted by the rotation phase extraction module 20 is the angular position output by the previous demodulation process.

[0039] In a feasible implementation manner, as shown in reference Figure 2 , the demodulation module includes a first multiplier m1, a second multiplier m2, and a fifth adder e; The input terminals of the first multiplier m1 are respectively connected to the output terminal of the fourth adder d and the modulator in the rotation digital converter, and are used to multiply the input second excitation signal and the resolver sine signal output by the modulator according to the input sine input signal, and output a first output signal; the input terminals of the second multiplier m2 are respectively connected to the output terminal of the third adder c and the modulator, and are used to multiply the input first excitation signal and the resolver cosine signal output by the modulator according to the input cosine input signal, and output a second output signal; the input terminals of the fifth adder e are respectively connected to the output terminal of the first multiplier m1 and the output terminal of the second multiplier m2, and are used to subtract the input first output signal and the second output signal, and output the demodulation signal.

[0040] Specifically, it is described in combination with Figure 2 . The first multiplier m1 and the second multiplier m2 in this embodiment are in a parallel relationship.

[0041] Among them, the input terminal of the first multiplier m1 is connected to the output terminal of the fourth adder d and the output terminal of the modulation module, and is used to perform multiplication processing on the input second excitation signal and the resolver sine signal , and outputs a first output signal .

[0042] At the same time, the input terminal of the second multiplier m2 is connected to the output terminal of the third adder c and the output terminal of the modulation module, and is used to perform multiplication processing on the input first excitation signal and the resolver cosine signal , and outputs a second output signal .

[0043] At this time, the fifth adder e accesses the first output signal and the second output signal Perform subtraction processing and output the demodulated signal .

[0044] In a feasible implementation manner, as shown in Figure 2 Figure, the orthogonality error detection module 30 includes a third multiplier m3, a fourth multiplier m4, and a sixth adder f; The input ends of the third multiplier m3 are respectively connected to the output end of the third adder c and the modulator, and are used for multiplying according to the accessed first excitation signal and the resolver sine signal, and outputting a third output signal; the input ends of the fourth multiplier m4 are respectively connected to the output end of the fourth adder d and the modulator, and are used for multiplying according to the accessed second excitation signal and the resolver cosine signal, and outputting a fourth output signal; the input ends of the sixth adder f are respectively connected to the output end of the third multiplier m3 and the output end of the fourth multiplier m4, and are used for adding the accessed third output signal and the fourth output signal, and outputting a detection signal.

[0045] Specifically, it will be described in combination with Figure 2 Figure. In the third multiplier m3, according to the accessed first excitation signal and the resolver sine signal output by the modulator perform multiplication to output a third output signal .

[0046] In the fourth multiplier m4, according to the accessed second excitation signal and the resolver cosine signal output by the modulator perform multiplication to output a fourth output signal .

[0047] At this time, send the third output signal and the fourth output signal to the sixth adder f, and perform addition in the sixth adder f to output a detection signal .

[0048] Furthermore, according to Figure 2 Figure, the input end of the filter module 301 is connected to the output end of the sixth adder f, and is used for filtering the accessed detection signal.

[0049] In a feasible implementation, the filter module 301 in this embodiment includes a cascaded integrator comb filter and a notch filter. First, after low-pass filtering is achieved by the cascaded integrator comb filter CIC using the method of phase-shifted addition or phase-shifted subtraction, a notch point is created at twice the excitation frequency by the notch filter Notch to eliminate the harmonic components at twice the excitation frequency in the detection signal. It should be noted that if the downsampling filtering of the cascaded integrator comb filter is eight times the excitation frequency, the notch filter Notch can be transformed into a half-band notch filter HB Notch.

[0050] It should be noted that with reference to Figure 3 As shown, in the case where the filter is a half-band notch filter, a cascaded integrator comb filter needs to be connected in front. After suppressing the interference of the excitation frequency by this cascaded integrator comb filter, the target signal is then extracted by the half-band notch filter.

[0051] In a feasible implementation, the filter module 301 in this embodiment can also be a CDS digital integrator, which directly subtracts for each quarter of the excitation frequency period of each integration.

[0052] After filtering the detection signal through the filter module 301 in the above steps and then determining whether the orthogonality error result corresponding to the filtered detection signal is within the preset threshold range. If the orthogonality error result is greater than the upper threshold within the preset threshold range, and considering the previous orthogonality error detection operations, the number of times that the orthogonality error result greater than the upper threshold within the preset threshold range obtained in this judgment has exceeded the preset rising upper threshold of the counter, then it is determined that there are situations such as amplitude mismatch and phase mismatch based on this orthogonality error result; if the orthogonality error result is less than the lower threshold within the preset threshold range, and considering the previous orthogonality error detection operations, the number of times that the orthogonality error result less than the lower threshold within the preset threshold range obtained in this judgment has exceeded the preset falling lower threshold of the counter, then it is determined that there are problems such as amplitude mismatch and phase mismatch based on this orthogonality error result.

[0053] It should be noted that according to Figure 4 the conventional orthogonality error detection device shown, by inputting the resolver sine signal and the sine output angle into an a multiplier, and inputting the resolver cosine signal and the cosine output angle into a b multiplier, the a output signal and the b output signal are respectively output and added to obtain the a excitation signal , input the a excitation signal and the b excitation signal into the multiplier of the last stage, and output the detection signal .

[0054] It can be seen from this that in the conventional orthogonality error detection device, two multipliers and multipliers are required, where the operation of the multiplier is to first perform a shift operation on a set of data to obtain m groups of data, and then multiply and add each bit of data in the m groups of data with other bit data. Therefore, one multiplier is equivalent to m multipliers and m adders. Therefore, there is a problem of huge hardware implementation cost. By using the orthogonality error detection module 30 in this embodiment, and the modules in the embodiments of the present invention, the required multipliers are all multipliers, and multipliers are not required, which greatly reduces the hardware implementation cost.

[0055] An embodiment of the present application also proposes an orthogonality error detection method. Refer to Figure 5 as shown, Figure 5 which is a schematic flowchart of an embodiment of the orthogonality error detection method of the present application.

[0056] In this embodiment, the orthogonality error detection method includes steps S10 to S50: Step S10, process the excitation phase output by the rotation phase and excitation phase correction module through the frequency synthesis module to obtain a first excitation signal and a second excitation signal; Step S20, process the resolver sine signal, resolver cosine signal, the first excitation signal, and the second excitation signal through the demodulation module to obtain a demodulation signal and a detection signal.

[0057] Step S30, suppress the quantization noise in the detection signal through a filter.

[0058] Step S40, suppress the double excitation frequency interference in the detection signal through a filter.

[0059] Step S50, judge the detection signal after the suppression operation and output the orthogonality error result.

[0060] The implementation processes of steps S10 to S50 can refer to the description corresponding to Figures 1 - 4 , and will not be repeated here.

[0061] In step S20, the orthogonality error detection method further includes step S21: Step S21, adding an excitation phase correction coefficient to the excitation phase.

[0062] The implementation process of step S21 can be referred to Figure 5 the corresponding description, and will not be repeated here.

[0063] In step S20, the orthogonality error detection method further includes steps S22 to S24: Step S22, multiplying the resolver sine signal in the second excitation signal and the modulation signal accessed to output a first output signal, and multiplying the resolver cosine signal in the first excitation signal and the modulation signal accessed to output a second output signal; Step S23, subtracting the first output signal from the second output signal to output the demodulation signal, multiplying the first excitation signal accessed and the resolver sine signal to output a third output signal, and multiplying the second excitation signal accessed and the resolver cosine signal to output a fourth output signal; Step S24, adding the third output signal and the fourth output signal to output a detection signal.

[0064] The implementation processes of steps S23 to S24 can be referred to Figure 2 the corresponding description, and will not be repeated here.

[0065] Here, the principle that the demodulation module and the orthogonality error detection module 30 can be commonly connected to the frequency synthesis module 10 to perform corresponding operations is described.

[0066] In step S40, the orthogonality error detection method further includes step S41 or S42: Step S41, in the case where the filter includes a digital integrator, based on the digital integrator, controlling the subtraction of the integration of each quarter of the excitation frequency period of the integration to suppress the double excitation frequency interference; or, step S42, in the case where the filter includes a notch filter or a half-band notch filter, suppressing the double excitation frequency interference based on the notch filter or the half-band notch filter.

[0067] The implementation processes of steps S41 to S42 can be referred to Figure 2 the corresponding description, and will not be repeated here.

[0068] It should be noted that referring to Figure 6As shown, after suppressing the interference of the double excitation frequency through a notch filter or a comb filter (i.e., eliminating the harmonic components at twice the excitation frequency in the detection signal), it is also necessary to extract the useful signal at low frequencies through a low-pass filter.

[0069] First, it should be noted that traditional orthogonal error detection is generally achieved through the detection method of the sum of squares. Specifically, it is described in combination with Figure 7 as follows.

[0070] Figure 7 For the traditional orthogonal error detection using the sum-of-squares detection method, input signal one and input signal two are respectively multiplied by corresponding multipliers to obtain the squared signal of input signal one and the squared signal of input signal two . After that, the two squared signals are input into an adder for addition to obtain the detection signal .

[0071] For the specific process, refer to Figure 8 shown in Figure 8 which is obtained by the sum-of-squares operation of the input signal passing through Figure 7 . Figure 8 The signal frequency of Figure 8 is twice the input signal frequency, that is, the time required for the signal in the dashed box of

[0072] Figure 9 corresponds to the time of one signal cycle of the resolver input signal. Figure 8 is obtained by performing periodic area integration on Figure 8 . By performing periodic area integration on Figure 9 the waveform of Figure 8 can be obtained. Among them, the dashed box of

[0073] Figure 9 is one period of the area integration.

[0074] The amplitude of the waveform of

[0075] Figure 10 represents the value of the sum of the squares of cosθ and sinθ. If the input sine signal and cosine signal are orthogonal, the amplitude after each integration will reach 1. If the input sine signal and cosine signal are non-orthogonal, the amplitude after each integration will be less than 1. Figure 8 In addition to the method of periodic area integration, the sum-of-squares operation can also use the method of envelope extraction to detect orthogonality.

[0076] For a Nyquist sampling rate ADC such as a SAR ADC, orthogonality can be detected by means of a sum-of-squares operation, followed by a periodic area integration method or an envelope extraction method. However, this operation method has certain drawbacks. Since the SAR ADC outputs multi-bit digital codes, a very large multiplier is required for the sum-of-squares operation, resulting in excessive device hardware costs. That is, the following problems exist: ① If signals one and two are not converted into digital codes by an ADC (Analog-to-Digital Converter), then signals one and two are analog signals. Therefore, at this time Figure 7 the multiplier in it is an analog multiplier, and analog multipliers have the disadvantages of poor linearity, harmonic distortion, and high power consumption.

[0077] ② If signals one and two are digital codes that have been converted by an ADC, then at this time Figure 2 the multiplier in it is a digital multiplier. However, an ADC, such as a DSM ADC (Delta-Sigma Modulation Analog-to-Digital Converter), has a noise shaping function. Therefore, the 1-bit digital code converted by this ADC needs to be filtered before the sum-of-squares detection method operation can be performed, which requires the operation of setting up two additional filters.

[0078] If the 1-bit digital code is directly used for the sum-of-squares detection method operation without filtering, quantization noise aliasing will occur, as shown in the specific Figure 11 spectrum diagram. Assume that the DSM ADC outputs a signal. After the signal is noise-shaped, the noise components at the high frequencies of the signal will be very large. Therefore, if this signal is directly subjected to a sum-of-squares operation without filtering, a spectrum diagram as shown in Figure 12 will be obtained. Based on Figure 12 it can be seen that during the quantization convolution process, the useful signal at the DC will be aliased. That is, the after the sum-of-squares operation has a large amount of noise at low frequencies, and the signal will be submerged in the noise and no effective output can be obtained. Therefore, it needs to be filtered.

[0079] ③If Signal 1 and Signal 2 are generated by a multi-bit non-noise shaping ADC, such as a SAR ADC (Successive Approximation Register Analog-to-Digital Converter), since there is no noise shaping, there is no problem of large noise at high frequencies for Signal 1 and Signal 2, so there is no need to add a filter. However, the output of such an ADC is an n-bit digital code, so 2 multipliers are required, and since one multiplier is equivalent to n multipliers and n adders, there is a situation where the device hardware cost is too high.

[0080] To address the above problems, a conventional orthogonality error detection device as shown in Figure 4 is conventionally proposed. Figure 4 The sine output angle and cosine output angle in are not generated by the ADC. Therefore, there are no noise components at high frequencies for the sine output angle and cosine output angle . Although the resolver cosine signal and resolver sine signal are 1-bit digital codes generated by, for example, a DSM ADC and there are noise components at high frequencies, because the high frequencies of the sine output angle and cosine output angle corresponding to them respectively have no noise components, the signal after multiplication is a valid signal. Refer to the spectrogram shown in Figure 13 .

[0081] Figure 13 In , (a) is the spectrogram of . It can be seen from this figure that after noise shaping by the DSM ADC has noise components at high frequencies. However, as can be seen from (b) in Figure 13 , since is not generated by the DSM ADC, has no noise components at high frequencies. Multiplying and gives (c) in Figure 13 . It can be seen from this figure that will not be submerged in noise, that is, an effective output can be obtained.

[0082] Therefore, the above implementation method has the following advantages: ①It avoids the use of analog multipliers, thus avoiding the defects of analog multipliers.

[0083] ②Because there are no noise components at the high frequencies of the sine output angle and the cosine output angle no filtering process is required between the output detection signals, thus avoiding the addition of filters.

[0084] ③Since the modulation signal is multiplied by the corresponding output angle instead of the modulation signal being squared, there is no aliasing of quantization noise.

[0085] At this time, the detection signal Figure 4 in is transformed to obtain Equation ①: — Equation ① where and are determined by the modulator and cannot be changed, so only and can be transformed to obtain Equation ②: ———— Equation ② Substituting Equation ② into Equation ① gives the following Equation ③:

[0086] In the conventional demodulation process, the output conventional demodulation signal is as shown in Equation ④ below:

[0087] Transforming Equation ④ into the following Equation ⑤:

[0088] According to the conversion equation shown in Equation ②, Equation ⑤ can be transformed into Equation ⑥:

[0089] Equation ③ represents the orthogonality error detection operation process of the rotational digital converter's orthogonality error detection, and Equation ⑥ represents the demodulation operation process of the rotational digital converter's demodulation. Observing Equation ③ and Equation ⑥, it can be seen that in addition to the same modulation signal being connected in both Equation ③ and Equation ⑥, the excitation signal and the excitation signal are also the same, and the excitation signal and the excitation signal can adopt the LUT / CORDIC method, and can be obtained through mapping to get 、 、 and , therefore, based on this, this embodiment designs an architecture as shown by the lookup combination unit in Figure 2 . Through this architecture, the excitation signals required for the demodulation operation process and the orthogonality error detection operation process can be obtained, enabling the orthogonality error detection operation process and the demodulation operation process to share a frequency synthesis module. In this way, the architectures required for the orthogonality error detection operation and the demodulation operation are integrated into one device, which not only avoids the problem of increased hardware costs due to the need to separately set up relatively independent devices for the two operations, but also avoids the problem of increased circuit area costs caused by the need to occupy the corresponding circuit area when separately setting up relatively independent devices for the two operations.

[0090] The full name of LUT is Look-Up Table, that is, the method of lookup table. The sine and cosine values of specific phases can be obtained through mapping; while the CORDIC algorithm is an algorithm of "simplifying complexity", which converts many complex operations into an iterative operation of "only requiring shift and addition".

[0091] In this embodiment, the frequency synthesis module processes the excitation phase output by the rotation phase and excitation phase correction module to obtain the first excitation signal and the second excitation signal; the demodulation module processes the resolver sine signal, resolver cosine signal, the first excitation signal, and the second excitation signal to obtain the demodulation signal and the detection signal, and judges the detection signal to output the orthogonality error result. Since the modules corresponding to the demodulation operation and the modules corresponding to the orthogonality error detection operation are in the same orthogonality error detection device, the problem of increased circuit area costs caused by the need to occupy the corresponding circuit area when separately setting up relatively independent devices for the two operations is avoided.

[0092] This application provides a rotary digital converter, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the orthogonality error detection method in the above embodiment.

[0093] Next, refer to Figure 14 , which shows a schematic structural diagram of a rotary digital converter suitable for implementing the embodiments of this application. The rotary digital converter in the embodiments of this application may include, but is not limited to, mobile terminals such as laptop computers, PADs (Portable Application Description: tablet computers), PMPs (Portable Media Player: portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 14The illustrated rotary digital converter is merely an example and should not impose any limitations on the functions and scope of use of the embodiments of the present application.

[0094] As Figure 14 shown, the rotary digital converter may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the rotary digital converter are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, etc.; an output device 1008 including, for example, a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the rotary digital converter to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a rotary digital converter with various systems, it should be understood that it is not required to implement or have all the shown systems. More or fewer systems may be alternatively implemented or had.

[0095] Specifically, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0096] The rotary digital converter provided by the present application adopts the orthogonality error detection method in the above-mentioned embodiment, which can solve the technical problems of quantization noise aliasing, increased circuit area, and increased hardware cost existing in the solution of adding a hardware structure for orthogonality error detection in order to ensure the accuracy of demodulation. Compared with the prior art, the beneficial effects of the rotary digital converter provided by the present application are the same as those of the orthogonality error detection method provided by the above-mentioned embodiment, and other technical features in the rotary digital converter are the same as those disclosed in the method of the previous embodiment, which will not be elaborated here.

[0097] It should be understood that the various parts disclosed in the present application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0098] As mentioned above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0099] The present application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the orthogonality error detection method in the above-mentioned embodiment.

[0100] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, device, or component. The program code contained on the computer-readable storage medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0101] The above computer-readable storage medium can be included in a rotary digital converter; it can also exist separately and not be assembled into the rotary digital converter.

[0102] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by the rotary digital converter, the rotary digital converter is caused to: process the excitation phase output by the rotary phase and excitation phase correction module through a frequency synthesis module to obtain a first excitation signal and a second excitation signal; process the resolver sine signal, resolver cosine signal, first excitation signal, and second excitation signal through a demodulation module to obtain a demodulated signal and a detection signal; suppress quantization noise in the detection signal through a filter; suppress double excitation frequency interference in the detection signal through a filter; judge the detection signal after the suppression operation and output an orthogonality error result.

[0103] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0104] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of the code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0105] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0106] The readable storage medium provided by this application is a computer-readable storage medium. The computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned orthogonality error detection method, which can solve the technical problems of quantization noise aliasing, increased circuit area, and increased hardware cost existing in the solution of adding a hardware structure for orthogonality error detection in order to ensure the accuracy of demodulation. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by this application are the same as those of the orthogonality error detection method provided by the above embodiment, and will not be elaborated here.

[0107] The above are only partial embodiments of this application, and thus do not limit the patent scope of this application. Any equivalent structural transformation made under the technical concept of this application by using the content of the specification and drawings of this application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of this application.

Claims

1. An orthogonal error detection device, characterized in that: The orthogonal error detection device is applied to a rotary digital converter, and the orthogonal error detection device comprises an excitation phase correction module, a frequency synthesis module, a demodulation module, a rotation phase extraction module and an orthogonality error detection module; The frequency synthesis module processes the rotation phase and the excitation phase output by the excitation phase correction module to obtain a first excitation signal and a second excitation signal; The resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal are processed by the demodulation module to obtain a demodulation signal and a detection signal; Controlling the demodulated signal to output the rotation phase through the rotation phase extraction module; as well as, The detection signal is controlled to pass through the filter module to output an output signal, and then the output signal is controlled to pass through the orthogonality error detection module to obtain an orthogonality error signal.

2. The orthogonal error detection device according to claim 1, characterized in that: The frequency synthesis module includes a first adder and a second adder; The input end of the first adder is respectively connected to the rotation phase and the excitation phase for addition, and outputs a first target input signal; The input end of the second adder is respectively connected to the rotation phase and the excitation phase for subtraction, and outputs a second target input signal; The frequency synthesis module also includes a search combination unit, a third adder and a fourth adder; The input end of the search combination unit is connected to the output end of the first adder and the output end of the second adder, and is used to search for corresponding sine values ​​and cosine values ​​according to the first target input signal and the second target input signal, and output a first sine signal, a second sine signal, a first cosine signal, and a second cosine signal; The input end of the third adder is connected to the cosine output end of the search combination unit, and is used to operate the first cosine signal and the second cosine signal output by the cosine output end, and output the first excitation signal; The input end of the fourth adder is connected to the sinusoidal output end of the search combination unit, and is used to operate the first sinusoidal signal and the second sinusoidal signal output from the sinusoidal output end to output the second excitation signal.

3. The orthogonal error detection device according to claim 2, characterized in that: The demodulation module includes a first multiplier, a second multiplier and a fifth adder; The input end of the first multiplier is connected to the output end of the fourth adder and the modulator in the rotary digital converter respectively, and is used to multiply the second excitation signal and the resolver sinusoidal signal in the modulation signal to output a first output signal; The input end of the second multiplier is connected to the output end of the third adder and the modulator respectively, and is used to multiply the first excitation signal and the resolver cosine signal in the modulation signal to output a second output signal; The input end of the fifth adder is connected to the output end of the first multiplier and the output end of the second multiplier respectively, and is used to subtract the first output signal and the second output signal connected thereto, and output the demodulated signal.

4. The orthogonal error detection device according to claim 3, characterized in that: The orthogonality error detection module includes a third multiplier, a fourth multiplier and a sixth adder; The input end of the third multiplier is connected to the output end of the third adder and the modulator respectively, and is used to multiply the first excitation signal and the resolver sinusoidal signal to output a third output signal; The input end of the fourth multiplier is connected to the output end of the fourth adder and the modulator respectively, and is used to multiply the second excitation signal and the resolver cosine signal connected thereto to output a fourth output signal; The input end of the sixth adder is connected to the output end of the third multiplier and the output end of the fourth multiplier respectively, and is used to add the connected third output signal and the fourth output signal to output a detection signal.

5. An orthogonality error detection method, characterized in that: The orthogonality error detection method is applied to the orthogonality error detection device according to any one of claims 1 to 4, and the orthogonality error detection method comprises: The excitation phase output by the rotation phase and excitation phase correction module is processed by the frequency synthesis module to obtain a first excitation signal and a second excitation signal; The resolver sine signal, the resolver cosine signal, the first excitation signal and the second excitation signal are processed by a demodulation module to obtain a demodulation signal and a detection signal; Suppressing quantization noise in the detection signal by a filter; Suppressing the double excitation frequency interference in the detection signal by using a filter; The detection signal after the suppression operation is judged and the orthogonality error result is output.

6. The orthogonality error detection method according to claim 5, characterized in that: Before the step of performing operation on the received modulation signal and outputting the detection signal, the step further includes: An excitation phase correction factor is added to the excitation phase.

7. The orthogonality error detection method according to claim 6, characterized in that: The step of processing the resolver sine signal, the resolver cosine signal, the first excitation signal, and the second excitation signal through a demodulation module to obtain a demodulation signal and a detection signal comprises: The connected second excitation signal is multiplied by the resolver sine signal in the modulation signal to output a first output signal, and the connected first excitation signal is multiplied by the resolver cosine signal in the modulation signal to output a second output signal; subtracting the first output signal from the second output signal to output the demodulated signal; and, The first excitation signal connected to the resolver sine signal is multiplied to output a third output signal, and the second excitation signal connected to the resolver cosine signal is multiplied to output a fourth output signal; The third output signal and the fourth output signal are added to output the detection signal.

8. The orthogonality error detection method according to claim 7, characterized in that: The step of suppressing the double excitation frequency interference in the detection signal by using a filter comprises: In the case where the filter includes a digital integrator, based on the digital integrator, the integral of a quarter of the excitation frequency period of each integral is controlled to be subtracted to suppress the double excitation frequency interference; or, In a case where the filter includes a notch filter or a half-band notch filter, the double excitation frequency interference is suppressed based on the notch filter or the half-band notch filter.

9. A rotation digitizer, characterized in that: The rotation digitizer comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the orthogonality error detection method according to any one of claims 5 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the orthogonality error detection method according to any one of claims 5 to 8 are implemented.

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