A fast current sampling circuit

Abstract

The application provides a current sampling circuit, which comprises a sampling tube, an error amplifier, a sample-and-hold circuit, a first transistor, a second transistor and a third transistor. The sampling tube and the first transistor are connected in series, the first transistor and the second transistor establish a feedback loop with the error amplifier when the sampling tube is turned off, the second transistor is disconnected from the loop of the error amplifier when the sampling tube is turned on, and the first transistor and the error amplifier form a feedback loop. Since the loop of the error amplifier has been established when the sampling tube is turned off, the loop does not need to be re-established when the sampling tube is turned on again, and the current sampling speed is greatly improved. Meanwhile, the circuit can realize peak sampling, valley sampling, average sampling or current sampling in a certain period of inductance current, and the circuit is simple, flexible and easy to realize.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a fast current sampling circuit applied to a switching converter. BACKGROUND

[0002] Switching converters are widely used in various industrial electronic devices and consumer electronic devices. In a switching converter, the on and off of the switching elements in the switching converter can be controlled by different control methods, so as to convert the input voltage received by the switching converter into a suitable output voltage.

[0003] In some control circuits, the current of the circuit needs to be collected for further control of the circuit. Generally, the sampling circuit contains one or more poles, which will result in a relatively slow response speed in the sampling establishment process. It is desirable to propose a current sampling circuit with a faster response speed. SUMMARY

[0004] The purpose of the present application is to provide a fast current sampling circuit to solve the technical problem of slow response speed in the related art.

[0005] To achieve the above object, the application provides a current sampling circuit applied to a switching converter. The switching converter comprises a high-side switch, a low-side switch and an inductor, and the common end of the high-side switch and the low-side switch is a switching node. The current sampling circuit comprises: a sampling transistor having a first end, a second end and a control end, the second end of the sampling transistor being coupled to the switching node, and the control end of the sampling transistor receiving a sampling control signal; an error amplifier having a first input end, a second input end and an output end, the first input end of the error amplifier being coupled to the first end of the sampling transistor, and the error amplifier amplifying the difference between the voltages at the first end and the second end to output an error signal at the output end; a sample-and-hold circuit holding the value of the error signal and generating a holding voltage; a first transistor having a first end, a second end and a control end, the first end of the first transistor receiving a first voltage, the second end of the first transistor being coupled to the first input end of the error amplifier, and the control end of the first transistor being coupled to the output end of the error amplifier; a second transistor having a first end, a second end and a control end, the first end of the second transistor receiving the first voltage, the control end of the second transistor being coupled to the output end of the error amplifier through the sample-and-hold circuit, and the second end of the second transistor being coupled to the second input end of the error amplifier through the first switch; and a third transistor having a first end, a second end and a control end, the first end of the third transistor receiving the first voltage, the control end of the third transistor being coupled to the control end of the second transistor, and the second end of the third transistor outputting a current sampling signal as an output end of the sampling circuit. When the sampling transistor is off, the first switch is on, the first input end of the error amplifier is coupled to a second voltage through a first resistor, and the second input end of the error amplifier is coupled to the second voltage through a second resistor. When the sampling transistor is on, the first switch is off, the first input end of the error amplifier is disconnected from the first resistor, and the second input end of the error amplifier is disconnected from the second resistor and coupled to a third voltage. The above technical solution can realize fast sampling of the current, and can flexibly realize sampling of a certain specific value of the inductor current or sampling of the current value in a continuous time period. The circuit is simple and easy to realize. Other features and advantages of the application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0007] Figure 1 Fig. 1 shows a current sampling circuit according to an embodiment of the application;

[0008] Figure 2 Fig. 2 shows a switching converter with a current sampling circuit according to an embodiment of the application. DETAILED DESCRIPTION

[0009] The following is a non-limiting description of specific embodiments of the present invention with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the disclosure. References to “one embodiment” or “an embodiment” throughout this specification mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases “in one embodiment” or “in an embodiment” appearing throughout this specification do not necessarily refer to the same embodiment. Terms such as “first,” “second,” etc., are used for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. The verbs “comprising” and “having” are used herein as open-ended limitations, neither excluding nor requiring the presence of any unrecited features. Unless expressly stated otherwise, the features recited in the dependent claims may be freely combined with each other. The use of “a” or “an” (i.e., the singular form) to define an element throughout the document does not exclude the possibility of multiple such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify a direct electrical connection between circuit elements, while the term "coupled" is used to specify an electrical connection between circuit elements that may be direct or may be connected via one or more other elements. Conversely, when an element is referred to as "directly connected to" or "directly coupled to" another element, no intermediate element is present. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0010] Figure 1 The diagram illustrates a current sampling circuit according to an embodiment of the present invention. This current sampling circuit can be applied to a switching converter, which typically includes a power switch and an inductor. By controlling the on and off switching of the power switch, energy is stored and released in the inductor, thereby realizing the transfer of electrical energy. Generally, the power switch includes a high-side switch and a low-side switch, and the common node of the high-side and low-side switches is marked as the switching node SW. One end of the inductor is coupled to this switching node, and the inductor current can be obtained by sampling the current flowing through the high-side or low-side switch. This current sampling circuit is coupled to one end of the switching node SW and can sample the current flowing through the high-side or low-side switch in the switching converter.

[0011] like Figure 1 As shown, the current sampling circuit includes a sampling transistor Msen, an error amplifier EA, a sample-and-hold circuit 10, a first transistor M1, a second transistor M2, a third transistor M3, and a first switching transistor S1.

[0012] like Figure 1As shown, the sampling transistor Msen has a first end, a second end and a control end, the second end of the sampling transistor Msen is coupled to the switch node SW, and the control end of the sampling transistor Msen receives a sampling control signal EN-sen.

[0013] The error amplifier EA has a first input end, a second input end and an output end, the first input end of the error amplifier EA is coupled to the first end of the sampling transistor Msen, and the error amplifier EA amplifies the difference between the voltages on its first and second input ends to output an error signal Vea at its output end.

[0014] The sample-and-hold circuit 10 holds the value of the error signal Vea and generates a hold voltage Vh. The hold voltage Vh is used to represent the value of the current flowing through the sampling transistor Msen. In one embodiment, the hold voltage is a specific value representing the peak value, the valley value or any specific current value of the current flowing through the sampling transistor Msen. In another embodiment, the hold voltage Vh is a continuously changing value representing the current flowing through the sampling transistor Msen over a period of time. The sample-and-hold circuit 10 can flexibly set the value of the hold voltage Vh according to the specific topology of the switching converter or the current to be sampled.

[0015] The first transistor M1 has a first end, a second end and a control end, the first end of the first transistor M1 receives the first voltage V1, the second end of the first transistor M1 is coupled to the first input end of the error amplifier EA, and the control end of the first transistor M1 is coupled to the output end of the error amplifier EA.

[0016] The second transistor M2 has a first end, a second end and a control end, the first end of the second transistor M2 receives the first voltage, the control end of the second transistor M2 is coupled to the output end of the error amplifier EA through the sample-and-hold circuit 10, and the second end of the second transistor M2 is coupled to the second input end of the error amplifier EA through the first switch transistor.

[0017] The third transistor M3 has a first end, a second end and a control end, the first end of the third transistor M3 receives the first voltage V1, the control end of the third transistor M3 is coupled to the control end of the second transistor M2, and the second end of the third transistor M3 outputs a current sampling signal ICS as the output end of the sample-and-hold circuit 10.

[0018] When the sampling transistor Msen is off, the first switch transistor S1 is on, the first input of the error amplifier EA is coupled to the second voltage V2 through the first resistor, and the second input of the error amplifier EA is coupled to the second voltage V2 through the second resistor. At the same time, the hold voltage Vh is maintained at the value at the moment when the sampling transistor Msen is switched from on to off. At this time, the first transistor M1 and the error amplifier EA form a loop through the first input of the error amplifier EA, and the second transistor M2 and the error amplifier EA form a loop through the first switch transistor S1 and the second input of the error amplifier EA, and two equal voltage values are established at the first input and the second input of the error amplifier EA, respectively. At this time, the value of the error signal Vea will be adjusted to equal the value of the hold voltage Vh. The hold voltage Vh serves as the voltage at the control terminal of the third transistor M3, which controls the third transistor M3 to generate a current sampling signal Ics at the second terminal of the third transistor M3. The current sampling signal Ics will change with the change of the hold voltage Vh.

[0019] When the sampling transistor Msen is on, the first switch transistor S1 is off, the second terminal of the second transistor M2 is floating (disconnected from the second input of the error amplifier EA), and at the same time, the second input of the error amplifier EA is coupled to the third voltage V3. At this time, the first transistor M1, the sampling transistor Msen and the error amplifier EA form a loop. The current Isen flowing through the first transistor M1 and the sampling transistor Msen is proportional to the current flowing through the inductor, and the proportionality coefficient is the ratio of the on-resistance of the sampling transistor Msen to the on-resistance of the corresponding power switch (high-side switch transistor or low-side switch transistor). At the same time, the sample-and-hold circuit 10 will generate a hold voltage Vh according to the error signal Vea. In one embodiment, if the sample-and-hold circuit 10 generates the hold voltage Vh at a certain current (such as peak, valley or average, etc.) of the sampling transistor Msen, the hold voltage Vh represents the current flowing through the sampling transistor Msen at that certain moment, and therefore, the current sampling signal Ics generated by the third transistor M3 at its second terminal under the control of the hold voltage Vh can represent the current flowing through the sampling transistor Msen at that certain moment. In another embodiment, the hold voltage Vh generated by the sample-and-hold circuit 10 is a continuously changing value, which can change according to the change of the current flowing through the sampling transistor Msen, and therefore, the current sampling signal Ics generated by the third transistor M3 at its second terminal under the control of the hold voltage Vh is also changing, which can represent the current flowing through the sampling transistor Msen in a period of time (for example, during the on period of the sampling transistor Msen).

[0020] Since the feedback loop of the error amplifier EA has been established when the sampling tube Msen is disconnected, the value of the error signal Vea has been adjusted to equal the value of the hold voltage Vh, thus when the sampling tube Msen is turned on again, the feedback loop of the error amplifier EA does not need to be re-established, and the current sampling speed will be greatly improved. At the same time, by flexibly setting the sampling and holding time of the error signal Vea in the sample and hold circuit 10, peak sampling, valley sampling, average sampling or current sampling in a time period of the inductor current can be realized.

[0021] It should be noted that the forms of the first resistor and the second resistor are not fixed, and in Figure 1 In the embodiment shown in FIG. 2, since it is illustrated that the first input terminal and the second input terminal of the error amplifier EA are clamped to a voltage value through the second switch tube S2 and the third switch tube S3, in some embodiments, if the on-voltage drop values of the second switch tube S2 and the third switch tube S3 meet the requirements of loop establishment, their respective on-resistances can be used as the first resistor and the second resistor, respectively. In other embodiments, for example, in the embodiment shown in FIG. 3, two resistors R1 and R2 can be introduced separately as the first resistor and the second resistor, respectively. Figure 2

[0022] In one embodiment, whether the third voltage V3 is connected or not can be controlled by introducing a fourth switch tube S4 in the current sampling circuit. Specifically, the fourth switch tube S4 is coupled between the second input terminal of the error amplifier EA and the third voltage V3, and the fourth switch tube S4 is synchronously turned on with the sampling tube Msen. In one embodiment, the first switch tube S1, the second switch tube S2 and the third switch tube S3 are controlled by the inverse phase signal EN-sen-b of the sampling control signal, and the fourth switch tube S4 is controlled by the sampling control signal EN-sen.

[0023] In one embodiment, the first switch tube S1, the second switch tube S2, the third switch tube S3 and the fourth switch tube S4 are all transistors. In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the first switch tube S1, the second switch tube S2, the third switch tube S3 and the fourth switch tube S4 include any suitable controllable semiconductor device, for example, a metal semiconductor field effect transistor (MOSFET), in one embodiment, the first end is the source of the MOSFET, the second end is the drain of the MOSFET, and the control end is the gate of the MOSFET.

[0024] ​In one embodiment, a capacitor C0 is further included in the current sampling circuit. The capacitor C0 is used to compensate the loop so that the voltage on the control terminal of the first transistor M1 changes slowly, and the loop is more stable.

[0025] Further, in one embodiment, the first voltage V1, the second voltage V2, the third voltage V3 and the specific topology of the selected switching converter or the selected type of transistor are related to the selected sampled current. In the following, a circuit schematic of one specific embodiment will be shown in Figure 2

[0026] As shown in Figure 2 , the switching circuit 20 in the switching converter is shown as a buck (BUCK) topology formed by a high-side switch HS, a low-side switch LS, an inductor L and a filter capacitor. The high-side switch HS and the low-side switch LS are coupled in series between the input of the switching circuit 20 and a reference ground, and the common node of the high-side switch HS and the low-side switch LS is marked as a switching node SW. The inductor L is coupled between the switching node SW and the output of the switching circuit 20. The filter capacitor is coupled between the output and the reference ground. A control signal HS-on of the high-side switch is used to control the on and off time of the high-side switch HS, and a control signal LS-on of the low-side switch is used to control the on and off time of the low-side switch LS. Generally, in the non-discontinuous mode, the control signal HS-on of the high-side switch and the control signal LS-on of the low-side switch are logic complementary signals. By controlling the on and off switching of the high-side switch HS and the low-side switch LS, the input voltage signal VIN is converted to the output voltage signal VOUT. Those skilled in the art can understand that the embodiments disclosed in the present application are not limited to be applied in the switching converter of the BUCK topology, but can also be applied in the switching converter of other topologies, such as the boost (BOOST) switching converter, etc.

[0027] In the embodiment shown in Figure 2 , the sampling circuit is shown to sample the current flowing through the low-side switch LS in the switching circuit 20, so the sampling control signal EN-sen can be the control signal LS-on of the low-side switch. In actual design, the sampling control signal EN-sen and the control signal LS-on of the low-side switch have a certain time difference, which ensures that the sampling switch Msen is turned on after the low-side switch LS is turned on. In addition, since the current flowing through the low-side switch LS is sampled, the first voltage V1 can be the supply voltage VCC inside the sampling circuit, and the second voltage V2 and the third voltage V3 are both the reference ground potential. Generally, the supply voltage VCC is generated by the input voltage VIN.

[0028] In the embodiment shown in Figure 2 ​In the illustrated embodiment, the first transistor M1, the second transistor M2 and the third transistor M3 are illustrated as P-type MOSFETs, and the high-side switch HS, the low-side switch LS and the sampling transistor Msen are illustrated as N-type MOSFETs. The first voltage V1, the second voltage V2 and the third voltage V3, as well as the types of all transistors, can be flexibly set according to different application scenarios. For example, when the sampling circuit needs to sample the current flowing through the high-side switch HS in the switching circuit 20, the first transistor M1, the second transistor M2 and the third transistor M3 can be selected as N-type MOSFETs, the first voltage V1 is set as a reference ground, and the second voltage V2 and the third voltage V3 are set as the input voltage VIN of the switching converter. Similarly, in a BOOST switching converter, if the current of the high-side switch in the BOOST switching converter needs to be collected, the first voltage V1 can be set as a reference ground, and the second voltage V2 and the third voltage V3 can be set as the output voltage VOUT of the switching converter.

[0029] Continuing to refer to Figure 2 In Figure 2 In the illustrated embodiment, the circuit structure of a sample-and-hold circuit 10 is specifically illustrated, which is illustrated as including a pulse signal generator, a transmission gate 101 and a first capacitor C1.

[0030] The pulse signal generator receives a sampling control signal EN-sen and generates a pulse signal on-pls at a certain time according to the sampling control signal EN-sen. The pulse signal generator can generate the pulse signal on-pls at the rising edge of the sampling control signal EN-sen, or at the falling edge of the sampling control signal EN-sen, or at other selected appropriate time. In an embodiment, the pulse signal on-pls is a narrow pulse signal with a certain fixed pulse width, generally tens of nanoseconds. The transmission gate 101 has a first end, a second end, a first control end and a second control end. The first end of the transmission gate 101 is coupled to the output end of the error amplifier EA, the second end of the transmission gate is coupled to the control end of the second transistor M2, the first control end of the transmission gate 101 receives the pulse signal on-pls, and the second control end of the transmission gate 101 receives the inverse signal on-pls-b of the pulse signal on-pls. The first capacitor C1 is coupled between the first end and the control end of the first transistor M1.

[0031] In an embodiment, when the low-side switch LS is turned on, the pulse signal on-pls turns on the transmission gate 101 during its effective pulse width, and samples and holds the value of the error signal Vea at this time on the first capacitor C1, and then the transmission gate 101 is turned off. At this time, the value on the capacitor C1 can represent the peak value of the current flowing through the low-side switch LS.

[0032] In another embodiment, at the moment when the low-side switch LS is turned off, the pulse signal on-pls turns on the transmission gate 101 during its active pulse width, and samples and holds the value of the error signal Vea onto the first capacitor C1 at this moment, and then the transmission gate 101 is turned off. At this moment, the value on the capacitor C1 can represent the valley value of the current flowing through the low-side switch LS.

[0033] In yet another embodiment, the sample-and-hold circuit 10 can omit the pulse signal generator, and only include the transmission gate 101 and the first capacitor C1. The first capacitor C1 is still coupled between the first terminal and the control terminal of the first transistor M1. The first terminal of the transmission gate 101 is coupled to the output terminal of the error amplifier EA, the second terminal of the transmission gate 101 is coupled to the control terminal of the second transistor M2, the first control terminal of the transmission gate 101 no longer receives the pulse signal on-pls, but directly receives the sampling control signal EN-sen, and the second control terminal of the transmission gate 101 receives the inverse signal EN-sen-b of the sampling control signal EN-sen. At this moment, during the on period of the sampling transistor Msen, the transmission gate 101 remains on, and samples and holds the value of the error signal Vea onto the first capacitor C1. Since the error signal Vea varies with the current flowing through the sampling transistor Msen, the hold voltage Vh is also a continuously varying value, and the third transistor M3 generates the current sampling signal Ics at its second terminal, which represents the current flowing through the sampling transistor Msen during the on period.

[0034] The preferred embodiments of the present disclosure are described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure. In addition, it should be noted that various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations. Furthermore, various different embodiments of the present disclosure can also be combined in any manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A current sampling circuit applied to a switching converter, the switching converter comprising a high-side switch, a low-side switch, and an inductor, wherein the common terminal of the high-side switch and the low-side switch serves as a switching node, characterized in that, The current sampling circuit includes: The sampling tube has a first end, a second end, and a control end. The second end of the sampling tube is coupled to a switching node, and the control end of the sampling tube receives a sampling control signal. An error amplifier has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier is coupled to the first terminal of the sampling tube. The error amplifier amplifies the voltage difference between its first and second input terminals to output an error signal at its output terminal. The sample-and-hold circuit holds the value of the error signal and generates a holding voltage; The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor receives a first voltage. The second terminal of the first transistor is coupled to the first input terminal of the error amplifier. The control terminal of the first transistor is coupled to the output terminal of the error amplifier. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor receives a first voltage. The control terminal of the second transistor is coupled to the output terminal of the error amplifier through a sample-and-hold circuit. The second terminal of the second transistor is coupled to the second input terminal of the error amplifier through a first switch. The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor receives a first voltage. The control terminal of the third transistor is coupled to the control terminal of the second transistor. The second terminal of the third transistor serves as the output terminal of the sampling circuit, outputting a current sampling signal. When the sampling tube is turned off, the first switching tube is turned on, and the first input terminal of the error amplifier is also coupled to the second voltage through the first resistor, and the second input terminal of the error amplifier is also coupled to the second voltage through the second resistor. When the sampling tube is turned on, the first switching tube is turned off, the first input terminal of the error amplifier is disconnected from the first resistor, and the second input terminal of the error amplifier is disconnected from the second resistor and coupled to the third voltage.

2. The current sampling circuit according to claim 1, characterized in that, Further includes: The second switch is coupled between the first input terminal of the error amplifier and the second voltage, and the first resistor includes the on-resistance of the second switch after it is turned on. The third switch is coupled between the second input terminal of the error amplifier and the second voltage, and the second resistor includes the on-resistance of the third switch after it is turned on. The fourth switch is coupled between the second input terminal of the error amplifier and the third voltage. Among them, the second and third switching transistors are complementary to the sampling transistor, and the fourth switching transistor is synchronously connected with the sampling transistor.

3. The current sampling circuit according to claim 1, characterized in that, Further includes: The second switch and the first resistor are connected in series between the first input terminal of the error amplifier and the second voltage. The third switch is connected in series with the second resistor between the second input terminal of the error amplifier and the second voltage. The fourth switch is coupled between the second input terminal of the error amplifier and the third voltage. Among them, the second and third switching transistors are complementary to the sampling transistor, and the fourth switching transistor is synchronously connected with the sampling transistor.

4. The current sampling circuit according to claim 1, characterized in that, When the sampled inductor current is the current flowing through the low-side switch, the first voltage includes the supply voltage, the second and third voltages include the reference ground, and the sampling control signal includes the control signal of the low-side switch.

5. The current sampling circuit according to claim 1, characterized in that, When the sampled inductor current is the current flowing through the high-side switch, the first voltage includes the reference ground, the second and third voltages include the input voltage of the switching converter, and the sampling control signal includes the control signal of the high-side switch.

6. The current sampling circuit according to claim 1, characterized in that, The resistance values ​​of the first resistor and the second resistor are equal.

7. The current sampling circuit according to claim 1, characterized in that, The holding voltage represents the peak, valley, or any specific current value flowing through the sampling tube.

8. The current sampling circuit according to claim 1, characterized in that, The holding voltage is a continuously changing value, representing the current flowing through the sampling tube over a period of time.

9. The current sampling circuit according to claim 1, characterized in that, The sample-and-hold circuit includes: The transmission gate has a first terminal, a second terminal, a first control terminal, and a second control terminal. The first terminal of the transmission gate is coupled to the output terminal of the error amplifier, and the second terminal of the transmission gate is coupled to the control terminal of the second transistor. The first control terminal of the transmission gate receives a sampling control signal, and the second control terminal of the transmission gate receives the inverted signal of the sampling control signal. The first capacitor is coupled between the first terminal of the second transistor and the control terminal.

10. The current sampling circuit according to claim 1, characterized in that, The sample-and-hold circuit includes: A pulse signal generator receives a sampling control signal and generates a pulse signal at a specific moment according to the sampling control signal. A transmission gate has a first terminal, a second terminal, a first control terminal, and a second control terminal. The first terminal of the transmission gate is coupled to the output terminal of an error amplifier, and the second terminal of the transmission gate is coupled to the control terminal of a second transistor. The first control terminal of the transmission gate receives a pulse signal, and the second control terminal of the transmission gate receives the inverted signal of the pulse signal. The first capacitor is coupled between the first terminal of the second transistor and the control terminal.

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