Analog circuit soft fault diagnosis method and system based on deep neural network

Abstract

The invention belongs to the related technical field of analog circuit fault diagnosis, and discloses an analog circuit soft fault diagnosis method and system based on a deep neural network, and the method comprises the steps: carrying out the decomposition and reconstruction of a voltage time sequence signal X1 outputted by a circuit through a multi-wavelet function, generating a plurality of reconstructed voltage time sequence signals and then forming a multi-dimensional time sequence feature X2; performing feature screening on the multi-dimensional time sequence feature X2 by using a principal component analysis method to obtain a dimension-reduced time sequence feature X3; splicing the feature X2 and the feature X3 to obtain an input feature X4; and enabling the feature X4 to sequentially pass through a multi-scale convolutional network and a TimesNet model, and then outputting the fault type of the circuit through a full connection layer. According to the method, the preprocessing process and the learning model combining the multi-scale convolution and the TimesNet are integrated, only the single-point voltage output of the analog circuit needs to be analyzed, the used model is simple in structure, the training difficulty is small, the method is simple, and the diagnosis precision is high.

Description

Technical Field

[0001] The present invention belongs to the technical field related to analog circuit fault diagnosis, and more specifically, relates to a method and system for soft fault diagnosis of analog circuits based on a deep neural network. Background Art

[0002] According to statistics, in electronic devices composed of digital-analog hybrid circuits, 80% of the faults occur in the analog part of the circuit. In circuit testing, the cost of analog circuit testing accounts for 95% of the total cost of electronic circuit testing. Traditional methods for analog circuit fault diagnosis usually rely on the physical characteristics and behaviors of the circuit, and use classical circuit theories (such as Kirchhoff's laws, nodal analysis, etc.) to provide accurate fault descriptions. By using classical signal processing techniques such as frequency-domain and time-domain analysis, abnormal signals in the circuit are identified. Traditional methods also include Bayesian models, correlation-based methods, polynomial and V-transform coefficient-based methods, and entropy-based methods. As the structure of analog circuits becomes more complex, the modeling will increase accordingly, resulting in limited diagnostic accuracy and thus affecting the reliability of electronic circuits.

[0003] The method for diagnosing analog circuits based on a deep neural network relies on input-output data, so there is no need to model the corresponding system. It is becoming increasingly convenient to collect corresponding signals in the circuit, so the method based on a deep neural network is more suitable for fault diagnosis of complex circuits.

[0004] Chinese Patent CN106483449B discloses a method for analog circuit fault diagnosis using deep learning and complex features. At each measurement point, the amplitude and phase of the fault-free signal are measured respectively, the real and imaginary values of the signal are calculated, the real and imaginary values are used to construct a sample vector, and label marking is performed according to the fault state; a classification network is composed of an autoencoder network and a classifier, and the sample vector and the corresponding label are used for training. Then, when fault diagnosis needs to be performed on the analog circuit, different representative working frequencies are set in turn, the current amplitude and phase are measured at each measurement point, a sample vector is constructed in the same way, and then the trained classification network is input, and the classification result obtained is the fault diagnosis result. However, this method requires measurements at multiple measurement points, and the diagnostic operation has a certain workload.

[0005] The literature "An auxiliary classifier generative adversarial network based fault diagnosis for analog circuit." proposed an Auxiliary Classifier Generative Adversarial Network (ACGAN) based on Transformer, which uses pure Transformer components to construct the generator and discriminator for circuit fault diagnosis. This method adopts a deep neural network and combines it with the attention mechanism to achieve soft fault diagnosis of analog circuits. However, due to the large model, the training difficulty is increased for this method. Summary of the Invention

[0006] In view of the above defects or improvement requirements of the prior art, the present invention provides a method and system for soft fault diagnosis of analog circuits based on a deep neural network, aiming to realize the application of the deep neural network in soft faults of analog circuits in a simpler way and ensure the diagnosis accuracy.

[0007] To achieve the above object, the present invention provides a method for soft fault diagnosis of analog circuits based on a deep neural network, which includes:

[0008] Decompose and reconstruct the voltage time series signal X1 output by the circuit using a multi-wavelet function, and generate multiple reconstructed voltage time series signals to form a multi-dimensional time series feature X2;

[0009] Use the principal component analysis method to screen the features of the multi-dimensional time series feature X2 to obtain the time series feature X3 after dimensionality reduction;

[0010] Concatenate the feature X2 and the feature X3 to obtain the input feature X4;

[0011] Make the feature X4 pass through a multi-scale convolutional network and a TimesNet model in sequence, and then output the fault type of the circuit through a fully connected layer.

[0012] Optionally, the multi-scale convolutional network includes three parallel feature extraction channels and a concatenation layer for concatenating the features output by all channels;

[0013] Each channel includes three convolutional blocks connected in series, and each convolutional block includes a convolutional layer, a LeakyReLU layer, a Batchnorm layer, and a Drouput layer connected in sequence along the data flow direction.

[0014] Optionally, the three channels are the first to the third channels, where:

[0015] In the first channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 9×9, 7×7, and 5×5;

[0016] In the second channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 7×7, 5×5, and 3×3;

[0017] In the third channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 9×9, 7×7, and 5×5.

[0018] Optionally, the dropout ratio used by the Drouput layer is 0.5.

[0019] Optionally, the TimesNet model has three TimesBlocks, and the three TimesBlocks perform residual connections.

[0020] Optionally, the features output by the TimesNet model sequentially pass through the GeLU activation layer and the Drouput layer and then enter the fully connected layer to output the fault type of the circuit.

[0021] The present invention also provides a simulation circuit soft fault diagnosis system based on a deep neural network, which includes:

[0022] A reconstruction unit, configured to decompose and reconstruct the voltage time series signal X1 output by the circuit by using a multi-wavelet function, generate multiple reconstructed voltage time series signals, and then form a multi-dimensional time series feature X2;

[0023] A principal component analysis unit, configured to perform feature screening on the multi-dimensional time series feature X2 by using the principal component analysis method to obtain the time series feature X3 after dimensionality reduction;

[0024] An input unit, configured to splice the feature X2 and the feature X3 to obtain an input feature X4;

[0025] A fault identification unit, configured to enable the feature X4 to sequentially pass through a multi-scale convolutional network and the TimesNet model, and then output the fault type of the circuit through the fully connected layer.

[0026] The present invention also provides an electronic device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above are implemented.

[0027] The present invention also provides a computer-readable storage medium, on which a computer program is stored, where when the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0028] The present invention also provides a computer program product, including a computer program or instruction, where when the computer program or instruction is executed by a processor, the steps of the method described above are implemented.

[0029] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the present invention mainly has the following beneficial effects:

[0030] The method proposed by the present invention includes two key stages. First, data preprocessing is carried out and then input into a deep learning model for fault identification. Among them, when performing data preprocessing, combining multi-wavelet transform and principal component analysis method, first use multi-wavelet transform to convert the time-series information characteristics of the analog circuit output point voltage signal output by the oscilloscope into information-rich multi-dimensional feature samples, minimizing the possible noise and interference in the circuit output, expanding the sample dimension, and then using principal component analysis method to reduce the dimension of the original fault multi-dimensional data, enhancing the difference between multi-dimensional circuit fault characteristics, optimizing the data samples, which helps to improve the accuracy of subsequent analysis. Through data preprocessing, the inherent characteristics of the fault signal are retained, providing high-quality data for model training. And, the deep learning model used in the present invention combines multi-scale convolution (MSC) and TimesNet. TimesNet has a powerful extraction ability for processing time-series tasks, especially for periodic features. The present invention cleverly introduces multi-scale convolution operation before using TimesNet. The multi-scale convolution operation can extract feature information at different levels, reducing the differences caused by different receptive field sizes, making up for the limitation of traditional convolution algorithms that only use one receptive field, helping the neural network learn more robust feature representations, enhancing the network's modeling ability, and improving the feature extraction rate. Therefore, by combining the cross-dimensional extraction advantage of multi-scale convolution and the periodic feature extraction ability of TimesNet, by utilizing the inductive bias of multi-scale convolution and the powerful feature capturing ability of TimesNet, it is possible to better process the input data and improve the model performance, reducing the risk of overfitting, thereby improving the diagnostic accuracy. In summary, the soft fault diagnosis method of analog circuits based on deep neural network proposed by the present invention only needs to analyze the single-point voltage output of the analog circuit to diagnose its soft faults, and the learning model used has a simple structure and a small training difficulty. Therefore, the present invention can realize the application of deep neural network in the soft faults of analog circuits in a simpler way and ensure the diagnostic accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a flowchart of the steps of the soft fault diagnosis method of analog circuits based on deep neural network in an embodiment of the present invention;

[0032] Figure 2 is a signal flow diagram during the soft fault diagnosis of analog circuits in an embodiment of the present invention;

[0033] Figure 3 is a signal flow diagram of the data preprocessing process in an embodiment of the present invention;

[0034] Figure 4 It is the signal flow diagram of the multi-scale convolutional network in an embodiment of the present invention;

[0035] Figure 5 It is the structural schematic diagram of the multi-scale convolutional network in an embodiment of the present invention;

[0036] Figure 6 It is the structural schematic diagram of the TimesNet model in an embodiment of the present invention;

[0037] Figure 7 It is the structural schematic diagram of Test Circuit 1;

[0038] Figure 8 It is the structural schematic diagram of Test Circuit 2;

[0039] Figure 9 It is the result confusion matrix of soft fault diagnosis for Test Circuit 1 using the solution of the present invention;

[0040] Figure 10 It is the result confusion matrix of soft fault diagnosis for Test Circuit 2 using the solution of the present invention. Detailed Embodiment

[0041] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0042] Embodiment 1

[0043] As Figure 1 shown is the step flowchart of the soft fault diagnosis method for analog circuits based on a deep neural network in an embodiment of the present invention, which includes the following steps:

[0044] Step S1: Decompose and reconstruct the voltage time series signal X1 output by the circuit using a multi-wavelet function to generate multiple reconstructed voltage time series signals, and then form a multi-dimensional time series feature X2;

[0045] Step S2: Use the principal component analysis method to screen the features of the multi-dimensional time series feature X2 to obtain the time series feature X3 after dimensionality reduction;

[0046] Step S3: Concatenate the feature X2 and the feature X3 to obtain the input feature X4;

[0047] Step S4: Make the feature X4 pass through the multi-scale convolutional network and the TimesNet model in sequence, and then output the fault type of the circuit through the fully connected layer.

[0048] As Figure 2 shown is the signal flow diagram during the soft fault diagnosis of the analog circuit in an embodiment of the present invention.

[0049] The method proposed by the present invention includes two key stages, namely data preprocessing and the design of a deep learning model.

[0050] As Figure 3 shown is the signal flow diagram of the data preprocessing process in an embodiment of the present invention.

[0051] In the data preprocessing stage, the present invention combines multiple wavelet reconstructions (MWR) with the principal component analysis method (PCA) to achieve data feature expansion.

[0052] Specifically, the voltage waveform of a certain node of the circuit is collected by an oscilloscope as the voltage time series signal X1. After obtaining the voltage time series signal X1, the voltage time series signal X1 is structurally decomposed using a multi-wavelet function and then reconstructed to generate multiple time series signals, constituting the multi-dimensional time series feature X2.

[0053] The decomposition and reconstruction of the signal by the multi-wavelet function can be realized by conventional means. The following briefly describes this process.

[0054] In the wavelet decomposition stage, the signal is decomposed into wavelet coefficients of different scales and frequencies through wavelet transform:

[0055]

[0056] The expression W(a, b) represents the wavelet coefficient calculated using the scale parameter a and the translation parameter b. Here, x[n] represents the discrete sample of the input signal X1 at the time point n, and ψ * (t) represents the complex conjugate of the wavelet function ψ(t). The parameter affects the time and frequency resolution of the wavelet, and b controls its time position.

[0057] In the wavelet reconstruction stage, these wavelet coefficients are recombined into the original signal through the inverse wavelet transform. The selection of the wavelet basis function and the dimension of the principal component analysis mapping depend on various factors. Seven different wavelet basis functions are used for reconstruction in this method, namely Daubechies-2, Daubechies-3, Haar, Coiflet-1, Coiflet-2, Symlet-2, and Symlet-3. The wavelet reconstruction obtains an approximation or reconstruction of the original signal by multiplying the wavelet coefficients at each scale and position by the corresponding wavelet basis function and summing them. In practical applications, the wavelet reconstruction process is usually realized through the inverse wavelet transform, which is the inverse process of wavelet analysis and is used to reconstruct the original signal from the wavelet coefficients.

[0058]

[0059] In the context of wavelet analysis, x[n] represents the discrete samples of the input signal at time point n. The wavelet coefficient W(a, b) represents the result of the wavelet transform at scale a and translation b. The function ψ(t) represents the wavelet function used in the transform. The parameters a and b are discrete values that control the scale and translation of the wavelet function respectively, affecting the time and frequency resolution of wavelet analysis.

[0060] After wavelet reconstruction, all the reconstructed signals are combined to obtain the multi-dimensional time series feature X2. Subsequently, the multi-dimensional time series feature X2 is processed by the principal component analysis method to obtain the time series feature X3 after dimensionality reduction.

[0061] Among them, the conventional principal component analysis method can be adopted. The following is a simple description of this process.

[0062] The principal component analysis method transforms a set of possibly correlated variables into a set of linearly uncorrelated variables through an orthogonal transformation. The resulting set of variables is called the principal components. The basic concept of the principal component analysis method is to map the n-dimensional features to m dimensions (m < n), where m is the number of principal components. These are orthogonal features created by projecting the data along the maximum direction. This process helps to distinguish the data. Consider a scenario with m-dimensional data, X = [x 1 , x 2 ,..., x m , where each x is an n-dimensional column vector:

[0063]

[0064] The coordinate values of each data point in this direction are as follows: w T x i , then the variance is:

[0065]

[0066] Therefore, the target can be obtained by identifying the maximum value of D(x). Calculate the covariance matrix and perform eigenvalue decomposition on the covariance matrix to obtain the eigenvalue matrix (columns from the largest to the smallest eigenvalues), and take the first k columns to form the matrix P n×k . Project the original data onto the P coordinate system to obtain the dimensionality-reduced data:

[0067] Y k×m = P n×k X n×m .

[0068] Finally, the features X2 and X3 are concatenated to obtain the input feature X4. Thus, the process of data preprocessing is completed.

[0069] In the present invention, before inputting features into a neural network, preprocessing is first performed. Combining multi-wavelet transform and principal component analysis, the time-series information features of the analog circuit output point voltage signal output by the oscilloscope are first transformed into multi-dimensional feature samples with rich information by using multi-wavelet transform, minimizing the possible noise and interference in the circuit output, expanding the sample dimension. Then, principal component analysis is used to reduce the dimension of the original fault multi-dimensional data, enhancing the difference between multi-dimensional circuit fault features and optimizing the data samples, which helps improve the accuracy of subsequent analysis. Through data preprocessing, the inherent features of the fault signal are retained, providing high-quality data for model training.

[0070] After completing the data preprocessing, a deep learning model can be used to identify faults. In the present invention, specifically, feature X4 is sequentially passed through a multi-scale convolutional network and a TimesNet model, and then the fault type of the circuit is output through a fully connected layer. It should be noted that the parameters in the deep learning model are learnable parameters, and the model parameters can be determined through training. When training, the data preprocessing introduced above also needs to be performed before inputting into the deep learning model for training, and the model parameters are adjusted through backpropagation. After training, it can be directly used for fault diagnosis of analog circuits.

[0071] TimesNet has a powerful extraction ability for processing time-series tasks, especially for periodic features, and can capture more potential features, achieving remarkable success in various time-series prediction tasks. However, directly applying TimesNet to the fault diagnosis of analog circuits does not yield ideal results.

[0072] Therefore, the present invention combines multi-scale convolution (MSC) and TimesNet to achieve fault diagnosis of analog circuits. The multi-dimensional time-series feature data after data preprocessing is fed into multi-scale convolution processing. By using convolution kernels of different sizes, feature information at different levels can be extracted, minimizing the differences caused by different receptive field sizes, making up for the limitation of traditional convolution algorithms that only use one receptive field, helping the neural network learn more robust feature representations, enhancing the network's modeling ability, and improving the feature extraction rate. In the present invention, multi-scale convolution is introduced because they have powerful spatial inductive biases and local feature extraction capabilities. By cleverly applying them to time-series tasks, combining the cross-dimensional extraction advantages of multi-scale convolution with the periodic feature extraction ability of TimesNet, through utilizing the inductive biases of multi-scale convolution and the powerful feature capture ability of TimesNet, the input data can be better processed, the model performance can be improved, and the risk of overfitting can be reduced, thereby improving the diagnostic accuracy. Experiments have proven that combining multi-scale convolution (MSC) and TimesNet is superior to using only TimesNet in the fault diagnosis effect of analog circuits.

[0073] As shown in Figure 4 FIG. 1 is a signal flow diagram of a multi-scale convolutional network in an embodiment of the present invention. As shown in Figure 5 FIG. 2 is a schematic structural diagram of a multi-scale convolutional network in an embodiment of the present invention. In one embodiment, the multi-scale convolutional network includes three parallel feature extraction channels and a splicing layer for splicing the features output by all channels; each channel includes three convolutional blocks connected in series, and each convolutional block includes a convolutional layer, a LeakyReLU layer, a Batchnorm (abbreviated as BN) layer, and a Drouput layer connected in sequence along the data flow direction. Among them, the LeakyReLU layer prevents neuron death by providing a small negative slope for negative inputs, retains more feature information, avoids gradient disappearance, thereby accelerating training and enhancing the non-linear expression ability of the network. The BN layer standardizes features of different scales, alleviates the difference in feature distribution, reduces internal covariate shift, thereby accelerating convergence, stabilizing training, and improving the generalization ability of the model. The Drouput layer randomly sets the outputs of some neurons to zero during the training process, thereby reducing the over-dependence of the neural network on specific neurons and improving the generalization ability of the model. To improve the training effect of the model and prevent overfitting during training. A Drouput layer with a parameter of 0.5 is added after each layer of CNN. In this embodiment, three channels are used for multi-level feature extraction, and finally the features passing through three different extraction channels are spliced to fuse the features, thereby enhancing the model's perception ability of different scale information, improving the model's representation and understanding ability of complex images, and further improving the performance of tasks such as classification, detection, and segmentation. Through the combination of convolutional kernels of different scales, features can be extracted from multiple levels, capturing richer details, thereby enhancing the expressiveness and generalization ability of the model.

[0074] Further, the three channels are the first to third channels, where: in the first channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 9×9, 7×7, and 5×5; in the second channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 7×7, 5×5, and 3×3; in the third channel, the convolutional kernel sizes of the three convolutional layers along the data flow direction are 9×9, 7×7, and 5×5. In this embodiment, larger convolutional kernels are used to capture low-frequency band features, helping to identify the overall trend and large-scale changes of the signal; medium-sized convolutional kernels are used to extract medium-frequency features, capturing frequency changes in the signal. Since the frequency change may become an important determination factor when the voltage signal fails, it can help to judge the fault type; smaller convolutional kernels are used to extract detailed features of high-frequency components. These details sometimes represent instantaneous fault changes or some minute electrical features, such as overload, instantaneous interference, etc. Therefore, by adopting the above convolutional kernel design, richer details can be better captured.

[0075] After being processed by the above multi-scale convolutional network, a preliminary understanding of multi-dimensional time series features can be achieved.

[0076] Such as Figure 6 Shown is a schematic structural diagram of the TimesNet model in an embodiment of the present invention. It has three TimesBlocks, and the three TimesBlocks perform residual connections. After extracting time series features through their respective steps in these parts, the obtained feature maps are converted into feature vectors by a pooling layer. Finally, the feature vectors are input into a fully connected layer, where the Softmax function is used to classify the soft faults of the analog circuit. In this embodiment, the design of the TimesNet model can prevent the problems of gradient disappearance or gradient explosion, thereby enhancing the extraction of periodic features and implicit features.

[0077] Finally, the output result of TimesNet is sent to the fully connected layer to obtain the output. In an embodiment, the output result of TimesNet first passes through a GeLU activation layer and a Drouput layer and then enters the fully connected layer to output the fault type of the circuit. GeLU is an activation function. Since the activation function is smooth in the non-linear range, it helps the gradient descent optimization algorithm to converge more easily. The Droupout layer randomly sets the outputs of some neurons to zero during the training process, thereby reducing the over-dependence of the neural network on specific neurons and improving the generalization ability of the model. The Linear layer is a fully connected layer.

[0078] Generally speaking, the present invention combines the preprocessing process of multi-wavelet reconstruction (MWR) and principal component analysis method (PCA) and the learning model combining multi-scale convolution and TimesNet. It only needs to analyze the single-point voltage output of the analog circuit to diagnose its soft faults, and the learning model used has a simple structure and low training difficulty. Therefore, the present invention can realize the application of deep neural network in the soft faults of analog circuits in a simpler way and ensure the diagnostic accuracy.

[0079] Embodiment 2

[0080] The present invention also relates to a soft fault diagnosis system for analog circuits based on a deep neural network, including:

[0081] A reconstruction unit for decomposing and reconstructing the voltage time series signal X1 output by the circuit using a multi-wavelet function to generate multiple reconstructed voltage time series signals and then forming a multi-dimensional time series feature X2;

[0082] A principal component analysis unit for performing feature screening on the multi-dimensional time series feature X2 using the principal component analysis method to obtain the reduced-dimensional time series feature X3;

[0083] An input unit for splicing feature X2 and feature X3 to obtain an input feature X4;

[0084] A fault identification unit for passing the feature X4 through a multi-scale convolutional network and a TimesNet model in sequence, and then outputting the fault type of the circuit through a fully connected layer.

[0085] Understandably, the above fault diagnosis system can be used to implement the fault diagnosis method in Embodiment 1. Each unit thereof can complete the corresponding steps in the method. For specific details, reference can be made to the above introduction and will not be elaborated herein.

[0086] Embodiment 3

[0087] The present invention further relates to an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above method are implemented.

[0088] The electronic device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The so-called processor can be a Central Processing Unit (CPU), or can also be other general-purpose processors, Digital Signal Processors (DSPs), Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory can be used to store computer programs and / or modules. The processor, by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory, realizes various functions of the electronic device.

[0089] Embodiment 4

[0090] The present invention further relates to a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0091] Specifically, the memory can include high-speed random access memory, and can also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0092] Embodiment 5

[0093] An embodiment of the present invention provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps of the method of the above embodiment of the present invention.

[0094] Hereinafter, the advantages of the present invention will be illustrated by specific examples.

[0095] Two common circuits are adopted as test circuits for specific implementation, namely, the Sallen-Key band-pass filter circuit shown in Figure 7 is used as test circuit 1 and the four-op-amp second-order high-pass filter circuit shown in Figure 8 is used as test circuit 2. The normal parameter values of the test circuits are marked in the figure. The tolerance ranges of resistors and capacitors in the circuit are set to 10%. All fault types existing in test circuit 1 and test circuit 2 are collected in the experiment, and 200 samples collected for each fault type are as evenly distributed as possible within the fault range interval to ensure the accuracy of the experiment.

[0096] The inputs of both test circuits adopt pulses with an amplitude of 2.5V, a width of 10us, and a period of 1ms as the excitation. An oscilloscope is used to collect the voltage waveform of one cycle at the output point. The test environment data is shown in Table 1 below. The experimental equipment includes an oscilloscope Tektronix TDS1012C-SC, a signal generator RIGOL-DG1022Z, and model training is carried out on a personal computer with a 2.5GHz processor and 8GB of RAM. The precision op-amp model adopted in the experimental circuit is OPA333AIDBVR. The MSC-TimesNet model and all training are completed in the pytorch environment.

[0097] Table 1

[0098] Parameter Configuration Oscilloscope Tektronix-TDS1012C-SC Signal Generator RIGOL-DG1022Z Operational Amplifier OPA333AIDBVR CPU Model AMD Ryzen 5 5500(3.60GHz) GPU Model NVIDIA GefForce GTX 1080(8GB) RAM 16G Operating System Windows 10 Language Python 3.9.0 IDE PyCharm 2023 Deep Learning Framework Pytorch 1.11.0 CUDA Version CUDA 11.3

[0099] When the circuit element parameters deviate from the normal values by 10% to 50%, it can be considered that a soft fault situation has occurred. The fault list of test circuit 1 is shown in Table 2 below, and the fault list of test circuit 2 is shown in Table 3 below. The fault types include all soft fault types of resistors and capacitors in the tested circuits. The table indicates the fault value interval range, the normal value range, and the classification label corresponding to each fault type under the test circuit. 200 samples are collected for each fault type, and an oscilloscope is used to collect voltage signal samples at the output point of the corresponding test circuit in the experiment. Then, the collected signals are processed by MWR-PCA and used as training samples.

[0100] Table 2

[0101]

[0102]

[0103] Table 3

[0104]

[0105]

[0106] For the division of the sample set, the hold-out method is adopted. 140 samples out of 200 samples of each fault type are used as the training set, and 60 samples are used as the test set. The divided samples are input into MSC-TimesNet for training and testing.

[0107] For the application of the proposed solution of the present invention (using the MSC-TimesNet model) in the field of soft fault classification of analog circuits, four of the most popular models in the time series field, namely Crossformer, Informer, MICN, and FEDformer, are carefully selected as the benchmark comparison methods for this solution, and extensive experiments are conducted on them. Additionally, in order to highlight the improvement effect on TimesNet, a comparison experiment of only using the TimesNet model (without adding multi-scale convolution) for fault diagnosis is added on two test circuits. Each of the above diagnostic methods is trained ten times to reduce the influence of the random splitting of the training set and the test set.

[0108] As Figure 9 shown is the confusion matrix of the results of soft fault diagnosis of Test Circuit 1 using the proposed solution of the present invention. As Figure 10 shown is the confusion matrix of the results of soft fault diagnosis of Test Circuit 2 using the proposed solution of the present invention. It can be seen from this that the accuracy of this solution for analog circuit fault diagnosis is relatively high.

[0109] Table 4 below shows the average values and variances of the accuracies of the method of the present invention and various comparison methods. It can be seen that, compared with models such as Crossformer, Informer, MICN, and FEDformer, when our MWR-PCA is combined with the MSC-TimesNet model, it performs excellently in the soft fault classification task of analog circuits, significantly improving the classification accuracy. This is mainly because of the unique advantages of the MWR-PCA method in feature representation and the superior performance of the MSC-TimesNet model in feature extraction and classification. The proposed data preprocessing method has a good effect on the extraction and feature mining of the characteristics between analog circuit fault signals. At the same time, the MSC-TimesNet model makes full use of the advantages of the multi-scale convolution structure to fully learn multi-dimensional time series features. Our model not only considers the internal relationship between the multi-dimensional features of soft faults, but also deeply studies the relationship between the periodic features of soft fault voltage signals. In both test circuits, the classification accuracy of this method is much higher than that of the other several methods.

[0110] Table 4

[0111]

[0112] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification. It should be noted that the "in one embodiment", "for example", "again for example", etc. of the present invention are intended to illustrate the present invention, rather than to limit the present invention.

[0113] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A method for soft fault diagnosis of analog circuits based on deep neural networks, characterized in that: include: The voltage time series signal X1 output by the circuit is decomposed and reconstructed using multiple wavelet functions, and multiple reconstructed voltage time series signals are generated to form a multi-dimensional time series feature X2; The principal component analysis method is used to screen the multidimensional time series feature X2 to obtain the time series feature X3 after dimensionality reduction; Concatenate feature X2 and feature X3 to obtain input feature X4; The feature X4 is passed through the multi-scale convolutional network and the TimesNet model in sequence, and then the fault type of the circuit is output through the fully connected layer.

2. The analog circuit soft fault diagnosis method according to claim 1, characterized in that: The multi-scale convolutional network includes three parallel feature extraction channels and a splicing layer for splicing features output by all channels; Each channel consists of three convolution blocks connected in series, and each convolution block includes a convolution layer, a LeakyReLU layer, a Batchnorm layer, and a Drouput layer connected sequentially along the data flow.

3. The analog circuit soft fault diagnosis method according to claim 2, characterized in that: The three channels are the first to third channels, where: In the first channel, the convolution kernel sizes of the three convolutional layers along the data flow are 9×9, 7×7, and 5×5; In the second channel, the convolution kernel sizes of the three convolutional layers along the data flow are 7×7, 5×5, and 3×3; In the third channel, the convolution kernel sizes of the three convolutional layers along the data flow are 9×9, 7×7, and 5×5.

4. The analog circuit soft fault diagnosis method according to claim 2 or 3, characterized in that: The Drouput layer uses a drop ratio of 0.

5.

5. The analog circuit soft fault diagnosis method according to claim 1, characterized in that: The TimesNet model has three TimesBlocks, and the three TimesBlocks are residually connected.

6. The analog circuit soft fault diagnosis method according to claim 1, characterized in that: The features output by the TimesNet model are passed through the GeLU activation layer and the Drouput layer in sequence and then enter the fully connected layer to output the fault type of the circuit.

7. An analog circuit soft fault diagnosis system based on deep neural network, characterized in that: include: A reconstruction unit, used to decompose and reconstruct the voltage time series signal X1 output by the circuit using multiple wavelet functions, and generate multiple reconstructed voltage time series signals to form a multi-dimensional time series feature X2; A principal component analysis unit is used to perform feature screening on the multidimensional time series feature X2 using the principal component analysis method to obtain the time series feature X3 after dimensionality reduction; An input unit, used to concatenate feature X2 and feature X3 to obtain input feature X4; The fault identification unit is used to make the feature X4 pass through the multi-scale convolutional network and the TimesNet model in sequence, and then output the fault type of the circuit through the fully connected layer.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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