Method for optical proximity correction, electronic device and storage medium

Abstract

The embodiment of the invention relates to a method for optical proximity correction, electronic equipment and a storage medium. The method comprises the following steps: determining a difference value between the size of a test pattern in a design layout and the measurement size of a photoetching pattern formed on a wafer by taking the design layout as a mask plate pattern; pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference value to form a pre-adjusted boundary; and performing optical proximity correction on the design layout by taking the pre-adjustment boundary as an initial boundary. According to the technical scheme provided by the invention, the time required for running the OPC program can be greatly shortened, and the condition of excessive correction or wrong correction direction can be prevented.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to integrated circuits, and more particularly, to methods, electronic devices, and storage media for optical proximity correction. Background Art

[0002] Computational lithography technology is an important driving force for the continuous development of graphic miniaturization technology since the 1990s. It aims to break through the hardware limitations of the minimum exposure size by improving software technologies such as resolution under the condition that the hardware environment of existing lithography machines and other equipment remains unchanged, thus greatly promoting the development of advanced semiconductor processes.

[0003] Optical proximity correction (OPC) is the core technology in computational lithography, and even usually refers to all computational lithography technologies by OPC. When specifically applying OPC technology to correct the chip design layout, the computing resources of thousands or even tens of thousands of CPU cores are often required (based on different technology nodes, more computing resources will be required for advanced technology nodes). Therefore, the algorithm optimization of the OPC correction program is a key to improving efficiency and reducing costs. During the operation of the OPC correction program, how to make the corresponding graphic segments be corrected in place more quickly is a key issue. In traditional solutions, especially at advanced process nodes, many loops are often required to be corrected in place, resulting in extremely long OPC correction times. Summary of the Invention

[0004] According to an exemplary embodiment of the present disclosure, a solution for optical proximity correction is provided to at least partially overcome the above or other potential defects.

[0005] According to one aspect of the present disclosure, a method for optical proximity correction is provided. The method includes: determining a difference between the size of a test pattern in a design layout and the measured size of a lithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout with the pre-adjusted boundary as a starting boundary. The technical solution of the present disclosure can greatly reduce the time required for the operation of the OPC correction program and can prevent overcorrection or incorrect correction direction from occurring.

[0006] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, which when executed by the processor cause the device to perform operations, the operations including: determining a difference between the size of a test pattern in a design layout and the measured size of a lithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout with the pre-adjusted boundary as the starting boundary. The technical solution of the present disclosure can greatly reduce the time required for the operation of the OPC correction program and can prevent overcorrection or incorrect correction direction from occurring.

[0007] In some embodiments, the test pattern includes at least one of the following: a one-dimensional pattern; and a line-end pattern in a two-dimensional pattern.

[0008] In some embodiments, pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary includes: determining the type of the test pattern based on the boundary properties of the test pattern; and moving the boundary of the test pattern accordingly based on the type of the test pattern.

[0009] In some embodiments, moving the boundary of the test pattern accordingly based on the type of the test pattern includes: in response to determining that the test pattern is a one-dimensional pattern, translating the boundary of the one-dimensional pattern by a first distance, where the first distance is less than or equal to a first difference, and the first difference is the average of the difference between the size of the one-dimensional pattern at a predetermined point on the boundary and the measured size at the corresponding point of the lithographic pattern on the wafer; and in response to determining that the test pattern is a line-end pattern, translating the boundary of the line-end pattern by a second distance, where the second distance is less than or equal to a second difference, and the second difference is the average of the difference between the size of the line-end pattern at a predetermined point on the boundary and the measured size at the corresponding point of the lithographic pattern on the wafer.

[0010] In some embodiments, in response to the difference being positive, translating the boundary of the test pattern in the design layout outward from the test pattern; and in response to the difference being negative, translating the boundary of the test pattern in the design layout inward toward the test pattern.

[0011] In some embodiments, pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary further includes: adjusting the boundary of the test pattern based on the spacing between the test patterns in the design layout and the widths of the test patterns.

[0012] In some embodiments, adjusting the boundaries of test patterns based on the spacing between the test patterns and the widths of the test patterns in the design layout includes: determining a corresponding adjustment value based on an adjustment table, wherein in the adjustment table, the spacing between the test patterns is divided into a first number of intervals, the widths of the test patterns are divided into a second predetermined number of intervals, and a corresponding adjustment value is set at a position corresponding to each interval of the first number and each interval of the second number; and pre-adjusting the boundaries of the test patterns based on the adjustment value.

[0013] In some embodiments, the determination of the difference does not consider the structures in the test patterns with dimensions smaller than the minimum design rule.

[0014] In some embodiments, the determination of the difference does not consider the structures in the test patterns with dimensions greater than a predetermined multiple of the minimum design rule.

[0015] In a third aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, it implements the method according to the first aspect of the present disclosure.

[0016] It will be understood from the following description that the technical solution of the present disclosure can greatly reduce the time required for the operation of the OPC correction program, and can prevent overcorrection or incorrect correction direction from occurring, significantly improving the OPC correction efficiency.

[0017] The Summary of the Invention is provided to introduce a selection of concepts in a simplified form, which will be further described in the Detailed Description below. The Summary of the Invention is not intended to identify the key features or main features of the present disclosure, nor is it intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram showing an exemplary environment in which embodiments of the present disclosure can be implemented; Figure 2 A flowchart showing a method for optical proximity correction according to some embodiments of the present disclosure; Figure 3 A schematic diagram showing a design layout and a corresponding simulation profile according to some embodiments of the present disclosure; Figure 4 A schematic diagram showing a corrected layout generated without using a pre-adjustment method; Figure 5 A schematic diagram showing a layout formed after pre-adjustment and subsequent OPC correction according to some embodiments of the present disclosure; Figure 6 A schematic diagram showing a plurality of patterns according to some embodiments of the present disclosure; Figure 7A block diagram of a computing device capable of implementing multiple embodiments of the present disclosure is shown.

[0019] In the various figures, the same or corresponding reference numerals denote the same or corresponding parts. Detailed implementation

[0020] The principles of the present disclosure will be described below with reference to various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only for enabling those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that, where feasible, similar or identical reference numerals may be used in the figures, and similar or identical reference numerals may represent similar or identical functions. Those skilled in the art will readily recognize that alternative embodiments of the structures and methods described herein may be employed without departing from the principles of the invention described herein.

[0021] As used herein, the term "comprising" and its variations mean open-ended inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0022] Currently, in the OPC correction (also known as calibration) process, the correction starts from the original (or adjusted target) layout. In advanced processes, in order to obtain a larger lithography process window, in many cases there is a large difference from the mask to the photoresist, that is, the mask and the lithography linewidth deviation (usually called printing bias, abbreviated as bias). And in advanced processes, the signal contrast is often poor, so to obtain the final correction result, more correction cycles are often required, which results in low efficiency. For example, in a certain case: the size of the photoresist on the final required wafer is 45 nm, while the size of the corresponding pattern on the mask needs to be 55 nm (the bias is 10 nm), but the correction starts from the 45 nm size. Due to the poor signal contrast, the edge of the pattern can only be moved little by little, and it may take more than 20 cycles to finally reach the 55 nm mask size, with very low efficiency.

[0023] In view of this, the present disclosure provides an improved solution. Specifically, embodiments of the present disclosure provide an improved method for optical proximity correction. The method includes: determining a difference between the size of a test pattern in a design layout and the measured size of a lithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as a starting boundary. By pre-adjusting the design layout, embodiments of the present disclosure can greatly reduce the time required for the OPC correction program to run and prevent over-correction or incorrect correction direction, significantly improving the correction efficiency.

[0024] Embodiments of the present disclosure will be specifically described below with reference to the accompanying drawings.

[0025] Figure 1 FIG. shows a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. As Figure 1 shown, the example environment 100 includes a computing device 110 and a client 120.

[0026] In some embodiments, the computing device 110 can interact with the client 120. For example, the computing device 110 can receive an input message from the client 120 and output a feedback message to the client 120. In some embodiments, the input message from the client 120 can be design layout data. The computing device 110 can perform corresponding mathematical operations on the design layout data and output the corresponding operation results to the client 120.

[0027] In some embodiments, the computing device 110 can include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant PDA, a media player, etc.), a consumer electronic product, a small computer, a large computer, cloud computing resources, etc.

[0028] It should be understood that describing the structure and function of the example environment 100 only for exemplary purposes is not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. This environment is merely illustrative and is not used to limit the application environment of the embodiments of the present disclosure.

[0029] To more clearly explain the principle of the solution of the present disclosure, the following will be described in more detail with reference to Figure 2 .

[0030] Figure 2 FIG. shows a flowchart of a method 200 for optical proximity correction according to some embodiments of the present disclosure.

[0031] At block 202, a difference between a dimension of a test pattern in a design layout and a measured dimension of a lithographic pattern formed on a wafer using the design layout as a mask layout is determined.

[0032] In some embodiments, the test pattern may include at least one of the following: a one-dimensional pattern; and an end-of-line pattern in a two-dimensional pattern. The one-dimensional pattern and the end-of-line pattern in the two-dimensional pattern are relatively simple patterns in the pattern, and are particularly suitable for applying the method of the embodiments of the present disclosure. It should be understood that the embodiments of the present disclosure are not limited thereto, but may be applied to other patterns according to actual needs.

[0033] In some embodiments, a difference between mask data (generally referring to dimension data) of the test pattern and corresponding wafer measurement data is checked. As described above, generally, the test pattern at least considers a one-dimensional pattern and an end-of-line pattern.

[0034] In some embodiments, when determining the difference, junction trenches in the test pattern with dimensions smaller than the minimum design rule are not considered. For example, for a one-dimensional pattern, all structures smaller than the minimum design rule may be removed (or excluded). The remaining test pattern data is used to calculate the bias. If the structures smaller than the minimum design rule are not removed but are calculated and pre-adjusted, it may be misleading and cause the final result after OPC correction to deviate from the target. By excluding all structures smaller than the minimum design rule, an accurate result can be ensured.

[0035] In the case of using a large printing bias process, the result obtained by subtracting the corresponding wafer measurement data from the mask data (mask dimension) at this time has consistency (all negative or all positive). The obtained results can be averaged. For example, this average value can be assumed to be B. Subsequently, the boundaries of the test pattern can be pre-adjusted based on the value B. This will be described in detail later.

[0036] In some embodiments, when determining the difference, structures with dimensions greater than a predetermined multiple (such as more than 4 times) of the minimum design rule are also not considered. For example, all structures exceeding 4 times the minimum design rule data may be removed. Because from an optical perspective, no matter how the energy is adjusted, the bias here generally changes little, and in OPC correction, larger patterns are not critical. It should be understood that the 4 times mentioned here is illustrative and can be adjusted according to actual process needs. For example, it can also be 3 times or other multiples. Compared with not removing structures exceeding a predetermined multiple (such as 4 times) of the minimum design rule data, the efficiency will be higher and the result will be more reliable after removal.

[0037] The line-end pattern is the simplest type in two-dimensional structures. For line-end patterns, all structures smaller than the minimum design rule can also be removed (corresponding to the one-dimensional patterns that generate the line ends). The deviation of the remaining data can be calculated, and after averaging, this value is assumed to be L. It should also be noted that for line-end patterns, there is no issue of removing structures that are a predetermined multiple of the minimum design rule data, because in the test patterns, the corresponding lines in the line-end patterns will not have structures that exceed a predetermined multiple of the minimum design rule, such as 4 times, because such structures need to be processed as one-dimensional patterns in OPC and cannot be processed as "line ends".

[0038] See below Figure 3 for further description. Figure 3 FIG. shows a schematic diagram of a design layout and a corresponding simulation profile according to some embodiments of the present disclosure. Figure 3 In (A) of FIG., the initial design layout 302 is shown,[[]] Figure 3 and in (B) of FIG., the initial design layout 302 and the corresponding simulation profile 304 are shown. As can be seen from Figure 3 (B) of FIG., due to the lack of OPC correction, the difference between the simulation profile and the initial design layout is relatively large. Figure 3 In (C) of FIG., the initial design layout 302 and the target simulation profile 306 are shown. It can be seen from this figure that the profiles or boundaries of the two are very close.

[0039] In Figure 3 (B) of FIG., P1, P2, P3, and P4 represent the positions for measuring the difference between the mask size (taking the design layout as the mask layout) and the measured size of the lithographic pattern. Among them, the positions of P1 and P2 represent the positions for measuring the difference of one-dimensional patterns, and P3 and P4 represent the positions for measuring the difference of line-end patterns. For one-dimensional patterns, the average value of the difference between the size at a predetermined point on the boundary of the one-dimensional pattern and the measured size at the corresponding point of the lithographic pattern on the wafer can be used as the said difference. For example, calculate Figure 3 the difference at the position of P1 and the difference at the position of P2 in (B) of FIG., and take the average value of the two as the difference. For line-end patterns, the average value of the difference between the size at a predetermined point on the boundary of the line-end pattern and the measured size at the corresponding point of the lithographic pattern on the wafer can be used as the said difference. For example, calculate Figure 3 the difference at the position of P3 and the difference at the position of P4 in (B) of FIG., and take the average value of the two as the difference. The average value can be a simple arithmetic mean. In some embodiments, according to actual needs, a weighted average can also be used.

[0040] It should be noted that when actually performing wafer measurement, not every point will be measured. For a one-dimensional pattern, usually only the most stable middle position is measured. For a line end, only the most prominent position is measured. Precise measurement results cannot be obtained near the corner, so it will not be measured. The data used for calculating the "deviation" in the embodiments is the difference between the mask size and the wafer measurement result. Therefore, only positions P1, P2, P3, and position P4 may have measurement results here.

[0041] Suppose there are multiple test patterns in the layout. In this case, taking the average can be done by taking the average for each pattern separately, that is, taking the average of the respective differences of the relevant positions (such as P1 and P2) on one pattern. It can also be done by adding up the deviations of the relevant positions of each pattern and then taking the average. Correspondingly, when performing pre-adjustment, different adjustment values can be moved for the boundaries of each pattern separately, that is, each pattern is adjusted individually. For example, one-dimensional pattern A may be moved by B / 2, and another one-dimensional pattern B may be moved by C / 2, etc., where B and C can be different values. Additionally, for the case of adding up the deviations of the relevant positions of each pattern and then taking the average, it can also be that the boundaries of all one-dimensional patterns are adjusted by the same distance. Both methods can achieve the desired purpose.

[0042] Figure 3 In the pattern shown in, it is overall a "two-dimensional pattern", but during processing, according to its corresponding boundary, it is treated as two parts: a one-dimensional pattern and a line end. As shown in (A) of 3, the part of the test pattern in the layout enclosed by the ellipse e1 represents a one-dimensional pattern, and the part of the test pattern enclosed by the ellipse e2 represents a line end pattern.

[0043] Refer to the following Figure 4 , Figure 4 shows a schematic diagram of the corrected layout directly generated without pre-adjustment. As in the design layout shown in Figure 4 , since there is no pre-adjustment, OPC correction needs to be performed starting from the boundary of the initial design layout 302 until the final corrected boundary 402 is formed. This requires going through relatively many cycles and has low efficiency.

[0044] Return to Figure 2 , at block 204, based on the boundary nature of the test pattern and the difference, pre-adjust the boundary of the test pattern in the design layout to form a pre-adjusted boundary.

[0045] In some embodiments, the type of the test pattern can be determined based on the boundary properties of the test pattern; and the boundary of the test pattern can be moved accordingly based on the type of the test pattern. As mentioned above, the types of the test pattern at least include one-dimensional patterns and line-end patterns. The boundary properties can be defined based on a conventional method. For example, the boundary properties can be defined according to the edge classification of the OPC correction program. Exemplarily, the edges can be classified into types such as line ends, corners, dense / isolated line edges, etc. The purpose of classifying the edges into different types is to correspond to the correction method according to the type. For example, for a line-end edge (LineEnd), its characteristic is the area at the end of the line, which is prone to imaging shortening or rounding due to diffraction effects. This definition process is the default in the OPC operation. After defining the boundary properties and after determining the signal sampling points, the layout boundary can be pre-adjusted. In some embodiments, for example, for a one-dimensional pattern, the boundary compensation is moved by B / 2, and for a line-end pattern, the compensation is moved by L / 2.

[0046] In some embodiments, moving the boundary of the test pattern accordingly based on the type of the test pattern may include: in the case where the test pattern is determined to be a one-dimensional pattern, translating the boundary of the one-dimensional pattern by a first distance, where the first distance is less than or equal to a first difference, and the first difference is the average value of the difference between the dimension of the one-dimensional pattern at a predetermined point on the boundary and the measured dimension at the corresponding point of the lithography pattern on the wafer. For example, if the difference is B, it can be moved by B / 2, as Figure 5 shown in (A) of. And in the case where the test pattern is determined to be a line-end pattern, translating the boundary of the line-end pattern by a second distance, where the second distance is less than or equal to a second difference, and the second difference is the average value of the difference between the dimension of the line-end pattern at a predetermined point on the boundary and the measured dimension at the corresponding point of the lithography pattern on the wafer. For example, if the difference is L, it can be moved by L / 2, as Figure 5 shown in (B) of. As mentioned above, the average value can be a simple arithmetic average. In some embodiments, according to actual needs, a weighted average can also be used.

[0047] In some embodiments, when the difference is positive, the boundary of the test pattern in the design layout is translated outward from the test pattern; and when the difference is negative, the boundary of the test pattern in the design layout is translated inward from the test pattern.

[0048] See Figure 5 , Figure 5 shows a schematic diagram of a layout formed after pre-adjustment and subsequent OPC correction according to some embodiments of the present disclosure. Figure 5 In (A) of, the pre-adjustment boundary 502 of the layout formed after pre-adjusting the initial design layout 302 is shown. As Figure 5As shown in (A) therein, where the two longitudinal boundaries of the initial design layout 302 are each moved outward by B / 2, and the boundaries at the top and bottom are moved outward by L / 2. It should be understood that, as shown in (A) and (B) of Figure 5 As shown in (A) and (B) of

[0049] Figure 5 (B) shows the mask layout formed after the initial design layout 302 is pre-adjusted and then subjected to OPC correction. The boundaries of the finally OPC-corrected pattern are indicated by 504. That is, through the solution of the embodiment of the present disclosure, first, the boundaries of the initial design layout are globally pre-adjusted, which can also be called "coarse adjustment". On this basis, "fine adjustment" is performed through OPC correction. The time spent in this coarse adjustment process is much lower than the time spent in adjusting the same distance in the traditional OPC correction process.

[0050] In addition, for the sake of clarity of concepts, a brief description of "design layout", "mask layout", and "wafer measurement data" is as follows: The design layout needs to go through a series of processes such as OPC before it can become a mask layout, and there are differences between the two. The design layout is the source of the mask layout, and the goal of the mask layout is to generate the structure of the design layout on the wafer. Specifically, after the OPC solution is established, the normal design layout needs to go through a series of processes such as OPC before it can become a mask layout. In the embodiments of the present disclosure, before the OPC solution is established, there is actually no benchmark. At this time, a mask can be published (generated), with a series of test patterns set on it, and then the lithography process is used to obtain the lithography pattern on the wafer, and then the corresponding results of the lithography pattern on the wafer are measured and compared with the test patterns. At this time, the "design layout" and the "mask layout" of the test pattern are the same.

[0051] In some embodiments, the boundaries of the test patterns can be adjusted based on the spacing between the test patterns and the widths of the test patterns in the design layout. This is further described below.

[0052] See Figure 6 , Figure 6 shows a schematic diagram of multiple patterns according to some embodiments of the present disclosure. As Figure 6 shown, each pattern 602 has a width W, and there is a spacing S between two adjacent patterns.

[0053] In some embodiments, according to actual needs, more detailed classification discussions can also be carried out for one-dimensional and two-dimensional graphics, and more complex but more specific data fitting the printing bias process can be designed. For example, more detailed classification pre-adjustments can be carried out during the pre-adjustment process. For the size of the compensation movement, it can also be adjusted according to the specific bias distribution (for example, adjusted from 1 / 2 to 2 / 3 or even larger).

[0054] In some embodiments, adjusting the boundaries of the test patterns based on the spacing between the test patterns and the widths of the test patterns in the design layout may include: determining corresponding adjustment values based on an adjustment table, where the spacing between the test patterns in the adjustment table is divided into a first number of intervals, the widths of the test patterns are divided into a second predetermined number of intervals, and corresponding adjustment values are set at the positions corresponding to each interval of the first number and each interval of the second number; the boundaries of the test patterns can be pre-adjusted based on the corresponding adjustment values.

[0055] The following is an example of a pre-adjustment table for one-dimensional graphics (which is already a relatively complex adjustment table at this time).

[0056] See the following table:

[0057] This table shows the spacing, width, and corresponding adjustment values of the graphics. Specifically, each row on the left side of the table shows the spacing (abbreviated as S in the table), for example, S<50 means the spacing is less than 50 nm. Each column on the right side of the table shows the width of the graphics (abbreviated as W in the table). For example, W<50 means the width is less than 50 nm.

[0058] The adjustment values are shown in the cells where each row intersects with each column. For example, the adjustment value in the cell where the row corresponding to S<50 intersects with the column corresponding to W<50 is 0, indicating that no adjustment is required. The adjustment value in the cell where the row corresponding to 100<=S intersects with the column corresponding to 100<=W is 40, indicating that the boundaries of the test patterns with the spacing and width falling into this interval need to be moved 40 nm. And so on for the rest.

[0059] In fact, the part with a value of 0 in the adjustment table refers to the structural part that is "less than the minimum design rule". Since it will not appear in the actual layout, the value taken here is not important and can be directly set to 0. By setting the above adjustment table, more precise adjustment of the test patterns can be achieved. It should be understood that the above adjustment table is illustrative, and the specific content and specific setting methods in the table can vary according to actual needs.

[0060] An example of a pre - adjustment table for a one - dimensional pattern is shown above. It should be understood that for line - end patterns, the pre - adjustment table can be set similarly, and details are not described here.

[0061] As mentioned before, under large - deviation processes, a larger correction amount is required (starting from the initial layout), and the correction amount required starting from the pre - adjusted layout is smaller. In advanced processes, the contrast of the model is smaller, so a larger correction amount requires more correction cycles to obtain, and the more correction cycles mean more correction time. It should be noted that the time for layout pre - adjustment is less than the time spent in one correction cycle.

[0062] In addition, it should be pointed out that the adjustment method here can completely follow the operations in the correction target adjustment module in the OPC process, except that the adjusted layout is not used as the correction target but as the correction starting point.

[0063] Back to Figure 2 , at block 206, optical proximity correction is performed on the design layout with the pre - adjusted boundary as the starting boundary.

[0064] In some embodiments, starting from a new starting point, that is, the pre - adjusted boundary, OPC correction is performed to finally obtain the required post - OPC corrected layout. The subsequent method for OPC correction can adopt general methods, which are not elaborated here.

[0065] Some embodiments of the present disclosure disclose a method for determining the initial layout adjustment by using the corresponding CD size on the mask and the wafer measurement results. The method is particularly applicable to advanced processes where the difference is greater than or equal to 10 nm, that is, large - deviation processes.

[0066] Some embodiments of the present disclosure provide a method for optical proximity correction. It should be noted that the examples given in the above embodiments are only for illustrating the solutions of the embodiments of the present disclosure and do not limit the solutions of the present disclosure.

[0067] The embodiments of the present disclosure can greatly reduce the time required for the OPC correction program to run by pre - adjusting the design layout, and can prevent over - correction or incorrect correction direction, significantly improving the correction efficiency and the correction accuracy.

[0068] It should be understood that the embodiments shown in the drawings are only for schematically showing the solutions of some embodiments of the present disclosure and do not limit the present disclosure. The embodiments of the present disclosure can also have various other forms.

[0069] Embodiments of the present disclosure also disclose an electronic device. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein, which when executed by the processor cause the device to perform operations, the operations including: determining a difference between the size of a test pattern in a design layout and the measured size of a lithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as a starting boundary.

[0070] Embodiments of the present disclosure also disclose a computer-readable storage medium having a computer program stored thereon, which when executed by a processor implements a method for optical proximity correction according to embodiments of the present disclosure.

[0071] Figure 7 FIG. shows a schematic block diagram of an electronic device according to some exemplary embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as, for example, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0072] As Figure 7 shown, the device 700 includes a CPU 701, which can perform various appropriate operations and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the device 700 can also be stored. The CPU 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0073] A plurality of components in the device 700 are connected to the I / O interface 705, and the plurality of components include: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disc, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0074] Each of the processes and treatments described above, such as method 200, can be executed by CPU 701. For example, in some embodiments, method 200 can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by CPU 701, one or more steps of method 200 described above can be executed.

[0075] The solution according to an embodiment of the present disclosure can be a method, apparatus, system, and / or computer program product. The computer program product can include a computer-readable storage medium having thereon computer-readable program instructions for performing various aspects of the present disclosure. The computer-readable storage medium can be a tangible device that can retain and store instructions used by an instruction execution device. The computer-readable program instructions can be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network.

[0076] The embodiments of the present disclosure have been described above. The above description is exemplary and only optional embodiments of the present disclosure, not exhaustive, and is not used to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features that are explicit or implicit in this disclosure or any generalization thereof, regardless of whether it relates to the same solution in any of the currently claimed rights. It should be understood that new claims can be formulated for these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0077] The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or enable other ordinary technicians in the technical field to understand the embodiments disclosed herein. For those skilled in the art, various changes and modifications can be made to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A method for optical proximity correction, comprising: Determine the difference between the size of the test pattern in the design layout and the measured size of the photolithography pattern formed on the wafer using the design layout as the mask layout, wherein the difference is determined without considering the structure in the test pattern whose size is smaller than the minimum design rule; pre-adjusting a boundary of the test pattern based on a boundary property of the test pattern and the difference value to form a pre-adjusted boundary; and An optical proximity correction is performed on the design layout using the pre-adjusted boundary as a starting boundary.

2. The method according to claim 1, wherein the test pattern comprises at least one of the following: One-dimensional graphics; and Line end graphics in two-dimensional graphics.

3. The method according to claim 1, wherein pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary comprises: determining a type of the test pattern based on a boundary property of the test pattern; as well as The boundary of the test pattern is moved accordingly based on the type of the test pattern.

4. The method according to claim 3, wherein moving the boundary of the test pattern accordingly based on the type of the test pattern comprises: In response to determining that the test pattern is a one-dimensional pattern, translating a boundary of the one-dimensional pattern by a first distance, wherein the first distance is less than or equal to a first difference value, the first difference value being an average value of differences between a dimension of the one-dimensional pattern at a predetermined point on the boundary and a measured dimension of a corresponding point of a lithographic pattern on a wafer; as well as In response to determining that the test pattern is a line end pattern, the boundary of the line end pattern is translated by a second distance, wherein the second distance is less than or equal to a second difference value, and the second difference value is an average value of the difference between the size of the line end pattern at a predetermined point on the boundary and the measured size at a corresponding point of the lithography pattern on the wafer.

5. The method according to claim 3, wherein: In response to the difference being positive, translating a boundary of the test pattern toward an outer side of the test pattern; as well as In response to the difference being negative, the boundary of the test pattern is translated toward the inside of the test pattern.

6. The method according to claim 1, wherein pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary further comprises: The boundaries of the test patterns are adjusted based on the spacing between the test patterns in the design layout and the width of the test patterns.

7. The method according to claim 6, wherein adjusting the boundary of the test pattern based on the spacing between the test patterns in the design layout and the width of each test pattern comprises: determining corresponding adjustment values ​​based on an adjustment table, wherein the spacing between the test patterns in the adjustment table is divided into a first number of intervals, the width of the test patterns is divided into a second predetermined number of intervals, and corresponding adjustment values ​​are set at positions corresponding to each interval in the first number of intervals and each interval in the second number of intervals; and The boundary of the test pattern is pre-adjusted based on the adjustment value.

8. The method according to any one of claims 1 to 7, wherein determining the difference does not take into account junction trenches in the test pattern whose size is smaller than a minimum design rule.

9. The method according to any one of claims 1 to 7, wherein the difference is determined without taking into account structures having a size greater than a predetermined multiple of a minimum design rule.

10. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions comprising: Determine the difference between the size of the test pattern in the design layout and the measured size of the photolithography pattern formed on the wafer using the design layout as the mask layout; Pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary; and An optical proximity correction is performed on the design layout using the pre-adjusted boundary as a starting boundary.

11. A computer-readable storage medium having machine-executable instructions stored thereon, and when the machine-executable instructions are executed by a processor, the processor is enabled to implement the method according to any one of claims 1 to 9.

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