Method, electronic device and storage medium for optical proximity correction

Abstract

Embodiments of the present disclosure relate to a method, electronic device, and storage medium for optical proximity correction (OPC). The method includes determining the difference between the dimensions of a test pattern in a design layout and the measured dimensions of a photolithographic pattern formed on a wafer using the design layout as a mask; pre-adjusting the boundaries of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as a starting boundary. The technical solution of the present disclosure can significantly reduce the time required to run an OPC correction program and prevent over-correction or correction in the wrong direction.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to integrated circuits, and more particularly, to methods, electronic devices, and storage media for optical proximity correction. Background Art

[0002] Computational lithography technology has been an important driving force for the continued development of graphic miniaturization technology since the 1990s. It aims to break through the hardware limitations of the minimum exposure size by improving software technologies such as resolution while keeping the hardware environment of existing lithography equipment unchanged, thereby greatly promoting the development of advanced semiconductor processes.

[0003] Optical proximity correction (OPC) is a core technology in computational lithography, and OPC is often used to refer to all computational lithography technologies. Applying OPC to modify chip design layouts often requires the computing resources of thousands or even tens of thousands of CPU cores (depending on the technology node, with advanced nodes requiring even more computing resources). Therefore, optimizing the OPC correction algorithm is key to improving efficiency and reducing costs. During the execution of the OPC correction program, a key issue is how to quickly correct the corresponding graphic segments. Traditional solutions, especially at advanced process nodes, often require numerous cycles to achieve the desired correction, resulting in extremely long OPC correction times. Summary of the Invention

[0004] According to example embodiments of the present disclosure, a scheme for optical proximity correction is provided to at least partially overcome the above or other potential drawbacks.

[0005] According to one aspect of the present disclosure, a method for optical proximity correction (OPC) is provided. The method includes: determining the difference between the dimensions of a test pattern in a design layout and the measured dimensions of a photolithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundaries of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as the starting boundary. The technical solution of the present disclosure can significantly reduce the time required to run an OPC correction program and prevent over-correction or correction in the wrong direction.

[0006] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform an action, the action comprising: determining the difference between the size of a test pattern in a design layout and the measured size of a photolithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as the starting boundary. The technical solution of the present disclosure can significantly reduce the time required to run an OPC correction program and can prevent over-correction or correction in the wrong direction.

[0007] In some embodiments, the test pattern includes at least one of the following: a one-dimensional pattern; and a line end pattern in a two-dimensional pattern.

[0008] In some embodiments, pre-adjusting the boundary of a test pattern in a design layout based on the boundary properties and the difference of the test pattern to form a pre-adjusted boundary includes: determining the type of the test pattern based on the boundary properties of the test pattern; and moving the boundary of the test pattern accordingly based on the type of the test pattern.

[0009] In some embodiments, moving the boundary of the test pattern accordingly based on the type of the test pattern includes: in response to determining that the test pattern is a one-dimensional pattern, translating the boundary of the one-dimensional pattern by a first distance, wherein the first distance is less than or equal to a first difference, and the first difference is an average value of the difference between the size of the one-dimensional pattern at a predetermined point on the boundary and the measured size at a corresponding point of the photolithography pattern on the wafer; and in response to determining that the test pattern is a line end pattern, translating the boundary of the line end pattern by a second distance, wherein the second distance is less than or equal to a second difference, and the second difference is an average value of the difference between the size of the line end pattern at a predetermined point on the boundary and the measured size at the corresponding point of the photolithography pattern on the wafer.

[0010] In some embodiments, in response to a positive difference, the boundary of the test pattern in the design layout is shifted toward the outside of the test pattern; and in response to a negative difference, the boundary of the test pattern in the design layout is shifted toward the inside of the test pattern.

[0011] In some embodiments, pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties and difference of the test pattern to form a pre-adjusted boundary also includes: adjusting the boundary of the test pattern based on the spacing between each test pattern in the design layout and the width of each test pattern.

[0012] In some embodiments, adjusting the boundaries of the test patterns based on the spacing between the test patterns and the width of the test patterns in the design layout includes: determining corresponding adjustment values based on an adjustment table, wherein in the adjustment table, the spacing between the test patterns is divided into a first number of intervals, and the width of each test pattern is divided into a second predetermined number of intervals, and corresponding adjustment values are set at positions corresponding to each first number of intervals and each second number of intervals; and pre-adjusting the boundaries of the test patterns based on the adjustment values.

[0013] In some embodiments, determining the difference value does not consider trenches in the test pattern that are smaller than the minimum design rule.

[0014] In some embodiments, determining the difference value does not consider structures in the test pattern whose size is larger than a predetermined multiple of the minimum design rule.

[0015] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0016] It will be understood from the following description that the technical solution of the present disclosure can greatly reduce the time required to run the OPC correction program, and can prevent over-correction or correction in the wrong direction, thereby significantly improving the OPC correction efficiency.

[0017] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram illustrating an example environment in which embodiments of the present disclosure can be implemented;

[0019] Figure 2 A flowchart illustrating a method for optical proximity correction according to some embodiments of the present disclosure is shown;

[0020] Figure 3 shows a design layout and a corresponding simulation outline schematic diagram according to some embodiments of the present disclosure;

[0021] Figure 4 A schematic diagram showing a corrected layout generated without pre-adjustment is shown;

[0022] Figure 5 A schematic diagram illustrating a layout formed after pre-conditioning and subsequent OPC correction according to some embodiments of the present disclosure is shown;

[0023] Figure 6A schematic diagram illustrating a plurality of graphs according to some embodiments of the present disclosure;

[0024] Figure 7 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown.

[0025] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0026] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals can be used in the figures where possible, and similar or identical reference numerals can represent similar or identical functions. Those skilled in the art will readily recognize, from the description below, that alternative embodiments of the structures and methods described herein can be adopted without departing from the principles of the present invention described herein.

[0027] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0028] Currently, in the OPC correction (also known as calibration) process, correction begins with the original (or adjusted target) layout. In advanced processes, to achieve a wider lithography process window, there is often a significant difference between the mask and the photoresist, known as the mask-to-resist linewidth deviation (commonly referred to as printing bias). Signal contrast in advanced processes is often poor, so achieving the final correction result often requires many correction cycles, resulting in low efficiency. For example, in one scenario, the desired photoresist size on the wafer is 45nm, while the corresponding pattern size on the mask needs to be 55nm (with a deviation of 10nm). However, the correction starts at 45nm. Due to the poor signal contrast, the pattern edge can only be moved incrementally, potentially requiring over 20 cycles to achieve the final 55nm mask size, which is very inefficient.

[0029] In view of this, the present disclosure provides an improved solution. Specifically, an embodiment of the present disclosure provides an improved method for optical proximity correction. The method includes: determining the difference between the size of a test pattern in a design layout and the measured size of a photolithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as the starting boundary. The embodiments of the present disclosure can greatly reduce the time required for the OPC correction program to run by pre-adjusting the design layout, and can prevent over-correction or correction in the wrong direction, thereby significantly improving the correction efficiency.

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 1 shows a schematic diagram of an example environment 100 in which embodiments according to the present disclosure can be implemented. Figure 1 As shown, the example environment 100 includes a computing device 110 and a client 120 .

[0032] In some embodiments, computing device 110 may interact with client 120. For example, computing device 110 may receive input messages from client 120 and output feedback messages to client 120. In some embodiments, the input messages from client 120 may be design layout data. Computing device 110 may perform corresponding mathematical operations on the design layout data and output the corresponding operation results to client 120.

[0033] In some embodiments, computing device 110 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0034] It should be understood that the structure and functionality of the example environment 100 is described for illustrative purposes only and is not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. This environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0035] In order to explain the principle of the present disclosure more clearly, the following will refer to Figure 2 Let's describe it in more detail.

[0036] Figure 2 A flow chart of a method 200 for optical proximity correction according to some embodiments of the present disclosure is shown.

[0037] At block 202 , a difference between a size of a test pattern in a design layout and a measured size of a lithographic pattern formed on a wafer using the design layout as a mask layout is determined.

[0038] In some embodiments, the test pattern may include at least one of the following: a one-dimensional pattern; and a line end pattern in a two-dimensional pattern. One-dimensional patterns and line end patterns in two-dimensional patterns are relatively simple patterns and are particularly suitable for applying the methods of the embodiments of the present disclosure. It should be understood that the embodiments of the present disclosure are not limited thereto and can be applied to other patterns as needed.

[0039] In some embodiments, the difference between the mask data (usually referring to the dimension data) of the test pattern and the corresponding wafer metrology data is checked. As mentioned above, generally speaking, the test pattern at least considers a one-dimensional pattern and a line end pattern.

[0040] In some embodiments, the difference calculation excludes trenches within the test pattern whose dimensions are smaller than the minimum design rule. For example, for a one-dimensional pattern, all structures smaller than the minimum design rule can be removed (or excluded). The remaining test pattern data is then used for bias calculation. Calculating and pre-adjusting structures smaller than the minimum design rule without removing them can be misleading, causing the final OPC-corrected result to deviate from the target. By excluding all structures smaller than the minimum design rule, accurate results are ensured.

[0041] In the case of a process with large printing bias, the mask data (mask dimensions) minus the corresponding wafer metrology data yields consistent results (either all negative or all positive). These results can be averaged, for example, assuming this average value is B. This value B can then be used to pre-adjust the test pattern boundaries. This is described in detail below.

[0042] In some embodiments, structures whose dimensions exceed a predetermined multiple (e.g., 4 times or more) of the minimum design rule are not considered when determining the difference. For example, all structures exceeding 4 times the minimum design rule data can be removed. This is because, from an optical perspective, the deviation here generally changes little regardless of energy adjustment, and larger features are not critical during OPC correction. It should be understood that the 4 times mentioned here is illustrative and can be adjusted based on actual process requirements, for example, 3 times or other multiples. Compared to not removing structures exceeding a predetermined multiple (e.g., 4 times) of the minimum design rule data, removing them will result in higher efficiency and more reliable results.

[0043] Line-end patterns are the simplest type of two-dimensional structure. For line-end patterns, all structures smaller than the minimum design rule (corresponding to the one-dimensional patterns that generate line ends) can be removed. The remaining data can be averaged and the deviation value assumed to be L. It should also be noted that for line-end patterns, structures that exceed the minimum design rule data multiples are not removed. This is because in the test pattern, the corresponding lines in the line-end pattern will not exceed the minimum design rule multiples, such as 4 times. Such structures are treated as one-dimensional patterns in OPC and cannot be treated as "line ends."

[0044] See below Figure 3 Further description. Figure 3 Schematic diagrams of design layouts and corresponding simulation outlines according to some embodiments of the present disclosure are shown. Figure 3 (A) shows the initial design layout 302, Figure 3 (B) in FIG. 3 shows the initial design layout 302 and the corresponding simulation outline 304. Figure 3 As can be seen in (B), due to the lack of OPC correction, the difference between the simulation outline and the initial design layout is quite large. Figure 3 (C) in FIG. 3 shows the initial design layout 302 and the target simulation outline 306 . As can be seen from the figure, the outlines or boundaries of the two are very close.

[0045] exist Figure 3 In (B), P1, P2, P3, and P4 represent the positions for measuring the difference between the mask size (using the design layout as the mask layout) and the measured size of the lithography pattern, where P1 and P2 represent the positions for measuring the difference of the one-dimensional pattern, and P3 and P4 represent the positions for measuring the difference of the line end pattern. For a one-dimensional pattern, the average value of the difference between the size of the one-dimensional pattern at a predetermined point on the boundary and the measured size of the lithography pattern at the corresponding point on the wafer can be used as the difference. For example, calculate Figure 3 The difference at position P1 and the difference at position P2 in (B) are calculated, and the average value of the two is used as the difference value. For line end graphics, the average value of the difference between the size of the line end graphics at a predetermined point on the boundary and the measured size at the corresponding point of the photolithographic pattern on the wafer can be used as the difference value. For example, Figure 3 The difference at position P3 and the difference at position P4 in (B) are averaged as the difference. The average can be a simple arithmetic average. In some embodiments, a weighted average can also be used according to actual needs.

[0046] It's important to note that during actual wafer metrology, not every point is measured. For a one-dimensional pattern, only the most stable center position is typically measured. For line ends, only the most prominent position is measured. Accurate measurements cannot be obtained near corners, so they are not measured. The "deviation" calculation in this embodiment uses the difference between the mask size and the wafer metrology result, so the only possible measurement results here are for positions P1, P2, P3, and P4.

[0047] Suppose there are multiple test patterns in a layout. In this case, averaging can be performed for each pattern individually, averaging the differences between relevant positions on a pattern (such as P1 and P2). Alternatively, the deviations at the relevant positions of each pattern can be added together to form the average. Accordingly, during pre-adjustment, the boundaries of each pattern can be moved by different adjustment values, meaning each pattern is adjusted individually. For example, one-dimensional pattern A might be moved by B / 2, another one-dimensional pattern B by C / 2, and so on, where B and C can be different values. Alternatively, when averaging the deviations at the relevant positions of each pattern, the boundaries of all one-dimensional patterns can be adjusted by the same distance. Both approaches can achieve the desired goal.

[0048] Figure 3 The pattern shown in the figure is a two-dimensional figure as a whole, but is processed as a one-dimensional figure and a line end figure based on its corresponding boundaries. As shown in 3 (A), the portion of the test pattern in the layout enclosed by ellipse e1 represents the one-dimensional figure, and the portion of the test pattern enclosed by ellipse e2 represents the line end figure.

[0049] See below Figure 4 , Figure 4 Figure 2 shows a schematic diagram of a modified layout generated directly without pre-adjustment. Figure 4 The design layout shown has not been pre-adjusted, so OPC correction needs to be performed starting from the boundary of the initial design layout 302 until the final corrected boundary 402 is formed. This requires many cycles and is inefficient.

[0050] Back to Figure 2 At block 204 , the boundary of the test pattern in the design layout is pre-adjusted based on the boundary properties of the test pattern and the difference value to form a pre-adjusted boundary.

[0051] In some embodiments, the type of test pattern can be determined based on the boundary properties of the test pattern, and the boundaries of the test pattern can be moved accordingly based on the type of test pattern. As previously mentioned, the types of test patterns include at least one-dimensional patterns and line end patterns. The boundary properties can be defined using conventional methods, for example, based on the edge classification of the OPC correction program. For example, edges can be classified into types such as line ends, corners, and dense / isolated line edges. The purpose of classifying edges into different types is to adapt the correction method to the type. For example, a line end edge (LineEnd) is characterized by the end area of a line, which is prone to imaging shortening or rounding due to diffraction effects. This definition process is the default in OPC operations. After defining the boundary properties and determining the signal sampling points, the layout boundaries can be pre-adjusted. In some embodiments, for example, the one-dimensional pattern boundary compensation is shifted by B / 2, and the line end pattern compensation is shifted by L / 2.

[0052] In some embodiments, moving the boundary of the test pattern accordingly based on the type of the test pattern may include: when determining that the test pattern is a one-dimensional pattern, translating the boundary of the one-dimensional pattern by a first distance, wherein the first distance is less than or equal to a first difference value, and the first difference value is an average value of the difference between a dimension of the one-dimensional pattern at a predetermined point on the boundary and a measured dimension of a corresponding point of the photolithographic pattern on the wafer, for example, if the difference value is B, the boundary of the test pattern may be moved by B / 2, such as Figure 5 As shown in (A); and when the test pattern is determined to be a line end pattern, the boundary of the line end pattern is translated by a second distance, wherein the second distance is less than or equal to a second difference value, and the second difference value is an average value of the difference between the size of the line end pattern at a predetermined point on the boundary and the measured size at a corresponding point of the photolithographic pattern on the wafer. For example, if the difference value is L, it can be moved by L / 2, as shown in FIG. Figure 5 As shown in (B) of FIG. As mentioned above, the average value can be a simple arithmetic average. In some embodiments, according to actual needs, a weighted average can also be used.

[0053] In some embodiments, when the difference is positive, the boundary of the test pattern in the design layout is translated toward the outside of the test pattern; and when the difference is negative, the boundary of the test pattern in the design layout is translated toward the inside of the test pattern.

[0054] See also Figure 5 , Figure 5 A schematic diagram illustrating a layout formed after pre-conditioning and subsequent OPC correction according to some embodiments of the present disclosure is shown. Figure 5 (A) in FIG. 3 shows the pre-adjusted boundary 502 of the layout formed after the initial design layout 302 is pre-adjusted. Figure 5As shown in (A), the two vertical boundaries of the initial design layout 302 are moved outward by B / 2, and the top and bottom boundaries are moved outward by L / 2. Figure 5 As shown in (A) and (B), the initial design layout 302 corresponds to a test pattern, or in other words, the initial design layout 302 shown in the figure is a design layout of a test pattern, and the boundary of the initial design layout 302 is the boundary of the test pattern.

[0055] Figure 5 (B) in the figure shows the mask layout resulting from pre-adjustment of the initial design layout 302 and subsequent OPC correction. The boundary of the final pattern after OPC correction is indicated by 504. Specifically, through the solution of the disclosed embodiment, the boundaries of the initial design layout are first pre-adjusted as a whole, which can also be called "rough adjustment." On this basis, "fine adjustment" is performed through OPC correction. This coarse adjustment process takes much less time than adjusting the same distance during traditional OPC correction.

[0056] In addition, for the sake of conceptual clarity, the following explanation is given for "design layout", "mask layout" and "wafer measurement data": the design layout must undergo a series of processes such as OPC before it can become a mask layout, and there is a difference between the two. The design layout is the source of the mask layout, and the goal of the mask layout is to produce the structure of the design layout on the wafer. Specifically, after the OPC solution is established, the normal design layout must undergo a series of processes such as OPC before it can become a mask layout. In the embodiment of the present disclosure, before the OPC solution is established, there is actually no benchmark. At this time, a mask can be published (generated) with a series of test patterns set on it, and then the photolithography process is used to obtain the photolithography pattern on the wafer, and then the corresponding results of the photolithography pattern on the wafer are measured to compare with the test pattern. At this time, the "design layout" of the test pattern is the same as the "mask layout".

[0057] In some embodiments, the test pattern boundaries may be adjusted based on the spacing between test patterns and the width of each test pattern in the design layout, as further described below.

[0058] See also Figure 6 , Figure 6 Schematic diagrams of multiple graphs according to some embodiments of the present disclosure are shown. Figure 6 As shown, each graphic 602 has a width W, and there is a space S between two adjacent graphics.

[0059] In some embodiments, depending on actual needs, a more detailed classification and discussion can be conducted for one-dimensional and two-dimensional graphics to design more complex data that better matches the specific printing bias process. For example, a more detailed classification and pre-adjustment can be performed during the pre-adjustment process. The compensation shift size can also be adjusted based on the specific bias distribution (for example, from 1 / 2 to 2 / 3 or even larger).

[0060] In some embodiments, adjusting the boundaries of the test patterns based on the spacing between the test patterns in the design layout and the width of the test patterns may include: determining corresponding adjustment values based on an adjustment table, wherein the spacing between the test patterns in the adjustment table is divided into a first number of intervals, and the width of each test pattern is divided into a second predetermined number of intervals, and corresponding adjustment values are set at positions corresponding to each first number of intervals and each second number of intervals; the boundaries of the test patterns may be pre-adjusted based on the corresponding adjustment values.

[0061] The following is an example of a pre-adjustment table for a one-dimensional graph (this is already a relatively complex adjustment table).

[0062] See the table below:

[0063]

[0064] This table shows the spacing and width of the patterns, along with their corresponding adjustment values. Specifically, the left-hand rows show the spacing (abbreviated as S). For example, S < 50 indicates a spacing less than 50 nm. The right-hand columns show the width (abbreviated as W). For example, W < 50 indicates a width less than 50 nm.

[0065] The grids at the intersection of each row and column show the adjustment value. For example, the grid where S < 50 and W < 50 has an adjustment value of 0, indicating no adjustment is required. The grid where 100 <= S and 100 <= W has an adjustment value of 40, indicating that the test pattern boundary with spacing and width falling within this range needs to be moved 40 nm. The same applies to the rest of the grids.

[0066] In practice, the values ​​set to 0 in the adjustment table refer to the structural parts "less than the minimum design rule." Since they will not appear in the actual layout, the value here is not important and can be set directly to 0. By setting up this adjustment table, the test pattern can be adjusted more precisely. It should be understood that the above adjustment table is illustrative only, and the specific contents and settings in the table can be varied according to actual needs.

[0067] The above shows an example of a pre-adjustment table for a one-dimensional graphic. It should be understood that a pre-adjustment table can be similarly set for a line end graphic, which will not be described in detail here.

[0068] As mentioned earlier, processes with high deviations require larger corrections (starting from the initial layout), while those starting from a pre-conditioned layout require smaller corrections. In advanced processes, the model contrast is lower, so larger corrections require more correction cycles to achieve. More correction cycles mean more correction time. It's important to note that the time required to pre-condition the layout is less than the time required for a single correction cycle.

[0069] In addition, it should be pointed out that the adjustment method here can completely follow the operations in the correction target adjustment module in the OPC process, except that the adjusted layout is not used as the correction target, but as the correction starting point.

[0070] Back to Figure 2 At block 206 , optical proximity correction is performed on the design layout using the pre-adjusted boundary as a starting boundary.

[0071] In some embodiments, OPC correction is performed from a new starting point, ie, the pre-adjusted boundary, to ultimately obtain the desired post-OPC correction layout. The subsequent OPC correction method can adopt a common method and will not be described in detail here.

[0072] In some embodiments of the present disclosure, a method for determining initial layout adjustments using the corresponding CD size on the mask and wafer measurement results is disclosed. The method is particularly suitable for advanced processes where the difference is greater than or equal to 10nm, i.e., large deviation processes.

[0073] Some embodiments of the present disclosure provide methods for optical proximity correction. It should be noted that the examples given in the above embodiments are only for illustrating the solutions of the embodiments of the present disclosure and are not intended to limit the solutions of the present disclosure.

[0074] The embodiments of the present disclosure can greatly reduce the time required to run the OPC correction program by pre-adjusting the design layout, and can prevent over-correction or correction in the wrong direction, thereby significantly improving correction efficiency and accuracy.

[0075] It should be understood that the embodiments shown in the drawings are only for schematically illustrating some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0076] The present disclosure also discloses an electronic device, comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, including: determining a difference between a size of a test pattern in a design layout and a measured size of a photolithographic pattern formed on a wafer using the design layout as a mask layout; pre-adjusting a boundary of the test pattern in the design layout based on boundary properties of the test pattern and the difference to form a pre-adjusted boundary; and performing optical proximity correction on the design layout using the pre-adjusted boundary as a starting boundary.

[0077] An embodiment of the present disclosure further discloses a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for optical proximity correction according to the embodiment of the present disclosure is implemented.

[0078] Figure 7 Schematic block diagrams of electronic devices according to some exemplary embodiments of the present disclosure are shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0079] like Figure 7 As shown, device 700 includes a CPU 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. Various programs and data required for the operation of device 700 may also be stored in RAM 703. CPU 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to bus 704.

[0080] Multiple components in device 700 are connected to I / O interface 705, including an input unit 706, such as a keyboard, mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, optical disk, etc.; and a communication unit 709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0081] The various processes and processing described above, such as method 200, can be executed by CPU 701. For example, in some embodiments, method 200 can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by CPU 701, one or more steps in method 200 described above can be performed.

[0082] The solutions according to the embodiments of the present disclosure may be methods, devices, systems, and / or computer program products. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network.

[0083] Various embodiments of the present disclosure have been described above. The above descriptions are exemplary and are only optional embodiments of the present disclosure. They are not exhaustive and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features disclosed herein, whether explicitly or implicitly or in any generalization thereof, regardless of whether it relates to the same scheme in any claim currently claimed. It should be understood that new claims may be formulated to these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0084] The terminology used herein is selected to best explain the principles of the various embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the various embodiments disclosed herein. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure are intended to be included within the scope of protection of this disclosure.

Claims

1. A method for optical proximity correction, comprising: Determining a difference between a size of a test pattern in a design layout and a measured size of a photolithographic pattern formed on a wafer using the design layout as a mask layout, wherein the difference is determined without considering structures in the test pattern that are smaller than a minimum design rule; Pre-adjusting the boundary of the test pattern based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary, specifically comprising: determining a type of the test pattern based on the boundary property of the test pattern, and moving the boundary of the test pattern accordingly based on the type of the test pattern; as well as Optical proximity correction is performed on the design layout using the pre-adjusted boundary as a starting boundary.

2. The method according to claim 1, wherein the test pattern comprises at least one of the following: One-dimensional graphics; and Line end graphics in two-dimensional graphics.

3. The method according to claim 1 , wherein moving the boundary of the test pattern accordingly based on the type of the test pattern comprises: In response to determining that the test pattern is a one-dimensional pattern, translating a boundary of the one-dimensional pattern by a first distance, wherein the first distance is less than or equal to a first difference value, the first difference value being an average of differences between a dimension of the one-dimensional pattern at a predetermined point on the boundary and a measured dimension of a corresponding point of a photolithographic pattern on a wafer; as well as In response to determining that the test pattern is a line end pattern, the boundary of the line end pattern is translated by a second distance, wherein the second distance is less than or equal to a second difference value, the second difference value being an average of differences between a dimension of the line end pattern at a predetermined point on the boundary and a measured dimension of a corresponding point of a photolithographic pattern on a wafer.

4. The method according to claim 1, wherein: In response to the difference being positive, shifting the boundary of the test pattern toward an outer side of the test pattern; as well as In response to the difference being negative, the boundary of the test pattern is translated toward the inside of the test pattern.

5. The method according to claim 1 , wherein pre-adjusting the boundary of the test pattern in the design layout based on the boundary property of the test pattern and the difference to form a pre-adjusted boundary further comprises: The boundaries of the test patterns are adjusted based on the spacing between the test patterns and the width of the test patterns in the design layout.

6. The method according to claim 5, wherein adjusting the boundaries of the test patterns based on the spacing between the test patterns and the width of the test patterns in the design layout comprises: determining corresponding adjustment values based on an adjustment table, wherein the spacing between test patterns in the adjustment table is divided into a first number of intervals, the width of each test pattern is divided into a second predetermined number of intervals, and a corresponding adjustment value is set at a position corresponding to each interval in the first number of intervals and each interval in the second number of intervals; and The boundary of the test pattern is pre-adjusted based on the adjustment value. 7 . The method according to claim 1 , wherein the difference is determined without taking into account structures having a size greater than a predetermined multiple of a minimum design rule.

8. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions comprising: Determining a difference between a size of a test pattern in a design layout and a measured size of a photolithographic pattern formed on a wafer using the design layout as a mask layout, wherein the difference is determined without considering structures in the test pattern that are smaller than a minimum design rule; Pre-adjusting the boundary of the test pattern in the design layout based on the boundary properties of the test pattern and the difference to form a pre-adjusted boundary, specifically comprising: determining a type of the test pattern based on the boundary properties of the test pattern, and moving the boundary of the test pattern accordingly based on the type of the test pattern; and Optical proximity correction is performed on the design layout using the pre-adjusted boundary as a starting boundary.

9. A computer-readable storage medium having machine-executable instructions stored thereon, wherein when the machine-executable instructions are executed by a processor, the processor is caused to implement the method according to any one of claims 1 to 7.

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