Power consumption control method and device of power distribution network monitoring control chip and storage medium

Abstract

The invention discloses a power consumption control method and device for a power distribution network monitoring control chip and a storage medium, and the method comprises the steps: carrying out the clock domain division of the power distribution network monitoring control chip, and obtaining a target clock domain; obtaining current load data and historical load data of the target clock domain; according to the historical load data, trend prediction processing is carried out by using an autoregressive moving average model to obtain predicted load data; according to the predicted load data and the power consumption state of the control chip, performing action evaluation processing by using preset reinforcement learning to obtain a state action function value; calculating a to-be-adjusted clock frequency and a to-be-adjusted voltage according to the current load data; determining a predicted clock frequency and a predicted voltage according to the state action function value; and performing power consumption control on the target clock domain according to the target clock frequency and the target voltage to obtain a power consumption control result. The power consumption control is realized, and the resource utilization rate and the control efficiency are improved. The method can be widely applied to the technical field of electric power engineering.

Description

Technical Field

[0001] The present invention relates to the technical field of power engineering, and particularly to a power consumption control method, device and storage medium for a distribution network monitoring and control chip. Background Art

[0002] Distribution network monitoring and control chips are increasingly widely used in smart grids and are continuously developing towards high performance and low power. Traditional power consumption control methods set a fixed clock frequency or voltage for the chip, but the system load changes dynamically, resulting in waste of chip performance or high power consumption, low resource utilization, and low control efficiency under different load conditions.

[0003] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0004] Embodiments of the present invention provide a power consumption control method, device and storage medium for a distribution network monitoring and control chip, effectively improving resource utilization and control efficiency.

[0005] On the one hand, embodiments of the present invention provide a power consumption control method for a distribution network monitoring and control chip, including the following steps:

[0006] Perform clock domain partitioning processing on the distribution network monitoring and control chip to obtain a target clock domain;

[0007] Obtain the current load data and historical load data of the target clock domain;

[0008] According to the historical load data, perform trend prediction processing using an autoregressive moving average model to obtain predicted load data;

[0009] According to the predicted load data and the power consumption state of the control chip, perform action evaluation processing using a preset reinforcement learning to obtain a state-action function value;

[0010] According to the current load data, calculate the clock frequency to be adjusted and the voltage to be adjusted;

[0011] According to the state-action function value, determine the predicted clock frequency and predicted voltage;

[0012] According to the target clock frequency and target voltage, perform power consumption control on the target clock domain to obtain a power consumption control result, where the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

[0013] In some embodiments, the performing clock domain partitioning processing on the distribution network monitoring and control chip to obtain a target clock domain includes:

[0014] Partition the power distribution network monitoring and control chip to obtain multiple clock domains;

[0015] Select one clock domain from the multiple clock domains as the target clock domain.

[0016] In some embodiments, the trend prediction process using the autoregressive moving average model based on the historical load data to obtain the predicted load data includes:

[0017] Denoise the historical load data to obtain denoised data;

[0018] Normalize the denoised data to obtain normalized data;

[0019] Perform time series segmentation on the normalized data to obtain segmented data;

[0020] Use the autoregressive moving average model to predict the segmented data to obtain the predicted load data.

[0021] In some embodiments, the action evaluation process using the preset reinforcement learning based on the predicted load data and the power consumption state of the control chip to obtain the state-action function value includes:

[0022] Initialize the reinforcement learning state according to the predicted load data and the power consumption state of the control chip;

[0023] Select an action from the action space as the target action, where the action space includes several combinations of clock frequencies and voltages;

[0024] Perform system simulation adjustment according to the target action to obtain feedback data, where the feedback data includes the power consumption reduction value, task completion rate or response time;

[0025] Calculate the state-action function value using the Bellman equation according to the feedback data, reward value, learning rate and discount factor;

[0026] Update the reinforcement learning state according to the state-action function value until the state-action function value meets the preset requirements.

[0027] In some embodiments, the calculation of the clock frequency to be adjusted and the voltage to be adjusted according to the current load data includes:

[0028] Calculate the clock frequency to be adjusted according to the current load data and the preset load threshold;

[0029] Calculate the voltage to be adjusted according to the clock frequency to be adjusted.

[0030] In some embodiments, the method further includes:

[0031] Perform stability detection on the power consumption control result to obtain a stability detection result;

[0032] If the stability detection result indicates that the system is unstable, perform a fallback adjustment process using the fallback strategy based on the clock frequency and voltage at the previous moment.

[0033] In some embodiments, the method further includes:

[0034] Perform adjustment frequency detection on the power consumption control result to obtain an adjustment frequency detection result;

[0035] If the adjustment frequency detection result indicates frequent adjustment, classify the computing tasks to obtain critical tasks and non-critical tasks;

[0036] Assign priorities to the critical tasks and the non-critical tasks to obtain corresponding target priorities, where the target priorities include high priority, medium priority, and low priority;

[0037] Adjust the thread execution order according to the target priorities and the inter-thread dependency relationship, so that high-priority tasks are processed first.

[0038] On the other hand, an embodiment of the present invention provides a power consumption control device for a distribution network monitoring and control chip, including:

[0039] A first module for performing clock domain partitioning processing on the distribution network monitoring and control chip to obtain a target clock domain;

[0040] A second module for obtaining the current load data and historical load data of the target clock domain;

[0041] A third module for performing trend prediction processing using an autoregressive moving average model based on the historical load data to obtain predicted load data;

[0042] A fourth module for performing action evaluation processing using a preset reinforcement learning based on the predicted load data and the power consumption state of the control chip to obtain a state-action function value;

[0043] A fifth module for calculating the clock frequency and voltage to be adjusted based on the current load data;

[0044] A sixth module for determining the predicted clock frequency and predicted voltage based on the state-action function value;

[0045] A seventh module, configured to perform power consumption control on the target clock domain according to a target clock frequency and a target voltage, so as to obtain a power consumption control result, where the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

[0046] On the other hand, an embodiment of the present invention provides a computer device, including:

[0047] At least one processor;

[0048] At least one memory, configured to store at least one program;

[0049] When the at least one program is executed by the at least one processor, the at least one processor implements the method described above.

[0050] On the other hand, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0051] The beneficial effects of the present invention are as follows:

[0052] In the embodiment of the present invention, first, clock domain division processing is performed on a power distribution network monitoring and control chip to obtain a target clock domain, and current load data and historical load data of the target clock domain are acquired. Then, according to the historical load data, trend prediction processing is performed using an autoregressive moving average model to obtain predicted load data. And according to the predicted load data and the power consumption state of the control chip, action evaluation processing is performed using a preset reinforcement learning to obtain state-action function values. Then, according to the current load data, the clock frequency to be adjusted and the voltage to be adjusted are calculated. According to the state-action function values, the predicted clock frequency and the predicted voltage are determined. Finally, power consumption control is performed on the target clock domain according to the target clock frequency and the target voltage to obtain a power consumption control result. Thus, power consumption control can be achieved by adjusting different clock frequencies and voltages, thereby improving resource utilization and control efficiency.

[0053] Other features and advantages of the present invention will be described in the following description, and, in part, will be obvious from the description, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the description and the drawings. Description of the Drawings

[0054] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0055] Figure 1 It is a flowchart of a power consumption control method for a power distribution network monitoring and control chip according to an embodiment of the present invention;

[0056] Figure 2 It is a schematic diagram of a multi-level clock domain division and independent adjustment process according to an embodiment of the present invention;

[0057] Figure 3 It is a schematic diagram of an adaptive power consumption scheduling process according to an embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of a dynamic clock adjustment process according to an embodiment of the present invention;

[0059] Figure 5 It is a schematic diagram of a software and hardware collaborative optimization process according to an embodiment of the present invention;

[0060] Figure 6 It is a schematic diagram of the structure of a power consumption control device for a power distribution network monitoring and control chip according to an embodiment of the present invention;

[0061] Figure 7 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0062] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description involves the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0063] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0064] The terms "at least one", "a plurality of", "each", "any one", etc. used in this application, at least one includes one, two or more than two, a plurality of includes two or more than two, each refers to each one of the corresponding plurality, and any one refers to any one of the plurality.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0066] Before elaborating on the embodiments of this application in detail, some of the nouns and terms involved in the embodiments of this application are first explained, and the nouns and terms involved in the embodiments of this application are applicable to the following explanations.

[0067] Autoregressive Moving Average (ARMA): A statistical model commonly used in time series analysis.

[0068] Q-learning reinforcement learning: A model-free algorithm based on reinforcement learning, aiming to learn the optimal policy through interaction with the environment.

[0069] Power Management Unit (PMU): A component in an integrated circuit used to manage the system power supply, responsible for controlling the power distribution and regulation of the chip to ensure the stability and efficiency of the power supply.

[0070] Dynamic Voltage and Frequency Scaling (DVFS): A technology used to adjust the power consumption of a chip, which dynamically adjusts the voltage and clock frequency of the processor according to the load conditions, so as to optimize the energy efficiency while ensuring performance.

[0071] Clock Frequency: Refers to the oscillation frequency of the internal clock signal of a computer or electronic device, usually expressed in Hertz (Hz). The clock frequency determines the speed at which the system executes operations. The higher the frequency, the more operations the processor can execute per second, thereby improving the overall performance of the system.

[0072] In the related art, distribution network monitoring and control chips are increasingly widely used in smart grids. With the development of technology, the functions of the chips are gradually evolving towards high performance and low power consumption. Existing distribution network monitoring and control chips have certain limitations in low-power control, mainly reflected in insufficient power consumption management in different working states of the chips. Traditional power consumption optimization methods usually rely on static frequency or voltage adjustment and cannot be dynamically adjusted according to real-time requirements, resulting in unstable power consumption under different workloads. Traditional power consumption control methods rely on fixed clock frequencies and voltage settings and cannot be dynamically adjusted according to the real-time changes in system load, leading to problems of performance waste or excessive power consumption under different load conditions. Existing methods have a relatively lagged response to changes in system load and cannot effectively predict and avoid frequent adjustment fluctuations, thus affecting system stability and performance. There is a lack of a cooperative optimization mechanism between hardware and software, and load prediction and scheduling strategies are not fully utilized to balance power consumption and performance requirements.

[0073] In view of this, the embodiments of the present invention aim to solve problems such as insufficient dynamic adjustment, difficulty in balancing power consumption and performance, and lagging prediction of load changes in the prior art. Through dynamic clock adjustment, load prediction mechanisms, reinforcement learning algorithms, clock domain partitioning, and cooperative optimization of hardware and software, power consumption control is achieved, resource utilization and control efficiency are improved, and the energy efficiency and performance of the system are effectively enhanced.

[0074] The power consumption control method for a distribution network monitoring and control chip provided by the embodiments of the present application relates to the technical field of power engineering. The power consumption control method for a distribution network monitoring and control chip provided by the embodiments of the present application can be applied to terminals, servers, or software running on terminals or servers. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a vehicle-mounted terminal, etc., but is not limited thereto; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements the power consumption control method for a distribution network monitoring and control chip, etc., but is not limited to the above forms.

[0075] This application can be used in numerous general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multi-processor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This application can also be practiced in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0076] The following specifically explains the embodiments of this application in conjunction with the accompanying drawings:

[0077] Figure 1 It is an optional flowchart of the power consumption control method for the distribution network monitoring and control chip provided by the embodiment of this application. Figure 1 The method in may include but is not limited to steps S101 to S107.

[0078] Step S101: Perform clock domain partitioning processing on the distribution network monitoring and control chip to obtain a target clock domain;

[0079] Step S102: Obtain the current load data and historical load data of the target clock domain;

[0080] Step S103: According to the historical load data, use an autoregressive moving average model to perform trend prediction processing to obtain predicted load data;

[0081] Step S104: According to the predicted load data and the power consumption state of the control chip, use a preset reinforcement learning to perform action evaluation processing to obtain a state-action function value;

[0082] Step S105: Calculate the clock frequency to be adjusted and the voltage to be adjusted according to the current load data;

[0083] Step S106: Determine the predicted clock frequency and predicted voltage according to the state-action function value;

[0084] Step S107: Perform power consumption control on the target clock domain according to the target clock frequency and target voltage to obtain a power consumption control result, where the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

[0085] Steps S101 to S107 illustrated in the embodiments of the present application achieve power consumption control, improving resource utilization rate and control efficiency.

[0086] In some embodiments, in step S101, performing clock domain partitioning processing on the power distribution network monitoring and control chip to obtain a target clock domain may include but is not limited to the following steps:

[0087] Partitioning the power distribution network monitoring and control chip to obtain multiple clock domains;

[0088] Selecting one clock domain from the multiple clock domains as the target clock domain.

[0089] In some embodiments, the power distribution network monitoring and control chip may be first partitioned to obtain multiple clock domains, and then one clock domain is selected from the multiple clock domains as the target clock domain. Exemplarily, in this embodiment, the power distribution network monitoring and control chip is partitioned into multiple independent clock domains, and the target clock domain is selected. The frequency and voltage regulation of each clock domain are completely independent, so that subsequent dynamic adjustment can be performed based on load data. Each clock domain can independently adjust the clock frequency and voltage according to load prediction and real-time data to ensure that each clock domain can respond in a timely manner when the load changes. For example, when the load of a certain clock domain is low, the frequency of this clock domain can be adjusted to the lowest (200 MHz), and the voltage can be reduced to 0.8 V; while when the load is high, the clock frequency and voltage can be increased to 1 GHz and 1.1 V respectively. It can be understood that in this embodiment, by independently adjusting the frequency and voltage of each clock domain, the excessive power consumption caused by the consistent adjustment of the frequency and voltage of the entire chip can be effectively avoided. When only some modules are in a low-load state, the system only needs to reduce the clock frequency of these modules without affecting the performance of other high-load modules to assist in power consumption optimization. The independent adjustment design of this embodiment enables the high-load clock domain to promptly improve performance without being affected by low-load modules, thereby improving the overall system response speed and task processing efficiency and enhancing the system performance. Clock domain partitioning can reduce the problem of local overheating of the chip. When the high-load module increases the frequency, the low-load module can maintain a low-power state, thereby reducing the overall heat generation and optimizing the chip heat distribution to achieve thermal management. This embodiment can design independent adjustment strategies according to the working characteristics of different functional modules. For example, the memory clock domain can give priority to power consumption optimization, while the CPU clock domain gives priority to performance to enhance flexibility. At the same time, independent adjustment of the frequency and voltage of different clock domains can reduce the electrical interference between clock domains and improve system stability.

[0090] In some embodiments, in step S102, the current load data of the target clock domain can be obtained through a hardware performance counter, and the historical load data can be obtained through a power database. The current load data and the historical load data of the target clock domain can also be obtained by other means, which are not limited thereto. Exemplarily, a hardware performance counter can be embedded inside a power distribution network monitoring and control chip to collect the current load data of devices such as a CPU, a memory, or a peripheral in real time. The current load data can serve as the basis for subsequent power consumption management and provide key inputs for load prediction.

[0091] In some embodiments, in step S103, according to the historical load data, trend prediction processing is performed using an autoregressive moving average model to obtain predicted load data, which may include but is not limited to the following steps:

[0092] Perform denoising processing on the historical load data to obtain denoised data;

[0093] Perform normalization processing on the denoised data to obtain normalized data;

[0094] Perform time series segmentation processing on the normalized data to obtain segmented data;

[0095] Use the autoregressive moving average model to predict the segmented data to obtain predicted load data.

[0096] In some embodiments, the historical load data can be preprocessed. The preprocessing includes denoising, normalization, and time series segmentation, and the ARMA model (autoregressive moving average model) is used to predict the system load. The historical load data can be first denoised to obtain denoised data, the denoised data can be normalized to obtain normalized data, and the normalized data can be time series segmented to obtain segmented data to ensure the data quality and the prediction accuracy of the model. Then, the autoregressive moving average model is used to predict the segmented data to obtain predicted load data. It can be understood that the ARMA model analyzes the historical load data to predict the future load change trend. The ARMA model combines an autoregressive part and a moving average part to capture the short-term and long-term trends of load changes. Further, the autoregressive part of the ARMA model predicts the future through significant correlation patterns in the historical load data, while the moving average part supplements and corrects the prediction by analyzing the error terms. The prediction result (i.e., the predicted load data) will provide an early reference for subsequent clock frequency and voltage adjustment. Moreover, if the ARMA model predicts that the load will increase in the future for a period of time, measures can be taken in advance by adjusting the clock frequency and voltage to avoid excessive frequency fluctuations and power consumption, enabling the power system to be prepared for load changes in advance.

[0097] In some embodiments, in step S104, according to the predicted load data and the power consumption state of the control chip, using a preset reinforcement learning for action evaluation processing to obtain the state-action function value may include, but is not limited to, the following steps:

[0098] Initialize the reinforcement learning state according to the predicted load data and the power consumption state of the control chip;

[0099] Select an action as the target action from the action space, where the action space includes several combinations of clock frequencies and voltages;

[0100] According to the target action, perform system simulation adjustment to obtain feedback data, where the feedback data includes the power consumption reduction value, the task completion rate, or the response time;

[0101] According to the feedback data, the reward value, the learning rate, and the discount factor, use the Bellman equation to calculate the state-action function value;

[0102] Update the reinforcement learning state according to the state-action function value until the state-action function value meets the preset requirements.

[0103] In some embodiments, the optimal combination of clock frequencies and voltages can be selected through the Q-learning reinforcement learning algorithm. The Q-learning reinforcement learning algorithm takes the predicted load data and the power consumption state of the control chip as inputs and evaluates the benefits of different adjustment actions through the state-action value function (Q value). First, the reinforcement learning state S can be initialized according to the predicted load data and the power consumption state of the control chip t , and select an action as the target action A t from the action space, where the action space includes several combinations of clock frequencies and voltages. Exemplarily, the combination of clock frequencies and voltages can be adjusting the clock frequency to 1 GHz and adjusting the voltage to 0.8 V. The action selection can be based on a greedy strategy to balance the relationship between exploring new strategies and using existing experience. Then, according to the target action, perform system simulation adjustment to obtain feedback data, where the feedback data includes the power consumption reduction value, the task completion rate, or the response time. Exemplarily, according to the target action, simulate adjusting the clock frequency and voltage, and collect the power consumption and performance feedback after adjustment, that is, the feedback data. Then, according to the feedback data, the reward value, the learning rate, and the discount factor, use the Bellman equation (Bellman equation) to calculate the state-action function value (Q value), where the calculation expression of the state-action function value is: Q(S t , A t ) ← Q(S t , A t ) + α[R t + γmax A Q(S t+1 , A t+1 ) - Q(St ,A t )], where Q(S t ,A t ) is the state-action function value, S t is the reinforcement learning state at time t, S t+1 is the reinforcement learning state at time t+1, A t is the action at time t, A t+1 is the action at time t+1, R t is the reward value at time t, reflecting the comprehensive benefit of power consumption reduction and performance improvement. α is the learning rate, γ is the discount factor, and ← represents the update operation. It can be understood that the reinforcement learning state at the corresponding time can be obtained through feedback data. Finally, according to the state-action function value, the reinforcement learning state S t+1 is updated until the state-action function value meets the preset requirements, and the loop iteration ends. More specifically, the loop iteration can also end after reaching the preset number of iterations. It can be understood that the Q-learning algorithm will select the best adjustment action according to the predicted load data and the power consumption state of the control chip to maximize the long-term benefit and minimize the power consumption. The decision of Q-learning can optimize the future scheduling strategy based on the current load data and the adjustment effect. The feedback after each adjustment will be input into the Q-learning model to further optimize the power consumption scheduling of the system. Through continuous iterative learning, the Q-learning algorithm realizes the adaptive optimization of the balance between power consumption and performance, improving the scheduling efficiency and long-term benefit of the system.

[0104] In some embodiments, in step S105, calculating the clock frequency to be adjusted and the voltage to be adjusted according to the current load data may include, but is not limited to, the following steps:

[0105] Calculating the clock frequency to be adjusted according to the current load data and the preset load threshold;

[0106] Calculating the voltage to be adjusted according to the clock frequency to be adjusted.

[0107] In some embodiments, the clock frequency to be adjusted can be calculated based on the current load data and a preset load threshold first, and then the voltage to be adjusted can be calculated based on the clock frequency to be adjusted. Exemplarily, the clock frequency can be dynamically adjusted every 100 ms according to the currently monitored current load data. The preset load threshold can be set to 40%. By judging the current load data, when the load is less than 40%, the controller can adjust the clock frequency of the CPU to 300 MHz and synchronously adjust the voltage to 0.8 V through the DVFS technology, thereby reducing the power consumption. The preset load threshold can also be set to 75%. By judging the current load data, when the load exceeds 75%, the controller can increase the clock frequency of the CPU to 1 GHz and adjust the voltage to 1.1 V to meet the stability requirements and performance requirements under high load.

[0108] In some embodiments, in steps S106 - S107, the predicted clock frequency and the predicted voltage can be determined based on the state-action function value first. Exemplarily, after the reinforcement learning iteration ends, the final state-action function value can be obtained, which contains the optimal reinforcement learning state information. The clock frequency after iteration can be extracted from the state-action function value as the predicted clock frequency, and the voltage after iteration can be extracted from the state-action function value as the predicted voltage. Then, based on the target clock frequency and the target voltage, power consumption control is performed on the target clock domain to obtain a power consumption control result, where the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage. Exemplarily, when performing real-time data adjustment, parameter adjustment can be performed on the target clock domain, taking the clock frequency to be adjusted as the clock frequency of the target clock domain and the voltage to be adjusted as the voltage of the target clock domain to obtain a power consumption control result. When performing predicted data adjustment, parameter adjustment can be performed on the target clock domain, taking the predicted clock frequency as the clock frequency of the target clock domain and the predicted voltage as the voltage of the target clock domain to obtain a power consumption control result.

[0109] In some embodiments, the method further includes:

[0110] Performing a stability detection on the power consumption control result to obtain a stability detection result;

[0111] If the stability detection result indicates that the system is unstable, a fallback adjustment process is performed using a fallback strategy based on the clock frequency and voltage at the previous moment.

[0112] In some embodiments, the power consumption control result may be first subjected to stability detection to obtain a stability detection result. Exemplarily, to ensure the stability of the power system after clock frequency and voltage adjustment, the controller will monitor key system parameters through the built-in hardware stability detection module after each frequency adjustment to determine whether the adjustment is operating within a safe range. If the stability detection result indicates that the system is unstable, a fallback adjustment process will be performed according to the clock frequency and voltage at the previous moment using a fallback strategy. Exemplarily, when it is detected that the frequency or voltage adjustment causes instability, i.e., the stability detection result indicates that the system is unstable, the power system will restore to the operating state at the previous stable time through the fallback strategy. The fallback strategy includes reverting to the clock frequency and voltage at the previous moment and, if necessary, pausing the frequency adjustment to avoid damage to the power system.

[0113] In some embodiments, the method further includes:

[0114] Performing adjustment frequency detection on the power consumption control result to obtain an adjustment frequency detection result;

[0115] If the adjustment frequency detection result indicates frequent adjustment, classify the computing tasks to obtain critical tasks and non-critical tasks;

[0116] Assign priorities to the critical tasks and non-critical tasks to obtain corresponding target priorities, where the target priorities include high priority, medium priority, and low priority;

[0117] Adjust the thread execution order according to the target priorities and the dependencies between threads to give priority to high-priority tasks.

[0118] In some embodiments, at the software level, through a customized low-power scheduling strategy, combined with load prediction and optimization strategies, the operating state of the power system can be monitored in real time and task scheduling can be dynamically adjusted. The adjustment frequency of the power consumption control result can be detected to obtain the adjustment frequency detection result. If the adjustment frequency detection result indicates frequent adjustment, then by analyzing the load data and hardware feedback, the task allocation strategy can be adjusted to smooth the fluctuation trend and reduce the power consumption increase and system response delay that may be caused by frequent adjustments. The stability and efficiency of system power consumption management can be ensured by increasing the detection window period of frequency adjustment, limiting the amplitude of continuous adjustments, and preferentially optimizing the load distribution of modules with high fluctuation frequencies in task scheduling. First, the computing tasks can be classified to obtain critical tasks and non-critical tasks, and then priority assignments can be made to the critical tasks and non-critical tasks to obtain the corresponding target priorities, where the target priorities can include high priority, medium priority, and low priority. Finally, according to the target priorities and the dependencies between threads, the thread execution order can be adjusted so that high-priority tasks are processed first. Exemplarily, according to the predicted load data and the currently monitored current load data, non-critical tasks can be postponed or merged into subsequent time windows under low-load conditions to reduce unnecessary resource occupancy; under high load, the task execution order can be optimized to reduce resource contention during peak periods. By analyzing the dependencies between threads, the thread execution order and resource allocation can be adjusted so that high-priority tasks can be efficiently completed while reducing resource idling. Furthermore, the power system can adjust the priorities of tasks according to the current load data, postpone the execution of non-critical tasks when the load is low, and reduce unnecessary power consumption; under high load, optimize task scheduling to ensure performance while further reducing energy consumption. Further, through interaction with the hardware monitoring module, feedback data after load adjustment can be obtained in real time, and the scheduling strategy can be dynamically optimized. When the scheduling strategy causes a certain module (clock domain) to frequently enter a high-power state, the load pressure on this module (clock domain) can be reduced by adjusting task allocation. Additionally, at the hardware level, the PMU (Performance Monitoring Unit) works in coordination with the hardware performance counters to monitor the system load in real time, collect load data, and analyze it. The hardware performance counters are used to efficiently and low-powerly collect key load data (such as the loads of the CPU, memory, and peripherals) inside the chip in real time, while the PMU further utilizes this data in combination with dynamic adjustment strategies to achieve precise control of system power consumption. The combination of the two forms a complete load monitoring and adjustment mechanism, which not only meets the real-time nature of data collection but also provides support for dynamic power management. The voltage and clock frequency can be dynamically adjusted according to the load change information. When the system load is low, the PMU reduces the voltage to 0.8V and the clock frequency to 200MHz; when the load is high, the voltage is increased to 1.1V and the clock frequency is increased to 1GHz.

[0119] In some embodiments, the multi-level clock domain division and independent adjustment process is as follows Figure 2 As shown, the chip can be first divided into multiple clock domains, and each module (such as CPU, memory, etc.) is analyzed. Then, the load conditions (such as CPU, memory read and write, etc.) are monitored in real time, and a load prediction model is constructed (predicting load changes based on historical load data) to obtain Clock Domain 1, Clock Domain 2, and Clock Domain 3, and the clock frequencies and voltages of each clock domain are independently adjusted. For example, the range of adjustable clock frequency can be from 200 MHz to 1 GHz, and the range of adjustable voltage can be from 0.8 V to 1.1 V. Then, a load threshold judgment is made. If the load is lower than the threshold, the frequency and voltage are adjusted to the lowest level during low load; if the load is higher than the threshold, the frequency and voltage are adjusted to increase during high load, so as to minimize power consumption to the greatest extent. And it is dynamically adjusted, for example, it can be adjusted once every 100 ms. Adjustment is made according to the load prediction, and load changes can be anticipated in advance based on the prediction adjustment. Finally, verification is carried out after adjustment, and adjustment is made through a feedback mechanism to monitor system stability. The feedback mechanism makes adjustments based on the monitored data and adjusts all clock domains according to the feedback. Finally, system stability and performance are monitored to determine whether the performance requirements are met. If the performance requirements are not met, all clock domains are adjusted.

[0120] In some embodiments, the adaptive power consumption scheduling process is as follows Figure 3 As shown, the system load (CPU, memory, bandwidth) can be first monitored, the ARMA model is used to predict the future load to obtain the load prediction value, the Q-Learning algorithm is used to select the clock frequency and voltage, the clock frequency and voltage are adjusted, and then the adjustment structure is evaluated through a feedback mechanism to maintain the lowest power consumption and the best performance. Then, it is evaluated whether the performance adjustment is effective. If the adjustment is effective, it is judged whether the power consumption efficiency meets the requirements. If it does not meet the requirements, the future scheduling strategy is corrected.

[0121] In some embodiments, the dynamic clock adjustment process is as follows Figure 4 As shown, the system load can be first monitored. If the load is less than 40%, the clock frequency is set to 300 MHz and the voltage is synchronously adjusted. Then, historical load data analysis is carried out through a load prediction mechanism. If the load is greater than 75%, the clock frequency is set to 1 GHz. Then, stability inspection is carried out after frequency adjustment. If the frequency adjustment is unstable, it is judged whether there are frequent frequency fluctuations. If there are frequent fluctuations, the clock frequency and voltage are adjusted according to the load and the default frequency of 600 MHz is restored.

[0122] In some embodiments, the software and hardware co-optimization process is as follows Figure 5As shown, the system load (CPU, memory, etc.) can be monitored first and analyzed using load prediction and analysis algorithms. At the hardware level, the load status is judged through hardware power management (PMC and DVFS). If the load is low, the clock frequency is reduced to 200 MHz and the voltage is 0.8 V. If the load is high, the clock frequency is increased to 1 GHz and the voltage is 1.1 V. Then, performance and power consumption balance evaluation and adjustment are carried out. The system status is continuously monitored through a feedback mechanism and continuously adjusted. Final adjustment is made after feedback. At the software level, a software low-power scheduling strategy is designed. If the load is high, the execution of non-critical tasks is postponed to achieve optimized task execution and improved energy efficiency under high load. At the same time, task allocation is carried out according to priorities. Non-critical tasks are postponed and critical tasks are preferentially executed.

[0123] In some embodiments, this embodiment combines a dynamic clock adjustment mechanism with load prediction to precisely control the power consumption of the distribution network monitoring and control chip, giving full play to the advantages of the coordinated optimization of hardware and software. By real-time monitoring the system load and dynamically adjusting the clock frequency and voltage according to the load change, the system automatically reduces the clock frequency and voltage when the load is low, significantly reducing power consumption; while when the load is high, the system can quickly increase the frequency and voltage to ensure system performance. This embodiment breaks through the limitations of traditional static clock frequency settings and realizes efficient adaptive adjustment when the load changes. This embodiment introduces a load prediction mechanism, analyzes historical load data to predict future load change trends, and adjusts the clock frequency in advance to avoid performance bottlenecks and power consumption waste caused by frequent dynamic adjustments. Through intelligent prediction and control, the chip can flexibly adjust under different load conditions, minimizing power consumption to the greatest extent while ensuring real-time performance and system stability. Compared with the relatively single adjustment methods in the prior art, this embodiment can effectively improve the energy efficiency of the system, while maintaining high-performance output, meeting the requirements in various application scenarios. Through the coordinated optimization of hardware and software, this embodiment not only realizes precise power consumption adjustment under different loads, but also avoids over-adjustment and unnecessary power consumption waste by introducing a load prediction and adaptive adjustment mechanism, making it more adaptable and efficient in practical applications, providing an innovative solution for the low-power operation of the distribution network monitoring and control system.

[0124] The beneficial effects of implementing the embodiments of the present invention include: The embodiments of the present invention first perform clock domain division processing on the power distribution network monitoring and control chip to obtain the target clock domain, obtain the current load data and historical load data of the target clock domain, then perform trend prediction processing using the autoregressive moving average model based on the historical load data to obtain predicted load data, and perform action evaluation processing using the preset reinforcement learning based on the predicted load data and the power consumption state of the control chip to obtain the state-action function value. Then, according to the current load data, calculate the clock frequency to be adjusted and the voltage to be adjusted, determine the predicted clock frequency and predicted voltage according to the state-action function value, and finally perform power consumption control on the target clock domain according to the target clock frequency and target voltage to obtain the power consumption control result, so that power consumption control can be achieved by adjusting different clock frequencies and voltages, thereby improving resource utilization and control efficiency.

[0125] As Figure 6 shown, the embodiments of the present invention also provide a power consumption control device for a power distribution network monitoring and control chip, including:

[0126] The first module 801 is used to perform clock domain division processing on the power distribution network monitoring and control chip to obtain the target clock domain;

[0127] The second module 802 is used to obtain the current load data and historical load data of the target clock domain;

[0128] The third module 803 is used to perform trend prediction processing using the autoregressive moving average model based on the historical load data to obtain predicted load data;

[0129] The fourth module 804 is used to perform action evaluation processing using the preset reinforcement learning based on the predicted load data and the power consumption state of the control chip to obtain the state-action function value;

[0130] The fifth module 805 is used to calculate the clock frequency to be adjusted and the voltage to be adjusted according to the current load data;

[0131] The sixth module 806 is used to determine the predicted clock frequency and predicted voltage according to the state-action function value;

[0132] The seventh module 807 is used to perform power consumption control on the target clock domain according to the target clock frequency and target voltage to obtain the power consumption control result, where the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

[0133] The content in the above method embodiments is applicable to the device embodiments of the present invention. The functions specifically implemented by the device embodiments of the present invention are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0134] As shown in Figure 7 the following figure, an embodiment of the present invention further provides a computer device, including:

[0135] at least one processor 901;

[0136] at least one memory 902 for storing at least one program;

[0137] When the at least one program is executed by the at least one processor, the at least one processor implements Figure 1 the method shown in

[0138] All the content in the above method embodiments is applicable to the device embodiments of the present invention. The functions specifically implemented by the device embodiments of the present invention are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0139] An embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements Figure 1 the method shown in

[0140] All the content in the above method embodiments is applicable to the storage medium embodiments of the present invention. The functions specifically implemented by the storage medium embodiments of the present invention are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0141] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modification, equivalent replacement, and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A power consumption control method for a distribution network monitoring control chip, characterized in that: The following steps are involved: Perform clock domain division processing on the distribution network monitoring and control chip to obtain the target clock domain; Obtaining current load data and historical load data of the target clock domain; According to the historical load data, an autoregressive moving average model is used to perform trend forecasting processing to obtain forecast load data; According to the predicted load data and the power consumption state of the control chip, the action evaluation process is performed using preset reinforcement learning to obtain a state action function value; Calculating a clock frequency to be adjusted and a voltage to be adjusted according to the current load data; Determining a predicted clock frequency and a predicted voltage according to the state-action function value; The target clock domain is subjected to power consumption control according to a target clock frequency and a target voltage to obtain a power consumption control result, wherein the target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

2. The method according to claim 1, characterized in that The clock domain division process is performed on the distribution network monitoring control chip to obtain the target clock domain, including: Dividing the distribution network monitoring and control chip to obtain multiple clock domains; A clock domain is selected from the multiple clock domains as the target clock domain.

3. The method according to claim 1, characterized in that The method of performing trend forecasting processing based on the historical load data using an autoregressive moving average model to obtain forecast load data includes: Performing denoising processing on the historical load data to obtain denoised data; Normalizing the denoised data to obtain normalized data; Performing time series segmentation processing on the normalized data to obtain segmented data; The segmented data is predicted using the autoregressive moving average model to obtain the predicted load data.

4. The method according to claim 1, characterized in that: The step of performing action evaluation processing by using preset reinforcement learning according to the predicted load data and the power consumption state of the control chip to obtain a state action function value includes: Initializing a reinforcement learning state according to the predicted load data and the power consumption state of the control chip; Selecting an action from an action space as a target action, wherein the action space includes a plurality of clock frequency and voltage combinations; According to the target action, a system simulation adjustment is performed to obtain feedback data, wherein the feedback data includes a power consumption reduction value, a task completion rate or a response time; Calculating the state-action function value using the Bellman equation according to the feedback data, the reward value, the learning rate and the discount factor; According to the state-action function value, the reinforcement learning state is updated until the state-action function value meets a preset requirement.

5. The method according to claim 1, characterized in that The step of calculating the clock frequency to be adjusted and the voltage to be adjusted according to the current load data includes: Calculating the clock frequency to be adjusted according to the current load data and a preset load threshold; The voltage to be adjusted is calculated according to the clock frequency to be adjusted.

6. The method according to claim 1, characterized in that The method further comprises: Performing stability detection on the power consumption control result to obtain a stability detection result; If the stability detection result indicates that the system is unstable, a fallback adjustment process is performed using a fallback strategy according to the clock frequency and the voltage at the previous moment.

7. The method according to claim 1, characterized in that The method further comprises: Performing an adjustment frequency detection on the power consumption control result to obtain an adjustment frequency detection result; If the adjustment frequency detection result is frequent adjustment, the computing tasks are classified to obtain critical tasks and non-critical tasks; Assigning priorities to the critical tasks and the non-critical tasks to obtain corresponding target priorities, wherein the target priorities include high priority, medium priority and low priority; According to the target priority and the dependencies between threads, the thread execution order is adjusted so that high priority tasks are processed first.

8. A power consumption control device for a distribution network monitoring and control chip, characterized in that: include: The first module is used to perform clock domain division processing on the distribution network monitoring control chip to obtain the target clock domain; The second module is used to obtain the current load data and historical load data of the target clock domain; The third module is used to perform trend forecasting processing based on the historical load data using an autoregressive moving average model to obtain forecast load data; A fourth module is used to perform action evaluation processing using preset reinforcement learning according to the predicted load data and the power consumption state of the control chip to obtain a state action function value; A fifth module is used to calculate the clock frequency to be adjusted and the voltage to be adjusted according to the current load data; A sixth module, used to determine a predicted clock frequency and a predicted voltage according to the state action function value; The seventh module is used to control the power consumption of the target clock domain according to the target clock frequency and the target voltage to obtain the power consumption control result. The target clock frequency includes the clock frequency to be adjusted or the predicted clock frequency, and the target voltage includes the voltage to be adjusted or the predicted voltage.

9. A computer device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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