A forward equalizer, an inter-chip interconnection interface, and a server

Abstract

The present invention discloses a forward equalizer, an inter-chip interconnect interface, and a server, belonging to the field of equalization circuits, for performing forward equalization on a signal to be compensated, and solving the problems of large circuit area and high power consumption of the forward equalizer. Considering that the current value of the tail current transistor in the data flip-flop can determine the adjustment range of the data flip-flop for the amplitude of the signal to be compensated, the forward equalizer in the present invention includes a current control circuit, and the current value of the tail current transistor in the data flip-flop can be controlled through the current control circuit, so that the data flip-flop samples and shapes the received signal to be compensated based on the current of its own tail current transistor, and multiplies the signal to be compensated by a tap coefficient corresponding to itself, so as to adjust the amplitude of the signal to be compensated, thereby integrating the multiplication operation of the tap coefficient into the data flip-flop, and eliminating the need to design a separate multiplication circuit, thus reducing the circuit area and power consumption of the forward equalizer.

Description

Technical Field

[0001] The present invention relates to the field of equalization circuits, and particularly to a forward equalizer, an inter-chip interconnect interface, and a server. Background Art

[0002] With the continuous increase in the information transmission rate in various high-computing scenarios (such as artificial intelligence, 6G (Generation) communication, big data computing, automatic acceleration, etc.), the interconnect interfaces between different communication units are also facing application requirements such as high speed and high reliability. Currently, the transmitter in the inter-chip interconnect interface has gradually taken on the role of equalization compensation to reduce the equalization burden on the receiver. That is, the forward equalizer has gradually become an essential functional unit in the inter-chip interconnect interface. However, in the related art, there is a lack of a mature forward equalizer, resulting in problems such as large circuit area and high power consumption of the forward equalizer.

[0003] Therefore, how to provide a solution to the above technical problems is an issue that those skilled in the art need to solve currently. Summary of the Invention

[0004] The object of the present invention is to provide a forward equalizer, an inter-chip interconnect interface, and a server. The forward equalizer in the present invention includes a current control circuit, which can control the current value of the tail current transistor in the data flip-flop, so that the data flip-flop samples and shapes the received signal to be compensated based on the current of its own tail current transistor, and multiplies the signal to be compensated by the corresponding tap coefficient, so as to adjust the amplitude of the signal to be compensated, thereby integrating the multiplication operation of the tap coefficient into the data flip-flop, eliminating the need to design a separate multiplication circuit, and thus reducing the circuit area and power consumption of the forward equalizer.

[0005] To solve the above technical problems, the present invention provides a forward equalizer, including:

[0006] N data flip-flops arranged in series at the output end of the signal to be compensated, configured to sample and shape the received signal to be compensated based on the current of their own tail current transistors under the control of a clock signal, and multiply the signal to be compensated by the corresponding tap coefficient to adjust the amplitude of the signal to be compensated;

[0007] wherein, N is a positive integer;

[0008] Current control circuits corresponding to the data flip-flops one by one, configured to control the current value of the tail current transistors in the data flip-flops;

[0009] An adder connected to the data flip-flops, configured to superimpose the output signals of the data flip-flops to obtain the compensated signal to be compensated.

[0010] On the other hand, the forward equalizer further includes:

[0011] A preamble interference compensation circuit disposed between the output end of the signal to be compensated and N serially connected data flip - flops, for multiplying the signal to be compensated by a corresponding tap coefficient of itself, so as to compensate for the preamble interference of the signal to be compensated;

[0012] The adder is specifically configured to superimpose the output signal of the preamble interference compensation circuit and the output signal of the data flip - flop to obtain the compensated signal to be compensated.

[0013] On the other hand, the preamble interference compensation circuit includes:

[0014] A buffer, configured to buffer the signal to be compensated, and multiply the signal to be compensated by a corresponding tap coefficient of itself based on the current of its own tail current transistor, so as to adjust the amplitude of the signal to be compensated;

[0015] A current control circuit connected to the buffer, configured to control the current value of the tail current transistor in the buffer.

[0016] On the other hand, the load resistor in the buffer and the load resistor in the data flip - flop are both adjustable load resistors;

[0017] The forward equalizer further includes:

[0018] A resistance value adjustment circuit connected to the adjustable load resistor, configured to adjust the resistance value of the adjustable load resistor.

[0019] On the other hand, the current control circuit includes:

[0020] A current generation circuit, configured to generate a reference current;

[0021] A current mirror circuit, configured to copy the reference current and deliver the copied reference current to the corresponding adjustable load resistor and the tail current transistor respectively;

[0022] Wherein, the current mirror circuit serves as the resistance value adjustment circuit.

[0023] On the other hand, the adjustable load resistor includes a load resistor and a first controllable switch connected in parallel with the load resistor.

[0024] On the other hand, the current generation circuit includes a second controllable switch, a first resistor, and a third controllable switch;

[0025] The control terminal of the second controllable switch is connected to the output terminal of the control voltage. The first terminal of the second controllable switch is connected to the current mirror circuit. The second terminal of the second controllable switch is connected to the first terminal of the first resistor. The second terminal of the first resistor is respectively connected to the first terminal of the third controllable switch, the control terminal of the third controllable switch, and the current mirror circuit. The second terminal of the third controllable switch is connected to the current mirror circuit;

[0026] Wherein, the control voltage is used to adjust the current value of the reference current by controlling the opening degree of the second controllable switch.

[0027] On the other hand, both the second controllable switch and the third controllable switch are metal-oxide-semiconductor field-effect transistors.

[0028] On the other hand, the data flip-flop includes a master-slave data flip-flop;

[0029] The master-slave data flip-flop includes a master latch and a slave latch;

[0030] Both the master latch and the slave latch include a tail current transistor, a signal latch circuit, and a load resistor;

[0031] Wherein, the signal latch circuit is respectively connected to the tail current transistor and the load resistor.

[0032] On the other hand, the signal latch circuit includes a first sub-controllable switch, a second sub-controllable switch, a third sub-controllable switch, a fourth sub-controllable switch, a fifth sub-controllable switch, and a sixth sub-controllable switch;

[0033] The control terminals of the first sub-controllable switch and the second sub-controllable switch are both connected to the signal output terminal of the previous stage. The first terminals of the first sub-controllable switch and the second sub-controllable switch are respectively used to connect to the load resistor. The second terminals of the first sub-controllable switch and the second sub-controllable switch are both connected to the first terminal of the fifth sub-controllable switch. The control terminals of the fifth sub-controllable switch and the sixth sub-controllable switch are both used to connect to the clock signal. The common terminal formed by the second terminal of the fifth sub-controllable switch and the second terminal of the sixth sub-controllable switch is connected to the corresponding tail current transistor. The control terminal of the third sub-controllable switch is connected to the first terminal of the second sub-controllable switch. The control terminal of the fourth sub-controllable switch is connected to the first terminal of the first sub-controllable switch. The first terminals of the third sub-controllable switch and the fourth sub-controllable switch are both connected to the load resistor. The common terminal formed by the second terminal of the third sub-controllable switch and the second terminal of the fourth sub-controllable switch is connected to the first terminal of the sixth sub-controllable switch. The first terminals of the third sub-controllable switch and the fourth sub-controllable switch together serve as the output terminal of the latch;

[0034] Among them, the trigger levels of the fifth sub-controllable switch and the sixth sub-controllable switch are higher and lower levels to each other.

[0035] On the other hand, the buffer includes a tail current tube, a signal buffer circuit and a load resistor;

[0036] The signal buffer circuit is connected to the tail current tube and the load resistor respectively.

[0037] On the other hand, the signal buffer circuit includes a fourth controllable switch and a fifth controllable switch;

[0038] The first end of the fourth controllable switch is connected to the first end of the fifth controllable switch; the second end of the fourth controllable switch and the second end of the fifth controllable switch are respectively connected to the load resistor and serve as the output end of the signal buffer circuit; the control end of the fourth controllable switch and the control end of the fifth controllable switch are both connected to the output end of the signal to be compensated.

[0039] On the other hand, the forward equalizer is applied to inter-chip data communication in a server.

[0040] On the other hand, the forward equalizer further includes a delay adjustment circuit;

[0041] The delay adjustment circuit is used to generate a dedicated sub-clock signal for each data trigger based on the original clock signal;

[0042] Among any two adjacent data triggers, the phase of the sub-clock signal of the subsequent data trigger lags behind that of the previous data trigger by one delay cycle of the data trigger.

[0043] On the other hand, the delay adjustment circuit includes a frequency division inversion circuit and a signal selection circuit;

[0044] The frequency division and inversion circuit is used to obtain multiple standby clock signals by performing frequency division and inversion processing on the original clock signal;

[0045] The signal selection circuit is used to selectively obtain the sub-clock signal corresponding to each data trigger according to the standby clock signal.

[0046] On the other hand, the frequency division inversion circuit comprises:

[0047] A frequency divider, used for generating a backup clock signal with phases of zero degree and ninety degrees by dividing the original clock signal by two.

[0048] The inverter is used to invert the sub-clock signal output by the frequency divider to generate a standby clock signal with a phase of 180 degrees and 270 degrees.

[0049] On the other hand, the signal selection circuit includes a first selector, a second selector, a third selector, and a fourth selector;

[0050] The input terminals of the first selector are respectively connected to the first output terminal of the frequency divider and the first output terminal of the inverter. The input terminals of the second selector are respectively connected to the second output terminal of the frequency divider and the output terminal of the first selector. The input terminals of the third selector are respectively connected to the second output terminal of the frequency divider and the first output terminal of the inverter. The input terminals of the fourth selector are respectively connected to the output terminal of the third selector and the second output terminal of the frequency divider. The control terminals of the first selector and the third selector are both connected to a first control signal. The control terminals of the second selector and the fourth selector are both connected to a second control signal;

[0051] The first output terminal of the frequency divider is used to output a clock signal with a phase of 90 degrees. The second output terminal of the frequency divider is used to output a clock signal with a phase of 0 degree. The first output terminal of the inverter is used to output a clock signal with a phase of 180 degrees. The second selector is used to output a first sub-clock signal. The fourth selector is used to output a second sub-clock signal.

[0052] On the other hand, when the control signal received by the first selector is at a high level, it selects the clock signal at the first output terminal of the inverter; when the control signal received by the second selector is at a low level, it selects the clock signal at the second output terminal of the frequency divider; when the control signal received by the third selector is at a low level, it selects the clock signal at the first output terminal of the inverter, and when the control signal received by the fourth selector is at a low level, it selects the clock signal at the second output terminal of the frequency divider;

[0053] When the delay period of the data flip-flop is one clock signal period, the second control signal is at a low level;

[0054] When the delay period of the data flip-flop is half a clock signal period, both the first control signal and the second control signal are at a high level;

[0055] When the delay period of the data flip-flop is one-fourth of a clock signal period, the first control signal is at a low level and the second control signal is at a high level.

[0056] To solve the above technical problems, the present invention also provides an inter-chip interconnection interface, including the forward equalizer as described above.

[0057] To solve the above technical problems, the present invention also provides a server, including the inter-chip interconnection interface as described above.

[0058] Beneficial effects: The present invention provides a forward equalizer. Considering that the current value of the tail current transistor in the data flip-flop can determine the adjustment amplitude of the data flip-flop for the amplitude of the signal to be compensated, the forward equalizer in the present invention includes a current control circuit. The current value of the tail current transistor in the data flip-flop can be controlled through the current control circuit, so that the data flip-flop samples and shapes the received signal to be compensated based on the current of its own tail current transistor, and multiplies the signal to be compensated by the tap coefficient corresponding to itself, so as to adjust the amplitude of the signal to be compensated. Thus, the multiplication operation of the tap coefficient is integrated into the data flip-flop, eliminating the need to design a separate multiplication circuit, thereby reducing the circuit area and power consumption of the forward equalizer.

[0059] The present invention also provides an inter-chip interconnection interface and a server, which have the same beneficial effects as the above-mentioned forward equalizer. Description of the drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the related art and embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0061] Figure 1 It is a schematic structural diagram of a forward equalizer provided by the present invention;

[0062] Figure 2 It is a schematic structural diagram of another forward equalizer provided by the present invention;

[0063] Figure 3 It is a schematic structural diagram of a sampling weighted coupling circuit provided by the present invention;

[0064] Figure 4 It is a schematic structural diagram of a delay weighted coupling circuit provided by the present invention;

[0065] Figure 5 It is a schematic structural diagram of a delay adjustment circuit provided by the present invention;

[0066] Figure 6 It is a schematic diagram of the phase relationship between the first seed clock signals provided by the present invention;

[0067] Figure 7 It is a schematic diagram of the phase relationship between the second seed clock signals provided by the present invention;

[0068] Figure 8 It is a schematic diagram of the phase relationship between the third seed clock signals provided by the present invention. Detailed implementation manners

[0069] The core of the present invention is to provide a forward equalizer, an inter-chip interconnection interface, and a server. The forward equalizer in the present invention includes a current control circuit. The current value of the tail current transistor in the data flip-flop can be controlled through the current control circuit, so that the data flip-flop samples and shapes the received signal to be compensated based on the current of its own tail current transistor, and multiplies the signal to be compensated by the corresponding tap coefficient, so as to adjust the amplitude of the signal to be compensated, thereby integrating the multiplication operation of the tap coefficient into the data flip-flop, eliminating the need to design a separate multiplication circuit, and thus reducing the circuit area and power consumption of the forward equalizer.

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0071] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a forward equalizer provided by the present invention. The forward equalizer includes:

[0072] N data flip-flops 1 arranged in series at the output end of the signal to be compensated, which are used to sample and shape the received signal to be compensated based on the current of their own tail current transistors under the control of a clock signal, and multiply the signal to be compensated by the corresponding tap coefficient to adjust the amplitude of the signal to be compensated;

[0073] wherein, N is a positive integer;

[0074] Current control circuits 2 corresponding to the data flip-flops 1 one by one, which are used to control the current value of the tail current transistors in the data flip-flops 1;

[0075] An adder 3 connected to the data flip-flops, which is used to superimpose the output signals of the data flip-flops to obtain the compensated signal to be compensated.

[0076] Wherein, Figure 1 So in is the compensated signal to be compensated.

[0077] Specifically, considering the technical problems in the above background art and also considering that the current value of the tail current tube in the data flip-flop 1 can determine the adjustment range of the data flip-flop 1 for the amplitude of the signal to be compensated, therefore, by controlling the "current value of the tail current tube", in theory, the "multiplication operation of the tap coefficients" can be incorporated into the data flip-flop 1, so that the data flip-flop 1 incorporates the "multiplication operation of the tap coefficients" on the basis of sampling and shaping the signal to be compensated. Based on this, the design of the multiplication circuit for "multiplying the output signal of the data flip-flop 1 by the corresponding tap coefficient" can be omitted, which reduces the circuit area on the one hand and can also reduce the power consumption on the other hand.

[0078] Specifically, based on the above concept, the forward equalizer provided in the embodiment of the present invention first includes N data flip-flops 1 connected in series at the output end of the signal to be compensated. These data flip-flops 1 incorporate the functions of "sampling and shaping the signal to be compensated" and "multiplying the signal to be compensated by the tap coefficient corresponding to itself", and both of these operations can be performed based on the current of their own tail current tubes under the control of the clock signal. Correspondingly, the forward equalizer in the embodiment of the present invention is also provided with a current control circuit 2 corresponding to each data flip-flop 1, which can be used to control the current value of the tail current tube in the data flip-flop 1. Through the corresponding current control circuit 2, the current values of the tail current tubes in each data flip-flop 1 can be independently and differentially controlled, so that the data flip-flop 1 can accurately perform the above two operations; finally, the adder 3 can superimpose the output signals of the data flip-flop 1 to obtain the compensated signal to be compensated; and due to the design of the above current control circuit 2 and the data flip-flop 1, there is no need to set a multiplication circuit corresponding to each data flip-flop 1 in the forward equalizer of the embodiment of the present invention, but the effect of "tap coefficient multiplication" can be achieved through a simple current control circuit 2, which reduces the circuit area and power consumption of the forward equalizer.

[0079] Among them, the specific number N of the data flip-flops 1 can be flexibly set according to the actual situation. For example, it can be 3, etc., and the embodiment of the present invention does not limit this here.

[0080] Specifically, in the field of inter-chip interconnection interfaces, there are signal losses under high-speed transmission. The forward equalizer needs to process the input signal to compensate for the signal loss and reduce the equalization burden at the receiving end. Sampling and shaping are the basic steps for processing signals. By sampling, the continuous input signal Sin is discretized at specific moments, which is convenient for subsequent precise processing; shaping makes the signal more regular and stable, which is beneficial for the multiplier and the adder 3 to perform subsequent amplitude weighting and superimposing operations to achieve the signal compensation function of the entire forward equalizer.

[0081] Among them, the forward equalizer involves multi-stage signal processing and the compensation concepts for main label interference and post-label interference:

[0082] Among them, multi-order signal processing: In signal transmission, there are various interferences, such as main label interference, post-label interference, etc. Each DFF (Data Flip Flop) cooperates with the subsequent multiplier and adder 3 to perform targeted compensation for interferences of different orders. For example, the signal S1 processed by the first DFF is mainly used to compensate for the main label interference, the signal S2 processed by the second DFF is used to compensate for the first post-label interference, and the signal S3 processed by the third DFF is used to compensate for the second post-label interference, so as to achieve multi-order equalization compensation and improve the signal quality. Main label interference (main lobe interference): In signal transmission, the main label interference is the main factor affecting the signal quality, similar to the interference in the main lobe part of the signal spectrum. In the equalization process, usually the main label interference is compensated first, which can be regarded as the first-order processing. It is a relatively basic and important compensation link, directly affecting the restoration of the main characteristics of the signal. Post-label interference (side lobe interference): The post-label interference is the interference in the side lobe part of the signal spectrum. In signal processing, there may be multiple post-label interferences, such as the first post-label interference, the second post-label interference, etc., corresponding to second-order, third-order and higher-order processing. These interferences are relatively weaker than the main label interference, but when accumulated, they will also seriously affect the signal quality. The compensation for different post-label interferences is the signal processing for different orders. By gradually compensating for interferences of different orders, the signal is closer to the original state and the transmission quality is improved.

[0083] The present invention provides a forward equalizer. Considering that the current value of the tail current transistor in the data flip-flop can determine the adjustment range of the data flip-flop for the amplitude of the signal to be compensated, the forward equalizer in the present invention includes a current control circuit. Through the current control circuit, the current value of the tail current transistor in the data flip-flop can be controlled, so that the data flip-flop samples and shapes the received signal to be compensated based on the current of its own tail current transistor, and multiplies the signal to be compensated by the tap coefficient corresponding to itself, so as to adjust the amplitude of the signal to be compensated, thereby integrating the multiplication operation of the tap coefficient into the data flip-flop, eliminating the need to design a separate multiplication circuit, and thus reducing the circuit area and power consumption of the forward equalizer.

[0084] Based on the above embodiments:

[0085] As an optional embodiment, the forward equalizer further includes:

[0086] A pre-label interference compensation circuit provided at the output end of the signal to be compensated and between N mutually connected in series data flip-flops 1, for multiplying the signal to be compensated by the tap coefficient corresponding to itself, so as to compensate for the pre-label interference of the signal to be compensated;

[0087] The adder 3 is specifically configured to superimpose the output signal of the preamble interference compensation circuit and the output signal of the data flip-flop to obtain the compensated signal to be compensated.

[0088] Specifically, considering that during signal transmission, the current signal may be interfered by previous signals, that is, preamble interference. Therefore, in order to compensate for preamble interference, an embodiment of the present invention may further include a preamble interference compensation circuit disposed between the output end of the signal to be compensated and N mutually connected data flip-flops 1 in series, which is used to multiply the signal to be compensated by a tap coefficient corresponding to itself, so as to compensate for the preamble interference of the signal to be compensated. In this case, the output signal of the preamble interference compensation circuit can be added to the superposition term of the adder 3.

[0089] As an optional embodiment, the preamble interference compensation circuit includes:

[0090] A buffer, which is used to buffer the signal to be compensated and multiply the signal to be compensated by a tap coefficient corresponding to itself based on the current of its own tail current tube, so as to adjust the amplitude of the signal to be compensated;

[0091] A current control circuit 2 connected to the buffer, which is used to control the current value of the tail current tube in the buffer.

[0092] Specifically, considering that the buffer can buffer the signal to be compensated and the buffer also includes a tail current tube, by controlling the current of the tail current tube in the buffer, the effect of "multiplying the signal to be compensated by the tap coefficient" can be achieved. Therefore, the preamble interference compensation circuit in the embodiment of the present invention includes a buffer and a current control circuit 2 connected to the buffer. The current control circuit 2 can control the current value of the tail current tube in the buffer, so that the buffer multiplies the signal to be compensated by a tap coefficient corresponding to itself based on the current of its own tail current tube, so as to adjust the amplitude of the signal to be compensated.

[0093] Specifically, for better illustration of the embodiment of the present invention, please refer to Figure 2 , Figure 2 which is a schematic structural diagram of another forward equalizer provided by the present invention. Figure 2 The sampling weighted coupling circuit in -1 is the equivalent structural diagram of the data flip-flop 1 in the embodiment of the present invention, that is, it not only includes the sampling and shaping function of the original data flip-flop 1, but also has the function of a multiplier to "multiply the signal to be compensated by the tap coefficient". The delay weighted coupling circuit is the preamble interference compensation circuit in the embodiment of the present invention, which not only has the function of a buffer, but also has the function of a multiplier to "multiply the signal to be compensated by the tap coefficient". C

[0094] Among them, usingFigure 2 The solution in can integrate the data trigger 1 with the coefficient weighting function circuit, thus eliminating some circuits and reducing the area and power consumption of the circuit. The preamble interference compensation circuit can compensate for preamble interference. The first-stage sampling weighting coupling circuit can compensate for main marker interference. The second-stage sampling weighting coupling circuit can compensate for the first post-marker interference. The third-stage sampling weighting coupling circuit can compensate for the second post-marker interference, and so on. Among them, the preamble interference compensation circuit can perform delay and coefficient weighting processing on the signal to be compensated to achieve the signal amplitude corresponding to the preamble interference. Each stage of the sampling weighting coupling circuit can perform sampling shaping and coefficient weighting processing on the output signal of the preamble interference compensation circuit to respectively achieve the signal amplitudes corresponding to the main marker interference, the first post-marker interference, and the second post-marker interference.

[0095] As an alternative embodiment, the load resistors in the buffer and the load resistors in the data trigger 1 are both adjustable load resistors.

[0096] The forward equalizer further includes:

[0097] A resistance value adjustment circuit connected to the adjustable load resistor for adjusting the resistance value of the adjustable load resistor.

[0098] Specifically, except for the tail current transistor, both the buffer and the data trigger 1 further include load resistors. Considering that for the buffer and the data trigger 1, the adjustment of the signal amplitude of the signal to be compensated depends not only on the current value of the tail current transistor but also on the resistance value of the load resistor. By reducing the resistance value of the load resistor, the lower limit of the signal output can be reduced, thereby broadening the amplitude change range of the output signal of the "buffer and data trigger 1". Therefore, in the embodiments of the present invention, the load resistors in the buffer and the load resistors in the data trigger 1 are both adjustable load resistors. Correspondingly, in order to flexibly adjust the resistance value of the adjustable load resistor, the forward equalizer in the embodiments of the present invention further includes a resistance value adjustment circuit connected to the adjustable load resistor for adjusting the resistance value of the adjustable load resistor.

[0099] Among them, assuming that the resistance value of the original load resistor is R, and the resistance value range of the adjustable load resistor is [R - ∆, +∞], then when using the adjustable load resistor, the amplitude change range of the output signal can be changed from the original [I(R), +∞] to [I(R - ∆), +∞], that is, the amplitude change range of the output signal of the "buffer and data trigger 1" is broadened.

[0100] As an alternative embodiment, the current control circuit 2 includes:

[0101] A current generation circuit for generating a reference current.

[0102] A current mirror circuit is used to copy a reference current and deliver the copied reference current to a corresponding adjustable load resistor and a tail current transistor respectively;

[0103] Among them, the current mirror circuit serves as a resistance adjustment circuit.

[0104] Specifically, for a better illustration of the embodiments of the present invention, please refer to Figure 3 and Figure 4 , Figure 3 which is a schematic structural diagram of a sampling weighted coupling circuit provided by the present invention, Figure 4 which is a schematic structural diagram of a delay weighted coupling circuit provided by the present invention, Figure 3 The controllable switches M7 and M9 and the resistor between them in [] together constitute a current generation circuit. The controllable switch M8 and M 10 form a current mirror circuit, and the part on the right side of the current mirror is the structure of the master-slave data flip-flop. The weighted ratio circuit therein includes two tail current transistors belonging to the master latch and the slave latch respectively; Figure 4 The current control circuit 2 in [] is Figure 3 identical to Figure 4 The right side of the current mirror circuit in [] is the structure of the buffer.

[0105] Specifically, in [] and [], the controllable switch M7 can be controlled by the controllable voltage V Figure 3 and Figure 4 respectively. Then, based on the controllable switches M7, M9 and the resistor between them, a current is generated. The generated current can be input into the connected current mirror circuit (M8 and M ctrl ) to generate a reference current. The reference current can be input into the weighted ratio circuit through the mirror circuit to control the current value of the tail current transistor in the data flip-flop 1. 10 ) to generate a reference current. The reference current can be input into the weighted ratio circuit through the mirror circuit to control the current value of the tail current transistor in the data flip-flop 1.

[0106] Among them, the master-slave data flip-flop is implemented in a current-mode structure and consists of master-slave two-stage latches. With the joint action of the mirrored current, adjustable load resistor and clock signal, the weighted sum and sampling of the input signal are completed. D i and D j are the input signal and output signal respectively, clk is the clock signal, and Q o is the output signal of the master latch. The working state of the latch is divided into two states: sampling and latching, and the state conversion is realized by the clock signal. When the clock signal is at a high level, the transistor M5 is turned on and M6 is turned off. At this time, the master latch passes through the transistors M1 and M2 to the input signal (D i)Sampling is performed; at this time, the slave latch is in the latched state, maintaining the output value of the previous cycle. When the clock signal becomes low, transistor M5 is cut off and M6 is turned on. The master latch operates in the latched state, and the cross-coupled transistors M3 and M4 are also turned on, forming positive feedback to maintain the signal value sampled in the first half of the cycle. At this time, the slave latch is in the sampling mode, sampling the output signal Q of the master latch o for sampling, thereby changing the output signal D of the DFF j .

[0107] Specifically, considering that in the current control circuit 2, the current value can be driven to the tail current transistor through the ratio relationship between the switching transistors, and the resistance value of the adjustable load resistor can also be controlled by the current. Therefore, in the embodiment of the present invention, it is desired to simultaneously control the tail current transistor and the adjustable load resistor through the current control circuit 2. Therefore, the current control circuit 2 in the embodiment of the present invention includes a current generation circuit and a current mirror circuit. The current mirror circuit can copy the reference current generated by the current generation circuit and deliver the copied reference current to the corresponding adjustable load resistor and the tail current transistor respectively. On the one hand, the current value can be driven to the tail current transistor through the ratio relationship between the switching transistors, and on the other hand, the resistance value of the adjustable load resistor can be adjusted.

[0108] Among them, the embodiment of the present invention improves the reusability of the current control circuit 2, so that there is no need to set an additional resistance adjustment circuit, further reducing the circuit area and power consumption.

[0109] As an optional embodiment, the adjustable load resistor includes a load resistor and a first controllable switch connected in parallel with the load resistor.

[0110] Specifically, considering that when a first controllable switch is connected in parallel with the load resistor, the equivalent resistance value of the first controllable switch can be adjusted by controlling the first controllable switch, thereby adjusting the parallel resistance value of "the first controllable switch and the load resistor", realizing the adjustment of the resistance value of the adjustable load resistor, and the adjustable load resistor has the characteristics of simple structure and low cost.

[0111] Specifically, in Figure 3 and Figure 4 , both R1 and R2 are load circuits, and the controllable switches connected in parallel with the load resistor are all first controllable switches.

[0112] Of course, in addition to this specific form, the adjustable load resistor can also be in other various forms, which are not limited in the embodiment of the present invention.

[0113] As an optional embodiment, the current generation circuit includes a second controllable switch, a first resistor, and a third controllable switch;

[0114] The control terminal of the second controllable switch is connected to the output terminal of the control voltage. The first terminal of the second controllable switch is connected to the current mirror circuit. The second terminal of the second controllable switch is connected to the first terminal of the first resistor. The second terminal of the first resistor is respectively connected to the first terminal of the third controllable switch, the control terminal of the third controllable switch, and the current mirror circuit. The second terminal of the third controllable switch is connected to the current mirror circuit;

[0115] Wherein, the control voltage is used to adjust the current value of the reference current by controlling the opening degree of the second controllable switch.

[0116] Specifically, the current generation circuit in the above form has the advantages of simple structure and low cost.

[0117] Of course, in addition to the above specific form, the current generation circuit can also be of many other types, and the embodiments of the present invention do not limit this here.

[0118] As an optional embodiment, both the second controllable switch and the third controllable switch are metal-oxide-semiconductor field-effect transistors.

[0119] Specifically, MOSFET (Metal-Oxide-Semiconductor Field - Effect Transistor) has the advantages of fast response, small volume and low cost.

[0120] Of course, in addition to MOSFET, the second controllable switch and the third controllable switch can also be of other types, and the embodiments of the present invention do not limit this here.

[0121] As an optional embodiment, the data flip-flop 1 includes a master-slave data flip-flop;

[0122] The master-slave data flip-flop includes a master latch and a slave latch;

[0123] Both the master latch and the slave latch include a tail current tube, a signal latch circuit, and a load resistor;

[0124] Wherein, the signal latch circuit is respectively connected to the tail current tube and the load resistor.

[0125] Specifically, the master-slave data flip-flop has the characteristics of stable and reliable operation, strong anti-interference ability, and easy cascading.

[0126] Specifically, the master-slave data flip-flop includes a master latch and a slave latch, and both the master latch and the slave latch include a tail current tube, a signal latch circuit and a load resistor, so that the master-slave data flip-flop has the advantages of stable and reliable operation, strong anti-interference ability, and easy cascading.

[0127] Of course, in addition to the master-slave data flip-flop, the data flip-flop 1 can also be of other types. For example, it can be an edge-triggered data flip-flop 1 or a differential data flip-flop 1, etc. The embodiments of the present invention do not limit this here.

[0128] As an alternative embodiment, the signal latch circuit includes a first sub-controllable switch, a second sub-controllable switch, a third sub-controllable switch, a fourth sub-controllable switch, a fifth sub-controllable switch, and a sixth sub-controllable switch;

[0129] The control terminals of the first sub-controllable switch and the second sub-controllable switch are both connected to the signal output terminal of the previous stage. The first ends of the first sub-controllable switch and the second sub-controllable switch are respectively used to connect to the load resistors. The second ends of the first sub-controllable switch and the second sub-controllable switch are both connected to the first end of the fifth sub-controllable switch. The control terminals of the fifth sub-controllable switch and the sixth sub-controllable switch are both used to connect to the clock signal. The common terminal formed by the second end of the fifth sub-controllable switch and the second end of the sixth sub-controllable switch is connected to the corresponding tail current transistor. The control terminal of the third sub-controllable switch is connected to the first end of the second sub-controllable switch. The control terminal of the fourth sub-controllable switch is connected to the first end of the first sub-controllable switch. The first ends of the third sub-controllable switch and the fourth sub-controllable switch are both connected to the load resistors. The common terminal formed by the second end of the third sub-controllable switch and the second end of the fourth sub-controllable switch is connected to the first end of the sixth sub-controllable switch. The first ends of the third sub-controllable switch and the fourth sub-controllable switch together serve as the output terminal of the latch;

[0130] Among them, the trigger levels of the fifth sub-controllable switch and the sixth sub-controllable switch are high and low levels with respect to each other.

[0131] Specifically, the above specific form of the signal latch circuit has the advantages of simple structure, low cost, and strong stability.

[0132] Specifically, Figure 3 M1 to M6 in [[ ]] are the first sub-controllable switch to the sixth sub-controllable switch respectively.

[0133] Of course, in addition to the above specific form, the signal latch circuit can also be in other various forms. The embodiments of the present invention do not limit this here.

[0134] As an alternative embodiment, the buffer includes a tail current transistor, a signal buffer circuit, and a load resistor;

[0135] The signal buffer circuit is respectively connected to the tail current transistor and the load resistor.

[0136] Specifically, the buffer can include a tail current transistor, a signal buffer circuit, and a load resistor, and has the advantages of simple structure, small volume, and low power consumption.

[0137] Of course, in addition to this specific structure, the buffer can also have various other structures, which are not limited in the embodiments of the present invention.

[0138] As an alternative embodiment, the signal buffer circuit includes a fourth controllable switch and a fifth controllable switch;

[0139] The first end of the fourth controllable switch is connected to the first end of the fifth controllable switch; the second ends of the fourth controllable switch and the fifth controllable switch are respectively connected to a load resistor and serve as the output ends of the signal buffer circuit; the control ends of the fourth controllable switch and the fifth controllable switch are both connected to the output end of the signal to be compensated.

[0140] Specifically, this signal buffer circuit is composed of two controllable switches and has the advantages of simple structure, small volume, and low power consumption.

[0141] Of course, in addition to this specific form, the signal buffer circuit can also be of various other types, which are not limited in the embodiments of the present invention.

[0142] As an alternative embodiment, the forward equalizer is applied to inter-chip data communication in a server.

[0143] Specifically, considering the large demand for inter-chip data communication in a server, such as data communication between a CPU and various acceleration cards or storage devices, etc., the forward equalizer in the embodiments of the present invention can be applied to inter-chip data communication in a server.

[0144] Of course, in addition to inter-chip data communication in a server, the application scenarios of the forward equalizer can also be of various other types, such as inter-chip data communication in a data center, etc., which are not limited in the embodiments of the present invention.

[0145] As an alternative embodiment, the forward equalizer further includes a delay adjustment circuit;

[0146] The delay adjustment circuit is configured to generate exclusive sub-clock signals for each data flip-flop 1 based on the original clock signal;

[0147] Among them, in any two adjacent data flip-flops 1, the sub-clock signal of the subsequent data flip-flop 1 lags behind the sub-clock signal of the previous data flip-flop 1 by one delay period of the data flip-flop 1.

[0148] Specifically, considering the phase of the sub-clock signal received by the data trigger 1, the sampling position of the data trigger 1 in the signal to be compensated is determined, and different sampling positions affect the signal compensation accuracy. Through the phase control of the clock signal, the data trigger 1 can sample and process the signal to be compensated at the appropriate time, thereby ensuring the accuracy and consistency of the processing results of the data triggers 1 at each level. Therefore, in the embodiment of the present invention, according to the "delay period of the data trigger 1", based on the original clock signal, an exclusive sub-clock signal can be generated for each data trigger 1, wherein, in any two adjacent data triggers 1, the phase of the sub-clock signal of the rear-stage data trigger 1 lags behind that of the front-stage data trigger 1 by a delay period of the data trigger 1; thereby, the data trigger 1 can sample and process the signal to be compensated at the appropriate time, thereby ensuring the accuracy and consistency of the processing results of the data triggers 1 at each level.

[0149] The delay period of the data trigger 1 is usually based on the period of the clock signal, for example, it can be a single clock period, half a clock period, or a quarter of a clock period, etc., which is not limited in the embodiment of the present invention.

[0150] As an optional embodiment, the delay adjustment circuit includes a frequency division inversion circuit and a signal selection circuit;

[0151] A frequency division and inversion circuit, used for obtaining multiple standby clock signals by frequency division and inversion processing of the original clock signal;

[0152] The signal selection circuit is used to selectively obtain the sub-clock signal corresponding to each data trigger 1 according to the standby clock signal.

[0153] Specifically, considering that a plurality of spare clock signals with different phases can be obtained by dividing and inverting the original clock signal, and then the sub-clock signal corresponding to each data trigger 1 can be selectively obtained according to the spare clock signal through the signal selection circuit, the delay adjustment circuit in the embodiment of the present invention includes a frequency division and inversion circuit and a signal selection circuit. The frequency division and inversion circuit is used to obtain a plurality of spare clock signals by dividing and inverting the original clock signal, and the signal selection circuit is used to selectively obtain the sub-clock signal corresponding to each data trigger 1 according to the spare clock signal.

[0154] As an optional embodiment, the frequency division inversion circuit includes:

[0155] A frequency divider, used for generating a backup clock signal with phases of zero degree and ninety degrees by dividing the original clock signal by two.

[0156] An inverter is used to invert the sub-clock signal output by the frequency divider to generate standby clock signals with phases of 180 degrees and 270 degrees.

[0157] Specifically, considering that the standby clock signals obtained through a frequency divider and an inverter can meet the requirements of the sub-clock signal under most common "delay cycles of data flip-flop 1", in the embodiments of the present invention, the original clock signal can be divided by two through a frequency divider to generate standby clock signals with phases of 0 degrees and 90 degrees, and the inverter is used to invert the sub-clock signal output by the frequency divider to generate standby clock signals with phases of 180 degrees and 270 degrees. In this way, standby clock signals with phases of 0 degrees, 90°, 180°, and 270° are obtained, which meet the application scenarios where the "delay cycle of data flip-flop 1" is a single clock cycle, half a clock cycle, and a quarter of a clock cycle; and the combination of the frequency divider and the inverter has the advantages of simple structure and low cost.

[0158] Of course, in addition to this specific structure, the frequency division and inversion circuit can also be of other various types, which are not limited in the embodiments of the present invention.

[0159] As an alternative embodiment, the signal selection circuit includes a first selector, a second selector, a third selector, and a fourth selector;

[0160] The input terminals of the first selector are respectively connected to the first output terminal of the frequency divider and the first output terminal of the inverter. The input terminals of the second selector are respectively connected to the second output terminal of the frequency divider and the output terminal of the first selector. The input terminals of the third selector are respectively connected to the second output terminal of the frequency divider and the first output terminal of the inverter. The input terminals of the fourth selector are respectively connected to the output terminal of the third selector and the second output terminal of the frequency divider. The control terminals of the first selector and the third selector are both connected to the first control signal. The control terminals of the second selector and the fourth selector are both connected to the second control signal;

[0161] The first output terminal of the frequency divider is used to output a clock signal with a phase of 90 degrees. The second output terminal of the frequency divider is used to output a clock signal with a phase of 0 degrees. The first output terminal of the inverter is used to output a clock signal with a phase of 180 degrees. The second selector is used to output a first sub-clock signal. The fourth selector is used to output a second sub-clock signal.

[0162] Specifically, for a better description of the embodiments of the present invention, please refer to Figure 5 , Figure 5Schematic diagram of the structure of a delay adjustment circuit provided by the present invention, where Vctrl1 is the first control signal, Vctrl2 is the second control signal, clk is the original clock signal, clk1 is the first sub-clock signal, and clk2 is the second sub-clock signal.

[0163] Specifically, the signal selection circuit constructed by the above four selectors has the advantages of simple structure, small size and low cost.

[0164] Of course, in addition to the above specific structure, the signal selection circuit can also be of other various types, which are not limited in the embodiments of the present invention.

[0165] As an alternative embodiment, the first selector selects the clock signal at the first output terminal of the inverter when the received control signal is at a high level; the second selector selects the clock signal at the second output terminal of the frequency divider when the received control signal is at a low level; the third selector selects the clock signal at the first output terminal of the inverter when the received control signal is at a low level, and the fourth selector selects the clock signal at the second output terminal of the frequency divider when the received control signal is at a low level;

[0166] When the delay period of data flip-flop 1 is one clock signal period, the second control signal is at a low level;

[0167] When the delay period of data flip-flop 1 is half a clock signal period, both the first control signal and the second control signal are at a high level;

[0168] When the delay period of data flip-flop 1 is one-quarter of a clock signal period, the first control signal is at a low level and the second control signal is at a high level.

[0169] Specifically, through the control of the control signal in the above form, the generation of sub-clock signals in the scenarios where the "delay period of data flip-flop 1" is a single clock cycle, half a clock cycle, and one-quarter of a clock cycle can be accurately realized.

[0170] Specifically, for better illustration of the embodiments of the present invention, please refer to Figures 6 to 8 , Figure 6 Schematic diagram of the phase relationship between the first sub-clock signals provided by the present invention, Figure 7 Schematic diagram of the phase relationship between the second sub-clock signals provided by the present invention, Figure 8 Schematic diagram of the phase relationship between the third sub-clock signals provided by the present invention, Figures 6 to 8All include three sub-clock signals, that is, the sub-clock signals clk, clk1, and clk2 corresponding to the three data flip-flops 1 respectively. Among any two adjacent data flip-flops 1, for the subsequent data flip-flop 1 compared with the previous data flip-flop 1, the phase of the sub-clock signal lags behind by "one delay period of the data flip-flop 1". Figure 6 In it, "one delay period of the data flip-flop 1" is one clock signal period. Figure 7 In it, "one delay period of the data flip-flop 1" is half of the period of one clock signal. Figure 8 In it, "one delay period of the data flip-flop 1" is one-quarter of the clock signal period.

[0171] Specifically, to better illustrate the embodiments of the present invention, please refer to Table 1 below. Table 1 is a control signal and clock selection correspondence table. In the table, 1 of the control signal represents high level, and 0 represents low level.

[0172] Table 1

[0173]

[0174] The present invention also provides an inter-chip interconnection interface, including the forward equalizer in the foregoing embodiments.

[0175] For the introduction of the inter-chip interconnection interface provided by the present invention, please refer to the embodiments of the foregoing forward equalizer, and the embodiments of the present invention will not be elaborated here.

[0176] The present invention also provides a server, including the inter-chip interconnection interface in the foregoing embodiments.

[0177] For the introduction of the server provided by the present invention, please refer to the embodiments of the foregoing forward equalizer, and the embodiments of the present invention will not be elaborated here.

[0178] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. It should also be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising that element.

[0179] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A forward equalizer, characterized in that, Including: N data flip-flops connected in series and provided at the output end of the signal to be compensated, configured to sample and shape the received signal to be compensated based on the current of its own tail current transistor under the control of a clock signal, and multiply the signal to be compensated by a corresponding tap coefficient to adjust the amplitude of the signal to be compensated; wherein, N is a positive integer; Current control circuits corresponding to the data flip-flops one by one, configured to control the current value of the tail current transistors in the data flip-flops; An adder connected to the data flip-flops, configured to superimpose the output signals of the data flip-flops to obtain the compensated signal to be compensated; The feed-forward equalizer further includes: A preamble interference compensation circuit provided at the output end of the signal to be compensated and between the N data flip-flops connected in series, configured to multiply the signal to be compensated by a corresponding tap coefficient to compensate for the preamble interference of the signal to be compensated; Specifically, the adder is configured to superimpose the output signal of the preamble interference compensation circuit and the output signals of the data flip-flops to obtain the compensated signal to be compensated; The preamble interference compensation circuit includes: A buffer, configured to buffer the signal to be compensated and multiply the signal to be compensated by a corresponding tap coefficient based on the current of its own tail current transistor to adjust the amplitude of the signal to be compensated; A current control circuit connected to the buffer, configured to control the current value of the tail current transistor in the buffer; The load resistors in the buffer and the load resistors in the data flip-flops are both adjustable load resistors; The feed-forward equalizer further includes: A resistance value adjustment circuit connected to the adjustable load resistor, configured to adjust the resistance value of the adjustable load resistor; The current control circuit includes: A current generation circuit, configured to generate a reference current; A current mirror circuit, configured to copy the reference current and deliver the copied reference current to the corresponding adjustable load resistor and the tail current transistor respectively; wherein, the current mirror circuit serves as the resistance value adjustment circuit; The current generation circuit includes a second controllable switch, a first resistor, and a third controllable switch; The control end of the second controllable switch is connected to the output end of the control voltage, the first end of the second controllable switch is connected to the current mirror circuit, the second end of the second controllable switch is connected to the first end of the first resistor, the second end of the first resistor is respectively connected to the first end of the third controllable switch, the control end of the third controllable switch, and the current mirror circuit, and the second end of the third controllable switch is connected to the current mirror circuit; wherein, the control voltage is used to adjust the current value of the reference current by controlling the opening degree of the second controllable switch.

2. The forward equalizer according to claim 1, characterized in that, The adjustable load resistor includes a load resistor and a first controllable switch connected in parallel with the load resistor.

3. The forward equalizer according to claim 1, wherein Both the second controllable switch and the third controllable switch are metal-oxide-semiconductor field-effect transistors.

4. The forward equalizer according to claim 1, wherein The data flip-flop includes a master-slave data flip-flop; The master-slave data flip-flop includes a master latch and a slave latch; Both the master latch and the slave latch include a tail current transistor, a signal latching circuit, and a load resistor; Among them, the signal latch circuit is respectively connected to the tail current transistor and the load resistor.

5. The forward equalizer according to claim 4, characterized in that, The signal latch circuit includes a first sub-control switch, a second sub-control switch, a third sub-control switch, a fourth sub-control switch, a fifth sub-control switch and a sixth sub-control switch; The control terminals of the first sub-control switch and the second sub-control switch are both connected to the signal output terminal of the previous stage. The first ends of the first sub-control switch and the second sub-control switch are respectively used to connect the load resistor. The second ends of the first sub-control switch and the second sub-control switch are both connected to the first end of the fifth sub-control switch. The control terminals of the fifth sub-control switch and the sixth sub-control switch are both used to connect the clock signal. The common terminal formed by the second end of the fifth sub-control switch and the second end of the sixth sub-control switch is connected to the corresponding tail current transistor. The control terminal of the third sub-control switch is connected to the first end of the second sub-control switch. The control terminal of the fourth sub-control switch is connected to the first end of the first sub-control switch. The first ends of the third sub-control switch and the fourth sub-control switch are both connected to the load resistor. The common terminal formed by the second end of the third sub-control switch and the second end of the fourth sub-control switch is connected to the first end of the sixth sub-control switch. The first ends of the third sub-control switch and the fourth sub-control switch together serve as the output terminal of the latch; Among them, the trigger levels of the fifth sub-control switch and the sixth sub-control switch are high and low levels with respect to each other.

6. The forward equalizer according to claim 1, characterized in that, The buffer includes a tail current transistor, a signal buffer circuit and a load resistor; The signal buffer circuit is respectively connected to the tail current transistor and the load resistor.

7. The forward equalizer according to claim 6, wherein The signal buffer circuit includes a fourth control switch and a fifth control switch; The first end of the fourth control switch is connected to the first end of the fifth control switch; the second ends of the fourth control switch and the fifth control switch are respectively connected to the load resistor and serve as the output terminals of the signal buffer circuit; the control terminals of the fourth control switch and the fifth control switch are both connected to the output terminal of the signal to be compensated.

8. The forward equalizer according to claim 1, wherein The forward equalizer is applied to inter-chip data communication in a server.

9. The forward equalizer according to any one of claims 1 to 8, characterized in that, The forward equalizer further includes a delay adjustment circuit; The delay adjustment circuit is used to generate exclusive sub-clock signals for each data flip-flop based on the original clock signal; Among them, in any two adjacent data flip-flops, the sub-clock signal of the subsequent data flip-flop lags behind the sub-clock signal of the previous data flip-flop by one delay period of the data flip-flop.

10. The forward equalizer according to claim 9, characterized in that, The delay adjustment circuit includes a frequency division and inversion circuit and a signal selection circuit; The frequency division and inversion circuit is used to obtain a plurality of standby clock signals by performing frequency division and inversion processing on the original clock signal; The signal selection circuit is used to selectively obtain the sub-clock signals corresponding to each data flip-flop according to the standby clock signals.

11. The forward equalizer according to claim 10, wherein The frequency division and inversion circuit includes: A frequency divider for generating standby clock signals with phases of zero degrees and ninety degrees by dividing the original clock signal by two; An inverter, which is used to invert the sub-clock signal output by the frequency divider to generate standby clock signals with phases of 180 degrees and 270 degrees.

12. The forward equalizer according to claim 11, wherein The signal selection circuit includes a first selector, a second selector, a third selector, and a fourth selector; The input terminals of the first selector are respectively connected to the first output terminal of the frequency divider by two and the first output terminal of the inverter. The input terminals of the second selector are respectively connected to the second output terminal of the frequency divider by two and the output terminal of the first selector. The input terminals of the third selector are respectively connected to the second output terminal of the frequency divider by two and the first output terminal of the inverter. The input terminals of the fourth selector are respectively connected to the output terminal of the third selector and the second output terminal of the frequency divider by two. The control terminals of the first selector and the third selector are both connected to a first control signal. The control terminals of the second selector and the fourth selector are both connected to a second control signal; The first output terminal of the frequency divider by two is used to output a clock signal with a phase of 90 degrees. The second output terminal of the frequency divider by two is used to output a clock signal with a phase of 0 degree. The first output terminal of the inverter is used to output a clock signal with a phase of 180 degrees. The second selector is used to output a first sub-clock signal. The fourth selector is used to output a second sub-clock signal.

13. The forward equalizer according to claim 12, characterized in that, The first selector selects the clock signal at the first output terminal of the inverter when the received control signal is at a high level; the second selector selects the clock signal at the second output terminal of the frequency divider by two when the received control signal is at a low level; the third selector selects the clock signal at the first output terminal of the inverter when the received control signal is at a low level, and the fourth selector selects the clock signal at the second output terminal of the frequency divider by two when the received control signal is at a low level; When the delay period of the data flip-flop is one clock signal period, the second control signal is at a low level; When the delay period of the data flip-flop is half a clock signal period, both the first control signal and the second control signal are at a high level; When the delay period of the data flip-flop is one-fourth of a clock signal period, the first control signal is at a low level and the second control signal is at a high level.

14. An inter-chip interconnect interface, characterized in that, It includes the forward equalizer according to any one of claims 1 to 13.

15. A server, characterized in that, It includes the inter-chip interconnection interface according to claim 14.

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