Multi-memory plane commands

Abstract

The invention relates to a multi-memory plane command. In one embodiment, a method includes sending, by a controller, a command to perform an operation on a plurality of memory planes of a memory device, and performing the operation on the plurality of memory planes in response to the command without sending an additional command.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly to multi-memory plane commands. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present disclosure provides a method for multi-memory plane commands, which includes: sending, by a controller, a command for performing an operation on multiple memory planes of a memory device; and performing the operation on the multiple memory planes in response to the command and without the controller sending an additional command.

[0004] In another aspect, the present disclosure provides a device for multi-memory plane commands, which includes: a controller configured to: send a command for performing a read operation on a first memory plane and a second memory plane to the memory device; receive a data signal corresponding to the first memory plane; send a clock signal to the memory device after completing the read operation on the first memory plane; receive a dummy signal from the memory device in response to the clock signal; and receive a data signal corresponding to the second memory plane without sending an intermediate command to the memory device.

[0005] In another aspect, the present disclosure provides a system for multi-memory plane commands, which includes: a memory subsystem including a non-volatile memory device; and a processing device coupled to the memory subsystem, wherein the processing device is configured to: identify a first memory plane and a second memory plane from multiple memory planes of a common bus coupled to the memory device; send a command for performing a sequential read command on the first memory plane and the second memory plane among the multiple memory planes; receive a data signal associated with the first memory plane; send a dummy clock signal to the memory device after completing the command for the first memory plane; receive a dummy signal in response to the dummy clock signal; and receive a data signal associated with the second memory plane after completing the reception of the dummy signal. Brief Description of the Drawings

[0006] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 2 A system for providing multi - memory - plane commands according to some embodiments of the present disclosure is shown.

[0009] Figure 3 A system for providing multi - memory - plane commands according to some embodiments of the present disclosure is shown.

[0010] Figure 4 A timing diagram of multi - memory - plane commands according to some embodiments of the present disclosure is shown.

[0011] Figure 5 A flowchart of a method for providing multi - memory - plane commands according to some embodiments of the present disclosure is shown.

[0012] Figure 6 is a block diagram of an example computer system operable to implement embodiments of the present disclosure. Detailed Description

[0013] Aspects of the present disclosure relate to a controller providing multi - memory - plane commands and, more particularly, to a memory subsystem including multi - memory - plane command components. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system such as a solid - state drive (SSD). Examples of storage devices and memory modules are described below in connection with Figure 1 and elsewhere. Generally, a host system can utilize a memory subsystem that includes one or more components such as memory devices that store data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0014] The memory device can be a non - volatile memory device. An example of a non - volatile memory device is a "NAND" memory device (also known as flash technology). As used herein, a NAND memory device can include a collection of flash memory dies or a combination of flash memory dies and a non - volatile memory (NVM) controller. The NVM controller can include circuitry for performing read / write operations as described herein. Below in connection with Figure 1Describe other examples of non-volatile memory devices. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes (e.g., memory planes). A plane can be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a block refers to the unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or a single memory cell. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest erasable area. A page cannot be erased individually, and only an entire block can be erased.

[0015] Each of the memory devices can include one or more memory cell arrays. Depending on the cell type, a cell can be written to store binary information of one or more bits and have various logical states related to the number of bits being stored. The logical states can be represented by binary values such as "0" and "1" or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one bit of information and has two logical states.

[0016] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage change between a bit line and a word line. Other examples of NAND memory devices can employ a replacement gate architecture that can include using a word line layout that can allow charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0017] In some prior methods, a memory device, such as a NAND memory device, can utilize circuitry to couple multiple memory planes to a connection interface. In some prior methods, a controller can utilize a first command to perform a first operation on a first memory plane and a second command to perform a second operation on a second memory plane. In these prior methods, a sequential read operation of data stored on the first memory plane and the second memory plane can be performed using a first command signal and a second command signal. Thus, due to performing sequential read operations or other types of operations across multiple memory planes using multiple commands, the performance of the memory device may degrade.

[0018] Aspects of the present disclosure address the above and other deficiencies by the controller employing multi - memory - plane commands. For example, the present disclosure can perform operations for multiple memory planes using a single command, rather than using a corresponding command for each operation associated with the multiple memory planes. In this way, the amount of time associated with operations for multiple memory planes can be reduced, and memory device performance can be improved. In some embodiments, a host or controller may send a single command signal to the memory device. The single command signal may include instructions to perform sequential read operations on a first memory plane and a second memory plane. That is, in the absence of additional command signals to read data from multiple memory planes, a single command signal can be used to perform sequential read operations on multiple memory planes. In this example, the controller may send multiple clock signals during a period when the memory device switches between operations from the first memory plane to the second memory plane. In response to the multiple clock signals, the memory device may provide dummy data to the host or controller. In this way, the number of commands can be reduced from multiple commands associated with multiple memory planes to a single command associated with the multiple memory planes. Thus, the amount of time typically used to generate the multiple commands employed by prior methods can be reduced to the amount of time used to generate a single command, as described herein.

[0019] Figure 1 FIG. 1 illustrates an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non - volatile memory devices (e.g., memory device 130), or a combination thereof.

[0020] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid - state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in - line memory modules (DIMMs), small DIMMs (SO - DIMMs), and various types of non - volatile dual in - line memory modules (NVDIMMs).

[0021] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include but are not limited to a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1The memory subsystem 110 is shown as an example. In general, a host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., the memory device 130) include "NAND" (Negative AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change in bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130, 140 can include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these memory cell arrays. In some embodiments, a particular memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 can be grouped into pages, which can refer to logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0028] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND type memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 can be based on any other type of non-volatile memory or storage device such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] As described above, the memory component can be a memory die or a memory package that forms at least a part of memory device 130. In some embodiments, memory cell blocks can form one or more "super blocks". As used herein, a "super block" generally refers to a collection of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks can be deployed across multiple memory dies having multiple planes and / or pages associated therewith. In the context of the present disclosure, the terms "super block", "block", "memory cell block", and / or "interleaved NAND block" and variations thereof can be used interchangeably.

[0030] Memory subsystem controller 115 (or simply controller 115) can communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130, and other such operations. Memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. Memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] Memory subsystem controller 115 can be a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110 (including handling communication between memory subsystem 110 and host system 120).

[0032] In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although Figure 1 the example memory subsystem 110 in has been shown as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) associated with the memory device 130 and physical addresses (e.g., physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0034] In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130 and / or the memory device 140. For example, in some embodiments, the memory device 140 may be a DRAM and / or SRAM configured to act as a cache for the memory device 130. In this case, the memory device 130 may be NAND.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., the local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. The memory subsystem 110 may also include additional circuitry or components not shown.

[0036] The memory subsystem 110 may include a multi-memory plane command component 113, which may alternatively be referred to herein as a "controller". Although not shown in Figure 1 to avoid confusing the drawings, the multi-memory plane command component 113 may include various circuitry to facilitate aspects of multi-memory plane commands, as detailed herein. In some embodiments, the multi-memory plane command component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow the multi-memory plane command component 113 to arrange and / or execute the operations described herein.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the multi-memory plane command component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, the multi-memory plane command component 113 is part of the memory subsystem 110, an application, or an operating system.

[0038] In a non-limiting example, a device (e.g., the computing system 100) may include the multi-memory plane command component 113. The multi-memory plane command component 113 may reside on the memory subsystem 110. As used herein, the term "reside on" means that something is physically located on a particular component. For example, the multi-memory plane command component 113 "residing on the memory subsystem 110" means that the hardware circuitry including the multi-memory plane command component 113 is physically located on the memory subsystem 110. The term "reside on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0039] As referred to herein with respect to Figure 2 and Figure 3Further described, the memory subsystem 110 may include circuitry that can partition a certain amount of memory resources into multiple memory planes. As used herein, a memory plane (e.g., a NAND plane, etc.) refers to a specific subset of memory cells within a memory device. A NAND flash memory chip typically contains multiple planes, each consisting of a two-dimensional array of memory cells. In some embodiments, each memory plane is substantially a separate layer within the NAND flash memory chip, having its own set of word lines and bit lines that enable data storage and access. Memory cells within a plane can be organized into blocks and pages, where a block is a group of memory cells and a page is the smallest unit of data that can be read or programmed. In some embodiments, having multiple planes in a NAND flash memory chip can improve parallelism and overall performance. In the case of multiple planes, the memory controller can perform simultaneous operations, such as read, write, or erase, on different planes, which allows for higher data transfer rates and enhanced overall system performance.

[0040] By partitioning memory cells into planes, it is possible to perform operations independently on each plane, thereby reducing access latency and improving overall efficiency. It also allows for a more efficient implementation of features such as wear leveling, where erase and program operations are evenly distributed across the planes to extend the lifespan of the NAND flash memory.

[0041] In some embodiments, each of the multiple memory planes may include a specific amount of memory resources (e.g., capable of storing a specific number of bits, etc.). In these embodiments, circuitry can be used to couple the multiple memory planes to multiple electrical buses, which are coupled to electrical pads. In some embodiments, the host system 120 or the controller can access the multiple memory planes through the electrical pads and / or the multiple electrical buses. As used herein, an electrical bus or a memory bus refers to a communication path or interface through which data is transferred between the memory subsystem and other components within a computer system. The electrical bus can act as a channel for connecting a memory module or chip to the memory controller, thereby allowing for data exchange and access.

[0042] As described herein, the plurality of memory planes may include a first memory plane that is separate and distinct from a second memory plane. In these embodiments, additional memory planes may exist. For example, a memory system may include six separate and distinct memory planes. Although the examples herein describe six memory planes, additional memory planes may be utilized without departing from the present disclosure. In some embodiments, the first memory plane and the second memory plane are each coupled to circuitry that connects the first memory plane and the second memory plane to a common bus. In some embodiments, each plane within a NAND flash memory chip operates autonomously, and a memory controller coordinates and manages activities across all planes to ensure proper data access and storage. In some embodiments, the first memory plane and the second memory plane are sequentially coupled such that the last cell of the first memory plane and the first cell of the second memory plane are sequentially coupled to hardware. That is, in some embodiments, the first memory plane and the second memory plane are independent memory planes that are serially coupled to the circuitry of a memory device. An independent memory plane refers to a memory plane that is not dependent on another memory plane.

[0043] The multi-memory plane command component 113 may be configured to send commands for performing read operations on the first memory plane and the second memory plane to the memory device. As described herein, the read operation may be a sequential read operation. As used herein, a sequential read operation includes the process of reading data from consecutive memory locations in a continuous manner. It involves retrieving data from memory cells in sequential order without additional overhead or latency between each read operation. As described herein, the present disclosure describes how sequential read operations may be performed across multiple memory planes without utilizing additional commands for each of the multiple memory planes. During a sequential read operation, the memory controller reads data from one memory location and then automatically moves to the next adjacent location to read subsequent data. This process continues until the desired amount of data has been retrieved or until a specific termination condition is met. In this manner, data may be read from the last cell of the first memory plane and then automatically moved to the first cell location of the second memory plane.

[0044] In some embodiments, the command is a single command that identifies the first memory plane and the second memory plane for a sequential read operation. As described herein, a previous sequential read operation may automatically move from a first location within a particular (individual) memory plane to an adjacent location. The present disclosure provides a sequential read operation that automatically moves from the first memory plane to the second memory plane without an intermediate command. Thus, a single command may be utilized to perform a sequential read operation that includes data from the first memory plane and the second memory plane.

[0045] In some embodiments, the command includes a switching command for switching from a first memory plane to a second memory plane without an intermediate command. As used herein, the switching command may indicate that a switch from the first memory plane to the second memory plane will be performed to allow an ordered read operation to be automatically performed. In some embodiments, the switching command may be an inherent command that can be initiated in response to a start cell position and an end cell position. For example, a start cell position within the first memory plane and an end cell position within the second memory plane may indicate the presence of a switching command. In some embodiments, the command includes an ordered read of a first portion of the first memory plane and a second portion of the second memory plane. In some embodiments, the first portion includes a part of the first memory plane. The first portion of the first memory plane may include an end portion of the first memory plane such that the second portion of the second memory plane abuts the first portion of the first memory plane. In this way, an ordered read operation can be performed on the first portion of the first memory plane and then automatically switched to the second memory plane to sequentially read the second portion of the second memory plane.

[0046] In some embodiments, the multi-memory plane command component 113 is configured to send a command in response to a determination that the first memory plane and the second memory plane are sequential memory planes. In some embodiments, the multi-memory plane command component 113 may determine when an ordered read operation includes data from the first memory plane and the second memory plane that are sequential memory planes. In these embodiments, the multi-memory plane command component 113 may generate a single command that includes the address locations of the first portion of the first memory plane and the second portion of the second memory plane. In this way, an ordered operation, such as an ordered read operation, of the first portion and the second portion can be implemented or performed using a single command without using an intermediate command.

[0047] The multi-memory plane command component 113 may be configured to receive a data signal corresponding to the first memory plane. In these embodiments, the multi-memory plane command component 113 may receive a data signal corresponding to the stored data of the first memory plane. In some embodiments, the received data signal may correspond to a clock signal provided by the multi-memory plane command component 113.

[0048] The multi - memory - plane command component 113 can be configured to send a clock signal to the memory device after completion of a read operation on a first memory plane. Compared to previous embodiments where a second command would be sent by the controller after completion of the read operation on the first memory plane, the multi - memory - plane command component 113 can continue to send the clock signal during a transition period from the first memory plane to the second memory plane. In some embodiments, the amount of the clock signal can be determined based on the amount of time it takes for a particular memory device to switch from the first memory plane to the second memory plane. In this way, the clock signal can be provided for a duration corresponding to the duration it takes to switch from providing data from the first memory plane to providing data from the second memory plane.

[0049] The multi - memory - plane command component 113 can be configured to receive a dummy signal from the memory device in response to the clock signal. In some embodiments, the dummy signal represents dummy data that is not associated with the data stored by the first memory plane or the second memory plane. The dummy signal can be a signal in response to the clock signal provided by the multi - memory - plane command component 113 during the transition from the first memory plane to the second memory plane. In these embodiments, the multi - memory - plane command component 113 can ignore or skip the dummy signal. In some embodiments, the multi - memory - plane command component 113 can identify the dummy signal as a response signal to the clock signal generated by the multi - memory - plane command component 113.

[0050] The multi - memory - plane command component 113 can be configured to receive a data signal corresponding to the second memory plane without sending an intermediate command to the memory device. As described herein, when the memory device has switched from the first memory plane to the second memory plane, the multi - memory - plane command component 113 can continue to send the clock signal. In this way, when the memory device has completed the switch, the multi - memory - plane command component 113 will start receiving the data signal corresponding to the second memory plane.

[0051] Figure 2 A system 221 for providing multi - memory - plane commands according to some embodiments of the present disclosure is shown. The system 221 can include circuitry that can be used to connect multiple memory devices and / or memory planes to a host or host system. In some embodiments, the system 221 includes a top pad (pad_top) 222. In some embodiments, the top pad 222 can include the top - side pads or electrical contacts of a NAND device. The top pad 222 can be a physical interface through which the memory device communicates with an external device, such as a memory controller or a host system.

[0052] The solder pad 222 can act as a connection point for transmitting electrical signals, including data, control signals, and power, between the NAND flash chip and an external circuit system. It is typically a metal contact area located on the top surface of the NAND chip package. In some embodiments, the solder pad 222 can be coupled to a plurality of string drivers 223. The string drivers 223 can act as an interface between the memory controller and the NAND strings. In some embodiments, the string drivers 223 can adjust the voltage levels applied to the memory cells within the strings during read, program, and erase operations. The string drivers 223 ensure that the appropriate voltages are applied to the selected memory cells, enabling data storage, retrieval, and manipulation.

[0053] In some embodiments, the solder pad 222 can be coupled to a plurality of repeaters (RPT) 224. In some embodiments, the plurality of repeaters 224 can be used to prevent signal degradation between the memory plane and the solder pad 222. For example, the repeaters can be used to compensate for signal degradation or attenuation that occurs due to long interconnect lines or high capacitive loads within the memory system. It can be a circuit element that amplifies and regenerates the signal to ensure its integrity and reliability during data transmission. By compensating for signal attenuation, distortion, and timing issues, the repeaters enable reliable data transmission and improve the overall performance of the NAND device. It helps maintain signal integrity, reduce data errors, and ensure that the transmitted signals can be accurately received and processed by the memory controller or the host system.

[0054] Figure 3 A system 331 for providing multi-memory plane commands is shown in accordance with some embodiments of the present disclosure. In some embodiments, the system 331 utilizes Figure 2 the system 221 mentioned therein. For example, the system 331 can show a plurality of memory planes 332-0, 332-1, 332-2, 332-3, 332-4, 332-5 (referred to herein as memory planes 332), which are coupled to the solder pad 222 through a plurality of repeaters 224 and / or string drivers 223.

[0055] Figure 3A system including six memory planes 332 is shown. However, a greater or fewer number of memory planes may be utilized without departing from the present disclosure. In some embodiments, the multiple memory planes are sequentially numbered to identify sequentially connected memory planes. That is, plane 332-1 may be sequentially connected to plane 332-2. In this example, the end position or end bit of plane 332-1 may be sequentially connected to the start position or start bit of plane 332-2. In this way, plane 332-1 may be the first plane and plane 332-2 may be the second plane. In some embodiments, the first plane may be plane 332-0 and the second plane may be plane 332-2. In these embodiments, sequential read operations may be performed on planes 332-0, 332-1, and 332-2.

[0056] In some embodiments, a sequential read operation may be performed on multiple sequentially connected memory planes 332 using a single command signal. For example, a sequential read operation may be performed on planes 332-0 (P0), 332-1 (P1), 332-2 (P2), 332-3 (P3), 332-4 (P4), and 332-5 (P5) without an intermediate command signal between the multiple planes 332. In this way, a single command signal may be used to perform sequential commands on sequential memory planes among the multiple planes 332.

[0057] Figure 4 A timing diagram 441 of a multi-memory plane command according to some embodiments of the present disclosure is shown. The signal timing diagram may include a clock signal (dqs) 442, a column signal 443, a plane designation signal 444, and a data signal (dq) 445. The clock signal 442 may represent the clock signal provided by a host or a host controller. For example, the clock signal 442 may be a clock signal generated by the multi-memory plane command component 113 mentioned in Figure 1 As shown in Figure 4 When the plane designation signal 444 switches from a first plane (e.g., plane N) to a second plane (e.g., plane N+1), the clock signal 442 may remain constant.

[0058] The column signal may identify a request signal for a particular portion of the first plane corresponding to a particular clock signal. In some embodiments, a plane may include 1851 columns that may correspond to data stored by the plane. In some embodiments, the plane designation signal 444 may indicate which plane is being read via a read operation. In some embodiments, the data signal 445 may represent data provided by the memory resource in response to the column signal 443.

[0059] At 446, timing diagram 441 shows when plane N is read via a sequential read operation. In some embodiments, the column signals request bits 0 through 1851 of plane N, and the data signals 445 or responses are from A to Z. Thus, at 446, timing diagram 441 shows a read operation on plane N. At 447, the timing diagram shows a transition period when the memory device switches from plane N to plane N+1. As described herein, the transition period shown at 447 includes clock signal 442, and the response from the memory device shown by data signal 445 includes dummy data that does not correspond to the data stored by the memory device.

[0060] After completion of 447, timing diagram 441 moves to 448. At 448, clock signal 442 remains consistent with 447. The column signals 443 now correspond to the respective columns of plane N+1, and the data signals 445 correspond to the data a through z stored by plane N+1. In this way, a single operation command can allow an operation to be performed on plane N of the memory device, where the transition period is at 447 to allow an operation to be performed on plane N+1 of the memory device.

[0061] Figure 5 A flowchart showing a method 551 for providing multi-memory plane commands according to some embodiments of the present disclosure. Method 551 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 551 is executed by Figure 1 the multi-memory plane command component 113. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may occur in a different order and some processes may occur in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, all processes are not required in every embodiment. Other process flows are possible.

[0062] At operation 552, method 551 may be executed to send, by a controller, a command for performing an operation on multiple memory planes of a memory device. As described herein, a command may be an instruction or signal for performing a particular operation. In some embodiments, the command is a sequential read command for multiple memory planes. In these embodiments, the multiple memory planes are sequential memory planes. For example, the command may be an instruction for performing a sequential read operation on data stored on multiple memory planes. In these embodiments, the multiple memory planes may be sequentially connected memory planes. In this way, the command can be used to perform an operation on multiple memory planes without providing an intermediate command.

[0063] At operation 553, method 551 may be executed to perform an operation on multiple memory planes in response to a command without sending an additional command. As used herein, not sending an additional command means not sending an additional command or not sending any intermediate commands. As described herein, the operation may be a sequential read operation performed on multiple memory planes without having to send an additional command to switch from a first memory plane among the multiple memory planes to a second memory plane among the multiple memory planes. In some embodiments, the controller may continue to send a clock signal during a switch between multiple memory planes. For example, the controller may send a clock signal, and a memory device associated with the multiple memory planes may respond with dummy data or data not associated with the stored data of the memory plane back to the controller during a switch between a first memory plane and a second memory plane.

[0064] That is, in some embodiments, method 551 may be executed to send multiple clock signals to a memory device between performing an operation on a first memory plane among multiple memory planes and performing an operation on a second memory plane among the multiple memory planes. In these embodiments, method 551 may be executed to receive dummy data at the controller in response to the multiple clock signals. In some embodiments, the multiple clock signals are based on an amount of time for switching between receiving a data signal from a first memory plane and receiving a data signal from a second memory plane. As described herein, the multiple memory planes may be independent NAND memory planes coupled to corresponding electrical buses. In these embodiments, the corresponding electrical buses may be coupled to electrical pads.

[0065] In other embodiments, method 551 may be executed by a processing device of a system to identify a first memory plane and a second memory plane from multiple memory planes coupled to a common bus of a memory device. As described herein, the processing device or controller may identify when the first memory plane and the second memory plane are sequentially connected memory planes and / or contain data stored sequentially by the memory planes. In this way, the address locations of the data stored by the first memory plane and the second memory plane may be identified as stored sequentially, and a command identifying the sequentially stored data may be generated.

[0066] In other embodiments, method 551 may be executed by a processing device of a system to send commands for performing sequential read commands on a first memory plane and a second memory plane among a plurality of memory planes. In some embodiments, the commands include instructions for switching a communication path to a common bus from the first memory plane to the second memory plane after completion of the read command for the first memory plane. In this way, data provided by the memory device may be automatically switched from the first memory plane to the second memory plane after completion of the read command for the first memory plane. In some embodiments, the range of address locations of the commands may indicate the read portions of the first memory plane and the second memory plane as a single sequential read operation to indicate the switch from the first memory plane to the second memory plane.

[0067] In other embodiments, method 551 may be executed by a processing device of a system to receive a data signal associated with a first memory plane. As described herein, a command may be an instruction for performing a sequential read operation or other type of operation, where the memory device responds with a data signal. In this example, the command may be an instruction for performing a sequential read operation on data stored by the first memory plane and the second memory plane. In this way, the processing device of the system may receive a data signal associated with the first memory plane. That is, the processing device of the system may receive a data signal corresponding to data stored by the first memory plane.

[0068] In other embodiments, method 551 may be executed by a processing device of a system to send a dummy clock signal to the memory device after completion of the read command for the first memory plane. In some embodiments, the dummy clock signal may be a clock signal generated by the processing device and sent to the memory device without being associated with a request for data from the memory device. As described herein, the dummy clock signal may be a clock signal sent to the memory device during a transition period when the memory device switches from the first memory plane to the second memory plane. In some embodiments, the amount of the dummy clock signal may be calculated or determined based on the amount of time it takes for the memory device to switch from the first memory plane to the second memory plane. In this way, when the memory device has completed switching from the first memory plane to the second memory plane, the processing device may start sending a regular clock signal and a data request signal from the second memory plane.

[0069] In other embodiments, method 551 may be performed by a processing device of a system to receive a dummy signal in response to a dummy clock signal. As described herein, the dummy clock signal may be sent to a memory device, and the memory device may respond to the dummy clock signal with a dummy data signal or a dummy signal. As used herein, a dummy signal or a dummy data signal may be a signal generated by the memory device that does not correspond to data stored by the memory device. In some embodiments, the dummy clock signal may be sent to the memory device, and the memory device may respond with a dummy signal without changing the performance of the memory device. In some embodiments, the processing device may send an instruction to the memory device to ignore the dummy clock signal. For example, the processing device may send an instruction to notify the memory device that the dummy clock signal is not associated with a data request from the memory device. In these embodiments, the processing device may ignore the dummy data or the dummy signal received from the memory device.

[0070] In other embodiments, method 551 may be performed by a processing device of a system to receive a data signal associated with a second memory plane after receiving the dummy signal. As described herein, when the memory device switches from a first memory plane to a second memory plane, the processing device may receive a data signal associated with the second memory plane. In this way, the processing device may determine when the dummy clock signal has completed and when to receive a data signal associated with the second memory plane. For example, when a specific amount of the dummy clock signal has been sent, the processing device may determine that the dummy clock signal has completed. As described herein, a specific amount of the dummy clock signal may be sent to allow the memory device to switch from the first memory plane to the second memory plane.

[0071] Figure 6 is a block diagram of an example computer system operable to implement embodiments of the present disclosure. For example, Figure 6 illustrates an example machine of a computer system 600 within which instructions may be executed for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 memory subsystem 110) or may be used to perform the operations of a controller (e.g., executing an operating system to perform operations corresponding to Figure 1operation of the multi-memory plane command component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0072] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0073] Example computer system 600 includes a processing device 602, a main memory 604 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 618, which communicate with each other via a bus 630.

[0074] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, etc. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via network 620.

[0075] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting a machine-readable storage medium. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 the memory subsystem 110.

[0076] In one embodiment, the instructions 626 include instructions for implementing the functionality corresponding to a multi-memory plane command component (e.g., Figure 1 the multi-memory plane command component 113). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0077] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. In this specification, and in general, an algorithm is conceived to be a self-consistent sequence of operations that produce a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0078] However, it should be borne in mind that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0079] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0080] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various such systems will be presented as will be shown in the description below. Additionally, the present disclosure has been described without reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0081] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).

[0082] In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc. In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method (551) for multi-memory plane commands, comprising: A controller (115) sends a command for performing an operation on a plurality of memory planes (332-0, 332-1, 332-2, 332-3, 332-4) of a memory device (130); and The operations are performed on the plurality of memory planes (332-0, 332-1, 332-2, 332-3, 332-4) in response to the command and without the controller (115) sending additional commands.

2. The method according to claim 1, further comprising: sending a plurality of clock signals to the memory device between performing the operation on a first memory plane of the plurality of memory planes and performing the operation on a second memory plane of the plurality of memory planes; and Dummy data is received at the controller in response to the plurality of clock signals, wherein the plurality of clock signals are based on an amount of time to switch between receiving data signals from the first memory plane and receiving data signals from the second memory plane.

3. The method of claim 1, wherein the plurality of memory planes are independent NAND memory planes coupled to corresponding electrical buses, and wherein the corresponding electrical buses are coupled to electrical pads.

4. The method of claim 1, wherein the command is a sequential read command of the plurality of memory planes, and wherein the plurality of memory planes are sequential memory planes.

5. An apparatus for multi-memory plane commands, comprising: A controller (115) configured to: sending a command for performing a read operation on a first memory plane (332-0, 332-1, 332-2, 332-3, 332-4) and a second memory plane (332-0, 332-1, 332-2, 332-3, 332-4) to a memory device (130); receiving a data signal corresponding to the first memory plane (332-0, 332-1, 332-2, 332-3, 332-4); sending a clock signal to the memory device (130) after completing the read operation on the first memory plane (332-0, 332-1, 332-2, 332-3, 332-4); receiving a dummy signal from the memory device (130) in response to the clock signal; and A data signal corresponding to the second memory plane (332-0, 332-1, 332-2, 332-3, 332-4) is received without sending an intermediate command to the memory device (130).

6. The apparatus of claim 5, wherein the first memory plane and the second memory plane are independent memory planes that are sequentially coupled to circuitry of the memory device.

7. The apparatus of claim 5, wherein the dummy signal represents dummy data that is not associated with data stored by the first memory plane or the second memory plane.

8. The apparatus of claim 5, wherein the controller is further configured to send the command in response to determining that the first memory plane and the second memory plane are sequential memory planes.

9. The apparatus of claim 5, wherein the command is a single command that identifies the first memory plane and the second memory plane for a sequential read operation.

10. The apparatus of claim 5, wherein the command comprises a switch command for switching from the first memory plane to the second memory plane without an intervening command.

11. The apparatus of claim 5, wherein the command comprises a sequential read of a first portion of the first memory plane and a second portion of the second memory plane.

12. The apparatus of claim 5, wherein the first memory plane and the second memory plane are individually coupled to circuitry that connects the first memory plane and the second memory plane to a common bus.

13. A system (221, 331) for multi-memory plane commands, comprising: a memory subsystem (110) comprising a non-volatile memory device (130); and a processing device (117) coupled to the memory subsystem (110), wherein the processing device (117) is configured to: identifying a first memory plane (332-0, 332-1, 332-2, 332-3, 332-4) and a second memory plane (332-0, 332-1, 332-2, 332-3, 332-4) from a plurality of memory planes (332-0, 332-1, 332-2, 332-3, 332-4) coupled to a common bus (222, 630) of a memory device (130); sending a command for executing a sequential read command on a first memory plane (332-0, 332-1, 332-2, 332-3, 332-4) and the second memory plane (332-0, 332-1, 332-2, 332-3, 332-4) of the plurality of memory planes (332-0, 332-1, 332-2, 332-3, 332-4); receiving a data signal associated with the first memory plane (332-0, 332-1, 332-2, 332-3, 332-4); sending a dummy clock signal to the memory device after completing the command of the first memory plane (332-0, 332-1, 332-2, 332-3, 332-4); receiving a dummy signal in response to the dummy clock signal; and After completing receiving the dummy signal, a data signal associated with the second memory plane (332-0, 332-1, 332-2, 332-3, 332-4) is received.

14. The system of claim 13, wherein the processing device is further configured to send an instruction to the memory device to ignore the dummy clock signal.

15. The system of claim 13, wherein the command comprises instructions for switching a communication path to the common bus from the first memory plane to the second memory plane upon completion of the sequential read command of the first memory plane.

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