Expander device channel locking for memory devices

Abstract

The invention relates to extender device channel locking for memory devices. A method includes receiving, by a memory device interface, a signal from a host at a front side of a command enabled channel; locking, by the memory device interface, a back side of a command enabled channel in response to the signal; receiving, by the memory device interface, a command from the host at a data channel; and unlocking, by the memory device interface, the backside of the command enabled channel in response to receiving the command at the data channel.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to expander device channel locking of memory devices. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] Embodiments of the present disclosure provide a method for expander device channel locking, which includes: receiving, by a memory device interface, a signal from a host at a front side of a command enable channel, where the signal indicates that a command is to be received; locking, by the memory device interface in response to the signal, a rear side of the command enable channel; receiving, by the memory device interface, the command from the host at a data channel; and unlocking, by the memory device interface in response to receiving the command at the data channel, the rear side of the command enable channel.

[0004] Another embodiment of the present disclosure provides an apparatus for expander device channel locking, which includes: a plurality of memory dies; and a memory device interface for communicating between a host that can be coupled to the memory device interface and the plurality of memory dies, where the memory device interface includes a controller configured to: identify a low-to-high transition signal at a front side of a command enable channel; lock, in response to identifying the low-to-high transition signal, a rear side of the command enable channel; start a command timer to determine when a threshold amount of time has elapsed since receiving the low-to-high transition signal; and unlock, in response to receiving a command at the data channel within the threshold amount of time, the rear side of the command enable channel.

[0005] Another embodiment of the present disclosure provides a system for expander device channel locking, which includes: a memory subsystem including a non-volatile memory device; and a host that can be coupled to the memory subsystem through a plurality of memory device interfaces, where the first memory device interface includes a processing device configured to: identify a low-to-high transition signal at the front side of a command enable channel; lock the rear side of the command enable channel in response to identifying the low-to-high transition signal; start a command timer to determine when a threshold amount of time has elapsed since receiving the low-to-high transition signal; unlock the rear side of the command enable channel in response to receiving a capacity selection command selecting the first memory device interface at the data channel within the threshold amount of time; deactivate the data channel when the capacity selection command selects a second memory device interface; and unlock the rear side of the command enable channel when the threshold amount of time is satisfied. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 Illustrate an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 Illustrate a system including a multi-channel input / output expander according to some embodiments of the present disclosure.

[0009] Figure 3 Illustrate a system including a multi-channel input / output expander according to some embodiments of the present disclosure.

[0010] Figure 4 Illustrate a timing diagram for expander device channel locking for a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 is a flowchart corresponding to a channel locking method according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to expander device channel locking for memory devices, and more particularly, to memory subsystems including channel locking components. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. An example of the memory subsystem is a storage system, such as a solid state drive (SSD). The following is combined with Figure 1and other examples to describe storage devices and memory modules. Generally, a host system can utilize a memory subsystem that includes one or more components such as memory devices for storing data. The host system can provide data stored at the memory subsystem and can request data retrieved from the memory subsystem.

[0014] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND (Negative AND) memory device (also referred to as flash technology). As used herein, a NAND memory device can include a set of flash memory dies or a combination of flash memory dies and a non-volatile memory (NVM) controller. The NVM controller can include circuitry for performing read / write operations as described herein. Other examples of non-volatile memory devices are described below in conjunction with Figure 1 A non-volatile memory device is an encapsulation of one or more dies. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block hereinafter refers to the unit of the memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest area that can be erased. A page cannot be erased individually and only an entire block can be erased.

[0015] Each of the memory devices can include one or more memory cell arrays. Depending on the cell type, the cells can be written to store one or more binary information bits and have various logical states related to the number of stored bits. The logical states can be represented by binary values such as “0” and “1” or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one information bit and has two logical states.

[0016] Some NAND memory devices employ a floating gate architecture where memory access is controlled based on the relative voltage change between a bit line and a word line. Other examples of NAND memory devices can employ a replacement gate architecture that can include a word line layout that allows charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0017] In some prior methods, an input / output (IO) expander (IOE) device may be placed between a host and a memory die. For example, the IOE device may be placed between a host device and multiple NAND dies (or “LUNs”). The host side of the IOE device may be referred to as the front side (front end) and the memory die side of the IOE device may be referred to as the back side (back end). The IOE device may allow the host to view a single die load at the front side (FS) of the IOE device. The NAND die load may be distributed across multiple IOE back side channels. These prior IOE devices may implement a crossbar switch to route the intended traffic to the target NAND die. As used herein, a crossbar switch includes a set of switches arranged in a matrix configuration. The crossbar switch may have multiple input and output lines that form an intersecting pattern of interconnects, and connections between the interconnects may be established by closing switches (elements of the matrix) located at each intersection point.

[0018] In some prior methods, the IOE device may receive communications from the host device at the front side and provide the communications to the memory resources at the back side. In these prior methods, the host device may utilize commands during operation. In these prior embodiments, the command enable signal of the command may be passed to the same memory resources as the payload or other parts of the communication. In some prior embodiments, there may be a risk that signals will cause a memory resource failure. In some embodiments, it may be difficult or impossible to filter the signals without providing them to the memory resources, which may result in delays or failures related to communicating between the host and the memory resources. Additionally, prior embodiments may have an IOE device that utilizes data channels that are always active or capable of receiving data communications. These prior embodiments waste electrical power during operations when the data channels are not being used by the host.

[0019] Aspects of the present disclosure address the above and other drawbacks by employing an IOE device that utilizes channel locking. For example, aspects of the present disclosure may utilize a channel locking component that may be configured to receive a signal at a front side command enable channel indicating when a command is received at the front side of the data channel. In this way, the data channel may be deactivated during operation until the IOE device receives a signal at the front side command enable channel. In these embodiments, the IOE device may conserve or save power when not in use and still be capable of receiving data channel commands.

[0020] In some embodiments, commands can pass through the back end of the command enable channel and negatively impact the performance of memory devices (e.g., NAND, LUN, etc.) coupled to the back end of the IOE device. In some embodiments, the IOE device can lock the back side of the command enable channel in response to receiving a signal at the front side of the command enable channel. In this way, the host can send commands, such as a capacity selection command, without transmitting a command enable signal to the memory device coupled to the back side of the IOE device. In some embodiments, the IOE device can receive a command from the host and unlock the back side of the command enable channel in response to receiving the command at the front side of the data channel. In this way, the host can then continue to use the IOE device to communicate with the memory device coupled to the back side of the IOE device. In some embodiments, the IOE device can disable the data channel when the host selects a different IOE device with a command. In this way, the IOE device can conserve power until an additional signal is received by the host at the front side of the command enable channel.

[0021] Figure 1 An example computing system that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure is illustrated. The memory subsystem 110 can include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0022] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes memory and a processing device.

[0024] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1Describe an example of a host system 120 coupled to a memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0025] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 (e.g.) to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Describe the memory subsystem 110 as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) can be (but is not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is an array of cross-points of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance change along with a stacked cross-gate format data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasure of the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell (e.g., single-level cell (SLC)) can store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC)) can store multiple bits per cell. In some embodiments, each of memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of memory device 130 can be grouped into pages, which may refer to logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0030] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 can be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] As described above, the memory component can be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, memory cell blocks can form one or more "superblocks". As used herein, a "superblock" generally refers to a set of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks can be deployed across multiple memory dies having multiple planes and / or pages associated therewith. Given the context of the present disclosure, the terms "superblock", "block", "memory cell block", and / or "interleaved NAND block" and their variants can be used interchangeably.

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 can be a processor 117 (such as a processing device) configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, the local memory 119 can include memory registers for storing memory pointers, fetched data, etc. The local memory 119 can also include a read only memory (ROM) for storing microcode. Although the Figure 1 illustrated memory subsystem 110 has been described as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115 and instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical addresses (such as logical block addresses (LBAs), namespaces) associated with the memory device 130 and the physical addresses (such as physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0036] In some embodiments, the memory subsystem 110 may include a cache or buffer (such as DRAM) and address circuitry (such as a row decoder and a column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130 and / or the memory device 140. For example, in some embodiments, the memory device 140 may be a DRAM and / or SRAM configured to operate as a cache for the memory device 130. In such examples, the memory device 130 may be NAND.

[0037] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (such as the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device that is an original memory device combined with a local controller (such as the local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. The memory subsystem 110 may also include additional circuitry or components not shown.

[0038] The memory subsystem 110 may include a channel lock component 113, which may alternatively be referred to herein as a "controller". Although Figure 1Not shown in order not to obscure the figure, but the channel locking component 113 can include various circuitry to facilitate media management, as detailed herein. In some embodiments, the channel locking component 113 can include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that can allow the channel locking component 113 to orchestrate and / or perform the operations described herein.

[0039] In some embodiments, the memory subsystem controller 115 includes at least a portion of the channel locking component 113. For example, the memory subsystem controller 115 can include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the channel locking component 113 is part of the memory subsystem 110, an application, or an operating system.

[0040] In a non-limiting example, a device (e.g., computing system 100) can include the channel locking component 113. The channel locking component 113 can reside on the memory subsystem 110. As used herein, the term "reside on" refers to something being physically located on a particular component. For example, the channel locking component 113 "residing on the memory subsystem 110" refers to the situation where the hardware circuitry including the channel locking component 113 is physically located on the memory subsystem 110. In this document, the term "reside on" can be interchanged with other terms such as "deployed on" or "located on".

[0041] As further described herein, the computing system 100 can include an IOE device that can be used to connect a host (e.g., host system 120, etc.) to a memory device (e.g., memory device 130, etc.). In some embodiments, the IOE device can be coupled to the host on the front side and to the memory device on the back side. The host can configure the IOE device based on the nature of the memory device. For example, configuration signals from the host can be received at the chip enable pins of the IOE device. In previous methods, the configuration signals could be provided to the memory device even though the configuration signals were not intended to be received by the memory device. As described herein, the configuration signals can be harmful to the performance of the memory device. In some embodiments, the channel locking component 113 can be used to filter or prevent signals from being provided to the memory device.

[0042] The channel lock component 113 can be configured to identify a low-to-high transition signal at the front side of the command enable channel. As described herein, the channel lock component 113 can identify a signal received at the front side of the command enable channel of the IOE device. In some embodiments, the signal received at the front side of the command enable channel is a low-to-high transition signal. As used herein, a low-to-high transition signal refers to a binary signal transition from a low voltage level to a high voltage level. As further described herein, the front side of the IOE device can include a plurality of channels or connections coupled to the host. Additionally, the back side of the IOE device can include a plurality of channels or connections coupled to the memory device. In this way, the host can utilize the IOE device to convey or send signals to the memory device.

[0043] In some embodiments, a signal (such as a low-to-high transition signal, etc.) can be an indication to the channel lock component 113 that a data command will be received at the front side of the data channel. For example, the signal can be an indication to the IOE device or the channel lock component 113 that the host will send a command to the front side of the data channel of the IOE device. In this way, the host can send a signal to notify the IOE device that a specific command will be provided to the IOE device. In a particular instance, the host can send a low-to-high transition signal to the front side of the command enable channel of the IOE device. In this particular instance, the low-to-high transition signal can be an indication from the host that the host will send a capacity selection command to the front side of the data channel of the IOE device.

[0044] The channel lock component 113 can be configured to receive a de-assert signal for the command enable channel from the host. As used herein, a de-assert signal can be a signal used by the host to deactivate or cancel a specific function or operation. In these embodiments, the de-assert signal can be a low-to-high transition signal from the host that can be used to deactivate the back side of the command enable channel.

[0045] The channel lock component 113 can be configured to lock the back side of the command enabling channel in response to identifying a low-to-high transition signal. In some embodiments, the channel lock component 113 can identify a low-to-high transition signal from the host and determine that the host will send a command to the front side of the data channel of the IOE device. In some embodiments, the back side of the command enabling channel is locked to prevent signals associated with the command from reaching or being provided to the memory resources coupled to the back side of the IOE device. In a particular instance, when the back side of the command enabling channel is locked, the memory die in the plurality of memory dies does not record the command. For example, the data channel portion of the signal can be transmitted to the memory die, but since the command enabling portion of the signal is not transmitted to the memory die, the memory die does not record the command. In a particular instance, the channel lock component 113 can determine that a capacity selection command will be provided to one of the plurality of IOE devices coupled to the host. In this way, the capacity selection command can pass through the IOE device to the memory die, but since the back side of the command enabling channel is locked, the memory die can ignore the capacity selection command. In this way, the capacity selection command does not change the functionality or performance of the memory die.

[0046] As used herein, a capacity selection command can be an instruction from a host device indicating a specific capacity or storage unit for a subsequent operation. For example, a capacity selection command can be a logical partition or a physical storage device. The capacity can be used by the memory device to manage data within a computing system. In some embodiments, the capacity selection command can allow the host to select a specific capacity or storage unit on which subsequent operations (such as read, write, format, or management tasks) will be performed. This command provides a way to address and access data within a specific capacity rather than operating on the entire storage device.

[0047] The channel lock component 113 can be configured to start a command timer to determine when a threshold amount of time has elapsed since receiving the low-to-high transition signal. In some embodiments, the host can provide commands to different IOE devices associated with different memory devices. In some embodiments, the channel lock component 113 can determine that the threshold amount of time has elapsed and determine that the host has sent a command to a different IOE device. In this way, the channel lock component 113 can wait for the threshold amount of time before deactivating the data channel to receive a command from the host at the front side of the data channel. In this way, the data channel can remain deactivated unless the IOE device will receive a command from the host at the front side of the data channel.

[0048] The channel locking component 113 can be configured to unlock the back side of the command enabling channel in response to receiving a command at the data channel within a threshold amount of time. In some embodiments, the channel locking component 113 can determine that a command, such as a capacity selection command, is received at the front side of the data channel. In these embodiments, the channel locking component can implement the instructions of the command and unlock the back side of the command enabling channel to allow the host to send a command enabling signal through the command enabling channel. In this way, commands provided to the front side of the data channel do not affect the memory resources coupled to the back side of the IOE device, while subsequent commands provided by the host will be provided to the memory resources.

[0049] In other embodiments, the channel locking component 113 can be configured to identify a low-to-high transition signal at the front side of the command enabling channel. As described herein, the low-to-high transition signal can indicate or notify the channel locking component 113 that the host device will receive a command at the front side of the data channel of the IOE device. In these other embodiments, the channel locking component 113 can be configured to lock the back side of the command enabling channel in response to identifying the low-to-high transition signal. Locking the back side of the command enabling channel can prevent signals received from the front side of the command enabling channel from being provided to the memory resources coupled to the back side of the command enabling channel.

[0050] In these other embodiments, the channel locking component 113 can be configured to start a command timer to determine when a threshold amount of time has elapsed since receiving the low-to-high transition signal. In some embodiments, the command timer can be a timer device that can identify when a threshold amount of time has elapsed since receiving the low-to-high transition signal. In some embodiments, the channel locking component 113 can utilize the command timer to identify when a certain amount of time has passed since the low-to-high transition signal. In these embodiments, when the command timer has exceeded the threshold amount of time, the channel locking component 113 can determine that the command will not be provided.

[0051] In these other embodiments, the channel locking component 113 can be configured to unlock the back side of the command enabling channel in response to receiving a capacity selection command at the data channel within a threshold amount of time to select a first memory device interface. As described herein, the back side of the command enabling channel can be unlocked to allow the host to send a command enabling signal to the memory resources coupled to the first memory device interface in response to receiving the capacity selection command.

[0052] In these other embodiments, the channel unlock component 113 may be configured to deactivate the data channel when a capacity select command selects a second memory device interface. As described herein, the host may select a different IOE device. In these embodiments, the channel lock component 113 may determine that a different IOE device is selected by a capacity select command from the host, and in response, the channel lock component 113 may deactivate the data channel to conserve power because the host will utilize a different IOE for subsequent commands or instructions.

[0053] In these other embodiments, the channel lock component 113 may be configured to unlock the backside of the command enable channel when a threshold amount of time is met. As described herein, the channel lock component 113 may unlock the backside of the command enable channel to allow the host to provide a command enable signal to the IOE device and / or a memory resource associated with the IOE device.

[0054] Figure 2 Illustrate a system 221 including a multi-channel input / output expander (IOE) device 222 according to some embodiments of the present disclosure. The IOE device 222 may include a device that utilizes a first input channel 223-1 and a second input channel 223-2 that may be connected to a host device or a host system. In some embodiments, the IOE device 222 may operate in a single-channel mode and / or a dual-channel mode. In these embodiments, the IOE device 222 may utilize only the first input channel 223-1 in the single-channel mode and may utilize both the first input channel 223-1 and the second input channel 223-2 in the dual-channel mode. In some embodiments, the second input channel 223-2 is disabled to perform the single-channel mode using the first input channel 223-1.

[0055] In some embodiments, the IOE device 222 may include a first plurality of output channels 224-1, 224-2 and a second plurality of output channels 224-3, 224-4. In some embodiments, the first output channel 224-1 may be coupled to a first portion of the LUN 225-1, the second output channel 224-2 may be coupled to a second portion of the LUN 225-2, the third output channel 224-3 may be coupled to a third portion of the LUN 225-3, and the fourth output channel 224-4 may be coupled to a fourth portion of the LUN 225-4. In single-channel mode, the first input channel 223-1 may be used to access the plurality of LUNs 225-1, 225-2, 225-3, 225-4. In dual-channel mode, the first input channel 223-1 may be used to access the first portion of the LUN 225-1 and the second portion of the LUN 225-2 through the first plurality of output channels 224-1, 224-2, and the second input channel 223-2 may be used to access the third portion of the LUN 225-3 and the fourth portion of the LUN 225-4 through the second plurality of output channels 224-3, 224-4.

[0056] In some prior methods, the host may provide a signal to the IOE device 222 through one of the first input channel 223-1 and the second input channel 223-2. In these prior methods, the signal desired for the IOE device 222 may be transmitted to one or more of the plurality of LUNs 225-1, 225-2, 225-3, 225-4. As further described herein, the signal desired for the IOE device 222 may cause an unexpected or unintended change to the plurality of LUNs 225-1, 225-2, 225-3, 225-4. The present disclosure may utilize an IOE device 222 that includes a channel locking component (such as Figure 1 the channel locking component 113 referred to in etc.). The channel locking component may be configured to perform the methods and / or processes described herein.

[0057] Figure 3 Illustrates a system 331 that includes multi-channel input / output expanders 222-1, 222-2 according to some embodiments of the present disclosure. In some embodiments, the system 331 illustrates when multiple memory device interfaces are configured in a multi-point configuration. As used herein, a multi-point configuration refers to multiple devices connected to a shared communication bus. By sharing a common bus, multiple memory devices can be connected using fewer physical connections, thereby reducing overall system complexity and wiring requirements. This configuration is commonly used in scenarios where multiple memory devices need to be accessed or controlled by a single device (such as the host system 120, etc.).

[0058] System 331 may include a first IOE device 222-1 and a second IOE device 222-2 coupled to host system 120. Host system 120 may be coupled to the first IOE device 222-1 via a first input channel 223-1 and / or a plurality of first input channels 223-1. In a similar manner, host system 120 may be coupled to the second IOE device 222-2 via a second input channel 223-2 and / or a plurality of second input channels 223-2.

[0059] In some embodiments, the first IOE device 222-1 may include a first plurality of output channels 224-1, 224-2 and the second IOE device 222-2 may include a second plurality of output channels 224-3, 224-4. In some embodiments, the first output channel 224-1 may be coupled to a first portion of LUN 225-1, the second output channel 224-2 may be coupled to a second portion of LUN 225-2, the third output channel 224-3 may be coupled to a third portion of LUN 225-3, and the fourth output channel 224-4 may be coupled to a fourth portion of LUN 225-4.

[0060] In some prior methods, host system 120 may provide a signal to the first IOE device 222-1 or the second IOE device 222-2 via one of the first input channel 223-1 and the second input channel 223-2. In these prior methods, a signal desired for the first IOE device 222-1 or the second IOE device 222-2 may be transmitted to one or more of the plurality of LUNs 225-1, 225-2, 225-3, 225-4. As further described herein, a signal desired for the first IOE device 222-1 or the second IOE device 222-2 may cause an unexpected or unanticipated change to the plurality of LUNs 225-1, 225-2, 225-3, 225-4. The present disclosure may utilize the first IOE device 222-1 and / or the second IOE device 222-2 that includes a channel locking component (such as Figure 1 the channel locking component 113 referenced in etc.). The channel locking component may be configured to perform the methods and / or processes described herein.

[0061] In some embodiments, the host system 120 may send a low-to-high transition signal to the first IOE device 222-1 and / or the second IOE device 222-2. As described herein, the low-to-high transition signal may be used to notify or indicate to the first IOE device 222-1 and / or the second IOE device 222-2 that the host system 120 will provide a command to the first IOE device 222-1 and / or the second IOE device 222-2. In some embodiments, the command may be a capacity selection command that identifies one of the plurality of LUNs 225-1, 225-2, 225-3, 225-4. In this way, the first IOE device 222-1 and / or the second IOE device 222-2 may include a channel locking component for locking and unlocking the backside of the chip enable channel and / or activating and deactivating the data channel.

[0062] Figure 4 Illustrate a timing diagram 441 for expander device channel locking for a memory device according to some embodiments of the present disclosure. In some embodiments, the timing diagram 441 may show how a plurality of frontside signals 442-1, 442-2 correspond to a plurality of backside signals 443-1, 443-2. That is, the plurality of frontside signals 442-1, 442-2 may be signals received from the host at a plurality of corresponding signal pins of the IOE device. The timing diagram 441 may illustrate how the IOE device transfers the plurality of frontside signals 442-1, 442-2 from the host to the plurality of backside signals 443-1, 443-2 provided to the memory resources.

[0063] In some embodiments, the plurality of frontside signals 442-1, 442-2 may include a frontside chip enable signal 442-1, a frontside (data) command signal 442-2, and / or other frontside signals (such as a frontside clock signal, etc.). In a similar manner, the plurality of backside signals 443-1, 443-2 may include signals corresponding to the plurality of frontside signals 442-1, 442-2. For example, the plurality of backside signals 443-1, 443-2 may include a backside chip enable signal 443-1, a backside (data) command signal 443-2, and / or other backside signals.

[0064] As described herein, the IOE device may receive a signal at the front-side chip enable channel. The front-side chip enable signal includes a low-to-high transition signal at 445. As described herein, the IOE device may lock the back-side enable channel. In these embodiments, the back-side enable signal 443-1 may be locked at 447 to prevent subsequent signals from reaching the memory device coupled to the back-side enable channel of the IOE device. As described herein, the host device may provide a command to the front-side data channel of the IOE device after the low-to-high transition signal. The front-side data signal may include a command at 446. As described herein, the command at 446 may be provided to the back-side data signal at 448. As described herein, the command at 446 may be a capacity selection command for selecting a specific capacity of the memory resource coupled to the back-side of the IOE device.

[0065] As described herein, the IOE device may unlock the back-end chip enable channel after a threshold amount of time from receiving the low-to-high transition signal. The back-side chip enable signal 443-1 includes an unlock signal at 449. In this way, the back-side chip enable signal 443-1 may be provided to the memory resource after the unlock signal at 449.

[0066] Figure 5 is a flowchart corresponding to the channel locking method 551 according to some embodiments of the present disclosure. The method 551 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 551 is executed by Figure 1 the channel locking component 113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not every embodiment requires all of the processes. Other process flows are possible.

[0067] At operation 552, the method 551 may be executed to receive a signal from the host at the front side of the command enable channel by the memory device interface. In some embodiments, the signal indicates that a command will be received. In some embodiments, the signal is a low-to-high transition signal received from the host. In this way, the host may notify the memory device interface (e.g., the IOE device, etc.) that the host will send a command within a threshold amount of time. In some embodiments, the signal indicates that a capacity selection command will be sent to the memory device interface.

[0068] In some embodiments, method 551 may be executed to identify the amount of time between a received signal and a received command. In some embodiments, the memory device interface may determine the amount of wait time for a command from the host. In some embodiments, the amount of time may be specified or programmed into the memory device interface by the host such that the memory device interface waits for a threshold amount of time before determining that the command has not been received by the host device.

[0069] At operation 553, method 551 may be executed to lock the back side of the command enable channel by the memory device interface in response to the signal. In some embodiments, locking the back side of the command enable channel prevents a signal provided to the front side of the command enable channel from being provided to the memory resources coupled to the back side of the command enable channel.

[0070] In some embodiments, method 551 may be executed to activate the data channel in response to a signal received at the front side of the command enable channel. As described herein, the data channel may be activated in response to receiving the signal when the signal indicates that the host will send a command to the front side of the data channel. In this way, the front side of the data channel may be activated to receive a command (such as a capacity selection command, etc.). In some embodiments, the data channel may be activated from a deactivated state. The deactivated state may be an off or low power state that allows the IOE device to conserve power (such as electrical power, etc.).

[0071] At operation 554, method 551 may be executed to receive a command from the host at the data channel by the memory device interface. As described herein, the command may be a capacity selection command that includes an instruction to select a capacity or a portion of a memory resource. In some embodiments, the command may select a memory resource associated with the memory device interface or the command may select a memory resource associated with a different memory device interface.

[0072] At operation 555, method 551 may be executed to unlock the back side of the command enable channel by the memory device interface in response to receiving the command at the data channel. In some embodiments, the memory device interface may unlock the back side of the command enable channel after a threshold amount of time or when the command is received at the data channel. This may allow the host to provide a signal to the front side of the command enable channel and the signal may be provided or transmitted to the memory resources coupled to the back side of the command enable channel.

[0073] In some embodiments, the executable method 551 can deactivate the data channel when the command is a capacity selection command that includes instructions for selecting a different memory device interface. In some embodiments, the executable method 551 can deactivate the data channel when the command is received by a different memory device interface. In some embodiments, the data channel can be deactivated to save or conserve power. In some embodiments, the data channel can be deactivated in response to a capacity selection command selecting a different memory device interface. In this way, when the host utilizes a different memory device interface, the unselected memory device interface can conserve power.

[0074] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 6 illustrates an example machine of a computer system 600, within which a set of instructions can be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 can correspond to a host system (e.g., Figure 1 the host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 the memory subsystem 110) or can be used to perform the operations of a controller (e.g., for executing an operating system to perform operations corresponding to Figure 1 the channel lock component 113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0075] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a network device, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 600 includes a processing device 602, a main memory 604 (such as read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (such as flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0077] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 can also be one or more dedicated processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 can further include a network interface device 608 to communicate via a network 620.

[0078] The data storage system 618 can include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein are stored. The instructions 626 can also reside, at least partially, within the main memory 604 and / or the processing device 602 during execution by the computer system 600, and the main memory 604 and the processing device 602 also constitute a machine-readable storage medium. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 can correspond to Figure 1 the memory subsystem 110.

[0079] In one embodiment, the instructions 626 include instructions for implementing the functionality corresponding to a channel locking component (such as Figure 1 the channel locking component 113). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for a machine to execute and cause the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0080] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived as a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage systems of the computer system.

[0082] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will appear as described in the following description. In addition, the present disclosure has not been described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0084] The present disclosure may be provided as a computer program product or software that may include a machine readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic device) to perform a process in accordance with the present disclosure. The machine readable medium includes any mechanism for storing information in a form readable by a machine, such as a computer.

[0085] In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, and the like. In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method (551) for channel locking of an expander device, comprising: receiving, by the memory device interface (222), a signal from a host (120) at a front side (442-1) of a command enable channel, wherein the signal indicates that a command (446) is to be received; locking, by the memory device interface (222) in response to the signal, a back side (443-1) of the command enable channel; receiving, by the memory device interface (222), the command (446) from the host (120) at a data channel (442-2); and The back side (443-1) of the command enable channel is unlocked by the memory device interface (222) in response to receiving the command (446) at the data channel (442-2).

2. The method according to claim 1, further comprising: activating the data channel in response to receiving the signal at the front side of the command enable channel; and When the command is a capacity select command including an instruction to select a different memory device interface, the data channel is deactivated. 3 . The method of claim 1 , wherein locking the back side of the command enable channel prevents signals provided to the front side of the command enable channel from being provided to memory resources coupled to the back side of the command enable channel.

4. The method of claim 1, further comprising deactivating the data lane when the command is received by a different memory device interface, wherein the signal is a low-to-high transition signal received from the host. The method of claim 1 , further comprising identifying an amount of time between receiving the signal and receiving the command.

6. An apparatus for locking a channel of an expander device, comprising: a plurality of memory dies (225-1, 225-2, 225-3, 225-4); and A memory device interface (222) for transmitting communications between a host (120) capable of being coupled to the memory device interface (222) and the plurality of memory dies (225-1, 225-2, 225-3, 225-4), wherein the memory device interface (222) includes a controller (115) configured to: identifying a low to high transition signal at the front side (442-1) of a command enable channel; locking a back side of the command enable channel in response to identifying the low-to-high transition signal (443-1); starting a command timer to determine when a threshold amount of time from receipt of the low-to-high transition signal is met; and The back side (443-1) of the command enable channel is unlocked in response to receiving a command (446) at the data channel (442-2) within the threshold amount of time.

7. The apparatus of claim 6, further comprising the controller configured to activate the data channel in response to locking the back side of the command enable channel.

8. The apparatus of claim 6, further comprising the controller configured to deactivate the data channel when the command is not received at the data channel within the threshold amount of time, wherein the command enables the back side of the channel to lock within the threshold amount of time.

9. The apparatus of claim 6, wherein when the back side of the command enable channel is locked, the command is passed to a memory die of the plurality of memory dies and the memory die of the plurality of memory dies does not record the command.

10. A system for channel locking of an expander device, comprising: a memory subsystem (115) comprising a non-volatile memory device (130); and A host (120) capable of being coupled to the memory subsystem (115) through a plurality of memory device interfaces (222), a first memory device interface (222-1) comprising a processing device (117), the processing device (117) being configured to: identifying a low to high transition signal at the front side (442-1) of a command enable channel; locking a back side of the command enable channel in response to identifying the low-to-high transition signal (443-1); starting a command timer to determine when a threshold amount of time from receipt of the low-to-high transition signal is met; unlocking the back side (443-1) of the command enable channel in response to receiving a capacity select command (446) selecting the first memory device interface (222-1) at a data channel (442-2) within the threshold amount of time; When the capacity selection command (446) selects the second memory device interface (222-2), deactivating the data channel (442-2); and When the threshold amount of time is met, the back side of the command enable channel is unlocked (443-1).

11. The system of claim 10, wherein the host is coupled to the front side of the command enable channel of the first memory device interface and a front side of a command enable channel of the second memory device interface.

12. The system of claim 10, wherein the processing device is further configured to activate the data channel in response to receiving the low-to-high transition signal.

13. The system of claim 10, wherein the processing device is further configured to receive a de-assertion signal of the command enable channel from the host.

14. The system of claim 10, wherein the plurality of memory device interfaces are configured in a multi-drop configuration.

15. The system of claim 10, wherein the processing device is further configured to receive a plurality of commands at the front side of the command enable channel prior to receiving the capacity select command at the data channel, wherein the capacity select command selects a portion of a memory subsystem.

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