Read state command for obtaining channel state

Abstract

The invention relates to a read state command for obtaining a channel state. In some examples, a boot sequence can be initiated at a controller of a memory system based on receiving a power signal, and a first request for state information can be transmitted from the controller to a memory device of the memory system. The controller can receive an indication of an initialization state from the memory device and configure a channel interface for communication with the memory device based on the indication of the initialization state. Data can then be communicated between the controller and the memory device using the channel interface.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of priority of U.S. Patent Application No. 18 / 957,319, filed Nov. 22, 2024, entitled “READ STATUS COMMAND TO OBTAIN CHANNEL STATE” by Palmer, and U.S. Patent Application No. 63 / 604,767, filed Nov. 30, 2023, entitled “READ STATUS COMMAND TO OBTAIN CHANNEL STATE” by Palmer, each of which is assigned to its assignee and each of which is hereby incorporated by reference in its entirety.

[0003] The technical field relates to a read status command for obtaining a channel state. BACKGROUND OF THE INVENTION

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of an external power supply. Memory cells configured in a volatile configuration lose their stored state when disconnected from an external power supply. SUMMARY OF THE INVENTION

[0006] Describe a method. The method may include: at a controller of a memory system, initiate a boot sequence at least in part based on receiving a power signal; transmit a first request for status information from the controller to a memory device of the memory system; receive an indication of an initialization state from the memory device at least in part based on communicating the first request; configure a channel interface by the controller for communication with the memory device at least in part based on the indication of the initialization state; and communicate data between the controller and the memory device using the channel interface at least in part based on configuring the channel interface.

[0007] Describe a non - transitory computer - readable medium that stores code. The code includes instructions that may be executed by a processor to: at a controller of a memory system, initiate a boot sequence at least in part based on receiving a power signal; transmit a first request for status information from the controller to a memory device of the memory system; receive an indication of an initialization state from the memory device at least in part based on communicating the first request; configure a channel interface by the controller for communication with the memory device at least in part based on the indication of the initialization state; and communicate data between the controller and the memory device using the channel interface at least in part based on configuring the channel interface.

[0008] Describe a device. The device may include: a controller associated with a memory device, wherein the controller is configured to cause the device to: at a controller of a memory system, initiate a boot sequence at least in part based on receiving a power signal; transmit a first request for status information from the controller to a memory device of the memory system; receive an indication of an initialization state from the memory device at least in part based on communicating the first request; configure a channel interface by the controller for communication with the memory device at least in part based on the indication of the initialization state; and communicate data between the controller and the memory device using the channel interface at least in part based on configuring the channel interface.

[0009] Describe a device. The device may include: a processor; a memory coupled to the processor; and instructions stored in the memory and executable by the processor to cause the device to: initiate a boot sequence at a controller of a memory system at least in part based on receiving a power signal; transmit a first request for status information from the controller to a memory device of the memory system; receive an indication of an initialization state from the memory device at least in part based on communicating the first request; configure a channel interface by the controller at least in part based on the indication of the initialization state for communication with the memory device; and communicate data between the controller and the memory device using the channel interface at least in part based on configuring the channel interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Illustrate an example of a system supporting a read status command for obtaining channel status according to an example disclosed herein.

[0011] Figure 2 Illustrate an example of a system supporting a read status command for obtaining channel status according to an example disclosed herein.

[0012] Figure 3 Illustrate an example of a flowchart of a process supporting a read status command for obtaining channel status according to an example disclosed herein.

[0013] Figure 4 Illustrate a block diagram of a memory system supporting a read status command for obtaining channel status according to an example disclosed herein.

[0014] Figure 5 Illustrate a flowchart showing one or more methods supporting a read status command for obtaining channel status according to an example disclosed herein. DETAILED DESCRIPTION

[0015] Memory systems typically utilize multiple power supplies to operate different components. For example, a controller within a memory system (e.g., a memory system controller) may be powered by a first power supply, and a memory device (or memory devices) may be powered by a different power supply. Due to various reasons, the power supplies do not all experience the same power conditions. For example, a host system associated with the memory system may implement different power supplies or control circuits, where some power supplies experience a power-off condition while other power supplies remain stable. In some cases, the power-off condition affects the memory system controller rather than the memory device. Thus, power to the memory system controller is interrupted and configuration and / or communication settings are lost. However, the memory device may not have been power cycled and retains the configuration for communicating via a channel interface.

[0016] When power is restored to the memory system controller, the states of the channel interfaces used to communicate with the memory devices and the states of the memory devices may be unknown. This can result in latency because there is a lack of shared state for communication between the memory system controller and the memory devices via the channel interfaces. The memory system controller has to undergo a process of resetting and re-initializing its connections to the channel interfaces, which can result in latency. The memory system controller also has to reset the memory devices, which can result in additional training and configuration before communication can be restored, which can result in additional latency. However, if the memory devices have not been power cycled, then the configuration parameters of the channel interfaces are maintained by the memory devices. Thus, the additional training and configuration of the memory devices may not be necessary.

[0017] According to various aspects of the present disclosure, the memory system controller may convey status commands after a reset condition to obtain information about the states of the memory devices and the channel interfaces. In some instances, the status commands may be used to determine whether the memory devices are powered down or remain active. If the memory devices were previously configured (e.g., remain active), then the status commands may cause information about the channel interfaces (e.g., the currently configured data rate, timing mode, and / or protocol (e.g., serial command and address or legacy)) to be returned. The memory system controller may utilize the received information to configure its connections to the channel interfaces. The status commands may further be used to obtain some or all of the available status parameters associated with the channel interfaces. In some instances, the status commands may be valid in all timing modes or configurations of the channel interfaces. The memory system controller may thus successfully convey the status commands regardless of the channel configuration of the memory devices. In other instances, the status commands may be valid regardless of whether the memory devices are available or busy.

[0018] According to disclosed examples, status commands may be used for the memory system controller to implement a faster and more robust reset recovery process. In some instances, a reset or powered-on memory system controller may convey a status command to determine whether the memory devices have remained powered on, thereby avoiding the need to blindly reset the memory devices. The memory system controller may also avoid resetting memory devices that have already been configured and initialized. In some instances, the status commands may cause the memory system to achieve improved (e.g., faster) synchronization between the memory devices and the memory system controller while reducing the likelihood of failure. Additionally, the memory system controller may potentially skip unnecessary training and calibration steps that can result in operational latency.

[0019] First, the features of the present disclosure are described in the context of the systems, apparatuses, and circuits of Figure 1 The features of the present disclosure are described in the context of the systems of Figures 2 to 3 supporting a read status command for obtaining channel status and the flowchart of the process supporting a read status command for obtaining channel status. By referenceFigures 4 to 5 The device diagram and flowchart related to the read status command for obtaining the channel status are used to further illustrate and describe these and other features of the present disclosure in the context of the device diagram and flowchart.

[0020] Figure 1 An example of a system 100 that supports a read status command for obtaining a channel status according to the examples disclosed herein is described. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be included in a computing device such as a desktop computer, laptop computer, network server, mobile device, vehicle (such as an airplane, drone, train, car, or other transportation vehicle), Internet of Things (IoT) enabled device, embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or any other computing device that includes a memory and a processing device.

[0021] The memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Card (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other devices.

[0022] System 100 may include a host system 105 that can be coupled to the memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (such as a memory local to or included in the host system 105), a memory controller (such as an NVDIMM controller), and a storage protocol controller (such as a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1A memory system 110 is shown, but the host system 105 can be coupled to any number of memory systems 110.

[0023] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface can include (but are not limited to) SATA interface, UFS interface, eMMC interface, PCIe interface, USB interface, Fibre Channel interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interface, DIMM interface (e.g., DIMM slot interface supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interface. In some instances, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 can be coupled to the memory system 110 via the respective physical host interface of each memory device 130 included in the memory system 110 or via the respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled to the memory system controller 115).

[0024] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory device 130 can include one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example, the memory system 110 can include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, the different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0025] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an instance of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 and other such operations, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effect the desired access of the memory device 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 can convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshing, health monitoring, and address translation between a logical address (e.g., a logical block address (LBA)) associated with a command from the host system 105 and a physical address (e.g., a physical block address) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware can include circuitry having dedicated (e.g., hard-coded) logic for performing the operations ascribed to the memory system controller 115 herein. The memory system controller 115 can be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions ascribed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, e.g., internal storage or calculations related to the functions ascribed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130, and the data may be used within the local memory 120 for subsequent retrieval by or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] Although Figure 1 the example of the memory system 110 in has been illustrated as including a memory system controller 115, in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be respectively within the memory devices 130 to perform the functions ascribed to the memory system controller 115 herein. Generally, in some cases, one or more of the functions ascribed to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory devices 130 that are at least partially managed by the memory system controller 115 may be referred to as managed memory devices. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) local controller 135, which may perform operations on one or more memory cells of the corresponding memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions ascribed herein to memory system controller 115. For example, as Figure 1 illustrated, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some instances, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one information bit, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple information bits, which may be referred to as multi-level cells (MLCs) when configured to each store two information bits, triple-level cells (TLCs) when configured to each store three information bits, quad-level cells (QLCs) when configured to each store four information bits, or more generally as multi-level memory cells. The multi-level memory cells may provide greater storage density relative to the SLC memory cells, but may involve narrower read or write margins or greater complexity for the support circuitry in some cases.

[0034] In some cases, a plane 165 may refer to a number of groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, the concurrent operations may be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations on different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., be coupled to a common word line), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit (e.g., group of memory cells) of the memory that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., group of memory cells) of the memory that can be independently erased (e.g., concurrently erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0037] In some cases, the memory system controller 115 or the local controller 135 can perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or others or any combination thereof. For example, within the memory device 130, a block 170 can have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting until all pages 175 in a block 170 have invalid data before erasing and reusing the block 170, an algorithm called "garbage collection" can be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations that include (e.g.): selecting a block 170 containing both valid and invalid data; selecting a page 175 within the block that contains valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected page 175 as invalid; and erasing the selected block 170. Thus, the number of blocks 170 that have been erased can be increased such that more blocks 170 are available for storing subsequent data (e.g., data subsequently received from the host system 105).

[0038] In some cases, the memory system 110 can utilize the memory system controller 115 to provide a managed memory system, which can include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or within-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] System 100 may include any number of non-transitory computer-readable media that support read status commands for obtaining channel status. For example, a host system 105 (e.g., host system controller 106), a memory system 110 (e.g., memory system controller 115), or a memory device 130 (e.g., local controller 135) may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0040] In some instances, a memory system controller (e.g., memory system controller 115) may initiate a boot sequence at least in part based on receiving a power signal. The power signal may be interrupted as part of various operations or conditions experienced by the host system (e.g., host system 105). The memory system controller 115 may transmit a first request for status information to a memory device, such as memory device 130. In response, the memory system controller 115 may receive an initialization status from the memory device 130. The memory system controller 115 may then configure a channel interface for communication with the memory device 130 at least in part based on the received initialization status. The memory system controller 115 may then communicate data with the memory device 130 using the channel interface.

[0041] Figure 2 An example of a system 200 that supports read status commands for obtaining channel status in accordance with examples disclosed herein is described. In accordance with examples disclosed herein, system 200 may include a memory system 210 configured to operate using two or more power rails. Each power rail may be configured to supply voltage from a source (e.g., a host system 205 or a motherboard that supplies power to both the host system 205 and the memory system 210) to the memory system 210. A first power rail 215 (e.g., VccQ signal) may be used to power I / O operations of the memory system controller 230 and the memory device 235. A second power rail 220 (e.g., Vcc signal) may be used to power the memory device 235 (e.g., power internal functions of the memory device 235, such as a controller, data latches, or one or more NAND arrays). In some instances, the host system 205 or the motherboard may supply a third power rail 225 (e.g., VccQ2 signal), which may be used to power a memory system controller of legacy UFS devices (e.g., prior to UFS v3.0).

[0042] For example, a memory system implementing the UFS protocol (such as UFS v3.0 or later) can use a first power rail 215 to supply the VccQ signal to the I / O circuitry of the memory system controller 230 and the memory device 235, and use a second power rail 220 to supply the Vcc signal to the memory device 235. A memory system implementing an older UFS protocol (before UFS v3.0) can use the second power rail 220 to supply the Vcc signal to the memory device and use a third power rail 225 to supply the VccQ2 signal to the memory system controller 230. The voltages supplied to the first power rail 215, the second power rail 220, and the third power rail 225 can be different to accommodate the specific circuitry and protocol being implemented. For example, the VccQ signal supplied via the first power rail 215 can be nominally 1.2V, and the Vcc signal supplied via the second power rail 220 can be nominally 3.3V. Additionally, the VccQ2 signal supplied via the third power rail 225 can be nominally 1.85V. According to the illustrative example, the memory system 210 can include a channel interface 240 to facilitate communication between the memory system controller 230 and the memory device 235. In some instances, the channel interface 240 can implement the Open NAND Flash Interface (ONFI) protocol. The memory system controller 230 can include a controller channel interface 232 and the memory device 235 can include a memory channel interface 238. The controller channel interface 232 and the memory channel interface 238 can be configured to communicate according to the channel interface 240 (e.g., can be configured according to parameters for communication such as data interface type, differential signaling, interface mode, or data rate). In some data interface types or interface modes, training can be used to optimize the timing margin (e.g., strobe placement). When the memory system controller 230 and the memory device 235 are powered on, they can undergo the process of configuring (and training if applicable) the controller channel interface 232 and the memory channel interface 238 for communication via the channel interface 240. Once the configuration and training are complete, the memory device 235 can apply the configuration parameters for communication implemented using the channel interface 240.

[0043] According to one or more examples described herein, the host system 205 may intentionally or unintentionally power down the first power rail 215 (or VccQ rail) (e.g., power off or allow it to drop below the normal range), while the second power rail 220 (or Vcc rail) remains stable. This operation causes the memory system controller 230 to reset (e.g., power cycle). When the memory system controller 230 restarts from the reset condition, it does not know the current state of the memory channel interface 238. For example, the memory system controller 230 may not know whether the memory device 235 is reset or remains operational. According to an example, the channel interface 240 between the memory device 235 and the memory system controller 230 may be an on-demand interface. Thus, a time period during which the memory system controller 230 is reset (or powered down) may result in an idle period during which no communication occurs. In such cases, the memory device 235 may not know that the memory system controller 230 has been powered down. In some examples, the memory device 235 may be powered down simultaneously or separately from the memory system controller 230.

[0044] According to an example, the memory system controller 230 may query the memory device 235 by communicating a channel status request to determine whether the memory device 235 has been powered on through a power cycle event of the memory system controller 230. In such cases, the memory device 235 may have previous configuration parameters for communicating using the channel interface 240. According to the examples disclosed herein, the status request from the memory system controller 230 will cause the communication of the status parameters currently used by the memory channel interface 238 of the memory device 235 via the channel interface 240. The memory system controller 230 may use this information to configure the controller channel interface 232, thereby omitting the configuration (and training (if applicable)) and other operations to reconstruct the configuration of the memory channel interface 238 of the memory device 235 after a power reset.

[0045] According to one example, the memory system controller 230 may communicate a request for the channel status to the memory device 235. The request for the channel status may be communicated as a modification of the read status command defined for ONFI. However, the modified command may have additional properties that allow certain interface parameters to be communicated from the memory device 235 in response to the command being received. In some examples, the request for the channel status (or modified read status command) communicated from the memory system controller 230 may be a request to determine whether the memory device 235 has been configured. In other words, the modified command may determine whether the memory device 235 has not been powered down and is thus ready to receive commands and data. In one or more examples, if the memory system controller 230 determines that the memory device 235 has suffered a power loss, it may communicate a reset command to the memory device 235.

[0046] If the memory device 235 has been configured, then a request for the channel state may also cause communication of an indication of the speed mode in which the memory device 235 is operating. For example, the memory channel interface 238 of the memory device 235 may operate in a high speed mode or a low speed mode. In one instance, the memory device 235 may communicate an indication that the memory channel interface 238 is configured to operate in a given mode (e.g., high speed mode) to the memory system controller 230. According to the disclosed examples, the memory system controller 230 may communicate a second request to obtain additional configuration parameters (e.g., channel parameters) to improve and / or optimize communication with the memory device 235 via the channel interface 240. The memory system controller 230 may configure the controller channel interface 232 to operate in the mode indicated by the memory device 235 such that data communication may continue using the indicated mode without reconfiguring the memory channel interface 238.

[0047] Figure 3 An example of a flowchart illustrating a process 300 for supporting a read status command for obtaining a channel state in accordance with examples disclosed herein. At 320, the host system 305 may cycle (e.g., intentionally or unintentionally) a supply voltage provided to a first power rail. For example, this may correspond to a power off condition where power supply to the first power rail is interrupted for a certain amount of time. In some instances, the first power rail may correspond to a distribution node of the VccQ signal that supplies voltage to the PHY interfaces of the memory device 315, the memory system controller 310, etc. If the host system 305 (or motherboard) cycles the power of the first power rail (e.g., first power supply), then the memory system controller 310 loses power and is deactivated. In some instances, the host system 305 may include a power manager that may cause the power cycle (e.g., power off) of the first power rail 215 due to the power conditions of the host system 305. In other instances, the host system 305 or motherboard may include circuitry, code, and / or components for controlling and managing the power of the first power rail.

[0048] At 325, the memory system controller 310 is reset. This may correspond to the power-up sequence of the memory system controller 310. At 330, the memory system controller may begin its boot sequence operation. In some instances, the boot sequence may include initializing various components such that the memory system controller 310 can begin performing access operations (e.g., read, write, erase, etc.) on the memory device 315. At 335, the memory system controller 310 conveys a request for the channel status to the memory device 315. In some instances, the request for the channel status may be in the form of a NAND status command (e.g., read status command or modified read status command) to determine the initialization status of the memory device 315. In other instances, the request for the channel status may correspond to a first request for status information conveyed by the memory system controller 310. In other instances, the memory device 315 may include multiple memory dies, and the memory system controller 310 may poll the memory dies sequentially or in parallel. When the memory system controller 310 polls multiple memory dies sequentially, the CE pins on the memory device 315 may be used to select a memory die for a command. When the memory system controller 310 polls multiple memory dies in parallel, different dies may be assigned to different parts of the data bus of the channel interface such that the initialization status information of multiple memory dies can be received using a single request for the channel status.

[0049] According to at least one example, a request for channel status can be communicated by the memory system controller 310 using parameters that can be recognized by or are valid for the memory device 315 under any operating conditions. In some examples, such parameters can be in the form of default parameters available to the memory device 315 (e.g., the slowest speed of the channel interface, channel settings applicable to all operating modes). Thus, a request for channel status can be received from the memory system controller 310 regardless of the current operating mode of the memory device 315. More specifically, the request for channel status can be communicated such that it is valid in all timing modes, all configurations of channel interface parameters, both legacy and serial command and address (SCA) protocols. In some examples, a request for channel status can be issued even if it is determined that the memory device 315 is busy based on status bits used to represent command array operations in ONFI. For example, bits 5 and 6 of the status register can be used to determine whether the memory device 315 is busy or available. In some examples, bit 5 (ARDY) can be set to 1 (ARDY = 1) to indicate that no array operation is in progress. ARDY can be cleared (or set) to 0 (ARDY = 0) to indicate that a command is being processed or an array operation is in progress. Bit 6 (RDY) can be set to 1 (RDY = 1) to indicate that the LUN or plane address is ready for another command and all other bits in the status value are valid. RDY can be cleared to 0 (RDY = 0) to indicate that the last command issued has not been completed. Thus, a request for channel status can be issued regardless of the status values of RDY and ARDY.

[0050] At 340, the memory device can communicate the channel status to the memory system controller 310. Since the memory system controller 310 has been recently reset, it may not know the operating state of the memory device 315. For example, the memory device 315 may have also undergone a power cycle or a reset operation. In such cases, the channel status communicated by the memory device 315 can provide an indication that the memory device 315 has been recently reset and the channel interface has not been configured. Alternatively, when the memory system controller 310 has been reset, the memory device 315 may have been continuously powered. Thus, the memory device 315 may have maintained its internal settings and parameters as well as the configuration parameters of the channel interface. In such examples, the channel status communicated at 340 can include an indication of the initialization state of the memory device 315 for establishing communication through the channel interface.

[0051] According to one example, the channel state communicated at 340 may include configuration parameters associated with the channel interface. For example, the memory device 315 may drive the I / O on the bus to a value corresponding to the status bit. Thus, there may be one or more bits for speed, data rate, timing mode, etc. According to other examples, the channel state may include more than one configuration parameter associated with the channel interface. For example, if the memory device 315 remains active during a reset operation of the memory system controller 310, the channel state may include configuration information such as whether the channel interface is operating using a legacy or SCA protocol. The channel state may also include speed, data rate, timing mode, etc. associated with the channel interface. At 345, the memory system controller 310 may utilize the channel state information received at 340 to configure its connection to the channel interface, thereby enabling communication with the memory device 315. For example, the memory system controller 310 may utilize the channel state information to establish a specific data rate or timing mode that can be used to successfully exchange or communicate information with the memory device 315 via the channel interface.

[0052] At 350, the memory system controller 310 may resume operation of the memory device 315 based on the parameters used to configure its connection to the channel interface. According to one or more examples, the memory system controller 310 may utilize other configuration parameters to improve and / or optimize communication with the memory device 315. At 355, the memory system controller 310 may communicate a request for channel parameters to the memory device 315. The channel parameters may correspond to status parameters associated with the channel interface. In some examples, the request for channel parameters communicated at 355 may correspond to a second request communicated to the memory device 315. Similar to the channel state request communicated at 335, the request for channel parameters may be configured as a NAND status command, such as a read status command or a modified read status command.

[0053] In at least one example, the request for channel parameters may provide an indication that the memory system controller 310 is requesting a specific parameter. For example, the request for channel parameters may only specify the communication of interface mode parameters. In another example, the request for channel parameters may specify the communication of ZQ calibration status, warm-up cycle configuration, and duty cycle correction information. In other examples, the request for channel parameters may include an indication that all available channel parameters should be communicated. For example, such channel parameters may include interface mode (NV-DDR3 / NV-DDR4 / etc.), differential signaling usage, VrefQ configuration status, ZQ calibration status, warm-up cycle configuration, duty cycle correction information, read / write training information, etc. It should be noted that the above list is not intended to be exhaustive and other channel parameters are available.

[0054] At 360, the memory device 315 communicates channel parameters to the memory system controller 310. In one example, the memory device 315 may communicate only the channel parameters specified in a request from the memory system controller 310. Thus, the memory device 315 may communicate a single parameter or multiple parameters. In other examples, the memory device 315 may communicate all available parameters to the memory system controller 310. As previously discussed, for example, the channel parameters communicated by the memory device 315 may include interface mode (NV-DDR3 / NV-DDR4 / etc.), differential signaling usage, VrefQ configuration status, ZQ calibration status, warm boot cycle configuration, duty cycle correction information, read / write training information, etc. At 365, the memory system controller 310 may utilize the channel parameters received at 360 to modify or improve the configuration of its connection to the channel interface used to communicate with the memory device 315. At 370, the memory system controller 310 resumes operation of the memory device 315.

[0055] Figure 4 FIG. 400 is a block diagram illustrating a memory system 420 that supports a read status command for obtaining a channel status in accordance with examples disclosed herein. The memory system 420 may be an example of aspects of the memory system described in Figures 1 to 3 reference. The memory system 420 or its various components may be examples of components for performing various aspects of a read status command for obtaining a channel status as described herein. For example, the memory system 420 may include a boot sequence initiator circuit 425, a controller 430, a memory device 435, a channel interface 440, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0056] The boot sequence initiator circuit 425 can be configured to or otherwise support components for initiating a boot sequence at least in part based on a received power signal. In some instances, the boot sequence initiator circuit 425 can be part of the controller 430. The controller 430 can be configured to or otherwise support components for transmitting a first request for status information to a memory device (e.g., memory device 435) of the memory system 420. The controller 430 can be configured to or otherwise support components for receiving an indication of an initialization state from the memory device at least in part based on communicating the first request. In some instances, the memory device 435 can be configured to or otherwise support components for transmitting an indication of the initialization state of the memory device to the controller 430 at least in part based on receiving the first request for status information. In some instances, the controller 430 can be configured to or otherwise support components for configuring a channel interface (e.g., channel interface 440) for communication with the memory device at least in part based on the indication of the initialization state. The channel interface 440 can be configured to or otherwise support components for communicating data between the controller 430 and the memory device 435.

[0057] In some instances, the controller 430 can be configured to or otherwise support components for receiving at least one configuration parameter associated with the channel interface 440 from the memory device 435 at least in part based on the first request for status information.

[0058] In some instances, the controller 430 can be configured to or otherwise support components for receiving an indication of one or more of a type, a data rate, or a timing mode associated with the channel interface 440 from the memory device 435 at least in part based on the first request for status information.

[0059] In some instances, the controller 430 can be configured to or otherwise support components for transmitting a second request for status information associated with the channel interface 440 at least in part based on receiving the indication of the initialization state. In some instances, the controller 430 can be configured to or otherwise support components for receiving one or more status parameters associated with the channel interface 440 at least in part based on transmitting the second request, wherein configuring the channel interface 440 for communication with the memory device 435 is at least in part based on receiving the one or more status parameters.

[0060] In some instances, the one or more status parameters include one or more of a current interface mode, differential signaling usage, reference voltage (VrefQ) configuration, ZQ calibration status, warm boot cycle configuration, duty cycle correction information, or read / write training information.

[0061] In some instances, the controller 430 may be configured to or otherwise support components for transmitting a third request to the memory device 435 indicative of a power loss of the memory device 435 based at least in part on an indication of an initialization state, where the third request instructs the memory device to perform a reset operation.

[0062] In some instances, the channel interface 440 supports multiple timing modes each including one or more transmission parameters corresponding to different data communication rates, and a first request for status information is transmitted using values of the one or more transmission parameters supported by each of the multiple timing modes.

[0063] In some instances, the power signal received at the controller is a power supply for an input / output driver of the memory device.

[0064] Figure 5 The illustration presents a flowchart of a method 500 that supports a read status command for obtaining a channel state according to examples disclosed herein. Operations of method 500 may be implemented by the memory system or components thereof described herein. For example, operations of method 500 may be performed by the memory system referenced Figures 1 to 4 described. In some instances, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may perform aspects of the described functions using dedicated hardware.

[0065] At 505, the method may include initiating a boot sequence at a controller of the memory system based at least in part on receiving a power signal. Operation 505 may be performed according to examples disclosed herein. In some instances, aspects of operation 505 may be performed by the boot sequence initiator circuit 425 referenced Figure 4 described.

[0066] At 510, the method may include transmitting a first request for status information from the controller to a memory device of the memory system. Operation 510 may be performed according to examples disclosed herein. In some instances, aspects of operation 510 may be performed by the controller 430 referenced Figure 4 described.

[0067] At 515, the method may include receiving an indication of an initialization state from the memory device based at least in part on conveying the first request. Operation 515 may be performed according to examples disclosed herein. In some instances, aspects of operation 515 may be performed by the controller 430 referenced Figure 4 described.

[0068] At 520, the method may include configuring a channel interface for communicating with a memory device by a controller based at least in part on an indication of an initialization state. Operation 520 may be performed according to the examples disclosed herein. In some examples, aspects of operation 520 may be performed by the controller 430 described with reference to Figure 4 described.

[0069] At 525, the method may include communicating data between the controller and the memory device using the channel interface based at least in part on the configured channel interface. Operation 525 may be performed according to the examples disclosed herein. In some examples, aspects of operation 525 may be performed by the channel interface 440 described with reference to Figure 4 described.

[0070] In some examples, a device described herein may perform one or several methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0071] Aspect 1: A method, device, or non-transitory computer-readable medium including operations, features, circuitry, logic, components, or instructions or any combination thereof for: initiating a boot sequence at a controller of a memory system based at least in part on receiving a power signal; transmitting a first request for status information from the controller to a memory device of the memory system; receiving an indication of an initialization state from the memory device based at least in part on communicating the first request; configuring a channel interface for communicating with the memory device by the controller based at least in part on the indication of the initialization state; and communicating data between the controller and the memory device using the channel interface based at least in part on configuring the channel interface.

[0072] Aspect 2: The method, device, or non-transitory computer-readable medium according to aspect 1, further including operations, features, circuitry, logic, components, or instructions or any combination thereof for: receiving at least one configuration parameter associated with the channel interface from the memory device based at least in part on the first request for status information.

[0073] Aspect 3: The method, device, or non-transitory computer-readable medium according to any one of aspects 1 to 2, further including operations, features, circuitry, logic, components, or instructions or any combination thereof for: receiving an indication of one or more of a type, a data rate, or a timing pattern associated with the channel interface from the memory device based at least in part on the first request for status information.

[0074] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting, at least in part based on receiving the indication of the initialization state, a second request for status information associated with the channel interface from the controller; and receiving, at least in part based on transmitting the second request, one or more status parameters associated with the channel interface, wherein configuring the channel interface for communication with the memory device is at least in part based on receiving the one or more status parameters.

[0075] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to Aspect 4, wherein the one or more status parameters include one or more of a current interface mode, differential signaling usage, reference voltage (VrefQ) configuration, ZQ calibration status, warm boot cycle configuration, duty cycle correction information, or read / write training information.

[0076] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a third request to the memory device, at least in part based on the indication of the initialization state indicating a power loss of the memory device, wherein the third request instructs the memory device to perform a reset operation.

[0077] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein the channel interface supports multiple timing modes each including one or more transmission parameters corresponding to different data communication rates, and the first request for status information is transmitted using values of the one or more transmission parameters supported by each of the multiple timing modes.

[0078] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the power signal received at the controller is a power supply for an input / output driver of the memory device.

[0079] It should be noted that the described technology includes possible embodiments, and the operations and steps may be rearranged or otherwise modified and other embodiments are possible. Additionally, parts from two or more of the methods may be combined.

[0080] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0081] The terms “electronically communicate,” “electrically contact,” “connect,” and “couple” may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating (or electrically contacting or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are electronically communicating (or electrically contacting or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted over a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0082] The term “couple” (e.g., “electrically couple”) may refer to a condition of transitioning from an open-circuit relationship between components (where signals cannot currently pass between the components through a conductive path) to a closed-circuit relationship between components (where signals can pass between the components through a conductive path). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0083] The term “isolate” refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, if a switch located between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components through a conductive path that previously allowed signal flow.

[0084] The terms “layer” or “stratum” as used herein refer to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or stratum may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or stratum may be a three-dimensional structure where two dimensions are greater than the third dimension, such as a thin film. A layer or stratum may include different elements, components, and / or materials. In some instances, a layer or stratum may be composed of two or more sub-layers or sub-strata.

[0085] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term "substantially") need not be absolute, but is close enough to achieve the advantage of the characteristic.

[0086] As used herein, the term "electrode" may refer to an electrical conductor and, in some instances, may serve as an electrical contact for other components of a memory cell or memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0087] The terms "if," "when," "based on," or "at least partially based on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "at least partially based on" are used to describe a connection between conditional actions, conditional processes, or parts of a process, then the terms may be interchangeable.

[0088] The term "responsive to" may refer to a condition or action occurring at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the previous condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0089] Additionally, the terms "directly responsive to" or "directly respond to" may refer to a condition or action occurring directly as a result of a previous condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least partially based on," or "responsive to" some other step, action, event, or condition may alternatively or additionally (e.g., in an alternative instance) be performed "directly responsive to" or "directly respond to" this other condition or action.

[0090] The devices (including memory arrays) discussed in this document can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping using various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0091] The switching components or transistors discussed in this document can represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive materials, such as metals. The source and the drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and the drain can be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, then the transistor can be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, then the transistor can be "turned off" or "deactivated".

[0092] The descriptions presented in this document describe example configurations in conjunction with the accompanying drawings and do not represent all examples that can be implemented or are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". "Detailed description" includes specific details for providing an understanding of the described technology. However, the technology can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0093] In the drawings, like components or features can have the same reference numerals. Additionally, various components of the same type can be distinguished by following the reference numeral with a hyphen and a second numeral that differentiates the like components. If only the first reference numeral is used in the specification, then the description applies to any of the like components having the same first reference numeral, regardless of the second reference numeral.

[0094] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0095] For example, the various illustrative blocks and components described herein in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0096] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0097] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Thus, the terms "a", "at least one", "one or more", "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, then each of the individual functions may be performed by a single component or any combination of multiple components. Thus, the term "a component" with a particular or performing function may refer to "at least one of one or more components" having a particular characteristic or performing a particular function. Subsequently, the use of the term "the / said" to refer to a component introduced with the article "a" may refer to any or all of one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and subsequent reference to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components". Similarly, subsequent use of the term "the / said" to refer to a component introduced as "one or more components" may refer to any or all of one or more components. For example, subsequent reference to "one or more components" in the claim may be understood to be equivalent to referring to "at least one of one or more components".

[0098] Computer-readable media includes both non-transitory computer storage media and communication media, which includes any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that is accessible by a general or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code instructions or data structures in the form of and that is accessible by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable media. By way of example, if software is transmitted using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave, from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology such as infrared, radio, and microwave is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0099] The description provided herein enables a person of ordinary skill in the art to make or use the present disclosure. Those of ordinary skill in the art will understand the various modifications of the present disclosure, and without departing from the scope of the present disclosure, the general principles defined herein can be applied to other variations. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: initiating a boot sequence at a controller of the memory system based at least in part on receiving the power signal; transmitting a first request for status information from the controller to a memory device of the memory system; receiving an indication of an initialization status from the memory device based at least in part on communicating the first request; configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization state; and Data is communicated between the controller and the memory device using the channel interface based at least in part on configuring the channel interface.

2. The method according to claim 1, further comprising: At least one configuration parameter associated with the channel interface is received from the memory device based at least in part on the first request for status information.

3. The method according to claim 1, further comprising: An indication of one or more of a type, a data rate, or a timing mode associated with the channel interface is received from the memory device based at least in part on the first request for status information.

4. The method according to claim 1, further comprising: transmitting, from the controller, a second request for status information associated with the channel interface based at least in part on receiving the indication of the initialization status; and One or more state parameters associated with the channel interface are received based at least in part on transmitting the second request, wherein configuring the channel interface for communicating with the memory device is based at least in part on receiving the one or more state parameters.

5. The method of claim 4, wherein the one or more status parameters include one or more of current interface mode, differential signaling usage, reference voltage VrefQ configuration, ZQ calibration status, warm-up cycle configuration, duty cycle correction information, or read / write training information.

6. The method according to claim 1, further comprising: A third request is transmitted to the memory device based at least in part on the indication of the initialization state indicating a loss of power to the memory device, wherein the third request instructs the memory device to perform a reset operation.

7. The method of claim 1 , wherein the channel interface supports a plurality of timing modes that each include one or more transmission parameters corresponding to a different data communication rate, and the first request for status information is transmitted using values ​​of the one or more transmission parameters supported by each of the plurality of timing modes.

8. The method of claim 1, wherein the power signal received at the controller is a power supply for an input / output driver of the memory device.

9. A non-transitory computer readable medium storing code, the code comprising instructions executable by a processor to: initiating a boot sequence at a controller of the memory system based at least in part on receiving the power signal; transmitting a first request for status information from the controller to a memory device of the memory system; receiving an indication of an initialization status from the memory device based at least in part on communicating the first request; configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization state; and Data is communicated between the controller and the memory device using the channel interface based at least in part on configuring the channel interface.

10. The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the processor to: At least one configuration parameter associated with the channel interface is received from the memory device based at least in part on the first request for status information.

11. The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the processor to: An indication of one or more of a type, a data rate, or a timing mode associated with the channel interface is received from the memory device based at least in part on the first request for status information.

12. The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the processor to: transmitting, from the controller, a second request for status information associated with the channel interface based at least in part on receiving the indication of the initialization status; and One or more state parameters associated with the channel interface are received based at least in part on transmitting the second request, wherein configuring the channel interface for communicating with the memory device is based at least in part on receiving the one or more state parameters.

13. The non-transitory computer-readable medium of claim 12, wherein the one or more status parameters include one or more of a current interface mode, differential signaling usage, a reference voltage VrefQ configuration, a ZQ calibration state, a warm-up cycle configuration, duty cycle correction information, or read / write training information.

14. The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the processor to: A third request is transmitted to the memory device based at least in part on the indication of the initialization state indicating a loss of power to the memory device, wherein the third request instructs the memory device to perform a reset operation.

15. The non-transitory computer-readable medium of claim 9, wherein the channel interface supports a plurality of timing modes that each include one or more transmission parameters corresponding to a different data communication rate, and the first request for status information is transmitted using values ​​of the one or more transmission parameters supported by each of the plurality of timing modes.

16. The non-transitory computer-readable medium of claim 9, wherein the power signal received at the controller is a power supply for an input / output driver of the memory device.

17. An apparatus comprising: a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: initiating a boot sequence at a controller of the memory system based at least in part on receiving the power signal; transmitting a first request for status information from the controller to a memory device of the memory system; receiving an indication of an initialization status from the memory device based at least in part on communicating the first request; configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization state; and Data is communicated between the controller and the memory device using the channel interface based at least in part on configuring the channel interface.

18. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: At least one configuration parameter associated with the channel interface is received from the memory device based at least in part on the first request for status information.

19. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: An indication of one or more of a type, a data rate, or a timing mode associated with the channel interface is received from the memory device based at least in part on the first request for status information.

20. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: transmitting, from the controller, a second request for status information associated with the channel interface based at least in part on receiving the indication of the initialization status; and One or more state parameters associated with the channel interface are received based at least in part on transmitting the second request, wherein configuring the channel interface for communicating with the memory device is based at least in part on receiving the one or more state parameters.

21. The apparatus of claim 20, wherein the one or more state parameters include one or more of a current interface mode, differential signaling usage, a reference voltage VrefQ configuration, a ZQ calibration state, a warm-up cycle configuration, duty cycle correction information, or read / write training information.

22. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: A third request is transmitted to the memory device based at least in part on the indication of the initialization state indicating a loss of power to the memory device, wherein the third request instructs the memory device to perform a reset operation.

23. The apparatus of claim 17, wherein the channel interface supports a plurality of timing modes that each include one or more transmission parameters corresponding to a different data communication rate, and the first request for status information is transmitted using values ​​of the one or more transmission parameters supported by each of the plurality of timing modes.

24. The apparatus of claim 17, wherein the power signal received at the controller is a power supply for an input / output driver of the memory device.

25. An apparatus comprising: processor; a memory coupled to the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: initiating a boot sequence at a controller of the memory system based at least in part on receiving the power signal; transmitting a first request for status information from the controller to a memory device of the memory system; receiving an indication of an initialization status from the memory device based at least in part on communicating the first request; configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization state; and Data is communicated between the controller and the memory device using the channel interface based at least in part on configuring the channel interface.

26. The apparatus of claim 25, wherein the instructions are further executable by the processor to cause the apparatus to: At least one configuration parameter associated with the channel interface is received from the memory device based at least in part on the first request for status information.

27. The apparatus of claim 25, wherein the instructions are further executable by the processor to cause the apparatus to: An indication of one or more of a type, a data rate, or a timing mode associated with the channel interface is received from the memory device based at least in part on the first request for status information.

28. The apparatus of claim 25, wherein the instructions are further executable by the processor to cause the apparatus to: transmitting, from the controller, a second request for status information associated with the channel interface based at least in part on receiving the indication of the initialization status; and One or more state parameters associated with the channel interface are received based at least in part on transmitting the second request, wherein configuring the channel interface for communicating with the memory device is based at least in part on receiving the one or more state parameters.

29. The apparatus of claim 28, wherein the one or more state parameters include one or more of a current interface mode, differential signaling usage, a reference voltage VrefQ configuration, a ZQ calibration state, a warm-up cycle configuration, duty cycle correction information, or read / write training information.

30. The apparatus of claim 25, wherein the instructions are further executable by the processor to cause the apparatus to: A third request is transmitted to the memory device based at least in part on the indication of the initialization state indicating a loss of power to the memory device, wherein the third request instructs the memory device to perform a reset operation.

31. The apparatus of claim 25, wherein the channel interface supports a plurality of timing modes that each include one or more transmission parameters corresponding to a different data communication rate, and the first request for status information is transmitted using values ​​of the one or more transmission parameters supported by each of the plurality of timing modes.

32. The apparatus of claim 25, wherein the power signal received at the controller is a power supply for an input / output driver of the memory device.

Images