Verilog HDL code automatic generation method based on constant multiplier directed graph

Abstract

The invention provides a Verilog HDL code automatic generation method based on a constant multiplier directed graph, belongs to the technical field of computers, solves the problem that a traditional constant multiplier optimization method is difficult to cope with large-scale scene calculation, and comprises the steps that 1, adjacent matrix modeling is conducted on directed graph sets {DAG1 and DAG2} corresponding to constant sets {c1, c2,...}, and a matrix set MatrixList is obtained; step 2, splitting the matrix group MatrixList into a left matrix MatrixL and a right matrix MatrixR; 3, the bit width Width of an input signal x, the left matrix MatrixL and the right matrix MatrixR are input into Verilog HDL to generate a model to obtain corresponding Verilog HDL codes, constant multiplication under the optimal resource condition is achieved, constant multiplication comprises SCM, MCM, TmSCM and TmMCM, SCM is single constant multiplication, MCM is multi-constant multiplication, TmSCM is time division multiplexing single constant multiplication, and TmMCM is time division multiplexing multi-constant multiplication.

Description

Technical Field

[0001] The present invention relates to a method for automatically generating Verilog HDL code based on a directed graph of constant multipliers, belonging to the field of computer technology. Background Art

[0002] Constant Multiplier (CM) plays an important role in digital signal processing and hardware design. Its optimized design can significantly improve the efficiency and performance of hardware implementation. Different from general multipliers, constant multipliers focus on the multiplication operation of fixed constants and variables. By optimizing according to the characteristics of constants, it reduces hardware resource consumption and operation latency, and has become a key module in fields such as embedded systems, filter design, and image processing. In recent years, with the continuous expansion of application requirements, the implementation methods and optimization techniques of constant multipliers have been widely studied and deeply developed.

[0003] There are various implementation methods for constant multipliers. The direct expansion method is the most basic implementation way, generating hardware logic by decomposing constants into combinations of shifts and additions. This method is simple and easy to implement, but it is not efficient in high-bit-width and complex scenarios. In contrast, bit-level optimization techniques reduce the use of logic gates and adders by precisely calculating the bit-width of intermediate signals, significantly reducing the hardware resource requirements. In the scenario of Multiple Constant Multiplication (MCM), the commonly used shared partial product technique can identify the common partial products among multiple constants, thereby reducing redundant calculations and optimizing resource utilization. In addition, the graph-based modeling method formalizes the constant multiplication problem as a directed acyclic graph (DAG), and uses graph optimization algorithms (such as minimizing the number of adders) to further simplify the hardware implementation. In recent years, time-division multiplexing technology has also gradually received attention. By time-sharing scheduling to multiplex hardware resources, it effectively reduces the hardware area and power consumption while ensuring the operation accuracy.

[0004] Although significant progress has been made in the research of constant multipliers, there are still some challenges. The first is the issue of scale scalability. As the input bit-width and the number of constants increase, the circuit complexity grows exponentially, and traditional optimization methods are difficult to handle large-scale scenarios. Secondly, the automated design still needs to be further improved. Especially when generating optimized hardware code, how to achieve an efficient and accurate automated process is still a research hotspot.

[0005] The automatic generation method based on the adjacency matrix is an important trend. By modeling constant multiplication as an adjacency matrix, optimized Verilog code can be efficiently generated. This method has high efficiency and scalability, and is especially suitable for multi-constant and complex hardware scenarios. Summary of the Invention

[0006] To solve the problem that traditional constant multiplier optimization methods are difficult to handle large-scale scenario calculations, the present invention proposes a method for automatically generating Verilog HDL code based on a directed graph of a constant multiplier.

[0007] The technical solution adopted by the present invention to solve the above problems is as follows: The present invention includes the following steps:

[0008] Step 1: Model the adjacency matrix for the set of directed graphs {DAG 1 , DAG 2 ,...} corresponding to the constant set {c 1 , c 2}, and obtain a matrix group Matrix_List;

[0009] Step 2: Split the matrix group Matrix_List into a left matrix Matrix_L and a right matrix Matrix_R;

[0010] Step 3: Input the bit width Width of the input signal x, the left matrix Matrix_L, and the right matrix Matrix_R into the Verilog HDL generation model to obtain the corresponding Verilog HDL code, and implement constant multiplication under the condition of optimal resources. Among them, constant multiplication includes SCM, MCM, TmSCM, and TmMCM. Among them, SCM is single constant multiplication, MCM is multi-constant multiplication, TmSCM is time-division multiplexed single constant multiplication, and TmMCM is time-division multiplexed multi-constant multiplication.

[0011] Preferably, step 1 specifically includes:

[0012] Establish an adjacency matrix according to the displacement between nodes in the set of directed graphs corresponding to the constant set {c 1 , c 2 ,...}. Each parameter corresponds to an adjacency matrix. The directed graph includes v i nodes. The i-th column in the adjacency matrix represents the i-th adder / subtractor node v i . After the node moves, it is input to the next node v j . The displacement of the node corresponds to the element in the i-th row and j-th column of the adjacency matrix. The adder / subtractor includes two inputs. When the element on the diagonal of the adjacency matrix is non-zero, it indicates that the corresponding node is an output node, and the value on the diagonal is the displacement size of the corresponding node;

[0013] The expression of the adjacency matrix is:

[0014]

[0015] Preferably, step 2 specifically includes:

[0016] Step 2.1: For any column in the adjacency matrix, if an element in the adjacency matrix is negative, put the negative value element in the corresponding position of Matrix_R and the positive value element in the corresponding position of Matrix_L; if all elements in the adjacency matrix are positive, put the elements smaller than the average value of the elements in Matrix_L and the elements larger than the average value in Matrix_R; if an element in the adjacency matrix is already included in Matrix_L, put the other element in the corresponding position of Matrix_R; the elements on the diagonal are reserved;

[0017] Step 2.2: Repeat Step 2.2 until all matrices in the adjacency matrix group are traversed to obtain the left matrix Matrix_L and the right matrix Matrix_R.

[0018] Preferably, the Verilog HDL generation model includes a module definition generation module, an internal signal declaration generation module, and a logic description generation module;

[0019] The module definition generation module is used to generate the module name and port definition of the Verilog code;

[0020] The internal signal declaration generation module is used to calculate the bit width of the internal signal and declare the relevant internal signals to optimize the internal signal at the bit level;

[0021] The logic description generation module is used to generate the Verilog HDL code of the assignment statement to implement correct shift and addition / subtraction calculations.

[0022] Preferably, the module definition generation module generating the module name and port definition of the Verilog code specifically includes:

[0023] Generate the module name const_multiplier through the module definition generation module, define the ports, and the defined ports include the input signal x, the selection signal sel, and the output signal y i , the bit width of the input signal x is determined by the input signal Width, the bit width of the selection signal sel is determined by the number of matrices in the adjacency matrix group Matrix_List, and the output signal y i The value range of i in is determined by the maximum output number of the adjacency matrix, and the output signal y i The bit width of is determined by the maximum bit width of the output node.

[0024] Preferably, the internal signal declaration generation module calculating the bit width of the internal signal and declaring the relevant internal signals specifically includes:

[0025] Set the left input bit width of the left matrix Matrix_L of the current node as width_l_input, the right input bit width of the right matrix Matrix_R as width_r_input, and the node output bit width as width_v. For the i-th node, obtain the elements of the i-th column of Matrix_L to get the shift Shift_l; obtain the elements of the i-th column of Matrix_R to get the shift Shift_r, calculate the left input bit width width_l_input, the right input bit width width_r_input of the current node, and the bit width of the current output node, and generate corresponding Verilog HDL statements by combining the left input bit width width_l_input, the right input bit width width_r_input of the current node, and the bit width of the current output node;

[0026] The calculation formula for the left input bit width width_l_input is:

[0027] width_l_input = max(width_v + Shift__l)-Co_Shift_l (2);

[0028] In formula (2), Co_Shift_l is the common left shift / right shift bit width in Shift_l;

[0029] The calculation formula for the right input bit width width_r_input is:

[0030] width_r_input = max(width_v + Shift__r)-Co_Shift_r (3);

[0031] In formula (3), Co_Shift_r is the common left shift / right shift bit width in Shift_r;

[0032] The calculation formula for the bit width of the current output node is:

[0033] width_v = width_v ∪ (max(width_l_input_i, width_r_input_i)+1)(4).

[0034] Preferably, the Verilog HDL code for the assignment statement generated by the logic description generation module specifically includes:

[0035] Traverse each column of the left matrix Matrix_L and the right matrix Matrix_R, calculate the left input l_input_i and the right input r_input_i. For the i-th node, obtain the non-zero elements in the i-th column of Matrix_L and Matrix_R. When the number of non-zero elements is greater than 1, use the sel signal to determine the assignment. If Co_Shift_l > Co_Shift_r, based on the node result v i The node result v is obtained according to the calculation formula i , and is selected through the sel signal and the node result v i is assigned to the output y i ;

[0036] The calculation formulas for the left input l_input_i and the right input r_input_i are as follows:

[0037] l_input = generate_verilog(Matrix_L[:,i])(5);

[0038] r_input = generate_verilog(Matrix_R[:,i])(6);

[0039] The node result v i The calculation formula is:

[0040] v i [Co_Shift_r:0] = 0;

[0041] v i [(Co_Shift_l:Co_Shift_r + 1] = r_input_i[(Co_Shift_l - Co_Shift_r) - 1:0]; (7).

[0042] v i [width_v[i] - 1:Co_Shift_l + 1] = l_input + r_input[width_r_input - 1;

[0043] Co_Shift_l - Co_Shift_r]

[0044] The beneficial effects of the present invention are:

[0045] 1. The present invention simultaneously supports the adjacency matrix groups of SCM and MCM, achieving bit-level resource optimization;

[0046] 3. The implementation languages for automatically generating Verilog HDL code designed by the present invention include but are not limited to Python, C++, etc.

[0047] 3. One of the core advantages of the present invention is to generate module definitions, signal declarations, and logical descriptions in an automated manner, avoiding errors and repetitive labor that may occur when manually writing Verilog HDL code. The generated hardware description code can not only efficiently utilize hardware resources but also be customized according to specific application requirements, thus supporting multiplication calculation tasks of different scales. In addition, through precise bit-width calculation and reasonable hardware resource allocation, it can effectively run on hardware platforms of different scales and adapt to various application scenarios from small embedded systems to high-performance computing platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flowchart of a method for automatically generating Verilog HDL code based on a directed graph of a constant multiplier provided by the present invention;

[0049] Figure 2 is a schematic diagram of adjacency matrix modeling provided by the present invention;

[0050] Figure 3 is a schematic diagram of splitting the left and right matrices provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] DETAILED DESCRIPTION OF THE EMBODIMENT 1: In combination with Figures 1-3 explain this embodiment. As Figure 1 shown, the steps of a method for automatically generating Verilog HDL code based on a directed graph of a constant multiplier described in this embodiment include:

[0052] S1: Perform adjacency matrix modeling on the set of directed graphs {DAG 1 , DAG 2 ,...} corresponding to the set of constants {c 1 , c 2} to obtain a matrix group Matrix_List;

[0053] In the current research on constant multipliers, directed graphs are generally used to model the solutions to problems. Its advantage lies in the intuitive understanding of the solution process, but the data structure is relatively complex and not conducive to directly calculating or processing the directed graph. Therefore, this embodiment proposes to use an adjacency matrix to model the solution of the constant multiplier. The modeling method is as Figure 1 shown. The i-th column of the adjacency matrix represents the i-th adder (subtractor) node v i (by default, the input X is the 0th node). After the node is shifted left or right, it is input to the next node v j, whose displacement corresponds to the element in the \(i\)-th row and \(j\)-th column of the adjacency matrix. Each adder has two inputs. When the element on the diagonal is non-zero, it indicates that the node is an output node, and its value represents the magnitude of the displacement. After modeling the solution of the constant multiplier as an adjacency matrix, the properties of the matrix can be used to transform and calculate it, greatly simplifying the processing difficulty.

[0054] The present invention conducts research on modeling the constant multiplier problem using the adjacency matrix model, supports the input of any number of constants, and calculates the bit-width of the intermediate signals to generate the result with the minimum resource consumption.

[0055] S2: Split the matrix group Matrix_List into a left matrix Matrix_L and a right matrix Matrix_R;

[0056] The set of numbers \(\{c\) 1 , \(c\) 2 ,... \} The obtained directed graph through the solver is modeled by the adjacency matrix through the Figure 2 method. Each constant corresponds to an adjacency matrix, and together they form an adjacency matrix group Matrix_List. To maximize resource reuse, in this embodiment, the adjacency matrix group is merged into a joint matrix UnionMatrix. However, the joint matrix can only show the connection relationship between node \(i\) and node \(j\), and cannot distinguish whether it is a left input or a right input, resulting in an increase in resource overhead.

[0057] In view of the above situation, in this embodiment, the joint matrix is split into a left input matrix Matrix_L and a right input matrix Matrix_R. Taking TmSCM as an example, the conversion is carried out according to the following rules, and the conversion process is as Figure 3 shown:

[0058] For a certain column, if an element of the adjacency matrix is negative, it is placed in the corresponding position of Matrix_R, and the positive value is placed in the corresponding position of Matrix_L; if all elements of the adjacency matrix are positive, the smaller value is placed in Matrix_L and the larger value is placed in Matrix_R; if an element of the adjacency matrix is already included in Matrix_L (or Matrix_R), the other value is placed in the corresponding position of Matrix_R (or Matrix_L); the elements on the diagonal are reserved; the above operations are repeated for all matrices in the adjacency matrix group. For TmMCM, the only difference from TmSCM is that the number of non-zero elements on the diagonal is not 1, which is determined by the number of constants.

[0059] S3: Take the bit width Width of the input signal x, and input the left matrix Matrix_L and the right matrix Matrix_R into the VerilogHDL generation model to obtain the corresponding VerilogHDL code, realizing constant multiplication under the condition of optimal resources.

[0060] Generate module definitions, signal declarations, and logic descriptions in an automated manner, avoiding errors and repetitive labor that may be caused by manually writing VerilogHDL code. The generated hardware description code can not only efficiently utilize hardware resources but also be customized according to specific application requirements, thus supporting multiplication calculation tasks of different scales. In addition, through precise bit width calculation and reasonable hardware resource allocation, it can operate effectively on hardware platforms of different scales, adapting to various application scenarios from small embedded systems to high-performance computing platforms.

[0061] After obtaining the adjacency matrix group Matrix_List, the left matrix Matrix_L, the right matrix Matrix_R, and the bit width Width of the input signal x, input them into the Verilog HDL generation module to obtain the corresponding Verilog HDL code, realizing constant multiplication under the condition of optimal resources; The Verilog HDL generation module includes three main functional modules: a module definition generation module, an internal signal declaration generation module, and a logic description generation module. The module definition functional module is responsible for generating the module name and port definitions of the Verilog code; The internal signal declaration functional module is responsible for calculating the bit widths of internal signals and declaring relevant internal signals to achieve bit-level optimization; The logic description functional module is responsible for generating assignment statements to implement correct shift and addition / subtraction calculations. The specific steps are as follows:

[0062] S301: The function of the module definition functional module is to generate the module name const_multiplier and define the ports, including the input signal x, whose bit width is determined by the input signal Width; The selection signal sel, whose bit width is determined by the number of the adjacency matrix group Matrix_List; The output signal y i , the value range of i is determined by the maximum output number of the adjacency matrix, and its bit width is determined by the maximum bit width of the output node. The present invention supports single constant multiplication (SCM), multiple constant multiplication (MCM), time-division multiplexing single constant multiplication (TmSCM), and time-division multiplexing multiple constant multiplication (TmMCM);

[0063] S302: The function of the internal signal declaration generation module is to generate statements defining intermediate signals and calculate the corresponding bit widths. Each column of the adjacency matrix can be regarded as a basic calculation unit, which consists of a left input, a right input, and a node output. Therefore, it is necessary to traverse each column of the left matrix Matrix_L and the right matrix Matrix_R, and calculate the left input l_input_i, the right input r_input_i, and the node v i of the bit width. The pseudocode of the calculation process is shown in Table 1:

[0064] Table 1

[0065]

[0066] The bit width of the left input of the current node is denoted as width_l_input, the bit width of the right input is denoted as width_r_input, and the bit width of the node output is denoted as width_v. For the i-th node, obtain the elements of the i-th column of Matrix_L to get the shift Shift_l; obtain the elements of the i-th column of Matrix_R to get the shift Shift_r, and calculate the left input bit width width_l_input according to the 9th row in Table 1, where Co_Shift_l represents the common left or right shift bit width in Shift_l; calculate the right input bit width width_r_input according to the 10th row in Table 1, where Co_Shift_r represents the common left or right shift bit width in Shift_r; then obtain the bit width of the current output node according to the 11th row in Table 1. Finally, generate the corresponding Verilog HDL statements.

[0067] S303: The logic description function module is responsible for generating the shift and assignment statements of each adder unit. Traverse each column of the left matrix Matrix_L and the right matrix Matrix_R, and calculate the left input l_input_i, the right input r_input_i, and the node result v i The pseudocode of the calculation process is shown in Table 2:

[0068] Table 2

[0069]

[0070] For the i-th node, obtain the non-zero elements of the i-th column of Matrix_L and Matrix_R. When the number of non-zero elements is greater than 1, the sel signal is needed to determine the assignment. If Co_Shift_l > Co_Shift_r, calculate according to the formulas in the 7th - 10th rows of Table 2, and vice versa. For the multi-constant adjacency matrix group, different adjacency matrices often have different output nodes, and the sel signal is needed to select and assign the output node v i to y i, the value range of i is determined by the maximum output number of the adjacency matrix.

[0071] As described above, it is only the preferred embodiment of the present invention, and there is no limitation to the present invention in any form. Although the present invention has been disclosed above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments of equivalent changes within the scope of the technical solution of the present invention by using the above-disclosed technical content. However, as long as it does not depart from the technical solution content of the present invention and is based on the technical essence of the present invention, any simple modification, equivalent replacement, and improvement of the above embodiments still fall within the protection scope of the technical solution of the present invention.

Claims

1. A VerilogHDL code automatic generation method based on a constant multiplier directed graph, characterized in that: The steps of the VerilogHDL code automatic generation method based on the constant multiplier directed graph include: Step 1: Perform adjacency matrix modeling on the directed graph set {DAG1, DAG2} corresponding to the constant set {c1, c2, ...} to obtain the matrix group Matrix_List; Step 2: Split the matrix group Matrix_List into the left matrix Matrix_L and the right matrix Matrix_R; Step 3: Input the bit width Width of the input signal x, the left matrix Matrix_L and the right matrix Matrix_R into the VerilogHDL generation model to obtain the corresponding VerilogHDL code to implement constant multiplication under resource-optimal conditions, where constant multiplication includes SCM, MCM, TmSCM and TmMCM. SCM is single constant multiplication, MCM is multiple constant multiplication, TmSCM is time-sharing single constant multiplication, and TmMCM is time-sharing multiple constant multiplication.

2. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 1, characterized in that: Step 1 specifically includes: The adjacency matrix is ​​established according to the displacement between nodes in the directed graph set corresponding to the constant set {c1, c2, ...}. Each parameter corresponds to an adjacency matrix. The directed graph includes v i nodes, the i-th column in the adjacency matrix represents the i-th adder / subtractor node v i , the node is moved and then input to the next node v j , the displacement of the node corresponds to the element in the i-th row and j-th column of the adjacency matrix. The adder / subtractor includes two inputs. When the elements on the diagonal of the adjacency matrix are non-zero, it means that the corresponding node is an output node, and the value on the diagonal is the displacement size of the corresponding node; The expression of the adjacency matrix is:

3. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 1, characterized in that: Step 2 specifically includes: Step 2.1: For any column in the adjacency matrix, if an element of the adjacent matrix is ​​negative, put the negative element into the corresponding position of Matrix_R, and put the positive element into the corresponding position of Matrix_L; if the elements of the adjacent matrix are all positive, put the elements less than the average value of the elements into Matrix_L, and put the elements greater than the average value into Matrix_R; if an element of the adjacent matrix is ​​already included in Matrix_L, put another element into the corresponding position of Matrix_R; and keep the elements on the diagonal; Step 2.2: Repeat step 2.2 until all matrices of the adjacency matrix group are traversed to obtain the left matrix Matrix_L and the right matrix Matrix_R.

4. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 1, characterized in that: The Verilog HDL generation model includes a module definition generation module, an internal signal declaration generation module and a logic description generation module; The module definition generation module is used to generate the module name and port definition of the Verilog code; The internal signal declaration generation module is used to calculate the bit width of the internal signal and declare the related internal signal, so that the internal signal can be optimized at the bit level; The logic description generation module is used to generate Verilog HDL codes of assignment statements to achieve correct displacement and addition and subtraction calculations.

5. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 4, characterized in that: The module name and port definition of the module definition generation module to generate Verilog code specifically include: Generate a module through module definition. Generate a module name const_multiplier, define ports, and define ports including input signal x, selection signal sel, and output signal y. i The bit width of the input signal x is determined by the input signal Width, the bit width of the selection signal sel is determined by the number of adjacent matrix groups Matrix_List, and the output signal y i The value range of i is determined by the maximum number of outputs of the adjacency matrix, and the output signal y i The bit width of the output node is determined by the maximum bit width of the output node.

6. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 4, characterized in that: The internal signal declaration generation module calculates the bit width of the internal signal and declares the relevant internal signals, including: Set the left input bit width of the left matrix Matrix_L of the current node to width_l_input, the right input bit width of the right matrix Matrix_R to width_r_input, and the node output bit width to width_v. For the i-th node, obtain the i-th column element of Matrix_L to obtain the displacement Shift_l; obtain the i-th column element of Matrix_R to obtain the displacement Shift_r. Calculate the left input bit width width_l_input, right input bit width width_r_input of the current node and the bit width of the current output node. Combine the left input bit width width_l_input, right input bit width width_r_input of the current node and the bit width of the current output node to generate the corresponding Verilog HDL statement. The calculation formula for the left input width width_l_input is: width_l_input=max(width_v + Shift__l)-Co_Shift_l (2); In formula (2), Co_Shift_1 is the common left / right shift width in Shift_1; The calculation formula for the right input width width_r_input is: width_r_input=max(width_v + Shift__r)-Co_Shift_r (3); In formula (3), Co_Shift_r is the common left / right shift width in Shift_r; The calculation formula for the bit width of the current output node is: width_v=width_v∪(max(width_l_input_i, width_r_input_i)+1)(4).

7. The method for automatically generating Verilog HDL code based on a constant multiplier directed graph according to claim 4, characterized in that: The Verilog HDL code for the assignment statement generated by the logic description generation module specifically includes: Traverse each column of the left matrix Matrix_L and the right matrix Matrix_R, calculate the left input l_input_i and the right input r_input_i, for the i-th node, get the non-zero elements of the i-th column of Matrix_L and Matrix_R, when the number of non-zero elements is greater than 1, use the sel signal to determine the value, if Co_Shift_l>Co_Shift_r, based on the node result v i The calculation formula gets the node result v i , select through the sel signal and set the node result v i Assign value to output y i ; The calculation formula for the left input l_input_i and the right input r_input_i is: l_input=generate_verilog(Matrix_L[:,i])(5); r_input=generate_verilog(Matrix_R[:,i])(6); Node result v i The calculation formula is:

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