Divider operation method based on step-by-step comparison and remainder prediction and storage medium

Abstract

The invention discloses a divider operation method based on step-by-step comparison and remainder prediction, and the method guarantees a high-precision and rapid calculation result through step-by-step comparison, trial quotient, remainder prediction and dynamic adjustment of trial quotient values. The input dividend and divisor are preprocessed in the starting state; the calculation state adopts a bit-by-bit left shift and comparison strategy, and efficient operation is realized based on early termination optimization of remainder prediction; and outputting the quotient and the remainder obtained by calculation in the ending state, accumulating the product of the trial quotient value and the divisor, and adjusting the trial quotient value according to an intermediate result and preparing for next division operation by dynamically adjusting the bits of the remainder and the quotient. According to the method, unified calculation of division of any two digits, unsigned numbers and signed numbers is realized, unnecessary calculation steps can be remarkably reduced, and particularly, the effect is more obvious when the dividend and the divisor have certain characteristics (for example, the high order of the dividend is far smaller than the high order of the divisor); the method has the advantages of higher operation precision, higher execution speed and lower hardware resource consumption.

Description

Technical Field

[0001] The present invention relates to the field of computer data operations, and particularly to a division operation method and a storage medium based on step-by-step comparison and remainder prediction. Background Art

[0002] Dividers play a crucial role in digital systems and computer science. In modern processors, the speed and efficiency of dividers directly affect the overall computing performance of the system. A high-precision divider can ensure the accuracy of calculation results, which is particularly important in fields that require high-precision calculations (such as finance, engineering, and scientific research). Many algorithms (such as fast Fourier transform, matrix operations, etc.) require division operations. Without an efficient divider, the implementation of these algorithms will become complex and inefficient. In hardware design, optimizing the divider can reduce chip area, power consumption, and cost. Therefore, the design and optimization of dividers have always been an important research direction in the fields of computer engineering and digital circuit design. Summary of the Invention

[0003] The present invention provides a division operation method for a divider based on step-by-step comparison, dynamically adjusting the quotient, and remainder prediction, which can handle the division operations of any two numbers, including unsigned numbers and signed numbers. Through step-by-step comparison and trial division, dynamically adjusting the sizes of the quotient and remainder, and early termination optimization based on remainder prediction, digital format conversion and adjustment, it can achieve efficient division operations of any two numbers, while ensuring the accuracy of the results and the generality of the operations.

[0004] The division operation method of the present invention includes four states of idle, start, calculation, and end controlled by a state control unit to sequentially execute each stage of the division operation:

[0005] Idle state: Wait for the start signal of the division operation.

[0006] Start state: Preprocess the input dividend and divisor, including sign extension and absolute value processing.

[0007] Calculation state: Adopt a strategy of shifting left bit by bit and comparing. Complement N zeros to the highest bit of the dividend, where N is the bit width of the divider; start from the (N - 1)-th bit, set the quotient to 1 and subtract the divisor; if the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0; calculate the value of the quotient of the current iteration bit in each iteration; until after N iterations, obtain the final value of the quotient. Based on the early termination optimization of remainder prediction, achieve efficient division operations.

[0008] End state: Output the calculated quotient and remainder, accumulate the product of the trial quotient value and the divisor, adjust the positions of the remainder and the quotient dynamically, adjust the trial quotient value according to the intermediate result, and prepare for the next division operation.

[0009] Preferably, when the divider is in the idle state, it waits for the start signal. If the start signal (start_i = DivStart) is received, it loads the operands (dividend_i and divisor_i) into the registers and prepares to start the division operation. If the start signal does not trigger, the divider resets its state and prepares to receive new operands.

[0010] When the divider is in the start state, the divider starts to perform the division operation.

[0011] Preferably, for the division of signed numbers, first determine the signs of the dividend and the divisor, and then perform the division operation only on their absolute values. For the division of unsigned numbers, the operation can be performed directly. If the divisor (divisor_r) is zero, this will cause an error in the divider because the divisor cannot be zero. In this case, the result will be set to all 1s (indicating overflow), and the divider enters the idle state. If the divisor is not zero, the divider enters the calculation state (STATE_CALC) and starts to perform the division operation.

[0012] A new zero_cnt register is added to record the number of consecutive 0s. During the calculation, when the remainder is less than the divisor (the quotient is 0), zero_cnt is incremented. When zero_cnt reaches the set threshold (set to 5 here) and there are still many uncalculated bits left (judged by 32 - cnt > zero_cnt * 2), the calculation is terminated in advance, and the quotient and remainder are directly obtained, avoiding unnecessary calculations; repeat the above steps until all bits of the quotient are determined.

[0013] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-described divider operation method are implemented.

[0014] Technical features and effects of the present invention:

[0015] (1) The present invention is a design of a remainder prediction divider based on step-by-step comparison. First, it selects whether to process signed numbers or unsigned numbers according to the operation mode. For the division of signed numbers, first determine the signs of the dividend and the divisor, and then perform the division operation only on their absolute values. For the division of unsigned numbers, the operation can be directly carried out. If the divisor (divisor_r) is zero, this will cause an error in the divider because the divisor cannot be zero. In this case, the result will be set to all 1s (indicating overflow). If the divisor is not zero, the divider will start the division operation. Complement the highest bit of the dividend with N zeros (N is the bit width of the divider), start from the (N - 1)-th bit and set the quotient to 1, and subtract it from the divisor: If the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0. Each iteration can calculate the value of the quotient of the current iteration bit. After N iterations, the final quotient value can be obtained. Based on the early termination optimization of remainder prediction, efficient division operations are achieved. A new zero_cnt register is added to record the number of consecutive zeros. During the calculation process, when the remainder is less than the divisor (the quotient is 0), zero_cnt is incremented. When zero_cnt reaches the set threshold (set to 5 here) and there are still many uncalculated bits (judged by 32 - cnt > zero_cnt * 2), the calculation is terminated early, and the quotient and remainder are directly obtained, avoiding unnecessary calculations; repeat the above steps until all bits of the quotient are determined. It gradually approaches the result through a bit-by-bit comparison and subtraction module, and stores the result of each step in the div_result register. When all bits are processed, or an overflow occurs, or when the dividend is less than the divisor and no further subtraction operation can be performed, the calculation state ends. Output the calculated quotient and remainder, accumulate the product of the trial quotient value and the divisor, adjust the trial quotient value according to the intermediate result and prepare for the next division operation.

[0016] (2) Through step-by-step comparison and remainder prediction, the present invention realizes the division of any two numbers, unifies the calculation of unsigned numbers and signed numbers, improves the versatility of the divider; simplifies the hardware design, reduces costs and power consumption; improves the efficiency of division operations, can significantly reduce unnecessary calculation steps, improve the calculation speed, especially when the dividend and the divisor have certain characteristics (such as the high bit of the dividend is much smaller than the high bit of the divisor), and is applicable to high-speed digital signal processing and computer systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the overall operation architecture diagram of the present invention;

[0018] Figure 2 is the overall flowchart of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] Combined with the embodiments and the accompanying drawings, the technical solution of the present invention will be clearly and completely described below.

[0020] From Figure 1 it can be seen that the present invention mainly includes a step-by-step comparison unit, a remainder prediction unit, and a dynamic adjustment trial quotient value unit.

[0021] In the idle state, wait for the start signal of the division operation.

[0022] In the start state, preprocess the input dividend and divisor, including sign extension and absolute value processing.

[0023] The calculation state adopts a strategy of shifting left bit by bit and comparing. Complement N zeros (N is the bit width of the divider) to the highest bit of the dividend, start with a quotient of 1 from the (N - 1)-th bit, and subtract it from the divisor: if the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0. Each iteration can calculate the value of the quotient of the current iteration bit. After N iterations, the final quotient value can be obtained. Based on the early termination optimization of remainder prediction, an efficient division operation is realized.

[0024] In the end state, output the calculated quotient and remainder, accumulate the product of the trial quotient value and the divisor, adjust the bits of the remainder and quotient dynamically, adjust the trial quotient value according to the intermediate result and prepare for the next division operation.

[0025] When the divider is in the idle state, it waits for the start signal. If the start signal is received (start_i == DivStart), it will load the operands (dividend_i and divisor_i) into the register and prepare to start the division operation. If the start signal does not trigger, the divider will reset the state and prepare to receive new operands.

[0026] When the divider is in the start state, the divider starts to perform the division operation. For the division of signed numbers, first determine the signs of the dividend and the divisor, and then perform the division operation only on their absolute values. For the division of unsigned numbers, the operation can be directly performed. If the divisor (divisor_r) is zero, this will cause the divider to generate an error because the divisor cannot be zero. In this case, the result will be set to all 1s (indicating overflow), and the divider enters the idle state. If the divisor is not zero, the divider will enter the calculation state (STATE_CALC) and start to perform the division operation.

[0027] When the divider is in the calculation state, the divider performs the actual division operation. Complement the highest bit of the dividend with N zeros (N is the bit width of the divider), start from the (N - 1)-th bit and set the quotient to 1, and subtract it from the divisor: If the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0. Each iteration can calculate the value of the quotient for the current iteration bit. After N iterations, the final quotient value can be obtained.

[0028] A new zero_cnt register is added to record the number of consecutive zeros. During the calculation process, when the remainder is less than the divisor (the quotient is 0), zero_cnt is incremented. When zero_cnt reaches the set threshold (set to 5 here) and there are still many uncalculated bits left (judged by 32 - cnt > zero_cnt * 2), the calculation is terminated in advance, and the quotient and remainder are directly obtained, avoiding unnecessary calculations; repeat the above steps until all bits of the quotient are determined.

[0029] Let:

[0030] A[2] = 1 indicates that the numbers in bits 31 - 24 of the dividend are not all 0;

[0031] A[1] = 1 indicates that the numbers in bits 23 - 16 of the dividend are not all 0;

[0032] A[0] = 1 indicates that the numbers in bits 15 - 08 of the dividend are not all 0;

[0033] B[2] = 1 indicates that the numbers in bits 31 - 24 of the divisor are not all 0;

[0034] B[1] = 1 indicates that the numbers in bits 23 - 16 of the divisor are not all 0;

[0035] B[0] = 1 indicates that the numbers in bits 15 - 08 of the divisor are not all 0.

[0036] Regarding the relationship between the number of shift bits and the dividend and divisor, it is shown in the following table:

[0037] A B Number of bits shifted left 1xx 000 0 1xx 001 8 1xx 01x 16 1xx 1xx 24 01x 000 8 01x 001 16 01x 01x 24 01x 1xx 31 001 000 16 001 001 24 001 01x 31 001 1xx 31 000 000 24 000 001 31 000 01x 31 000 1xx 31

[0038] When the divider is in the end state: During the iteration process, when subtraction is not possible (the quotient is 0), the remainder is not restored, and addition is used in the next iteration operation to make up for the over-subtracted number. Let the remainder at the i-th time be R i = 2R i-1 - Y, there are the following two cases: If R i ≥ 0, then the above quotient is 1, and no operation needs to be performed on the above remainder result. After directly shifting it left by one bit, the next trial division can be performed to obtain the next remainder R i+1 = 2R i-Y; If R i < 0, then the above quotient is 0. For the remainder that needs to be restored, shift left by one bit for trial division, i.e.: R i+1 = 2(R i + Y)-Y = 2R i + Y. It can be seen that the above formula can be equivalently expressed as: in the next operation, it becomes an addition operation, and its result can be equivalently considered as restoring the remainder. When inputting, the absolute value of the dividend is taken. When outputting the final result, the signs of the quotient and the remainder are determined and corresponding conversions are made: if it is negative, just take the complement and add 1.

[0039] The divisor is not taken the absolute value, but when the divisor is negative, all the quotient logics are the same as the case when the remainder is positive, that is, the quotient and the remainder are always set to the absolute value, and the final sign will be converted according to the sign relationship between the dividend and the divisor.

[0040] The sign relationships between the remainder, the quotient, the dividend, and the divisor are shown in the following table:

[0041] Dividend Divisor Quotient Remainder + + + + + - - + - + - - - - + -

[0042] When all the quotient bits are calculated, or when the dividend is less than the divisor and no more subtraction operations can be performed, the calculation state ends. It gradually approaches the result through bit-by-bit comparison and an addition module, and stores the result of each step in the div_result register.

[0043] Output the calculated quotient and remainder, accumulate the product of the trial quotient value and the divisor, adjust the trial quotient value according to the intermediate result and prepare for the next division operation. Repeat the above steps until all the quotient bits are determined.

[0044] A design of a remainder prediction divider based on bit-by-bit comparison is given in the present invention. First, it selects whether to process signed numbers or unsigned numbers according to the operation mode. For the division of signed numbers, first determine the signs of the dividend and the divisor, and then perform the division operation only on their absolute values. For the division of unsigned numbers, the operation can be directly carried out. If the divisor (divisor_r) is zero, this will cause an error in the divider because the divisor cannot be zero. In this case, the result will be set to all 1s (indicating overflow). If the divisor is not zero, the divider will start the division operation. The sign of the calculation result can be obtained by performing an exclusive OR operation on the sign bits of the dividend and the divisor. If the signs of the two numbers are the same, the result is positive; if they are different, the result is negative. Shift the dividend left by one bit and compare it with the divisor; if the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0. A zero_cnt register is newly added to record the number of consecutive 0s. During the calculation process, when the remainder is less than the divisor (the quotient is 0), zero_cnt is incremented. When zero_cnt reaches the set threshold (set to 5 here) and there are still many uncalculated bits left (judged by 32 - cnt > zero_cnt * 2), the calculation is terminated in advance, and the quotient and the remainder are directly obtained, avoiding unnecessary calculations; repeat the above steps until all bits of the quotient are determined. It gradually approaches the result through bit-by-bit comparison and an addition module, and stores the result of each step in the div_result register. When all bits are processed, or an overflow occurs, or when the dividend is less than the divisor and no further subtraction operation can be performed, the calculation state ends. Output the calculated quotient and remainder, accumulate the product of the trial quotient value and the divisor, adjust the trial quotient value according to the intermediate result, and prepare for the next division operation.

[0045] The divider provided by the present invention realizes the division of any two numbers, the unified calculation of unsigned numbers and signed numbers, and improves the versatility of the divider through step-by-step comparison and remainder prediction; simplifies the hardware design, reduces costs and power consumption; improves the efficiency of the division operation, can significantly reduce unnecessary calculation steps, and improves the calculation speed, especially when the dividend and the divisor have certain characteristics (such as the high bits of the dividend are much smaller than the high bits of the divisor), and is applicable to high-speed digital signal processing and computer systems.

Claims

1. A divider operation method based on level-by-level comparison and remainder prediction, comprising four states of idle, start, calculation and end controlled by a state control unit, characterized in that: Idle state: waiting for the start signal of the division operation; Starting state: preprocess the input dividend and divisor, including sign extension and absolute value processing; Calculation status: Use bit-by-bit left shift and comparison strategy to fill the highest bit of the dividend with N zeros, where N is the bit width of the divider; start with the N-1th bit and add the quotient 1, and subtract it from the divisor; if the dividend is greater than or equal to the divisor, subtract the divisor from the dividend and set the corresponding bit of the quotient to 1; if the dividend is less than the divisor, keep the dividend unchanged and set the corresponding bit of the quotient to 0; calculate the value of the quotient of the current iteration bit each iteration; after N iterations, get the final quotient value; End state: output the calculated quotient and remainder, accumulate the product of the trial quotient and the divisor, dynamically adjust the bits of the remainder and quotient, adjust the trial quotient according to the intermediate results and prepare for the next division operation.

2. The divider operation method according to claim 1, characterized in that: The waiting for the start signal of the division operation in the idle state specifically includes: when the divider is in the idle state, it waits for the start signal; if the start signal is received, it will load the operand into the register and prepare to start the division operation; if the start signal is not triggered, the divider will reset the state and prepare to receive a new operand.

3. The divider operation method according to claim 1, characterized in that: In the starting state, the input dividend and divisor are preprocessed, specifically including: For the division of signed numbers, first determine the signs of the dividend and divisor, and then only perform the division operation on their absolute values; for the division of unsigned numbers, perform the operation directly; In the case where the divisor is zero, the result will be set to all 1s, indicating overflow, and the divider enters the idle state; if the divisor is not zero, the divider will enter the calculation state and start performing the division operation.

4. The divider operation method according to claim 1, characterized in that: The calculation state also includes: A new zero_cnt register is added to record the number of times the quotient is 0 continuously. During the calculation process, when the remainder is less than the divisor, that is, the quotient is 0, the zero_cnt register is incremented. By judging by 32-cnt>zero_cnt*2, when the zero_cnt register reaches the set threshold and there are many remaining uncalculated bits, the calculation is terminated in advance and the quotient and remainder are directly obtained. Repeat the above steps until all the bits of the quotient are determined. When all bits are processed or overflow occurs, the divider enters the end state.

5. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the divider operation method described in any one of claims 1 to 4 are implemented.

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