AND logic circuit based on sine wave frequency product and its control method

Abstract

The present invention discloses an AND logic circuit based on sinusoidal frequency product and a control method thereof. The circuit includes a multiplier, a low-pass filter, a high-pass filter, and a logic judgment unit. The first input of the multiplier is used to input a first sinusoidal signal A, and the second input of the multiplier is used to input a second sinusoidal signal B. The first sinusoidal signal A and the second sinusoidal signal B are sinusoidal signals of different frequencies. The output of the multiplier is respectively connected to the input of the low-pass filter and the high-pass filter, and the output of the low-pass filter and the high-pass filter are respectively connected to the input of the logic judgment unit. The present invention introduces a sinusoidal frequency product detection mechanism. By measuring and analyzing the sum frequency and difference frequency between the two sinusoidal signals, the signal state is verified, significantly enhancing the anti-interference capability and safety during the logic operation process.

Description

Technical Field

[0001] The present invention belongs to the technical field of logic circuit design, and in particular relates to an AND logic circuit based on sinusoidal wave frequency product and a control method thereof. Background Art

[0002] AND logic cells are essential building blocks in digital logic design and applications, widely used in integrated circuits, computer systems, and various digital signal processing devices. The function of AND logic is to determine whether to generate a specific output signal by determining the state of an input signal. Traditional AND logic cell design is primarily based on the basic cell library of integrated circuits, with the AND gate circuit in CMOS technology being one of the most common implementations. Traditional CMOS AND gate circuits achieve AND logic functionality through the coordinated action of pull-up and pull-down networks and inverters. However, in existing integrated circuit designs, the implementation of AND logic typically relies on the AND gate circuits of the basic cell. While these traditional AND gates offer advantages such as simple structure, fast response, and low power consumption, they exhibit significant limitations in applications with high safety standards. In critical sectors such as rail transportation, aerospace, and medical equipment, system safety and reliability are crucial. Due to the inherent physical properties of traditional AND gates, factors such as electromagnetic interference, temperature fluctuations, and power supply fluctuations can cause erroneous logic state flips or failures, compromising the accuracy and stability of signal transmission. In addition, in board-level design, although transformer-based AND gate solutions have been developed to enhance the system's anti-interference capabilities, such solutions have the disadvantage of being difficult to miniaturize and integrate, and therefore cannot be applied in the field of modern integrated circuit design. Summary of the Invention

[0003] To solve the above problems, the present invention provides an AND logic circuit based on sinusoidal wave frequency multiplication and its control method, so as to solve the problem that traditional AND logic gate circuits are easily affected by factors such as electromagnetic interference, temperature changes or power supply fluctuations, resulting in erroneous flipping or failure of the logic state, thereby affecting the accuracy and stability of signal transmission.

[0004] An AND logic circuit based on sine wave frequency product, comprising: a multiplier, a low-pass filter, a high-pass filter and a logic judgment unit;

[0005] The first input terminal of the multiplier is used to input a first sinusoidal wave signal A, and the second input terminal of the multiplier is used to input a second sinusoidal wave signal B, wherein the first sinusoidal wave signal A and the second sinusoidal wave signal B are sinusoidal wave signals of different frequencies;

[0006] The output end of the multiplier is connected to the input end of the low-pass filter and the high-pass filter respectively. The output end of the low-pass filter and the high-pass filter is connected to the input end of the logic judgment unit respectively.

[0007] According to a specific embodiment of the present invention, the first input terminal and the second input terminal of the multiplier are connected to the first signal source and the second signal source respectively.

[0008] A signal state detection chip based on sinusoidal wave frequency product comprises the above-mentioned AND logic circuit based on sinusoidal wave frequency product.

[0009] A signal state detection product based on sine wave frequency product includes the above-mentioned signal state detection chip based on sine wave frequency product.

[0010] A method for controlling AND logic based on sinusoidal frequency product, which is applied to the above-mentioned AND logic circuit based on sinusoidal frequency product, comprises:

[0011] Acquire a first sinusoidal wave signal A and a second sinusoidal wave signal B in real time;

[0012] Inputting the first sine wave signal A and the second sine wave signal B into the multiplier respectively to generate an intermediate node signal C;

[0013] The intermediate node signal C is input into the low-pass filter and the high-pass filter for filtering, and the difference frequency signal OUT0 and the sum frequency signal OUT1 are extracted accordingly;

[0014] Performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and determining the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 based on the spectrum analysis results;

[0015] An AND logic operation is performed based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 , and the logic operation result is output.

[0016] According to a specific embodiment of the present invention, performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and determining the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 based on the spectrum analysis results includes:

[0017] Perform spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and obtain the frequency characteristics of the difference frequency signal OUT0 and the sum frequency signal OUT1 accordingly;

[0018] The signal state of the difference frequency signal OUT0 is determined based on the frequency characteristics of the difference frequency signal OUT0 , and the signal state of the sum frequency signal OUT1 is determined based on the frequency characteristics of the sum frequency signal OUT1 .

[0019] According to a specific embodiment of the present invention, determining the signal state of the difference frequency signal OUT0 based on the frequency characteristics of the difference frequency signal OUT0, and determining the signal state of the sum frequency signal OUT1 based on the frequency characteristics of the sum frequency signal OUT1 further includes:

[0020] determining whether the beat frequency signal OUT0 meets a preset beat frequency threshold standard based on the frequency characteristics of the beat frequency signal OUT0; if so, the signal state of the beat frequency signal OUT0 is normal; otherwise, the signal state of the beat frequency signal OUT0 is abnormal;

[0021] Based on the frequency characteristics of the sum frequency signal OUT1 , it is determined whether the sum frequency signal OUT1 meets the preset sum frequency threshold standard. If so, the signal state of the sum frequency signal OUT1 is normal; otherwise, the signal state of the sum frequency signal OUT1 is abnormal.

[0022] According to a specific embodiment of the present invention, performing an AND logic operation based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 and outputting the logic operation result further includes:

[0023] An AND logic operation is performed based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1. If and only if the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 are both normal, the output logic operation result is 1; otherwise, the output logic operation result is 0.

[0024] According to a specific embodiment of the present invention, the first sinusoidal wave signal A and the second sinusoidal wave signal B are sinusoidal wave signals with different frequencies.

[0025] According to a specific embodiment of the present invention, the method further includes: generating a first sinusoidal wave signal A based on a first signal source, and generating a second sinusoidal wave signal B based on a second signal source.

[0026] Compared with the prior art, the AND logic circuit based on sinusoidal wave frequency product and the control method thereof provided by the present invention have the following advantages:

[0027] 1. This invention introduces a sine wave frequency product detection mechanism. By measuring and analyzing the sum and difference frequencies between two sinusoidal signals, it effectively identifies and verifies the identity of the signal source. Compared to traditional AND gate circuits, this invention can effectively prevent the activation of lower-level circuits when the input signal is abnormal, significantly enhancing the anti-interference capability and security of the logical operation process. Even in highly interfering environments, this invention can ensure the correct transmission of data signals, thereby avoiding system insecurity caused by abnormal input signals. This mechanism provides a solid physical foundation for the security and reliability of the system and is particularly suitable for applications with extremely high security requirements.

[0028] 2. The circuit structure of the present invention is not only simple and efficient, but also replaces the traditional static level voltage detection method by real-time monitoring and evaluation of the frequency characteristics of the signal, and transforms the traditional static operating voltage detection into dynamic frequency detection, thereby avoiding the risk of abnormal static operating voltage locking caused by circuit short circuit or open circuit.

[0029] 3. The present invention also has good integrability and compatibility, is easy to integrate into chip design and expand into existing electronic systems, can flexibly adapt to the upgrade needs of existing electronic systems, and provides a new solution for achieving higher levels of logical operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 1 is a diagram of an AND logic circuit based on sinusoidal wave frequency product according to an embodiment of the present invention.

[0032] Figure 2 FIG. 1 is a structural diagram of a traditional AND gate logic circuit according to an embodiment of the present invention.

[0033] Figure 3 4 is a flow chart of a control method of an AND logic circuit based on sinusoidal wave frequency product according to an embodiment of the present invention.

[0034] Figure 4 is a flow chart of a method for determining the state of an output signal based on spectrum analysis according to an embodiment of the present invention.

[0035] Figure 5 FIG. 4 is a flow chart of a method for determining the state of an output signal based on the frequency characteristics of the output signal according to an embodiment of the present invention.

[0036] Figure 6 1 is a waveform diagram of an input signal and an output signal under normal circumstances provided according to an embodiment of the present invention.

[0037] Figure 7 FIG. 4 is a spectrum analysis diagram of an input signal and an output signal under normal conditions provided by an embodiment of the present invention.

[0038] Figure 8 1 is a waveform diagram of an input signal and an output signal under abnormal conditions according to an embodiment of the present invention.

[0039] Figure 9 FIG. 4 is a spectrum analysis diagram of an input signal and an output signal under abnormal conditions according to an embodiment of the present invention.

[0040] Figure 10 FIG. 4 is a waveform diagram of an output signal under normal conditions provided according to an embodiment of the present invention.

[0041] Figure 11 FIG. 4 is a spectrum diagram of an output signal under normal conditions provided according to an embodiment of the present invention.

[0042] Figure 12 FIG. 4 is a waveform diagram of an abnormal output signal provided according to an embodiment of the present invention.

[0043] Figure 13 FIG. 4 is a spectrum diagram of an abnormal output signal provided according to an embodiment of the present invention.

[0044] Reference numerals:

[0045] 01-Multiplier; 02-Low-pass filter; 03-High-pass filter; 04-Logic judgment unit. DETAILED DESCRIPTION

[0046] In order to make those skilled in the art understand the concept and thought of the present invention more clearly, the present invention is described in detail below in conjunction with specific embodiment.It should be understood that the embodiment provided herein is only a part of all possible embodiments of the present invention.After reading the specification of the application, those skilled in the art have the ability to make improvements, transformations, or replacements to part or all of the following embodiments, and these improvements, transformations, or replacements are also included in the scope of protection claimed in the present invention.

[0047] In this document, the terms "first", "second" and other similar words are not intended to imply any order, quantity and importance, but are merely used to distinguish different elements. In this document, the terms "one", "an" and other similar words are not intended to indicate that there is only one thing, but rather that the relevant description is only for one of the things, and the thing may have one or more. In this document, the terms "comprise", "include" and other similar words are intended to indicate logical relationships, and cannot be regarded as indicating relationships in spatial structure. For example, "A includes B" is intended to indicate that B logically belongs to A, and does not mean that B is spatially located inside A. In addition, the meanings of the terms "comprise", "include" and other similar words should be regarded as open, not closed. For example, "A includes B" is intended to indicate that B belongs to A, but B does not necessarily constitute the whole of A, and A may also include other elements such as C, D, and E.

[0048] In this document, the terms "embodiment," "this embodiment," "one embodiment," and "an embodiment" do not indicate that the description applies only to a specific embodiment, but rather indicate that the description may also apply to one or more other embodiments. Those skilled in the art should understand that any description of a particular embodiment herein may be substituted, combined, or otherwise combined with the description of one or more other embodiments. New embodiments resulting from such substitution, combination, or other combination are readily conceivable by those skilled in the art and fall within the scope of protection of this invention.

[0049] Example 1

[0050] Additional aspects and advantages of embodiments of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of embodiments of the present invention. Figure 1 , an embodiment of the present invention provides an AND logic circuit based on the product of sinusoidal wave frequencies, comprising:

[0051] Multiplier 01, low-pass filter 02, high-pass filter 03 and logic judgment unit 04, the first input end and the second input end of the multiplier 01 are respectively connected to the first signal source and the second signal source, the first input end of the multiplier 01 is used to input the first sinusoidal wave signal A, and the second input end of the multiplier 01 is used to input the second sinusoidal wave signal B. The first sinusoidal wave signal A and the second sinusoidal wave signal B are sinusoidal wave signals of different frequencies. The output end of the multiplier 01 is respectively connected to the input end of the low-pass filter 02 and the high-pass filter 03, and the output end of the low-pass filter 02 and the high-pass filter 03 are respectively connected to the input end of the logic judgment unit 04.

[0052] In an embodiment of the present invention, a first sinusoidal wave signal A is generated by a first signal source, and a second sinusoidal wave signal B is generated by a second signal source. Multiplier 01 is used to multiply the first sinusoidal wave signal A and the second sinusoidal wave signal B to output an intermediate node signal C. The intermediate node signal C includes the sum frequency and difference frequency components of the first sinusoidal wave signal A and the second sinusoidal wave signal B. Subsequently, the intermediate node signal C is input into a low-pass filter 02 and a high-pass filter 03, respectively. The difference frequency component in the intermediate node signal C is filtered out by the low-pass filter 02, and a difference frequency signal OUT0 is output. The sum frequency component in the intermediate node signal C is filtered out by the high-pass filter 03, and a sum frequency signal OUT1 is output. The output difference frequency signal OUT0 and the sum frequency signal OUT1 are respectively input into a logic judgment unit 04 for an AND logic operation. If and only if both output signals are in a valid state, the logic judgment unit 04 outputs a logic '1', indicating that the AND logic condition is met. On the contrary, if any one of the signals fails to reach the effective threshold standard, the logic judgment unit 04 will output logic '0', indicating that the AND logic condition is not triggered.

[0053] like Figure 2 The traditional CMOS AND gate circuit structure shown in the figure consists of two stages connected in series: the first stage is a NAND gate composed of four MOS transistors, and the second stage is an inverter composed of two MOS transistors. Traditional CMOS AND gate circuits achieve AND logic functions through the synergistic effect of pull-up and pull-down networks and inverters. In traditional AND gate logic circuits, when either input signal A or signal B experiences an anomaly, the output intermediate node signal C may directly drive the lower-level circuit, failing to effectively identify and transmit the abnormal state of signal B. If both signal A and signal B are interfered with or fail, an uncontrollable signal data C will be output, making it unsuitable for applications requiring high safety performance. The AND logic circuit based on the product of sinusoidal wave frequencies provided by the present invention significantly enhances the anti-interference capability and safety of the logic operation process by detecting the difference and sum frequencies of the sinusoidal waves and performing the AND logic operation through a logic judgment unit. Even in highly interfering environments, the present invention can ensure the correct transmission of data signals and effectively avoid logical errors caused by interference. In addition, the present invention not only inherits the advantages of the traditional AND gate structure being simple and easy to implement, but also has good integrability and compatibility. It is easy to integrate into chip design and expand into existing electronic systems, providing a new solution for achieving a higher level of AND logic operations.

[0054] Example 2

[0055] Based on the AND logic circuit based on the sinusoidal wave frequency product provided in Example 1, the embodiment of the present invention further provides a control method for the AND logic circuit based on the sinusoidal wave frequency product, such as Figure 3-Figure 13 As shown, including:

[0056] S1: Acquire the first sine wave signal A and the second sine wave signal B in real time.

[0057] S2: Input the first sine wave signal A and the second sine wave signal B into the multiplier respectively to generate an intermediate node signal C.

[0058] S3: Input the intermediate node signal C into a low-pass filter and a high-pass filter respectively for filtering, and correspondingly extract a difference frequency signal OUT0 and a sum frequency signal OUT1.

[0059] S4: performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and determining the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 based on the spectrum analysis results.

[0060] S5 : performing an AND logic operation based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 , and outputting the logic operation result.

[0061] In an embodiment of the present invention, before obtaining the first sinusoidal wave signal A and the second sinusoidal wave signal B, the method further includes generating the first sinusoidal wave signal A based on a first signal source and generating the second sinusoidal wave signal B based on a second signal source. The first sinusoidal wave signal A and the second sinusoidal wave signal B are sinusoidal wave signals of different frequencies, and the phase relationship between the first sinusoidal wave signal A and the second sinusoidal wave signal B changes over time. Then, the first sine wave signal A and the second sine wave signal B are input to the multiplier 01 for multiplication processing to generate an intermediate node signal C. The intermediate node signal C contains the sum frequency and difference frequency components of the first sine wave signal A and the second sine wave signal B. Subsequently, the intermediate node signal C is input to the low-pass filter 02 and the high-pass filter 03 respectively. The difference frequency component in the intermediate node signal C is filtered out by the low-pass filter 02, and the difference frequency signal OUT0 is output. The sum frequency component in the intermediate node signal C is filtered out by the high-pass filter 03, and the sum frequency signal OUT1 is output. The signal status of the output difference frequency signal OUT0 and the sum frequency signal OUT1 is monitored in real time, and an AND logic operation is performed according to the signal status, and finally the logic operation result is output. Compared with the traditional AND logic circuit, the present invention significantly enhances the anti-interference ability and security of the logic operation process by introducing the sine wave difference frequency and sum frequency detection mechanism. Even in a highly interfering environment, this solution can ensure the correct transmission of data signals and effectively avoid logical errors caused by interference.

[0062] Specifically, step S4 performs spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and determines the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 based on the spectrum analysis results, including:

[0063] S41: performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and obtaining frequency characteristics of the difference frequency signal OUT0 and the sum frequency signal OUT1 accordingly.

[0064] S42: determining the signal state of the difference frequency signal OUT0 based on the frequency characteristics of the difference frequency signal OUT0, and determining the signal state of the sum frequency signal OUT1 based on the frequency characteristics of the sum frequency signal OUT1, further comprising:

[0065] S421: Determine whether the difference frequency signal OUT0 meets a preset difference frequency threshold standard based on the frequency characteristics of the difference frequency signal OUT0. If so, the signal state of the difference frequency signal OUT0 is normal; otherwise, the signal state of the difference frequency signal OUT0 is abnormal.

[0066] S422: Determine whether the sum frequency signal OUT1 meets a preset sum frequency threshold standard based on the frequency characteristics of the sum frequency signal OUT1. If so, the signal state of the sum frequency signal OUT1 is normal; otherwise, the signal state of the sum frequency signal OUT1 is abnormal.

[0067] The embodiments of the present invention simulate input signals under normal working conditions and input signals under abnormal working conditions to obtain corresponding output signals under normal working conditions and output signals under abnormal working conditions. The frequency characteristics of the output signals under normal working conditions and output signals under abnormal working conditions are analyzed to determine the signal states of the output signals under normal working conditions and under abnormal working conditions.

[0068] Under normal working conditions, the first sine wave signal A and the second sine wave signal B are sine waves of different frequencies, and the frequency difference between them is not large. The output waveform under normal working conditions is as follows Figure 6 As shown, the intermediate node signal C is the product of the first sine wave signal A and the second sine wave signal B, and the overall shows a periodic change. The spectrum analysis of the first sine wave signal A, the second sine wave signal B and the intermediate node signal C is performed respectively, as shown in FIG. Figure 7 As shown, the first sine wave signal A and the second sine wave signal B are periodic sine waves, appearing as a single pulse on the spectrum. When these two sine wave signals with different frequencies pass through the multiplier, the output intermediate node signal C contains the sum and difference frequency components of the first sine wave signal A and the second sine wave signal B. Therefore, on the spectrum, the intermediate node signal C appears as two pulses, corresponding to the difference and sum of the frequencies, respectively.

[0069] In an abnormal working state, it is assumed that the first sine wave signal A is a normal sine wave signal, while the second sine wave signal B is abnormal and shows a continuous constant high level. The output waveform in the abnormal working state is as follows: Figure 8 As shown in the figure, the intermediate node signal C output by the multiplier now has the same waveform characteristics as the first sinusoidal signal A. If the second sinusoidal signal B shows a continuous constant low level, the intermediate node signal C will remain at a low level and will not cause misjudgment of the subsequent circuit, so it will not be discussed in detail here. The spectrum analysis of the first sinusoidal signal A, the second sinusoidal signal B and the intermediate node signal C is shown in the figure below. Figure 9As shown, the second sinusoidal signal B, due to its constant high-level state, has a spectrum analysis result showing almost zero frequency components or an extremely low noise level. The first sinusoidal signal A and the intermediate node signal C, on the other hand, have identical waveforms and exhibit the same spectral characteristics, primarily concentrated at the fundamental frequency of signal A, which is outside the preset difference and sum frequency ranges. While the intermediate node signal C, under abnormal operating conditions, has the same waveform as signal A, its spectral characteristics have changed significantly. This change in spectral characteristics provides important evidence for subsequent frequency detection.

[0070] Figure 10-13 The waveforms and spectra of the difference frequency signal OUT0 and sum frequency signal OUT1, output from the intermediate node signal C after processing with a high-pass filter or low-pass filter, are compared under normal and abnormal operating conditions. Under normal operating conditions, the difference and sum frequencies of the two input sinusoidal signals are relatively stable. After processing with a high-pass filter or low-pass filter, the spectrum of the output difference frequency signal OUT0 or sum frequency signal OUT1 exhibits only a single distinct peak, indicating that only signals near the preset frequency are filtered. When either input signal experiences a fault, the system enters an abnormal operating state. During this state, the frequency difference between the input signals increases significantly, causing the intermediate node signal C to lose the preset frequency component, making it impossible for the filter to obtain a valid signal. Under abnormal operating conditions, the amplitude of the filtered output signal is significantly lower, reaching only one-tenth of the amplitude of the normal filtered output signal or even lower. This significant amplitude attenuation prevents the signal from reaching the minimum threshold required to trigger the next-stage circuit, thus failing to effectively activate or drive the output response of subsequent circuits. Based on this frequency characteristic, the present invention uses the presence of the preset frequency in the output signal as a criterion for determining whether the output signal is normal, and can also be used as a criterion for determining whether the input signal is normal.

[0071] Specifically, step S5 performs an AND logic operation based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1, and outputs the logic operation result, further comprising:

[0072] An AND logic operation is performed based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1. If and only if the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 are both normal, the output logic operation result is 1; otherwise, the output logic operation result is 0.

[0073] The AND logic operation determines whether to generate a specific output signal by judging the state of the input signals. Specifically, for a two-input digital AND logic unit, the output signal is high only when both input signals are high (logical '1'). Conversely, if either input signal is low (logical '0'), the output signal is low. Based on this basic principle, embodiments of the present invention use the difference frequency signal OUT0 and the sum frequency signal OUT1 as the two input signals for the AND logic operation. If and only if the difference frequency signal OUT0 and the sum frequency signal OUT1 are both normal (logical '1'), the output logic result is 1, indicating that the AND logic condition is met. If either the difference frequency signal OUT0 or the sum frequency signal OUT1 is abnormal, the output logic result is 0, indicating that the AND logic condition is not triggered. Only when the logic result is 1 can the downstream circuit be driven.

[0074] In a specific embodiment of the present invention, it can be extended to a multi-input AND logic operation. If and only if all input signals are in a normal state, the output logic operation result can be 1, otherwise the output is 0.

[0075] Example 3

[0076] Based on the AND logic circuit based on sine wave frequency product provided in Example 1, an embodiment of the present invention further provides a signal state detection chip based on sine wave frequency product, including the above-mentioned AND logic circuit based on sine wave frequency product.

[0077] Furthermore, an embodiment of the present invention also provides a signal state detection product based on sine wave frequency product, including the above-mentioned signal state detection chip based on sine wave frequency product.

[0078] In summary, the AND logic circuit based on sinusoidal wave frequency product and the control method thereof provided by the present invention have the following advantages:

[0079] 1. This invention introduces a sine wave frequency product detection mechanism. By measuring and analyzing the sum and difference frequencies between two sinusoidal signals, it effectively identifies and verifies the identity of the signal source. Compared to traditional AND gate circuits, this invention can effectively prevent the activation of lower-level circuits when the input signal is abnormal, significantly enhancing the anti-interference capability and security of the logical operation process. Even in highly interfering environments, this invention can ensure the correct transmission of data signals, thereby avoiding system insecurity caused by abnormal input signals. This mechanism provides a solid physical foundation for the security and reliability of the system and is particularly suitable for applications with extremely high security requirements.

[0080] 2. The circuit structure of the present invention is not only simple and efficient, but also replaces the traditional static level voltage detection method by real-time monitoring and evaluation of the frequency characteristics of the signal, and transforms the traditional static operating voltage detection into dynamic frequency detection, thereby avoiding the risk of abnormal static operating voltage locking caused by circuit short circuit or open circuit.

[0081] 3. The present invention also has good integrability and compatibility, is easy to integrate into chip design and expand into existing electronic systems, can flexibly adapt to the upgrade needs of existing electronic systems, and provides a new solution for achieving higher levels of logical operations.

[0082] The concepts, principles, and concepts of the present invention have been described in detail above with reference to specific implementation methods (including embodiments and examples). Those skilled in the art should understand that the present invention may be implemented in more than just the forms described above. After reading this application document, those skilled in the art may make any possible improvements, substitutions, and equivalent forms to the steps, methods, systems, and components in the above-described implementation methods. Such improvements, substitutions, and equivalent forms should be deemed to fall within the scope of the present invention. The scope of protection of the present invention shall be determined solely by the claims.

Claims

1. A method for controlling AND logic based on sinusoidal frequency product, the method being applied to an AND logic circuit based on sinusoidal frequency product, the method comprising a multiplier, a low-pass filter, a high-pass filter, and a logic judgment unit, wherein a first input of the multiplier is used to input a first sinusoidal signal A, and a second input of the multiplier is used to input a second sinusoidal signal B, wherein the first sinusoidal signal A and the second sinusoidal signal B are sinusoidal signals of different frequencies; an output of the multiplier is connected to the inputs of the low-pass filter and the high-pass filter, respectively, and the outputs of the low-pass filter and the high-pass filter are connected to the input of the logic judgment unit, respectively; The first input terminal and the second input terminal of the multiplier are connected to the first signal source and the second signal source respectively, and the multiplier is characterized in that: include: Acquire a first sinusoidal wave signal A and a second sinusoidal wave signal B in real time; inputting the first sinusoidal wave signal A and the second sinusoidal wave signal B into a multiplier respectively to generate an intermediate node signal C; The intermediate node signal C is input into a low-pass filter and a high-pass filter respectively for filtering, and a difference frequency signal OUT0 and a sum frequency signal OUT1 are correspondingly extracted; Performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and judging the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 based on the spectrum analysis results, specifically includes: Performing spectrum analysis on the difference frequency signal OUT0 and the sum frequency signal OUT1 respectively, and obtaining frequency characteristics of the difference frequency signal OUT0 and the sum frequency signal OUT1 accordingly; Determining a signal state of the difference frequency signal OUT0 based on the frequency characteristics of the difference frequency signal OUT0, and determining a signal state of the sum frequency signal OUT1 based on the frequency characteristics of the sum frequency signal OUT1, further comprising: determining whether the beat frequency signal OUT0 meets a preset beat frequency threshold standard based on the frequency characteristic of the beat frequency signal OUT0; if so, the signal state of the beat frequency signal OUT0 is normal; otherwise, the signal state of the beat frequency signal OUT0 is abnormal; determining whether the sum frequency signal OUT1 satisfies a preset sum frequency threshold standard based on the frequency characteristic of the sum frequency signal OUT1; if so, the signal state of the sum frequency signal OUT1 is normal; otherwise, the signal state of the sum frequency signal OUT1 is abnormal; Performing an AND logic operation based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 and outputting the logic operation result specifically includes: An AND logic operation is performed based on the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1. If and only if the signal states of the difference frequency signal OUT0 and the sum frequency signal OUT1 are both normal, the output logic operation result is 1; otherwise, the output logic operation result is 0.

2. The AND logic control method based on sinusoidal wave frequency product according to claim 1, characterized in that: The first sinusoidal wave signal A and the second sinusoidal wave signal B are sinusoidal wave signals with different frequencies.

3. The AND logic control method based on sinusoidal wave frequency product according to claim 1, characterized in that: The method further includes generating a first sinusoidal wave signal A based on a first signal source, and generating a second sinusoidal wave signal B based on a second signal source.

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