Interconnection structure and method for achieving physically unimitable function thereof

Abstract

The invention discloses an interconnection structure for a physically unimitated function. The interconnection structure is formed by arranging a plurality of physically unimitated function units. Each physically unimitated functional unit comprises more than two L-shaped metal wires, each L-shaped metal wire comprises a first part and a second part and is adjacent to a dummy metal wire, and the first part of one L-shaped metal wire is electrically connected to the second part of another adjacent L-shaped metal wire in the vertical direction through a guide hole piece.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure for a physically unclonable function (PUF), and more particularly, to a semiconductor structure and method for achieving a physically unclonable function through an interconnect structure. Background Art

[0002] The Internet of Things (IoT) technology is to equip various electronic devices with sensors and software to connect and transmit data to each other, digitize many aspects and interactive information in the real world, bring scattered data closer, and integrate digital information between things. It is the basis for the intelligence of many industries, and its application scope is very wide, such as transportation and logistics, industrial manufacturing, health care, intelligent environments (homes, offices, factories), personal and social fields, etc.

[0003] However, the convenience of the IoT also brings higher cybersecurity risks. Since the IoT devices cover a wide range of fields, hackers can launch attacks from many aspects, and its security challenges are huge. In the past, when it came to the information security of the IoT, most people first thought of encrypted connections at the software and network levels. However, in addition to the security protection at the network level, there are also threats to the physical devices in the IoT. Once there are counterfeit chips or other problems, hackers may remotely control the devices through the network, obtain keys and other sensitive information, and thus cause losses to enterprises. Therefore, the software-based cybersecurity design is no longer sufficient to provide comprehensive security protection in the IoT field.

[0004] For this reason, the hardware security technology of physically unclonable function (PUF) has emerged. Its principle is to introduce various random variables in the semiconductor manufacturing process, so that the manufactured chips have slight differences in the microstructures. In the case where these random variables cannot be predicted and controlled, it is almost impossible to replicate the chip, which can reduce the concerns of reverse engineering or manipulation. Such randomness, uniqueness, and non-replicability make the physically unclonable function exist as a kind of chip fingerprint, and thus naturally become a popular choice under the new-generation cybersecurity Zero Trust architecture. Summary of the Invention

[0005] In view of the strong demand for hardware information security in today's Internet of Things technology, the present invention proposes a novel semiconductor structure, which is characterized by increasing the voltage range that can be read through the resistance variation caused by the metal layer, via, and the electrical connection between the two in the semiconductor back-end-of-line (BEOL) process, so as to achieve the purpose of enhancing the physical unclonable function random code.

[0006] One aspect of the present invention is to propose an interconnect structure for physical unclonable function, which has an array of physical unclonable function units. The array of physical unclonable function units is arranged by a plurality of physical unclonable function units. Each physical unclonable function unit includes: more than two L-shaped metal lines that overlap in the vertical direction. Each L-shaped metal line includes a first part and a second part. The first part extends in a first horizontal direction, and the second part extends in a second horizontal direction and one end thereof is connected to one end of the first part. The first horizontal direction is orthogonal to the second horizontal direction; a plurality of dummy metal lines extend in the first horizontal direction, and each dummy metal line is adjacent to the first part of an L-shaped metal line in the second horizontal direction; and a plurality of vias extend in the vertical direction, wherein the first part of the L-shaped metal line is electrically connected to the second part of another L-shaped metal line adjacent in the vertical direction through a via.

[0007] Another aspect of the present invention is to propose a method for achieving physical unclonable function through an interconnect structure, including providing an array of physical unclonable function units. The array of physical unclonable function units is arranged by a plurality of physical unclonable function units. Each physical unclonable function unit includes: more than two L-shaped metal lines that overlap in the vertical direction. Each L-shaped metal line includes a first part and a second part. The first part extends in a first horizontal direction, and the second part extends in a second horizontal direction and one end thereof is connected to one end of the first part. The first horizontal direction is orthogonal to the second horizontal direction; a plurality of dummy metal lines extend in the first horizontal direction, and each dummy metal line is adjacent to the first part of an L-shaped metal line in the second horizontal direction; and a plurality of vias extend in the vertical direction, wherein the first part of the L-shaped metal line is electrically connected to the second part of another L-shaped metal line adjacent in the vertical direction through a via; passing a certain current through the array of physical unclonable function units, and the certain current flows through each physical unclonable function unit to generate a voltage corresponding to the physical unclonable function unit; and when the voltage is less than a set value, determining that the random code of the corresponding physical unclonable function unit is 0, and when the voltage is greater than a set value, determining that the random code of the corresponding physical unclonable function unit is 1.

[0008] These and other objects of the present invention will become more apparent to those skilled in the art after reading the following detailed description of the preferred embodiments, which are described with reference to various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a plan view of an array of physically unclonable function (PUF) cells according to an embodiment of the present invention;

[0010] Figure 2 FIG. 2 is a perspective view of a PUF cell according to a preferred embodiment of the present invention;

[0011] Figure 3 FIG. 3 is a schematic diagram of the characteristic variations of metal layers, vias, and the electrical connections therebetween in various semiconductor back-end-of-line (BEOL) processes according to an embodiment of the present invention;

[0012] Figure 4 FIG. 4 is a schematic diagram of the broadened voltage distribution of PUF cells read according to an embodiment of the present invention;

[0013] Figure 5 FIG. 5 is a schematic diagram of the random encoded fingerprints inherent in multiple PUF chips according to an embodiment of the present invention; and

[0014] Figure 6 FIG. 6 is a functional block diagram of a system-on-chip having a PUF block according to an embodiment of the present invention.

[0015] It should be noted that all the drawings in this specification are for illustrative purposes only. For clarity and convenience of illustration, the components in the drawings may be presented with exaggerated or reduced dimensions and proportions. Generally, the same reference symbols in the drawings are used to denote corresponding or similar element features in modified or different embodiments.

[0016] SYMBOL DESCRIPTION

[0017] 100 PUF cell array

[0018] 102 PUF cell

[0019] 104 Input line

[0020] 106 Output line

[0021] 110 L-shaped metal line

[0022] 110a First part

[0023] 110b Second part

[0024] 110c dummy metal line

[0025] 120 L-shaped metal wire

[0026] 120a First part

[0027] 120b Second part

[0028] 120c dummy metal wire

[0029] 122 Rounding feature

[0030] 130 L-shaped metal wire

[0031] 130a First part

[0032] 130b Second part

[0033] 130c dummy metal wire

[0034] 140 via component

[0035] 200 PUF cell array

[0036] 300 PUF cell array

[0037] BUS Bus

[0038] CPU Central Processing Unit

[0039] D1 First horizontal direction

[0040] D2 Second horizontal direction

[0041] D3 Vertical direction

[0042] DRAM Dynamic Random Access Memory

[0043] HUK Hardware Unique Key

[0044] MUX Data Multiplexer

[0045] OTP One-Time Programmable Memory

[0046] PUF Physical Unclonable Function (block)

[0047] SoC System-on-Chip

[0048] SRAM Static Random Access Memory

[0049] TRNG True Random Number Generator

[0050] V cell Cell voltage Detailed implementation manner

[0051] Exemplary embodiments of the present invention will now be described in detail below, which will refer to the accompanying drawings to illustrate the described features for the reader to understand and achieve technical effects. The reader will understand that the description in the text is only by way of illustration and is not intended to limit the present case. The various embodiments of the present case and the various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Modifications, equivalents or improvements to the present case are understandable to those skilled in the art and are intended to be included within the scope of the present case without departing from the spirit and scope of the present invention.

[0052] The reader should be able to easily understand that the meanings of "on", "above", and "over" in the present case should be interpreted in a broad sense, so that "on" not only means "directly on" something, but also includes the meaning of being "on" something with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also can include the meaning of being "above" or "over" something with no intervening features or layers therebetween (i.e., directly on something). In addition, spatial-related terms such as "under", "below", "lower", "above", "upper", etc. may be used in this text for convenience of description to describe the relationship of one element or feature to another or more elements or features, as shown in the accompanying drawings.

[0053] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a lower or upper structure, or may have a scope smaller than the scope of the lower or upper structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along an inclined surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0054] A reader can generally understand terms at least in part from their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or property in a singular sense or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the", or "said" can also be understood to convey a singular usage or a plural usage. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors but can allow for the existence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0055] A reader can further understand that when words such as "comprising" and / or "including" are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or combinations thereof.

[0056] The proposed interconnect structure and related implementation methods of the present invention are used to achieve the physically unclonable function (PUF) of identifying hardware devices. Such a structure can be designed in an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The principle lies in establishing a challenge / response database when manufacturing a device or component, enabling the verification of the device without the need for an encryption authentication algorithm. While preventing the theft and tampering of the device's identity, it also eliminates the additional cost of injecting keys into the device and the risks of subsequent key loss and security vulnerabilities.

[0057] First, please refer to Figure 1, which is a plan view of a PUF cell array according to an embodiment of the present invention. Generally speaking, the structure of the present invention is a PUF cell array 100, which is formed by arranging a plurality of PUF cells 102. Each PUF cell 102 is located at a node where an input line 104 intersects an output line 106 and can be connected to a memory element. In the application of the preferred embodiment, current can be input into the PUF cell array 100 through the input line 104, and after flowing through the connected PUF cell 102, it is output from the output line 106. In this way, the characteristic voltage of each PUF cell 102 in the PUF cell array 100 can be obtained, which is used to generate a random code for it, such as 0 or 1. Thus, the PUF cell array 100 composed of a plurality of PUF cells 102 has an inherent electronic fingerprint, which can be used as a key to identify the chip or device.

[0058] Next, please refer to Figure 2 , which is a three-dimensional view of a PUF cell according to a preferred embodiment of the present invention. In the preferred embodiment of the present invention, the PUF cell 102 is composed of an interconnect structure (or can be called a metal trace) formed in the semiconductor back-end-of-line (BEOL) process, such as a metal layer and a via. As shown in the figure, each PUF cell 102 may include a plurality of L-shaped metal lines 110, 120, 130. Each L-shaped metal line 110, 120, 130 includes a first portion 110a, 120a, 130a and a second portion 110b, 120b, 130b. The first portions 110a, 120a, 130a extend in a first horizontal direction D1, and the second portions 110b, 120b, 130b extend in a second horizontal direction D2. The first horizontal direction D1 and the second horizontal direction D2 are substantially orthogonal, and one end of the two portions is connected to each other. In the preferred embodiment of the present invention, each L-shaped metal line 110, 120, 130 is located in a metal layer of the semiconductor back-end-of-line process (such as the first metal layer M1 to the top metal layer TM), and the L-shaped metal lines 110, 120, 130 partially overlap in the vertical direction D3. The vertical direction D3 is preferably orthogonal to the first horizontal direction D1 and the second horizontal direction D2. For example, the first portion 120a of the L-shaped metal line 120 overlaps with the second portions 110b, 130b of the L-shaped metal lines 110, 130 adjacent in the vertical direction D3, and the second portion 120b of the L-shaped metal line 120 overlaps with the first portions 110a, 130a of the L-shaped metal lines 110, 130 adjacent in the vertical direction D3. In this way, these portions can be electrically connected through the vias 140 therebetween.

[0059] Refer back to Figure 2。In addition to the L-shaped metal lines 110, 120, and 130, each PUF unit 102 also has multiple dummy metal lines 110c, 120c, and 130c. Each dummy metal line 110c, 120c, and 130c is adjacent to its corresponding L-shaped metal line 110, 120, and 130 (i.e., the L-shaped metal lines in the same metal layer). More specifically, as shown in the figure, in the preferred embodiment of the present invention, the dummy metal lines 110c, 120c, and 130c extend in the second horizontal direction D2 like the first portions 110a, 120a, and 130a of the L-shaped metal lines 110, 120, and 130, and are disposed at positions adjacent to the first portions 110a, 120a, and 130a and the second portions 110b, 120b, and 130b of the corresponding L-shaped metal lines 110, 120, and 130, but do not connect thereto. Different from the L-shaped metal lines 110, 120, and 130, the dummy metal lines 110c, 120c, and 130c are not connected to metal lines in other metal layers through any vias.

[0060] Refer back Figure 2 。In actual operation, a constant current is input from the via 140 at the top layer of the PUF unit 102, and its source can be an external circuit connected thereto, such as Figure 1 the input line 104. The constant current flows through the multiple L-shaped metal lines 110, 120, and 130 connected by the via 140, and finally outputs from the via 140 at the bottom layer of the PUF unit to the external circuit connected thereto, such as Figure 1 the output line 106. Since each PUF unit 102 has its respective L-shaped metal lines 110, 120, and 130, vias 140, and different connection situations therebetween, the total resistance value of its overall metal routing will be different, and the unit voltage of each PUF unit 102 that can be measured under a constant current will also be different. In the embodiment of the present invention, the unit voltage can be used to generate the PUF random code required for PUF applications to identify the device identity. It should be noted that in the embodiment of the present invention, the L-shaped metal lines and the dummy metal lines are not limited to Figure 2 the three groups shown in

[0061] Now please refer to Figure 3, which shows various feature variations that can be generated by the post-stage interconnect structure in the foregoing embodiments, all of which contribute to the randomness of the PUF chip encoding. In the ideal case where there is no manufacturing process variation, as shown in example (a), the line widths of the first part 120a, the second part 120b of the L-shaped metal line 120, and the dummy metal line 120c will be the same, and the horizontal cross-sectional size of the via 140 will also be the same and will be accurately located on the L-shaped metal line to be connected, that is, the horizontal cross-section of the via completely abuts against the L-shaped metal line. However, in the actual manufacturing process, manufacturing process variations will cause the actually formed L-shaped metal line and the dummy metal line 120c not to conform to the ideal situation as shown in example (a), and they may deviate from the preset value in all aspects. For example, in example (b), the via 140 may have an abnormally large or small horizontal cross-section formed due to abnormal photolithography manufacturing process, thus affecting the contact resistance between the via 140 and the L-shaped metal line. In addition, in the situation of example (e), the via 140 may also not be located at the predetermined position on the L-shaped metal line due to misalignment between the current layer and the previous layer, resulting in a significant increase in its contact resistance. On the other hand, in the embodiments of the present invention, the presence of the dummy metal line 120c also provides more variables for forming an ideal PUF cell pattern. For example, as shown in example (c), abnormal photolithography manufacturing process may cause the width or length of the dummy metal line 120c pattern to deviate from its set value, and then due to the microloading effect, the adjacent L-shaped metal line pattern may be abnormal, affecting its resistance value. In addition, as shown in example (d), the semiconductor line pattern actually formed by the photolithography manufacturing process is likely to form a rounded feature 122 at the corners of the pattern, and such pattern features caused by the manufacturing process will also change the resistance value of the PUF cell.

[0062] Now please refer to Figure 4 , which shows a schematic diagram of the widened voltage distribution of the PUF cells read according to the embodiments of the present invention. Under normal circumstances, as shown in the left figure, the cell voltage V cell measured by general PUF cells or structures will show a normal distribution due to manufacturing process variations, and it has an average value. In the generation of the PUF cell random code, we can define the random code of the PUF cell with a cell voltage V cell less than the average value as 0, and the random code of the PUF cell with a cell voltage greater than the average value as 1. In this way, after the PUF cell array 100 composed of multiple PUF cells is manufactured, an inherently inherent electronic fingerprint can be generated, as Figure 5 shown, multiple PUF cell arrays 100, 200, 300 have their individual electronic fingerprints composed of random codes 0 and 1.

[0063] However, although the PUF cells fabricated in the same manufacturing process can have the aforementioned randomness, since the goals of semiconductor manufacturing processes tend to be stable, uniform, and reduce variability, generally the Figure 4 range of the unit voltage V cell in the normal distribution curve is not large, which means that the randomness of the PUF cells is not large. In the present invention, based on the various Figure 3 specially designed abnormal metal line patterns shown above, after passing a constant current, the variation of the unit voltage V cell measured for each PUF cell will also become larger, as shown by the normal distribution curve on the right in Figure 4 , the range of the unit voltage V cell in the normal distribution curve becomes wider, and there is a tailing phenomenon. Thus, in the PUF application, the margin for generating and discriminating the "0" and "1" random codes of the logic level is larger, making the PUF cells less susceptible to environmental changes (such as the average value of the unit voltage V cell shifting due to different operating temperatures) resulting in incorrect or distorted reading results, enhancing the reliability and robustness of the PUF cells, and the randomness and uniqueness of the electronic fingerprints that can be obtained from the PUF cell array in the same manufacturing process are also greater.

[0064] Please refer to Figure 6 , which is a functional block diagram of a system-on-chip with a physically unclonable function block according to an embodiment of the present invention. The aforementioned PUF cell array 100 of the present invention can be used to fabricate the PUF block in the system-on-chip. As Figure 6 shown, the system-on-chip SoC can integrate functional blocks such as a data multiplexer MUX, a central processing unit CPU, a static random access memory SRAM, a dynamic random access memory DRAM, a security subsystem, and a physically unclonable function block PUF. Each block can be connected through a bus BUS. The physically unclonable function block PUF can further include sub-blocks such as a hardware unique key (HUK), a true random number generator (TRNG), and a one-time programmable memory OTP.

[0065] In the operation of physical unclonable functions, the physical unclonable function block PUF performs input and output, where the input-output matching depends on its PUF attributes. The input of the PUF is usually called challenges, and the output is called responses. Similarities can be found for each set of inputs through mathematical formulas. The purpose of the PUF block is to obtain stable and reproducible response values given challenge values on the same IC. On different chips, the response values are different and unique. The hardware unique key HUK is the basis for protecting each chip and the starting point of the trust chain for the entire system and related services. It creates a unique, inherent, and non-replicable key at the hardware level. The one-time programmable memory OTP can provide an option for key storage in the form of an anti-fuse memory. It forms a conductive path in a single-crystal oxide layer through the principle of quantum tunneling, leaving no visible traces on the surface, providing data invisibility. The data multiplexer MUX can select one signal from multiple analog or digital input signals for output and test the one-time programmable memory OTP through the bus BUS connection. The true random number generator TRNG has a digital simulation design that combines static and dynamic entropy sources to generate random numbers through physical processes rather than computer programs. The physical unclonable function block PUF is connected to the security subsystem to provide secure storage and a high-quality entropy source for the encryption function in the security subsystem.

[0066] Based on the description of the above embodiments, the present invention enhances the random coding of the PUF by specifically designing the patterns of the interconnect structures formed in the back-end manufacturing process in the existing semiconductor manufacturing process. It can effectively improve the randomness, uniqueness, and robustness of the PUF chip and is applicable to the hardware security technology of the Internet of Things under the new generation of zero-trust security architecture. It is an invention with novelty, progressiveness, and practicality.

[0067] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. An interconnect structure for physical unclonable function, having an array of physical unclonable function units, which is formed by arranging a plurality of physical unclonable function units, and each of the physical unclonable function units includes: More than two L-shaped metal lines that overlap in the vertical direction, and each of the L-shaped metal lines includes a first portion and a second portion. The first portion extends in a first horizontal direction, and the second portion extends in a second horizontal direction and one end thereof is connected to one end of the first portion. The first horizontal direction is orthogonal to the second horizontal direction; A plurality of dummy metal lines that extend in the first horizontal direction, and each of the dummy metal lines is adjacent to the first portion of the L-shaped metal line in the second horizontal direction; And A plurality of vias that extend in the vertical direction, wherein the first portion of the L-shaped metal line is electrically connected to the second portion of another L-shaped metal line adjacent in the vertical direction through the via.

2. The interconnect structure for physical unclonable function according to claim 1, wherein the first portion of the L-shaped metal line overlaps with the second portion of another L-shaped metal line adjacent in the vertical direction, and the second portion of the L-shaped metal line overlaps with the first portion of another L-shaped metal line adjacent in the vertical direction.

3. The interconnect structure for physical unclonable function according to claim 1, wherein the dummy metal line overlaps with the first portion of the L-shaped metal line adjacent in the vertical direction in the vertical direction.

4. The interconnect structure for physical unclonable function according to claim 1, wherein a constant current is input from the via at the uppermost layer of the interconnect structure and output from the via at the lowermost layer of the interconnect structure.

5. The interconnect structure for physical unclonable function according to claim 4, wherein the constant current flows through each of the physical unclonable function units to generate a voltage corresponding to the physical unclonable function unit, and the voltage is used to discriminate the random code of the corresponding physical unclonable function unit.

6. The interconnect structure for physical unclonable function according to claim 1, wherein the interconnect structure is an interconnect structure of a semiconductor back-end manufacturing process (BEOL).

7. A method for achieving physical unclonable function through an interconnect structure, comprising: Providing an array of physical unclonable function units, which is formed by arranging a plurality of physical unclonable function units, and each of the physical unclonable function units includes: More than two L-shaped metal lines that overlap in the vertical direction, and each of the L-shaped metal lines includes a first portion and a second portion. The first portion extends in a first horizontal direction, and the second portion extends in a second horizontal direction and one end thereof is connected to one end of the first portion. The first horizontal direction is orthogonal to the second horizontal direction; A plurality of dummy metal lines that extend in the first horizontal direction, and each of the dummy metal lines is adjacent to the first portion of the L-shaped metal line in the second horizontal direction; And A plurality of via members extending in the vertical direction, wherein the first portion of the L-shaped metal line is electrically connected to the second portion of another L-shaped metal line adjacent thereto in the vertical direction through the via members; Applying a constant current to the physical unclonable function unit array, and the constant current flows through each physical unclonable function unit to generate a voltage corresponding to the physical unclonable function unit; and When the voltage is less than the set value, it is determined that the random code of the corresponding physical unclonable function unit is 0, and when the voltage is greater than the set value, it is determined that the random code of the corresponding physical unclonable function unit is 1.

8. The method for achieving physical unclonable function through an interconnection structure according to claim 7, wherein the variation in the landing position of the via member on the L-shaped metal line causes a change in the resistance of the corresponding physical unclonable function unit, thereby changing the generated voltage.

9. The method for achieving physical unclonable function through an interconnection structure according to claim 7, wherein the variation in the horizontal cross-sectional area of the via member causes a change in the resistance of the corresponding physical unclonable function unit, thereby changing the generated voltage.

10. The method for achieving physical unclonable function through an interconnection structure according to claim 7, wherein the variation in the horizontal area of the dummy metal line causes a variation in the pattern of the adjacent first portion, thereby causing a change in the resistance of the corresponding physical unclonable function unit and further changing the generated voltage.

11. The method for achieving physical unclonable function through an interconnection structure according to claim 7, wherein the variation in the horizontal area of the dummy metal line causes a variation in the pattern of the adjacent first portion, thereby causing a change in the resistance of the corresponding physical unclonable function unit and further changing the generated voltage.

12. The method for achieving physical unclonable function through an interconnection structure according to claim 7, wherein the corner of the L-shaped metal line has a rounded feature, and the rounded feature causes a change in the resistance of the corresponding physical unclonable function unit and further changes the generated voltage.

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