Interrupt and exception handling system and method based on RISC-V and processor

Abstract

The invention provides an interrupt and exception handling system, method and processor based on RISC-V. The system comprises a core local interrupt controller used for generating software interrupt and timer interrupt; the platform-level interrupt controller is used for integrating a plurality of external interrupt sources into an external interrupt signal; the delivery module is arranged in the processor core, and after receiving interrupt signal requests of the core local interrupt controller and the platform-level interrupt controller or an abnormal signal request of an arithmetic logic unit in the processor core, the delivery module sends a first instruction count value of an assembly line flushing request and a re-fetch instruction to an instruction fetch stage and sends the first instruction count value of the assembly line flushing request and the re-fetch instruction to the instruction fetch stage; wherein the core local interrupt controller and the platform-level interrupt controller are mounted on the processor core. The circuit is simple in structure, low in power consumption and small in circuit area, and is suitable for embedded processor equipment which has low requirements on the performance of the processor but has low requirements on low-power-consumption design and area.

Description

Technical Field

[0001] The present invention relates to the field, and in particular, to an interrupt and exception handling system, method, and processor based on RISC-V. Background Art

[0002] In the process of the continuous evolution of modern computer architectures, RISC-V, as an emerging, highly open, and extensible instruction set architecture, is gradually widely used in many fields, from embedded systems to high-performance computing, etc. In such diverse application scenarios, implementing a simple and efficient interrupt and exception handling mechanism specifically for the embedded field plays a crucial role in the development of embedded RISC-V processors.

[0003] During operation, the RISC-V processor needs to handle interrupt requests from different sources and various exception situations. Traditional interrupt handling designs gradually expose many limitations when facing the characteristics of the RISC-V architecture and complex application requirements. Existing high-performance processors make a detailed division of interrupts and exceptions, and further divide different interrupt types and exception types. The complex and feature-rich interrupt and exception handling system has too high hardware overhead for processors used in the embedded field, and does not meet the requirements of low power consumption and small area. Summary of the Invention

[0004] In view of the above problems existing in the prior art, the present invention proposes an interrupt and exception handling system, method, and processor based on RISC-V, mainly solving the problem that the existing processor interrupt and exception handling designs are relatively complex and difficult to meet the requirements of low power consumption and miniaturization in the embedded field.

[0005] To achieve the above and other objectives, the technical solutions adopted by the present invention are as follows.

[0006] The present application provides an interrupt and exception handling system based on RISC-V, including: a core local interrupt controller for generating software interrupts and timer interrupts; a platform-level interrupt controller for integrating multiple external interrupt sources into an external interrupt signal; a delivery module disposed within the processor core, which, after receiving an interrupt signal request from the core local interrupt controller and the platform-level interrupt controller or an exception signal request from the arithmetic logic unit in the processor core, sends a pipeline flush request and a first instruction count value for refetching instructions to the fetch stage, where the core local interrupt controller and the platform-level interrupt controller are mounted on the processor core.

[0007] In an embodiment of the present application, the core local interrupt controller includes an msip register, an mtime register, and an mtimecmp register. The software interrupt is directly generated by the msip register and given to the processor core; the value of the timer is reflected by the mtime; the mtimecmp register provides a comparison value for the timer to generate the timer interrupt when the value of the timer is greater than or equal to the comparison value.

[0008] In an embodiment of the present application, the msip register is a 32-bit register, and only the lowest bit is the valid bit. The valid bit is directly used as the software interrupt and given to the processor core.

[0009] In an embodiment of the present application, the external interrupt sources include GPIO, UART, API, and I2C. The platform-level interrupt controller arbitrates multiple external interrupt sources into a single unit of the external interrupt signal and sends it to the delivery module for processing.

[0010] In an embodiment of the present application, when an asynchronous exception, a synchronous exception, and an interrupt occur simultaneously, the priority of the asynchronous exception is higher than that of the interrupt, and the priority of the interrupt is higher than that of the synchronous exception.

[0011] In an embodiment of the present application, the priority of the external interrupt is higher than that of the software interrupt, and the priority of the software interrupt is higher than that of the timer interrupt.

[0012] The present application also provides a method applied to the RISC-V-based interrupt and exception handling system described above, including: after receiving an interrupt request or an exception request, the processor enters the exception program and stops executing the current program flow; the exception program is executed starting from the second instruction count value defined by the mtvec register; the exception type is updated to the mcause register, and the return address of the exception or interrupt is saved to the mepc register; the memory access address or instruction encoding that causes the current exception or interrupt is updated to the mtval register; the threshold value in the mstatus register is updated to save the working mode and interrupt enable configuration before the exception occurs; the exception handling program is exited, and execution starts from the return address in the mepc register, and the threshold value in the mstatus register is updated again to restore the working mode and interrupt enable configuration before the exception occurs.

[0013] In one embodiment of the present application, the steps of saving the return address of an exception or an interruption into the mepc register include: when an interruption occurs, the interruption return address saved in the mepc register is updated to the instruction count value of the next unexecuted instruction; when an exception occurs, the return address saved in the mepc register is updated to the instruction count value of the instruction where the current exception occurs, and if the exception is caused by ecall or ebreak, the value in the mepc register is changed to point to the next instruction.

[0014] In one embodiment of the present application, the thresholds in the mstatus register include: the MIE field value, which is used to indicate whether interrupts are globally enabled in the machine mode; the MPIE field value, which is used to save the MIE threshold before an exception occurs; and the MPP threshold, which is used to indicate the working mode.

[0015] The present application also provides a processor, including the RISC-V based interrupt and exception handling system described above.

[0016] As described above, a RISC-V based interrupt and exception handling system, method and processor proposed by the present application have the following beneficial effects.

[0017] Both interrupts and exceptions in the present application will trigger the delivery module to send a pipeline flush request to the instruction fetch stage, integrating interrupts and narrow exceptions into broad exceptions, and then making separate processing for the specific processing details of exceptions and interrupts, which can effectively improve the processing efficiency of interrupts and exceptions, avoid complex interrupt handling and exception handling designs, reduce resource occupation, and meet the system performance requirements of low power consumption and small area of processors in the embedded field. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the architecture of a RISC-V based interrupt and exception handling system in one embodiment of the present application.

[0019] Figure 2 The memory mapped address of the core local interrupt controller in one embodiment of the present application.

[0020] Figure 3 It is a schematic flowchart of a method applied to the aforementioned RISC-V based interrupt and exception handling system in one embodiment of the present application.

[0021] Figure 4 It is a register comparison table required in an exception program in one embodiment of the present application.

[0022] Figure 5 It is a schematic diagram of the detailed format of the registers used in an exception program in one embodiment of the present application.

[0023] Figure 6It is a schematic flowchart of a method for an RISC-V-based interrupt and exception handling system in another embodiment of this application.

[0024] Figure 7 It is a schematic microarchitecture diagram of a processor in an embodiment of this application. Detailed implementation manners

[0025] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0026] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.

[0027] The inventor has found through research that:

[0028] In the process of the continuous evolution of modern computer architectures, RISC-V, as an emerging, highly open and extensible instruction set architecture, is gradually widely used in many fields, from embedded systems to high-performance computing, etc. In such diverse application scenarios, implementing a simple and efficient interrupt and exception handling mechanism specifically for the embedded field plays a crucial role in the development of embedded RISC-V processors.

[0029] During the operation of an RISC-V processor, it needs to handle interrupt requests from different sources and various exception situations. Traditional interrupt handling designs gradually expose many limitations when facing the characteristics of the RISC-V architecture and complex application requirements. For example, in terms of interrupt priority management, some existing general designs are too complex and implement too many functions, making it difficult to meet the requirements of embedded RISC-V processors for simple implementation, small area, and low power consumption, thereby affecting the real-time performance of the embedded processor system.

[0030] Existing high-performance processors make a detailed division for interrupts and exceptions, and further divide different interrupt types and exception types in a more meticulous way. For example, interrupt types are divided into external interrupts, timer interrupts, software interrupts, and debug interrupts, exceptions are divided into synchronous exceptions and asynchronous exceptions, and asynchronous exceptions are divided into precise asynchronous exceptions and imprecise asynchronous exceptions. Different interrupts and exception classifications are further carefully processed according to different causes. Such a complex and feature-rich interrupt and exception handling system has too high hardware overhead for processors used in the embedded field, and does not meet the requirements of low power consumption and small area.

[0031] In addition, in existing RISC-V processors, the handling methods of interrupts and exceptions are too complex and cumbersome. In terms of the interrupt nesting function, low-priority interrupts may unreasonably preempt the processing resources of high-priority interrupts, resulting in delays in the processing of high-priority interrupts, seriously affecting the real-time response ability of the system and the execution efficiency of critical tasks. At the same time, the context save and restore mechanism during the interrupt processing process also needs to be optimized. The current design often consumes more processor time and storage resources. Such interrupt and exception handling methods that occupy a large amount of resources and are complex and cumbersome cannot better meet the requirements of the embedded field for processors.

[0032] Based on the problems existing in the above-mentioned prior art, this application proposes an interrupt and exception handling system, method, and processor based on RISC-V. The technical solutions of this application will be elaborated in detail below with specific embodiments.

[0033] Please refer to Figure 1 , Figure 1This is a schematic diagram of the architecture of an RISC-V-based interrupt and exception handling system in an embodiment of the present application. The system in the embodiment of the present application includes: a core local interrupt controller, which is used to generate software interrupts and timer interrupts; a platform-level interrupt controller, which is used to integrate multiple external interrupt sources into an external interrupt signal; a delivery module, which is disposed within the processor core, and after receiving the interrupt signal requests from the core local interrupt controller and the platform-level interrupt controller or the exception signal request from the arithmetic logic unit in the processor core, sends a pipeline flush request and a first instruction count value for re-fetching instructions to the instruction fetch stage, wherein the core local interrupt controller and the platform-level interrupt controller are mounted on the processor core. The interrupt and exception handling in the embodiment of the present application mainly focuses on the processor execution stage. The CLINT module (Core Local Interrupt Controller) is the core local interrupt controller of the processor, which is a memory address mapping module and is mainly used to generate software interrupts and timer interrupts. The PLIC module (Platfrom Level InterruptController) is the platform-level interrupt controller, and this platform-level interrupt controller is also a memory address mapping module, which is responsible for aggregating and arbitrating multiple external interrupt sources and integrating them into a single interrupt signal to be delivered to the delivery module of the processor core. Among them, the external interrupt sources may include GPIO, UART, SPI, I2C, etc. The processor in the embodiment of the present application is designed based on the RV32IM subset of the RISC-V instruction set architecture and only supports machine mode. The present application integrates interrupts and exceptions into a generalized exception for processing. Because whether an interrupt occurs or an exception occurs, for the processor, it will suspend the currently executing program in the pipeline and instead process the interrupt and exception programs, and finally return to the program that was suspended before the processor executed the interrupt and exception. Therefore, the system in the embodiment of the present application unifies interrupts and exceptions into a generalized exception handling, but separates the handling of interrupts and exceptions in special details. Based on the generalized exception, whether an interrupt request or an exception request is received, the currently executing program will be suspended according to the same process, and the exception program will be executed starting from the PC (Program Counter) address defined in the exception entry base address. After entering the exception program, the handling methods of interrupts and exceptions will be distinguished. It should be noted that the PC address here is the instruction count value, and this value can represent the address of the instruction to be executed.

[0034] Figure 1In the text, "Regfile" refers to the register file, which is an array composed of multiple registers in the processor. The RISC-V register file usually has two read ports and one write port, enabling multi-way concurrent access to different registers, thereby improving data throughput capacity. OITF (Outstanding Instruction Track FIFO) is used to detect RAW and WAW dependencies related to long instructions. At each dispatch point when a long instruction is dispatched, an entry will be allocated in the OITF. This entry stores the source operand register index and the result register index of the long instruction. At the write-back point, after each long instruction is written back in order, the entry of this instruction in the OITF will be removed. The pipeline structure generally includes three stages: instruction fetch - decode - execute. The processor obtains instructions through decoding. Figure 1 In the text, "Decoder" is the decoder and is used in the decoding stage. The pipeline flush request means that during the pipeline processing, when the predicted execution result of an instruction is inconsistent with the actual execution result, the pipeline needs to restart from the instruction fetch stage and re - execute. This process is called "pipeline flush". A long instruction refers to an instruction that usually takes multiple clock cycles to complete execution and write - back, and is also called a "post - delivery long pipeline instruction".

[0035] In one embodiment, the core local interrupt controller includes the msip register, the mtime register, and the mtimecmp register. The software interrupt is directly generated through the msip register and given to the processor core; the value of the timer is reflected through the mtime; the mtimecmp register provides a comparison value for the timer to generate the timer interrupt when the value of the timer is greater than or equal to the comparison value. Specifically, please refer to Figure 2 , Figure 2The memory - mapped addresses of the core local interrupt controller are shown. The CLINT is used to generate two types of interrupts, namely software interrupts and timer interrupts. When generating software interrupts, a 32 - bit msip register is implemented in the CLINT module. Only the least significant bit of this register is valid, and this valid bit is directly used as the software interrupt signal to the processor core. When writing to the msip register by software triggers a software interrupt, the MSIP field in the CSR register mip will generate a 1 to indicate the current interrupt waiting state. Software can clear this software interrupt by writing 0 to the msip register. When generating timer interrupts, a 64 - bit register is implemented in the CLINT module. This register reflects the value of the 64 - bit timer. The timer counts based on a low - speed input clock signal and counts continuously by default. A 64 - bit mtimecmp register is also implemented in the CLINT module. This register serves as the comparison value for the timer. If the value of the timer mtime is greater than or equal to the value of mtimecmp, a timer interrupt is generated. Software can clear the timer interrupt by rewriting the value of mtimecmp (making it greater than the value of mtime).

[0036] In one embodiment, the PLIC (Platform Level Interrupt Controller) is also a module with a memory - address mapping. The PLIC connects external interrupt sources such as GIPO, UART, SPI, and I2C in the processor SoC of this application embodiment. The PLIC arbitrates multiple external interrupt sources into a single unit of interrupt signal and sends it to the processor core delivery module for processing. There are only the above - mentioned three types of processor interrupts in this application embodiment, and the interrupt priorities are in the order of external interrupt priority > software interrupt > timer interrupt. The mcause register selects and updates the value of the exception number in this priority order. In the interrupt handling of this application embodiment, the delivery module receives requests for 2 interrupt signals from the CLINT and the PLIC, as well as an exception signal request from the ALU (arithmetic and logic unit). The delivery module sends a pipeline flush request and the PC for re - fetching instructions to the fetch stage, so as to start fetching instructions from the new PC address. When asynchronous exceptions and synchronous exceptions and interrupts caused by the ALU occur simultaneously, the asynchronous priority caused by long instructions is the highest, the interrupt priority is the second, and the synchronous exception priority caused by the ALU is the lowest.

[0037] Please refer to Figures 3 - 5 , Figure 3 which is a schematic flowchart of the method applied to the aforementioned RISC - V - based interrupt and exception handling system in an embodiment of this application. Figure 4 which is a register comparison table required in the exception program in an embodiment of this application.Figure 5 This is a schematic diagram showing the detailed format of the registers used in an exception program in an embodiment of the present application. The method includes:

[0038] Step S300, after receiving an interrupt request or an exception request, the processor enters the exception program and stops executing the current program flow. Specifically, when an exception request is triggered, the processor immediately enters the exception program and stops the execution flow of the current program. Since interrupts and exceptions are integrated into a generalized exception, when receiving an interrupt and an exception, the current execution flow will be directly stopped and the exception program will be entered.

[0039] Step S310, start executing the exception program from the second instruction count value defined in the mtvec register. Here, the second instruction count value is the PC address of the exception program. It can be specified and modified through CSR (Control and status register).

[0040] Step S320, update the exception type to the mcause register and save the return address of the exception or interrupt to the mepc register.

[0041] In step S320, the step of saving the return address of the exception or interrupt to the mepc register includes: when an interrupt occurs, the interrupt return address saved in the mepc register is updated to the instruction count value of the next unexecuted instruction; when an exception occurs, the return address saved in the mepc register is updated to the instruction count value of the instruction where the current exception occurs, and if the exception is caused by ecall or ebreak, change the value in the mepc register to point to the next instruction. Specifically, after entering the exception program, first update the mcause register to reflect the specific type of the current exception. Software can read the value of this register to find out the cause of the exception. Then, save the return address of the exception to the mepc register, which is used to make the processor return to the PC value of the interrupted program after the exception ends. During this process, different treatments are performed for narrow interrupts and exceptions: if an interrupt occurs, the interrupt return address saved in mepc is updated to the PC value of the next unexecuted instruction; if an exception occurs, the interrupt return address saved in mepc is updated to the PC value of the instruction where the current exception occurs, and if an ecall or ebreak exception occurs, in the exception handler, software will set the value of the mepc register to mepc = mepc + 4 to ensure that the program can point to the next instruction and prevent getting stuck in a loop that jumps back to the ecall or ebreak instruction again.

[0042] Step S330, update the memory access address or instruction encoding that causes the current exception or interrupt to the mtval register.

[0043] In one embodiment, the mtval register is updated to reflect the memory access address or instruction encoding that caused the current exception.

[0044] Step S340: Update the threshold value in the mstatus register to save the working mode and interrupt enable configuration before the exception occurs.

[0045] In one embodiment, the threshold values in the mstatus register include: the MIE domain value, which is used to indicate whether interrupts are globally enabled in the machine mode; the MPIE domain value, which is used to save the MIE threshold value before the exception occurs; and the MPP threshold value, which is used to indicate the working mode. When an exception occurs, the value of the MIE domain is updated to 0, the value of the MPIE domain is updated to the value of the MIE domain before the exception occurs, and after the exception ends, the value of the MIE before the exception occurs is restored using the value of the MPIE domain. The value of the MPP domain is updated to the mode before the exception occurs. The processor core of the embodiment of the present application only supports the machine mode, and its MPP domain value is binary 11.

[0046] Step S350: Exit the exception handler, start execution from the return address in the mepc register, and update the threshold value in the mstatus register again to restore the working mode and interrupt enable configuration before the exception occurs. Use the mret instruction to exit the exception state, stop executing the current instruction stream, and instead start executing the program again according to the PC address defined by the mepc register. At the same time, update the mstatus register, update the MIE domain in the register to the current value of the MPIE domain, and update the value of the MPIE domain to 1.

[0047] For the specific method flow, reference can also be made to Figure 6, first, after sending an exception request, the processor enters the exception program. The processor stops executing the current program flow and instead starts executing from the PC address defined by the mtvec register. The mtvec register is the machine-mode exception entry base address (machine trap-vector base-address), which is a readable and writable register specified by the CSR. Software developers can change its value through programming. Update the mcause register to reflect the current exception type. Software can read the value of this register to query the specific cause of the exception. Save the exception return address to the mepc register, which is used to save the PC value of the interrupted program that the processor will return to after the exception ends. During the process of updating the mepc register, the embodiments of the present application distinguish between narrow interrupts and exceptions. When an interrupt occurs, the interrupt return address saved in mepc is updated to the PC value of the next unexecuted instruction. When an exception occurs, the interrupt return address saved in mepc is updated to the PC of the instruction where the current exception occurs. If an ecall or ebreak exception occurs, in the exception handler, the software changes the value of the mepc register and sets it to mepc = mepc + 4 to make it point to the next instruction, preventing it from jumping back to the ecall or ebreak instruction again and thus entering an infinite loop. Then update the mtval register to reflect the memory access address or instruction encoding that caused the current exception. Update the field values in the mstatus register, where the MIE field indicates whether interrupts are globally enabled in machine mode. The value of the MPIE field is updated to the value of the MIE field before the exception occurred. After the exception ends, the value of the MIE field is restored to the value before the exception occurred using the value of the MPIE field, and the value of the MIE field is updated to 0. The value of the MPP field is updated to the mode before the exception occurred. After the exception ends, the working mode before the exception occurred is restored using the value of the MPP field. The processor core of the present invention only supports machine mode, and the value of the MPP field is binary 11. Finally, after the processor completes exception handling, it uses the mret instruction to exit the exception, stops executing the current instruction flow, and instead starts executing from the PC address defined by the mepc register. At the same time, update the mstatus register, and the MIE field in this register is updated to the current value of the MPIE field, and the value of the MPIE field is updated to 1.

[0048] In one embodiment, the system of the present application can support 5 types of exceptions and 3 types of interrupts, and at the same time support 6 interrupt priorities. The interrupt priorities can be set according to the types and quantities of external interrupt sources, which are not limited here.

[0049] Please refer to Figure 7 , Figure 7It is a schematic diagram of the microarchitecture of a processor in an embodiment of the present application. PLIC and CLINT are mounted on the processor core, and external interrupt sources may include UART0, I2C0, GPIO, SPI, UART1, I2C1, etc. The architecture of a specific processor can be set and adjusted according to actual requirements, which is not limited here.

[0050] Based on the technical solutions of the embodiments of the present application above, it is possible to simply implement the interrupt and exception functions of the RV32IM instruction set architecture processor in machine mode. In addition, this design method has a simple structure, low power consumption, and a small circuit area, and is applicable to embedded processor devices with low requirements for processor performance but small requirements for low-power design and area, and has good engineering practicability.

[0051] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A RISC-V-based interrupt and exception handling system, characterized in that: include: A core-local interrupt controller, which is used to generate software interrupts and timer interrupts; A platform-level interrupt controller, which is used to integrate multiple external interrupt sources into an external interrupt signal; A delivery module is arranged in the processor core, and after receiving the interrupt signal request of the core local interrupt controller and the platform-level interrupt controller or the exception signal request of the arithmetic logic unit in the processor core, sends a pipeline flush request and a first instruction count value for re-fetching instructions to the instruction fetch stage, wherein the core local interrupt controller and the platform-level interrupt controller are mounted on the processor core.

2. The RISC-V-based interrupt and exception handling system according to claim 1, characterized in that: The core local interrupt controller includes an msip register, an mtime register and an mtimecmp register. The software interrupt is directly generated through the msip register and given to the processor core; the value of the timer is reflected through the mtime; and a comparison value is provided for the timer through the mtimecmp register to generate the timer interrupt when the value of the timer is greater than or equal to the comparison value.

3. The RISC-V-based interrupt and exception handling system according to claim 2, characterized in that: The msip register adopts a 32-bit register, and only the lowest bit is a valid bit, and the valid bit is directly given to the processor core as a software interrupt.

4. The RISC-V-based interrupt and exception handling system according to claim 1, characterized in that: The external interrupt sources include GPIO, UART, API and I2C. The platform-level interrupt controller arbitrates multiple external interrupt sources into one unit of the external interrupt signal and sends it to the delivery module for processing.

5. The RISC-V-based interrupt and exception handling system according to claim 1, characterized in that: When an asynchronous exception, a synchronous exception, and an interrupt occur simultaneously, the priority of the asynchronous exception is higher than the priority of the interrupt, and the priority of the interrupt is higher than the priority of the synchronous exception.

6. The RISC-V-based interrupt and exception handling system according to claim 1, characterized in that: The priority of the external interrupt is higher than the priority of the software interrupt, and the priority of the software interrupt is higher than the priority of the timer interrupt.

7. A method for the RISC-V based interrupt and exception handling system according to any one of claims 1 to 6, characterized in that: include: After receiving an interrupt request or an exception request, the processor enters the exception program and stops executing the current program flow; Execute the exception program starting from the second instruction count value defined by the mtvec register; Update the exception type to the mcause register and save the return address of the exception or interrupt to the mepc register; Update the memory access address or instruction code that caused the current exception or interrupt to the mtval register; Update the threshold in the mstatus register to save the working mode and interrupt enable configuration before the exception occurs; Exit the exception handling program, start execution from the return address in the mepc register, and update the threshold in the mstatus register again to restore the working mode and interrupt enable configuration before the exception occurs.

8. The method according to claim 7, characterized in that The steps to save the return address of an exception or interrupt into the mepc register include: When an interrupt occurs, the interrupt return address saved in the mepc register is updated to the instruction count value of the next unexecuted instruction; when an exception occurs, the return address saved in the mepc register is updated to the instruction count value of the instruction where the exception currently occurs, and if the exception is generated by ecall or ebreak, the value in the mepc register is changed to point to the next instruction.

9. The method according to claim 7, characterized in that: The thresholds in the mstatus register include: The MIE field value is used to indicate whether interrupts are enabled globally in this mode; MPIE domain value, used to save the MIE threshold before the abnormality occurs; MPP threshold, used to indicate the working mode.

10. A processor, characterized in that: Comprising a RISC-V-based interrupt and exception handling system as described in any one of claims 1-6.

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