Byte error correction

Abstract

A scheme is proposed for correcting at least one byte error in a binary sequence, wherein the binary sequence comprises a plurality of bytes and is a codeword of an error code in the absence of an error. The solution comprises the following steps: (i) determining at least one byte error position signal indicating whether the bytes of the binary sequence are wrong, (ii) determining at least one byte error correction value, according to which the byte position of the error identified by means of the byte error position signal can be corrected, (iii) wherein at least one byte error correction value is determined by determining a first value, a second value and a third value for each of the at least three byte positions according to coefficients of the locator polynomial, and (iv) the at least one byte error is corrected according to the at least one byte error correction value.

Description

Background Art

[0001] It is known to identify errors in data present in byte form byte by byte and correct them byte by byte. Here, a byte can include at least two bits. At least one error in at least one bit of a byte is called a byte error. If there is at least one error in at least one bit of a byte, there is a byte error. If there is at least one error in at least one bit of only a single byte, this corresponds to a 1-byte error.

[0002] For example, the correction of 1-byte errors is described in [Bossen, D.: b-Adjacent Error Correction, IBM J. Res. Dev., July 1970, pp. 402 to 408].

[0003] If bits in two different bytes are in error, this corresponds to a 2-byte error. Thus, it holds that: when bits in k bytes are in error (i.e., at least one bit in each of the k bytes is in error), there is a k-byte error.

[0004] The general motivation is to quickly correct errors in possibly erroneous bytes. For example, this holds if data present in bytes is to be read from a memory in parallel and provided in parallel. In such a scenario, it would be advantageous to perform error correction in parallel.

[0005] Here, parallel in particular means: performing error correction or a part of error correction on at least two bytes at least partly simultaneously (e.g., also at least partly time-overlapping).

[0006] For example, byte error correction can be performed by means of Reed-Solomon codes.

[0007] In OKANO [Okano, H., Imai, H.: A Construction Method of High-Speed Decoders Using ROM's for Bose-Chaudhuri-Hocquengiem and Reed-Solomon Codes, IEEE TRANSACTIONS ON COMPUTERS, VOL. C-36, NO. 10, October 1987, pp. 1165 to 1171], a circuit arrangement for correcting 2-byte errors using Reed-Solomon codes is described. Here, the disadvantage is that the 2-byte error correction described in OKANO is relatively slow. Summary of the Invention

[0008] The object of the present invention is to avoid the disadvantages of known solutions for correcting byte errors and in particular to enable error correction of errors in multiple bytes as quickly as possible.

[0009] In particular, one object is to provide error correction for m-byte errors in memory cells (such as MRAM memory cells, RRAM memory cells, etc.), where m≥2, thereby increasing the reliability of the data read from the memory cells.

[0010] This object is achieved according to the features of the independent claims. Preferred embodiments can in particular be derived from the dependent claims.

[0011] There is proposed a circuit arrangement for correcting at least one byte error in a binary sequence comprising a plurality of bytes, where in the error-free case the binary sequence is a codeword of an error code, and where the circuit arrangement is designed

[0012] - for determining at least one byte error position signal which indicates whether the bytes of the binary sequence are in error,

[0013] - for determining at least one byte error correction value, by means of which the byte positions in error identified with the aid of the byte error position signal can be corrected,

[0014] - where at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to the coefficients of a locator polynomial,

[0015] - for correcting at least one byte error according to at least one byte error correction value.

[0016] It should be noted here that: a byte error position signal can be determined for each byte of the binary sequence. Thus, the byte error position signals are linked or associated with each byte of the binary sequence. The value of the byte error position signal indicates whether the byte linked to the byte error position signal has an error.

[0017] The error code is, for example, an error correction and / or error identification code. For example, Reed-Solomon codes can be used as error codes.

[0018] An improvement is that the first value comprises: the correction value A multiplied by a first constant, where the first constant is determined by the position of the byte in error.

[0019] An improvement is that the third value comprises: the correction value C multiplied by a second constant, where the second constant is determined by the position of the byte in error.

[0020] An improvement is that the multiplication by the constant is a multiplication in the Galois field GF(2 m ) where m≥2.

[0021] An improvement is that the byte error correction value is determined according to the following formula:

[0022] v(L) = α L ·A + B + α 2L ·C, (1)

[0023] where

[0024] a L represents the first constant

[0025] a 2L represents the second constant

[0026] A and C represent correction values

[0027] B represents the second value and

[0028] + represents addition in the Galois field GF(2 m ), where m ≥ 2

[0029] An improved form is that the correction values A and C and the second value are the same for different byte positions

[0030] An improved form is that the second constant is the square of the first constant

[0031] An improved form is to correct the byte positions where the error correction value of the byte position error is not zero

[0032] An improved form is that 3 - byte errors can be corrected with the help of three - byte error position signals

[0033] An improved form is to determine the byte error correction values at least partially overlapping in time

[0034] In particular, at least two byte error correction values can be determined in parallel. Here, parallel specifically means: determining values at least partially parallel to each other, that is, for example, simultaneously or at least partially simultaneously

[0035] An improved form is that the components of the error syndrome of the error code can be used to determine the byte error position signal

[0036] An improved form is to determine at least one byte error correction value among the byte error correction values for at least one correct byte

[0037] An improved form is to correct 3 - byte errors

[0038] An improved form is that the error code is a Reed - Solomon code in the Galois field GF(2 m ), where m ≥ 2, and the Reed - Solomon code can correct at least 3 - byte errors

[0039] There is also proposed a method for correcting at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence is a codeword of an error code in the error-free case, and the method comprises the following steps:

[0040] - Determining at least one byte error position signal, which indicates whether the bytes of the binary sequence are in error,

[0041] - Determining at least one byte error correction value, based on which the error byte positions identified by means of the byte error position signal can be corrected,

[0042] - Wherein at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to the coefficients of a locator polynomial,

[0043] - Correcting at least one byte error according to at least one byte error correction value.

[0044] The above explanations regarding the device apply correspondingly to this method. The method steps described herein can be performed by means of this device. Description of the Drawings

[0045] Hereinafter, the above features, characteristics and advantages of the present invention and the manner and method of how to implement them will be described in conjunction with the schematic description of the embodiments, and the embodiments will be more specifically explained in conjunction with the drawings. Herein, for the sake of clarity, the same or identically acting elements may be provided with the same reference signs.

[0046] Wherein:

[0047] Figure 1 Shows an exemplary circuit arrangement for parallel formation of a byte error position signal for a 2-byte error,

[0048] Figure 2 Shows Figure 1 An alternative design of the circuit arrangement shown in

[0049] Figure 3 Shows another design of the circuit arrangement shown in Figure 1 With a central circuit component,

[0050] Figure 4 Shows Figure 3 An alternative exemplary implementation of the central circuit component shown in

[0051] Figure 5 Shows an example of a circuit arrangement for byte error correction for a 2-byte error,

[0052] Figure 6 ShowsFigure 5 An example of an implementation of a sub - circuit for forming a byte error correction value as shown in

[0053] Figure 7 shown Figure 5 Another example of an implementation of a sub - circuit for forming a byte error correction value as shown in

[0054] Figure 8 An example of a correction circuit for 1 - byte and 2 - byte errors using a circuit device for forming a byte error position signal for a 2 - byte error

[0055] Figure 9 An exemplary correction circuit for 1 - byte, 2 - byte up to t - byte errors using a circuit device for forming a byte error position signal for a 2 - byte error

[0056] Figure 10 shown Figure 8 An exemplary design of the sub - circuit as shown in

[0057] Figure 11 An error recognition circuit is shown

[0058] Figure 12 An error recognition circuit for identifying 3 - byte errors is shown

[0059] Figure 13 A table is shown that explains different representations of the elements of the Galois field GF(2 m ), where m = 5

[0060] Figure 14 An exemplary design for forming coefficients σ 1 and σ 2 is shown

[0061] Figure 15 An exemplary design for forming a term is shown

[0062] Figure 16 An exemplary design for forming a term is shown

[0063] Figure 17 An exemplary design for forming the value of a locator polynomial based on the coefficients σ 1 and σ 2 at byte positions i and j of the locator polynomial is shown

[0064] Figure 18 An exemplary design for forming a byte error correction value a(k) at byte positions i and j is shown

[0065] Figure 19 An exemplary design for correcting byte errors at positions i and L is shown.

[0066] Figure 20 An exemplary design for determining correction values A, B, and C is shown. Detailed Description

[0067] For example, the use of Reed - Solomon codes for correcting byte errors is discussed in depth below. Here, a byte can include multiple bits.

[0068] For each correctable byte position, a signal (also referred to as a byte error position signal) is determined, based on which it can be confirmed whether the byte is in error. For example, if the byte is in error, the value of the byte error position signal is 1; if the byte has no error, the value of the byte error position signal is 0.

[0069] The byte error position signal is preferably determined by the value of a locator polynomial. In the case of a byte error correction code, its own locator polynomial can be used for each number of errors.

[0070] Thus, in particular, it is proposed to determine the byte error position signal for the correctable byte positions of a byte error correction code, where the byte error correction code can in particular correct at least two byte errors.

[0071] Here, the correctable byte position is a byte position for which, if an error that can be corrected by the byte error correction code occurs, a correction is provided.

[0072] A byte is, for example, a data byte, a combination of a data byte and a parity byte, or a subset thereof. The data byte preferably contains valid data.

[0073] A byte error correction value can be determined for a byte position, and if an error occurs there, the byte position is corrected according to the byte error correction value. The byte error position signal indicates whether an error has occurred for the byte, and the error can be corrected by means of the byte error correction value. By means of the byte error position signal, therefore, individual byte positions that should not be corrected can be masked.

[0074] In particular, there is the option that the byte error correction value that should not be used for correction at a byte position (for example, because the byte position has no error) is multiplied by 0. In this regard, multiplying the byte error correction value by 0 also corresponds to not using the byte error correction value at the byte position.

[0075] Reed - Solomon Codes, General Description

[0076] Some terms and characteristics of Reed - Solomon codes are explained below.

[0077] For example, consider

[0078] -t-byte error correction code and

[0079] -t-byte error correction and (t + 1)-byte error detection code. In particular, consider the cases t = 2 and t = 1.

[0080] For example, Reed-Solomon codes known as byte error correction codes can be used. For Reed-Solomon codes, refer to [Lin, S., Costello, D.: Error Control Coding, Prentice Hall, 1983, pages 170 to 177] or [Wicker, S.: Error Control Systems for Digital Communications and Storage, Prentice Hall, 1995, pages 214 to 224], for example.

[0081] A 1-byte error correction and 2-byte error detection Reed-Solomon code has the following H matrix

[0082]

[0083] Here, α i is an element of the Galois field GF(2 m ). For example, the elements exist in exponential representation. α can be a primitive element of the Galois field GF(2 m ). The exponent j of α j can be interpreted as modulo 2 m - 1.

[0084] It is feasible to derive the H matrix from the H matrix according to formula (2) by multiplying the i-th column by α m for i = 0,..., (2 -i - 2).

[0085]

[0086] Thus, only the form of the H matrix changes, and the code does not change because α -i ≠ 0. For example, this is also described in [Fujiwara, E.: Code Design for Dependable Systems, Wiley, 2006, page 65], where the value "1" is used for α 0 , because α 0 is the identity element of the Galois field used.

[0087] The following H matrix is used for 2-byte error correction and 3-byte error detection code:

[0088]

[0089] Each column of the H matrix described in formula (4) corresponds to one byte.

[0090] If the length of the code is N bytes or m·N bits (where each byte has m bits), then only N columns of the H matrix according to formula (2) or formula (4) are used. For example, then the remaining (last) 2 m -2-N columns can be deleted.

[0091] Generally, for t-byte error correction and t + 1-byte error identification code, the H matrix can be described as follows:

[0092]

[0093] Below, consider by way of example a code that can correct 2-byte errors and identify 3-byte errors.

[0094] If an error occurs, the correct vector v = v 0 ,..., v N-1 is disturbed into the error vector v′ = v′ 0 ,..., v′ N-1 .

[0095] The components v 0 ,..., v N-1 of the vector v are bytes, and the bytes each include m bits, such that for i = 0,..., N - 1 it holds that Therefore, are the m bits of the i-th byte.

[0096] The m-bit byte can also be referred to as an element of the Galois field GF(2 m ).

[0097] If there is a 1-byte error, only a single byte is in error, that is, for a specific i ∈ {0,..., N - 1}, the corresponding i-th byte is in error.

[0098] If the correct i-th byte is represented by and the incorrect i-th byte is represented by , then 1 or 2 or up to m bits of the correct i-th byte may be different from the incorrect i-th byte.

[0099] The byte error in the i-th byte can be determined by

[0100] - the position i of the incorrect byte and

[0101] - the byte error value

[0102]

[0103] is described. Here, it should be noted that: represents an exclusive OR operation.

[0104] The position of the i-th byte can also be represented by α i is represented.

[0105] If the byte error value e in byte position i should be used i to correct the byte error, then for byte position i, a byte error correction value equal to the byte error value needs to be determined.

[0106] In this example, for the byte error to be corrected, the byte error value is equal to the byte error correction value; in this regard, the terms byte error value and byte error correction value can be used synonymously.

[0107] To avoid confusion in the number of indices, hereinafter, the byte error values are represented by the letters a, b, c.

[0108] The byte error correction value of the i-th byte can also be represented by a(i).

[0109] The byte positions can be represented by i, j, k,... or by αi, αj, αk,..., where α is a generating element of the Galois field GF(2 m ).

[0110] The syndrome s has syndrome components (also called components, syndrome components, partial syndromes, or partial corrections) s 1 , s 2 , s 3 , s 4 , s 5 , and the syndrome components are determined for the H matrix according to formula (4) as:

[0111] s 1 =(α 0 , α 0 ,..., α 0 )·(v′ 0 , v′ 1 , …, v′ N-1 ) T ,

[0112] s 2 =(α 0 , α 1 , …, α N-1 )·(v′ 0 , v′ 1 ,..., v′ N-1 ) T ,

[0113] s3 = (α 0 , α 2 ,..., α 2(N-1) )·(v′ 0 , v′ 1 ,..., v′ N-1 ) T ,

[0114] s 4 = (α 0 , α 3 ,..., α 3(N-1) )·(v′ 0 , ′ 1 ,..., v′ N-1 ) T ,

[0115] s 5 = (α 0 , α 4 ,..., α 4(N-1) )·(v′ 0 , v′ 1 , …, v′ N-1 ) T .

[0116] Here, (v′ 0 ,..., ′v′ N-1 ) T is a column vector with components v′ 0 ,..., v′ N-1 , and this column vector can also be called the transpose vector of the row vector (v′ 0 ,.., v′ N-1 ).

[0117] The syndrome components s 1 , s 2 , s 3 , s 4 , s 5 respectively form bytes with m bits. If there is no error, the following applies:

[0118] s 1 = s 2 = s 3 = s 4 = s 5 = 0.

[0119] If there is a 1-byte error with a byte error value α at the i-th byte error location, the following applies:

[0120] s 1 = α 0 ·a = a

[0121] s 2 = α i ·a

[0122] s 3 = α 2i ·a

[0123] s 4 = α 3i ·a

[0124] s 5 = α 4i ·a. (5)

[0125] If there is a 2 - byte error with byte error values a and b at byte error positions i and j, the following applies:

[0126] s 1 = α 0 a + α 0 b = a + b

[0127] s 2 = α i ·a + α j ·b

[0128] s 3 = α 2i ·α + α 2j ·b

[0129] s 4 = α 3i ·a + α 3j ·b

[0130] s 5 = α 4i ·α + α 4j ·b. (6)

[0131] If there is a 3 - byte error with byte error values a, b, and c at byte error positions i, j, and k, the following applies:

[0132] s 1 = α 0 a + α 0 b + α 0 c = a + b + c

[0133] s 2 = α i ·a + α j ·b + α k ·c

[0134] s 3 = α 2i ·a + α 2j ·b + α 2k ·c

[0135] s 4 = α 3i ·a + α 3j ·b + α 3k ·c

[0136] s 5 = α 4i ·a + α 4j ·b + α 4k ·c. (7)

[0137] Correct three-byte errors

[0138] One option is to transform the k-bit bytes of the bytes of a codeword forming a first error code (e.g., Reed-Solomon code) into n-bit bytes of multiple codewords forming a second error code. In this regard, reference is also made to US10,903,859B2. For example, Reed-Solomon code can be used, where parity bytes are added to data bytes to form codewords.

[0139] For example, the second error code is an r-out-of-n code, which has r 1s and n - r 0s. The codeword herein includes n bits.

[0140] The second error code can also include r 1 -out-of-n, r 2 -out-of-n to r q -out-of-n codes, having r1 1s and n - r 1 0s, r 2 1s and n - r 2 0s to r q 1s and n - r q 0s. In this example, the codeword also has n bits.

[0141] In the case of no error, it applies that the k-bit bytes of the first error code are reversibly and univocally transformed into n-bit bytes of the second error code, and the n-bit bytes are respectively stored in n memory cells. After reading the n memory cells, the read n-bit codewords of the second error code are transformed back into their corresponding k-bit bytes respectively.

[0142] In the case of an error (e.g., a read error), a word that is not a codeword (also called a non-codeword) of the second error code is read from the n memory cells. Based on the non-codeword, it can thus be confirmed that an error has occurred. Transforming the non-codeword back into k-bit bytes results in incorrect k-bit bytes of the first error code.

[0143] Thus, it can be recognized that as long as the codeword of the second error code is not read out from the n memory cells, an error occurs in the i-th byte of the first error code. Thus, it can be determined that there is an error at the i-th byte position. This i-th byte position is also referred to as an erasure (byte error position). For the i-th byte position of the first error code, it can be indicated by the byte error position signal BP Si whether there is an error in the i-th byte of the first error code. For example, it applies that

[0144] -BP Si = 1: The i-th byte of the first error code has an error.

[0145] -BP Si = 0: No error in the i-th byte is recognized.

[0146] Here, i can take values 0, 1,..., M - 1; in this case, the codeword of the first error code includes M bytes.

[0147] For example, if the first error code is a Reed - Solomon code over the Galois field GF(2 m ), then the value α i can be associated with the byte position i in a one - to - one and reversible manner, where α is a generating element of the Galois field.

[0148] Generally, the byte error position signal can thus be determined. When the n - bit codeword of the second error code appears, this byte error position signal takes a first value, and when a non - codeword of the second error code appears, this byte error position signal takes a second value. Here, for example, for the byte position i, the byte error position signal being equal to 1 should indicate that there is an error in the k - bit byte at the corresponding byte position in the Reed - Solomon code. Then, the value 1 of the byte error position signal indicates the byte error position (erasure) at the byte position i.

[0149] The k - bit bytes can form the bytes of the codeword of the byte error code, such as a Reed - Solomon code over the Galois field GF(2 m ), where m≥2. To correct the k - bit byte with errors according to the Reed - Solomon code, the position of the byte with errors (byte error position) and the byte error value are required.

[0150] According to the example explained here, the position of the byte with errors has been determined by the value of the byte error position signal. If it is determined that the value of the byte error position signal BP Sk is 1, then it can be concluded that the k - bit byte transformed back from the corresponding non - codeword of the second error code is in error. Then, there is no need to use the syndrome component or the check byte of the Reed - Solomon code to determine the position of the error in the k - bit byte because this position is already known. Thus, the check byte can be saved.

[0151] If there is a single-byte error at a known byte error position, only one parity byte of the Reed-Solomon code is required for correction. If there are two-byte errors at two known byte error positions, only two parity bytes of the Reed-Solomon code are required to correct these two-byte errors. If there are three-byte errors at all three known byte error positions, only three parity bytes of the Reed-Solomon code are required for correction.

[0152] Generally applicable is that: If M error-free k-bit bytes B 0 、B 1 、...、B M-1 form a codeword of the Reed-Solomon code with byte positions 0, 1, 2, ..., M-1, then the elements α 0 、α 1 、…、α M-1 of the Galois field GF(2m) can be associated with the byte positions in a reversible and unambiguous manner. Then, a byte error can be described by the byte error position i or equivalently by α i and the byte error value v(i). The byte error value v(i) is a k-bit byte.

[0153] If the byte error position signal BP sL = 0, then the L-th byte without error is corrected. This situation can also be described as follows: The L-th byte for which the byte error value v(L) has been determined is corrected to BP s1 ·v(L) = 0, such that no correction is made due to multiplication by 0.

[0154] If the byte error position signal BP sL = I, then the L-th byte B L has an error, and the corrected value BP s1 ·v(L) = v(L) is not equal to 0.

[0155] As an example, a Reed-Solomon code with three parity bytes and accordingly three syndrome components s 1 、s 2 、s 3 should be considered below.

[0156] If there are 3-byte errors at byte error positions i, j, k or α i 、α j 、α k with the following byte error values

[0157] v(i) = a,

[0158] v(j) = b,

[0159] v(k) = c,

[0160] Then the applicable one is:

[0161] s 1 = a + b + c, (8)

[0162] s 2 = α i a + α j b + α k c, (9)

[0163] s 3 = α 2i a + α 2j b + α 2k c. (10)

[0164] The addition and multiplication operations used can be interpreted as operations in the Galois field GF(2 m ).

[0165] Specifically proposed: Determine the k-bit wide value A, the k-bit wide value B, and the k-bit wide value C in the following manner:

[0166]

[0167] The values A, B, and C are also referred to as correction values. The correction values are based on three syndrome components s 1 , s 2 and s 3

[0168] S 1 = α i + α j + α k , (14)

[0169]

[0170] S 3 = α 3i + α 3j + α 3k (16)

[0171] and the symmetric functions of the powers of α i , α j , α k .

[0172] For each byte position L, which can also be stated as α L , the possible byte error value v(L) is determined from the correction values A, B, C, and the corresponding byte position α L as:

[0173] v(L) = α L·A + B + α 2L ·C. (17)

[0174] For each byte position considered, provide a first value A that is the same for different byte positions on a first m-bit wide line, a second value B that is the same for different byte positions on the m-bit wide line, and a third value C that is also the same for different byte positions on the m-bit wide line.

[0175] Figure 19 Show the correction of the byte error value v(i) at byte error position i and the byte error value v(L) at byte error position L by means of the byte error position signals BP Si and BP SL in an exemplary parallel implementation. Here, correction values A, B, and C according to formula (17) are used.

[0176] Exemplarily, the generation of the corrected signal v(i) kor is described. For this purpose, adders 1902, 1904, multipliers 1901, 1903, and an AND gate 1905 are used. Each adder is an adder in the Galois field GF(2 m ) and corresponds to a component-wise exclusive OR operation. If BP Si = 0 applies, the AND gate 1905 provides v(i) kor = 0 at its output. Otherwise (i.e., if BP Si = 1), it provides v(i) kor = v(i) at the output.

[0177] The correction value A is multiplied by a constant α i by means of the multiplier 1901 and added to the correction value B by means of the adder 1902.

[0178] The correction value C is multiplied by a constant α 2i by means of the multiplier 1903 and added together with the result of the adder 1902 in the adder 1904 to form the byte error value v(i), which is fed to the m-bit wide input of the AND gate 1905. The AND gate 1905 also has a 1-bit wide input that is connected to the byte error position signal BP Si . The m-bit wide corrected signal v(i) kor is provided at the output of the AND gate 1905.

[0179] In parallel with this, the corrected signal v(L) kor at the L-th byte position can be determined. For this purpose, corresponding components, here adders 1912, 1914, multipliers 1911, 1913, and the AND gate 1915 are used in combination with the byte error position signal BP SL .

[0180] Figure 20 An exemplary implementation for providing correction values A, B, and C is shown. For this purpose, adders 2001, 2003, 2004, 2009, 2011, 2013, 2016, multipliers 2007, 2008, 2010, 2012, 2014, 2015, 2017, a squarer 2006, a cube value generator 2002, and a reciprocal calculator 2005 are used. The lines shown are m-bit wide. Each adder is an adder in the Galois field GF(2 m ) and performs a component-wise exclusive OR operation. Each multiplier is a multiplier in the Galois field GF(2 m ). The reciprocal calculator 2005 is a reciprocal calculator in the Galois field GF(2 m ).

[0181] With the help of adder 2001, symmetric function S i , α j , α k is formed from the elements of according to formula (14). The cube value generator 2002 determines the value 1 from it and forwards it to adder 2004.

[0182] With the help of adder 2003, symmetric function S 3i , α 3j , α 3k is formed from the elements of according to formula (16), and the symmetric function is added to 3 in adder 2004.

[0183] The output of adder 2004 is connected to the input of reciprocal calculator 2005. Therefore, the term

[0184]

[0185] is provided at the output of reciprocal calculator 2005. The correction value B is determined as follows: The output of adder 2001 is connected to the input of squarer 2006 and to the input of multiplier 2007. The other input of multiplier 2007 is connected to the syndrome component s 3 , and the output of multiplier 2007 is connected to the input of adder 2009. The output of squarer 2006 provides and is connected to the input of multiplier 2008. The syndrome component s 2 is provided at the other input of multiplier 2008. The outputs of adders 2007 and 2008 are connected to different inputs of adder 2009. Therefore, the term ​​

[0186] The output terminal of the adder 2009 is connected to the input terminal of the multiplier 2010, and the other input terminal of the multiplier 2010 is connected to the output terminal of the reciprocal calculator 2005. The output terminal of the multiplier 2010 is connected to the input terminal of the adder 2011, and the syndrome component s 1 is applied at the other input terminal of the adder 2011. Therefore, a correction value is provided at the output terminal of the adder 2011 according to formula (12)

[0187]

[0188] The correction value A is determined as follows: The output terminal of the squarer 2006 is connected to the input terminal of the multiplier 2012, and the other input terminal of the multiplier 2012 is connected to the syndrome component s 1 is connected. The output terminal of the multiplier 2012 is connected to the input terminal of the adder 2013, and the syndrome component s 3 is provided at the other input terminal of the adder 2013. The output terminal of the adder 2013 is connected to the input terminal of the multiplier 2014. The other input terminal of the multiplier 2014 is connected to the output terminal of the reciprocal calculator 2005. Therefore, according to formula (11), the correction value

[0189]

[0190] is applied at the output terminal of the multiplier 2014.

[0191] The correction value C is determined as follows: The output terminal of the adder 2001 is connected to the input terminal of the multiplier 2015, and the other input terminal of the multiplier 2015 is connected to the syndrome component s 1 is connected. The output terminal of the multiplier 2015 is connected to the input terminal of the adder 2016, and the syndrome component s 2 is provided at the other input terminal of the adder 2016. The output terminal of the adder 2016 is connected to the input terminal of the multiplier 2017. The other input terminal of the multiplier 2017 is connected to the output terminal of the reciprocal calculator 2005. Therefore, according to formula (13), the correction value

[0192]

[0193] is applied at the output terminal of the multiplier 2017.

[0194] As explained in formula (17): For each considered byte position L, where L = 0,..., M - 1

[0195] - Multiply the correction value A by the first constant α corresponding to the L-th byte position L ,

[0196] - Multiply the correction value C by a second constant α corresponding to the L-th byte position 2L .

[0197] Add the correction value B, the correction value A multiplied by α L , and the correction value C multiplied by α 2L , where the addition is performed in the Galois field GF(2 m ). If the values to be added in GF(2 m ) are represented as m-component binary vectors in their vector representations, then the addition in the Galois field GF(2 m ) corresponds to component-wise addition modulo 2 or component-wise exclusive OR operation (XOR operation).

[0198] Here, for the three byte positions i, j, k where there are error bytes, the following applies to the byte error position signal:

[0199] BPs i = BPs j = BPs k = 1

[0200] And correction is performed at the said byte positions. For all other byte positions where there are no errors, the byte error position signal is equal to 0 and no correction is performed there.

[0201] By substituting formulas (8), (9), (10), (14), and (16) into formula (17), for the error byte error positions i, j, k to be corrected, we get:

[0202] v(i) = a, v(j) = b, v(k) = c. (18)

[0203] Here

[0204]

[0205] For the value BPs SL = 0 at the byte position L, the value BPs L ·v(L), regardless of the value of v(L), is 0·v(L) = 0, and thus no correction is performed, where there is no error at the said byte position L.

[0206] In formulas (11), (12), and (13), S 1 is determined according to formula (14) as S 1 = α 1 + α j + α k .

[0207] S 1 is the locator polynomial L 3The coefficient of (x) and is a symmetric function.

[0208] If a locator polynomial of the following form is used

[0209] L 3 (x) = (x + α i )(x + α j )(x + α k ) =

[0210] = x 3 + x 2 (α i + α j + α k ) + x(α i α j + α i α k + α j α k ) + α i α j α k ,

[0211] Then S 1 is the coefficient of x 2 .

[0212] S 1 is a symmetric function of α i , α j , α k and is the sum of the first powers of α i , α j , α k in the Galois field under consideration. If α i , α j , α k are used as binary vectors in their vector representation, then the sum can be implemented as a component-wise exclusive OR operation.

[0213] If a locator polynomial of the following form is used

[0214] L 3 (x)' = (1 + α i x)(1 + α j x)(1 + α k x) =

[0215] 1 + x(α i + α j + α k ) + x 2 (α i α j + α i α k + α j αk ) + α i α j α k ,

[0216] Then S 1 is the coefficient of x.

[0217] Derivation of the correction

[0218] The following shows how the formula (17) can be determined.

[0219] Given a Reed - Solomon code with H matrix

[0220]

[0221] Assume that there are 3 - byte errors in the byte error positions α

[0222] v(i) = a,

[0223] v(j) = b,

[0224] v(k) = c, where the byte error positions α i , α j , α k are known and the byte error values a, b, and c are unknown. The byte error values a, b, and c should be determined. Even if only three syndrome components s i , s j , and s k are determined, the 3 - byte errors can be corrected. 1 , s 2 and s 3

[0225] The unknown byte error value c = v(k) of the known byte error position α k can be determined as follows: by modifying the error syndrome of the 3 - byte error in the positions α i , α j , α k to the syndrome of the 2 - byte error in the byte error positions α i , α j with the byte error values a = v(i) and b = v(j), where the positions α i , α j , α k have the hypothesized and to - be - determined byte error value c and the known α k .

[0226] Thus, a formula for the byte error value c is derived, which allows: from the byte error positions α i , α j , α k ​and syndrome component s 1 、s 2 and s 3 to determine the byte error value c.

[0227] The solution can be summarized as follows:

[0228] The syndrome component s of a 3 - byte error with three byte error positions 1 = a + b + c is converted to the syndrome component s′ 1 = s 1 + c = a + b.

[0229] The syndrome component s of a 3 - byte error with three byte error positions 2 = α i a + α j b + α k c is converted to the syndrome component s′ 2 = s 2 + α k c = α i a + α j b.

[0230] The syndrome component s of a 3 - byte error with three byte error positions 3 = α 2i a + α 2j b + α 2k c is converted to the syndrome component s′ 3 = s 3 + α k c = α 2i a + α 2j b.

[0231] The converted syndrome component s′ 1 ,s′ 2 ,s′ 3 is the syndrome component of a 2 - byte error.

[0232] For a 2 - byte error with the coefficients σ′ 1 ,s′ 2 ,s′ 3 of the locator polynomial of the component sum of the Reed - Solomon code and 1 and σ′ 2 where

[0233] σ′ 1 = α i + α j ,

[0234] σ′ 2 = α i ·α j

[0235] and wherein

[0236] s′ 1 = a + b,

[0237] s′ 2 = α i ·a + α j ·b,

[0238] s′ 3 = α 2i ·a + α 2j ·b

[0239] Applicable:

[0240] s′ 1 ·σ′ 2 + s′ 2 ·σ′ 1 = s′ 3 . (21)

[0241] Derived using formulas (8) to (10):

[0242] s′ 1 = s 1 + c, (22)

[0243] s′ 2 = s 2 + α k ·c, (23)

[0244] s′ 3 = s 3 + α 2k ·c. (24)

[0245] Since the byte error positions α i 、α j 、α k are known, the byte error value c can be determined such that if s′ 1 、s 2 、s 3 and c are used to determine s′ 1 、s′ 2 and s′ 3 according to formulas (22) to (24), then formula (21) is satisfied. Applicable is:

[0246] (s 1 + c)(α i α j )+(s 2 + α k c)(α i + α j ) = s 3 + α2k c. (25)

[0247] Obtained by transformation:

[0248] s 1 α i α j +s 2 (α i +α j )+s 3 = c[α i +α j +α i α k +α j α k +α 2k .

[0249] In addition, the following applies:

[0250]

[0251] For the denominator N, the following applies

[0252] N = α i α j +α i α k +α j α k +α 2k =(α i +α k )(α j +α k ).

[0253] Since α i 、α j 、α k are pairwise different, the denominator N in formula (26) is always not equal to 0. Therefore, the solution of c is always possible. Formula (26) can also be expressed in the following form

[0254]

[0255] Correspondingly, for the byte error correction values a and b corresponding to the byte error positions α i and α j the following applies:

[0256]

[0257] and

[0258]

[0259] Up to this point, c = v(k) is obtained from s through formula (26) or formula (27)1 , s 2 , s 3 and α i , α j and α k are determined from

[0260] The following explains how a parallel solution for the byte position to be corrected can be achieved.

[0261] The denominator N is modified as follows:

[0262]

[0263] where

[0264] N 1 =(α i +α k )(α j +α k )(α i +α j ).

[0265] N 1 is a symmetric function of α i , α j , α k . With the symmetric functions S 1 and S 3 according to formulas (14) and (16), N 1 can be transformed into

[0266] N 1 =(S 1 )( 3 +S 3 (31)

[0267] Here, S 3 is the sum of the cubes of α i , α j , α k to the power of α 3i , α 3j , α 3k .

[0268] Formula (31) can be verified by recalculation. The symmetric functions S 1 and S 3 can be determined from the byte error positions α i , α j , α k .

[0269] Therefore, by factoring N 1 in formula (30), we get:

[0270] N1 =(α i +α k )(α j +α k )(α i +α j ) =

[0271] =(α i α j +α i α k +α j α k +α 2k )(α i +α j ) =

[0272] =α 2i α j +α i α 2j +α 2i α k +α i α j α k +α i α j α k +α 2j α k +α i α 2k +α j α 2k =

[0273] =α 2i α j +α 2i α k +α i α 2j +α 2j α k +α i α 2k +α j α 2 w =

[0274] =α 2i (α j +α k ) + α 2j (α i +α k ) + α 2k (α i +α j )。

[0275] On the other hand, according to formulas (14) and (16) and substituting into formula (31), we get:

[0276] (S 1 ) 3 +S 3 =(α i +α j +α k ) 3 +α 3i +α 3j +α 3k =

[0277] =(α i +α j +α k ) 2 (α i +α j +α k )+α 3i +α 3j +α 3k =

[0278] =(α 2i +α i α j +α i α k +α i α j +α 2j +α j α k +α i α k +α j α k +α 2k )·

[0279] ·(α i +α j +α k )+α 3i +α 3j +α 3k =

[0280] =(α 2i +α 2j +α 2k )(α i +α j +α k )+α 3i +α 3j +α 3k =

[0281] =α 3i +α 2i α j +α 2i α k +α 2j α i +α3j +α 2j α k +α i α 2k +α j α 2k +α 3k +

[0282] +α 3i +α 3j +α 3k =

[0283] =α 2i α j +α 2i α k +α 2j α i +α 2j α k +α i α 2k +α j α 2k =

[0284] =α 2i (α j +α k )+α 2j (α i +α k )+α 2k (α i +α j )=

[0285] =N 1 。

[0286] Therefore, for c = v(k), based on formulas (27), (30) and (31), we get

[0287]

[0288] Derived with the aid of formula (14)

[0289] α i +α j =S 1 +α k (33)

[0290] Because

[0291] (α i +α j ) 3 +α 3i +α 3j =(α i +α j ) 2 (αi +α j )+α 3i +α 3j =

[0292] =(α 2i +α 2j )(α i +α j )+α 3i +α 3j =

[0293] =α 3i +α 2i α j +α i α 2j +α 3j +α 3i +α 3j =

[0294] =α 2i α j +α i α 2j

[0295] And

[0296] α i α j (α i +α j )=α 2i α j +α i α 2j

[0297] If applicable, then we get

[0298] α i α j (α i +α j )=(α i +α j ) 3 +α 3i +α 3j (34)

[0299] Derived from formula (16)

[0300] α 3i +α 3j =S 3 +α 3k (35).

[0301] When substituting formulas (33) and (35) into formula (34), we get

[0302]

[0303] Derived from formula (32)

[0304]

[0305] With the aid of formula (36), formula (33) and

[0306]

[0307] Obtain

[0308]

[0309] Therefore, it is sufficient that:

[0310]

[0311] And

[0312]

[0313] Is formed only once. The multiplication with a in the k-th byte position k And a 2k Is a multiplication with a constant, and the multiplication can be implemented by some XOR gates.

[0314] Similarly, the byte error correction values a and b are determined as

[0315]

[0316] Generally, regardless of whether the byte position L is a byte error position, the value v(L) can be determined for each byte position L

[0317]

[0318] The value v(L) determined for a byte position L that is not a byte error position can be multiplied by the byte error position signal BP SL = 0. Regardless of the specific value v(L), correction by means of the value 0 is then performed in the byte position L. This corresponds to no correction.

[0319] Byte error position signal, where

[0320] For L ≠ i, j, k, BP Si = BP Sj = BP Sk = l and BP SL = 0

[0321] Explanation: The byte error values v(i), v(j), v(k) are used for correction, and the corrected byte error value v(L) cor = BPsL ·v(L) is equal to 0 for all other byte positions. The value of v(L) for L ≠ i, j, k is not important.

[0322] Error consideration

[0323] For the errors considered, the following relationships are satisfied:

[0324] 1. Applicable for 1-byte errors:

[0325] s 1 = a ≠ 0 (43)

[0326] and

[0327]

[0328] 2. Applicable for 2-byte errors:

[0329]

[0330] and

[0331]

[0332] 3. For 3-byte errors

[0333]

[0334] In the case of a 2-byte error occurring in the i-th and j-th bytes, the byte error positions α i and α j can be determined as the solutions, roots, or zeros of the following formula

[0335]

[0336] which can also be referred to as a second-order locator polynomial.

[0337] Correspondingly, the byte error position of a 1-byte error is determined by the zero of a first-order locator polynomial, and generally, for

[0338] 1 ≤ τ ≤ t

[0339] the error byte positions of τ-byte errors of a t-error byte correction code are determined by the zeros of a τ-order locator polynomial.

[0340] If the codeword consists of N·m bits and thus N bytes, there are only N different byte positions, which are considered as byte error positions. And in the corresponding bit correction code, there are m·N possible error bit positions.

[0341] In the case of a 1-byte error, a first-order locator polynomial is used, and in the case of a 2-byte error, a second-order locator polynomial is used.

[0342] Reed-Solomon code, supplementary implementation

[0343] In the case of a 2-byte error, the byte error correction value a(i) of the i-th byte can be determined only based on the syndrome components s 1 、s 2 、s 3 and the byte position i.

[0344] It is advantageous here that: multiple byte error correction values can be determined in parallel for, for example, at least three correctable bytes.

[0345] For example, assume that there are 2-byte errors. The byte error correction value for each byte position can be determined in parallel based on the provided syndrome components s 1 、s 2 、s 3 and the known position of each correctable byte. Byte error correction values are determined for two error bytes and at least for the error-free bytes.

[0346] The byte error correction value determined for the i-th byte position is consistent with the byte error value at that i-th position.

[0347] The byte error position signal determined in the same way (possibly in parallel) confirms whether there is a byte error in the considered byte and whether correction is made with the byte error correction value. If the byte error position signal indicates that there is no byte error in the corresponding position, no correction is made with the byte error correction value determined for that position.

[0348] In other words: the byte error position signal determines at which byte positions correction is made with the provided byte error correction value: if the byte error position signal indicates a byte error for a byte position, correction is made with the byte error correction value; if the byte error position signal does not indicate a byte error for the byte position, no correction is made.

[0349] If a t-byte error correction code is considered, before determining the byte error position signal for (all or some of) the byte positions, the corresponding byte error correction values can be determined for more than t correctable byte positions. The byte error correction values can also be determined in parallel with the byte error position signal.

[0350] If there is no byte error in the i-th byte, the byte error correction value determined for the i-th byte is not used for correction due to the value of the byte error position signal. In this case, it is not necessary either that: the byte error correction value determined for the error-free byte is equal to

[0351]

[0352] Because the byte error position signal excludes correction. Optionally, in this case, the byte error correction value of the i-th byte can be set

[0353]

[0354] If there are two-byte errors, then for the byte error position i, the byte error correction value a(i) of the i-th byte can be determined such that the following applies:

[0355]

[0356] If the byte positions i where byte errors occur are known for two-byte errors, then based on formula (49), for the incorrect byte position i, the value α determined from the byte position i i and the syndrome component s 1 、s 2 、s 3 are used to determine the byte error correction value a(i).

[0357] For the byte position k, regardless of whether there is actually an error at the byte position k, by means of

[0358]

[0359] For example, the byte error correction value a(k) is determined in parallel.

[0360] If the byte error position signal indicates that there is a byte error at the byte position k, then the k-th byte is error-corrected by means of the byte error correction value a(k) determined for the byte position k.

[0361] If the byte error position signal indicates that there is no byte error at the byte position k, then the k-th byte is not error-corrected, and the byte error correction value a(k) determined for the k-th byte is not used for error correction. Optionally, the byte error correction value can be set to 0.

[0362] Therefore, before it is determined whether there is actually an error at a byte position, the byte error correction value for that byte position can already exist.

[0363] For different byte positions, the corresponding byte error correction values can be determined in parallel. In particular, the byte error correction values can be determined in parallel for all correctable byte positions or for a subset of the correctable byte positions.

[0364] If a byte error correction code can correct up to t error bytes, more than t byte error correction values can be determined in parallel, for example, for all correctable byte positions or for a subset of at least t + 1 correctable byte positions, regardless of whether there is a byte error at a byte position.

[0365] Determining the value of the byte error position signal: Whether to use the byte error correction value to correct the corresponding byte.

[0366] The correctable byte positions can be, for example, all data bytes, a subset of data bytes, check bytes, all bytes of the codewords of the t-byte error correction code, or a subset of the bytes of the codewords of the t-byte error correction code.

[0367] For example, here the byte error position signal can be determined such that if a byte at a byte position is in error, the byte error position signal takes a first value for that byte position, and if the byte at that byte position is error-free, the byte error position signal takes a second value different from the first value.

[0368] The byte error position signal can be determined using a corresponding locator polynomial.

[0369] Byte error position signal for 1-byte error

[0370] For 1-byte error, the first-order locator polynomial is

[0371] x·s 1 =s 2 (51)

[0372] where the solution or zero is

[0373]

[0374] The byte error correction value a(i) of the byte position i of the error is

[0375] a(i)=s 1 。 (53)

[0376] For every k-th byte, the byte error correction value is determined

[0377] a(k)=s 1 =a (54)

[0378] If there is an error in the i-th byte with the byte error correction value α, such that s 1= a, then for each byte k, the byte error correction value a(k) = a is determined according to formula (54). The byte error correction value is for the i-th byte to be actually corrected, and bytes not to be corrected are masked (e.g., set to zero). Whether to correct a byte is determined based on the value of the corresponding byte error position signal.

[0379] In the case of 1-byte error, the byte error position signal is determined for each byte using formula (51). The byte error position signal for byte position i

[0380] - If α i is a zero of the locator polynomial according to formula (51), it is equal to 1, and

[0381] - If α i is not a zero of the locator polynomial of functional formula (51), it is equal to 0.

[0382] Only when α i is a zero of the locator polynomial according to formula (51), the i-th byte is corrected.

[0383] The byte error position signal for 2-byte error

[0384] The role of the byte error position signal when correcting 2-byte error is illustrated by examples:

[0385] If a t-byte error correction code with t ≥ 2 is used, in the case of 2-byte error, according to formula (48), the error byte positions are determined by the two zeros of the second-order locator polynomial.

[0386] If the error byte positions are positions i and j, then when α i and α j are zeros of the second-order locator polynomial according to formula (48) respectively, the byte error position signal is equal to 1 for example, and is equal to 0 in all other cases.

[0387] For each byte position k, the byte error correction value can be determined

[0388]

[0389] The byte error correction value can be determined at least partially in parallel.

[0390] The value of the byte error position signal for byte position k determines whether to correct at byte position k. If the byte error position signal is equal to 1, correction is performed; if the byte error position signal is equal to 0, no correction is performed.

[0391] For the byte position k = i, a byte error correction value a(i) is determined such that the i-th byte with an error is corrected by means of the byte error correction value a(i). Similarly, for the byte position k = j, a byte error correction value a(j) is determined such that the j-th byte with an error is corrected by means of the byte error correction value a(j).

[0392] For all other byte positions k ≠ i, j, there is no byte error such that no correction is required for the byte position. Even if a non-zero byte error correction value a(k) is determined, the byte error correction value is not used for correction because the byte error position signal at the byte position takes the value 0, thus indicating that no correction is required for the byte position.

[0393] Handling of 1-byte error, 2-byte error, and 3-byte error

[0394] The following describes how byte errors can be identified and distinguished. Taking the 2-byte error correction code as an example. Additionally, the 3-byte error identification is also described.

[0395] 1. First, start from the case where only 1-byte error or 2-byte error exists. In this example, for 2-byte error, formula (45) applies

[0396]

[0397] And for 1-byte error, formulas (43) and (44) apply

[0398] s 1 ≠0

[0399]

[0400] Additionally, the following case is also distinguished: that is, neither 1-byte error nor 2-byte error occurs. From s 1 = 0, it can already be concluded that neither 1-byte error nor 2-byte error occurs.

[0401] If the probability of 3-byte error is extremely small, it can be concluded for this case that no error occurs.

[0402] 2. Now consider the case where only 1-byte error or only 2-byte error or only 3-byte error exists. For 3-byte error, according to formula (47), it applies

[0403]

[0404]

[0405] ​

[0406] If there is a 2-byte error, additionally formula (45) applies.

[0407]

[0408] For a 1-byte error, formulas (43) and (44) apply again.

[0409] s 1 ≠ 0

[0410]

[0411] One cannot infer from the condition according to formula (45) alone that there is a 2-byte error, because this condition also applies to 3-byte errors.

[0412] The correction of a 2-byte error can be performed as follows: For each byte position i, where i ∈ {0, 1,..., N - 1}, according to

[0413]

[0414] determine the value of the second-order locator polynomial L(α i ).

[0415] If L(α i ) = 0, correct the i-th byte. If L(α i ) ≠ 0, do not correct the i-th byte. The byte error position signal BP Si can indicate whether the corresponding byte is corrected. The byte error position signal BP Si is determined, for example, by the following formula:

[0416]

[0417] In a circuit arrangement for implementing operations in the Galois field GF(2m), for example, multipliers, constant multipliers, squarers, (cubic) power generators, etc. are used. The circuit implementation of each such operation is known. It is shown below by way of example how multipliers, squarers, cubic power generators, and constant multipliers can be implemented in a Galois field determined, for example, by its modulus polynomial. For example, assume m = 5, such that one byte consists of m = 5 bits, and the corresponding Galois field is GF(2 5 ).

[0418] Example in the Galois field GF(2m) with m = 5

[0419] m = 5 is chosen by way of example such that the underlying Galois field

[0420] GF(2 m = GF(2 5 ) = GF(32)

[0421] There are a total of 32 elements.

[0422] The elements of the Galois field GF(32) in its various representations are shown in Figure 13 . The modulo polynomial of the Galois field GF(32) is the following polynomial

[0423] p(x) = 1 + x 2 + x 5 .

[0424] Figure 13 The first column of the table shown in includes the elements α 5 of GF(2 i ) ≠ 0 in exponential representation (also known as exponent representation), where i = 0, 1,..., 30. The zero element of the body does not have an exponential representation. In the second column of the table, all elements are listed in their polynomial representation with respect to the modulo polynomial p(x) to which they belong. The third column of the table shows the tuple or vector representation of the elements of GF(2 5 ). The vector representation of an element can be read directly from the polynomial representation. Here, the five components of the vector representation correspond from left to right to the coefficients of the powers x 0 , x 1 , x 2 , x 3 , x 4 in the polynomial representation.

[0425] By determining [x i modulo (1 + x 2 + x 5 ), the corresponding polynomial representation is obtained from the power representation α i . For example, the polynomial representation of α 5 is equal to 1 + x 2 , because

[0426] x 5 = modulo (1 + x 2 + x 5 ) = 1 + x 2

[0427] applies.

[0428] The product of two elements of the Galois field can be carried out in exponential representation or in polynomial representation. If the two elements of the Galois field GF(2 i and α j are given in exponential representation, then their product is obtained as: m ) = GF(2 5 ), then

[0429] α i ·αj = α k , where k = (i + j) modulo (2 m - 1) = (i + j) modulo 31.

[0430] If the Galois field elements to be multiplied exist in their vector representation or in their polynomial representation, the multiplication of said elements can be performed by means of a Galois field multiplier. Below, the multiplication of two elements in polynomial representation is described by way of example. In order to multiply two elements (the elements being given as elements of the Galois field GF(2 m ) = GF(2 5 )) with each other, the polynomials are directly multiplied with each other in the usual way, and the result is the modulus of the modulus polynomial.

[0431] For example, if the polynomials 1 + x 2 + x 3 and x + x 3 are given, their direct multiplication gives (1 + x 2 + x 3 (x + x 3 ) = x + x 4 + x 5 + x 6 .

[0432] Since

[0433] x 5 = 1 + x 2 modulo (1 + x 2 + x 5 and

[0434] x 6 = x + x 3 modulo (1 + x 2 + x 5 ),

[0435] then we get

[0436] x + x 4 + x 5 + x 6 = x + x 4 + 1 + x 2 + x + x 3 = 1 + x 2 + x 3 + x 4 .

[0437] Therefore, in the result:

[0438] (1 + x 2 + x 3 )·(x + x3 ) = 1 + x 2 + x 3 + x 4 .

[0439] The following describes a situation where, according to the situation, in the Galois field GF(2 5 + x 2 ) with the modulo polynomial m(x) = x 5 + x 4 x 4 + a 3 x 3 + a 2 x 2 + a 1 x + a 0 and the second element b(x) with b(x) = b 4 x 4 + b 3 x 3 + b 2 x2 + b 1 x + b 0 are multiplied. By directly multiplying the polynomials a(x) and b(x), an 8th - order polynomial is first obtained. By means of

[0440] x 5 modulo(1 + x 2 + x 5 ) = 1 + x 2 ,

[0441] x 6 modulo(1 + x 2 + x 5 ) = x + x 3 ,

[0442] x 7 modulo(1 + x 2 + x 5 ) = x 2 + x 4 ,

[0443] x 8 modulo(1 + x 2 + x 5 ) = 1 + x 2 + x 3

[0444] The following fourth - order polynomial is obtained:

[0445] c 4 x 4 + c 3 x 3 + c2 x 2 +c 1 x 1 +c 0 =a(x)·b(x) mod m(x)=

[0446] =(a 0 b 4 +a 1 b 3 +a 2 b 2 +a 3 b 1 +a 3 b 4 +a 4 b 0 +a 4 b 3 )· 4 +

[0447] +(a 0 b 3 +a 1 b 2 +a 2 b 1 +a 2 b 4 +a 3 b 0 +a 3 b 3 +a 4 b 2 +a 4 b 4 )·x 3 +

[0448] +(a 0 b 2 +α 1 b 1 +a 1 b 4 +a 2 b 0 +a 2 b 3 +a 3 b 2 +a 3 b 4 +a 4 b 1 +a 4 b 3 +a 4 b 4 )·x 2 +

[0449] +(α 0 b 1+a 1 b 0 +a 2 b 4 +a 3 b 3 +α 4 b 2 )·x 1 +

[0450] +(a 0 b 0 +a 1 b 4 +a 2 b 3 +a 3 b 2 +a 4 b 1 +a 4 b 4 )。

[0452] The relationship is implemented by a Galois field multiplier having five first binary inputs, five second binary inputs, and five binary outputs. This is explained in more detail below.

[0453] The binary values a 0 、a 1 、a 2 、a 3 、a 4 are applied at the five first inputs of the Galois field multiplier, and the b 0 、b 1 、b 2 、b 3 、b 4 are applied at the five second inputs, and the values c 0 、c 1 、c 2 、c 3 、c 4 are output at the five binary outputs, where

[0454] (a 0 b 0 +a 1 b 4 +a 2 b 3 +a 3 b 2 +a 4 b 1 +a 4 b 4 ) = c 0 , (58)

[0455] (a0 b 1 +a 1 b 0 +a 2 b 4 +a 3 b 3 +a 4 b 2 ) = c 1 (59)

[0456] (a 0 b 2 +a 1 b 1 +a 1 b 4 +a 2 b 0 +a 2 b 3 +a 3 b 2 +a 3 b 4 +a 4 b 1 +a 4 b 3 +a 4 b 4 ) = c 2 (60)

[0457] (a 0 b 3 +a 1 b 2 +a 2 b 1 +a 2 b 4 +a 3 b 0 +a 3 b 3 +a 4 b 2 +a 4 b 4 ) = c 3 (61)

[0458] (a 0 b 4 +a 1 b 3 +a 2 b 2 +a 3 b 1 +a 3 b 4 +a 4 b 0 +a 4 b3 ) = c 4 (62)

[0459] Here, the symbol “+” represents addition modulo 2 (exclusive - or operation).

[0460] The implementation of formulas (58) to (62) can be carried out with the aid of a Galois - field multiplier, for example, using AND gates and exclusive - or (XOR) gates. For example, synthesis tools can also be used within the scope of implementation.

[0461] If an element of the Galois field is squared, it must be multiplied by itself. If an element is represented as a polynomial

[0462] a(x) = a 0 + a 1 x 1 + a 2 x 2 + a 3 x 3 + a 4 x 4 ,

[0463] then it holds that

[0464] (a(x)) 2 mod m(x) =

[0465] = [a 0 + a 1 x 2 + a 2 x 4 + a 3 x 6 + a 4 x 8 mod (1 + x 2 + x 5 ) =

[0466] = (a 2 )x 4 +(a 3 + a 4 )x 3 +(a 1 + α 4 )x 2 + a 3 x 1 +(a 0 + α 4 ).

[0467] The squaring of an element in the Galois field GF(2 5 ) can be correspondingly implemented with a squarer having five binary inputs and five binary outputs. The binary values a 0 、a1 , a 2 , a 3 , a 4 are fed to five binary inputs of the squarer and binary values b are provided at five binary outputs 0 , b 1 , b 2 , b 3 , b 4 . Applicable are:

[0468] a 0 + a 4 = d 0 , (63)

[0469] a 3 = d 1 , (64)

[0470] a 1 + a 4 = d 2 , (65)

[0471] a 3 + a 4 = d 3 , (66)

[0472] a 2 = d 4 , (67)

[0473] where the symbol “+” again denotes addition modulo 2 (exclusive OR operation).

[0474] To implement a squarer in the Galois field GF(25) with the modulo polynomial m(x) = 1 + x 2 + x 5 , formulas (63) to (67) can be implemented, for example, by means of exclusive OR gates.

[0475] Described by way of example of the Galois field GF(25): How the cube of an element can be determined, where the element is illustrated by its polynomial representation.

[0476] If the polynomial

[0477] a(x) = a 0 + a 1 x 1 + a 2 x 2 + a 3 x 3 + a 4 x 4

[0478] cube of (a(x)) 3Determine the modulo polynomial \(m(x)=1 + x\) 2 + x 5 For finding the modulo, the following applies:

[0479] (a(x)) 3 mod \(m(x)=\)

[0480] (a 0 a 2 + a 0 a 4 + α 1 a 2 + a 1 a 3 + a 1 a 4 + a 2 a 3 + a 2 a 4 + a 3 + a 3 a 4 )·x 4 +

[0481] +(a 0 a 4 + a 1 + a 2 + a 2 a 3 + a 2 a 4 + a 3 + α 4 )·x 3 +

[0482] +(a 0 a 1 + a 0 a 2 + a 0 a 4 + a 1 a 2 + a 2 a 4 + a 3 a 4 + a 4 )·x 2 +

[0483] +(a 0 a 1 + a 0 a 3 + a 2 + a 3 + a 3 a 4 + a 4 )·x 1 +

[0484] +(a 0 +a 0 a 4 +a 1 a 2 +a 1 a 3 +a 2 a 3 )。

[0485] The cube powers of the elements forming in the Galois field GF(2 5 ) can correspondingly be implemented by means of a cube power former having five binary inputs and five binary outputs. The binary values a 0 , a 1 , a 2 , a 3 , a 4 are fed to the five binary inputs, and the binary values f 0 , f 1 , f 2 , f 3 , f 4 are provided at the five binary outputs. Applicable is:

[0486] f 0 = a 0 + a 0 a 4 + a 1 a 2 + a 1 a 3 + a 2 a 3 (68)

[0487] f 1 = a 0 a 1 + a 0 a 3 + a 2 + a 3 + a 3 a 4 + a 4 (69)

[0488] f 2 = a 0 a 1 + a 0 a 2 + a 0 a 4 + a 1 a 2 + a 2 a 4 + a 3 a4 +a 4 (70)

[0489] f 3 =a 0 a 4 +a 1 +a 2 +a 2 a 3 +a 2 a 4 +a 3 +a 4 (71)

[0490] f 4 =a 0 a 2 +a 0 a 4 +a 1 a 2 +a 1 a 3 +a 1 a 4 +a 2 a 3 +a 2 a 4 +a 3 +a 3 a 4 (72)

[0491] For example, in this example, in the Galois field GF(2 2 +x 5 ) with the modulo polynomial m(x)=1 + x 5 , a cubic power former can be realized only by implementing formulas (68) to (72).

[0492] Alternatively, the cubic power former can be implemented by a squarer and a downstream Galois field multiplier. Higher powers of the element a(x) can also be implemented in a corresponding manner using appropriate modules.

[0493] Below, the implementation of a constant multiplier in the Galois field GF(2 m ) is shown exemplarily for m = 5. The modulo polynomial is

[0494] m(x)=1 + x 2 +x 5 .

[0495] Let a ∈ GF(2 5 ) be an arbitrary element of the Galois field with the following polynomial representation

[0496] a(x)=a 0 +a 1x + a 2 x 2 + a 3 x 3 + a 4 x 4 。 (73)

[0497] For example, select α 9 as the constant to be multiplied. The polynomial representation of α 9 is given according to the table shown in Figure 13 and the table has

[0498] α 9 (x) = x + x 3 + x 4 (74).

[0499] As the multiplication result, we get

[0500] a(x)·α 9 (x) modulo (1 + x 2 + x 5 ) = b 0 + b 1 x + b 2 x 2 + b 3 x 3 + b 4 x 4 (75)

[0501] where

[0502] b 0 = a 1 + a 2 , (76)

[0503] b 1 = a 0 + a 2 + a 3 , (77)

[0504] b 2 = a 2 + a 3 + α 4 , (78)

[0505] b 3 = a 0 + a 3 + a 4 , (79)

[0506] b 4 = a 0 + a 1 + a 4 . (80)

[0507] Output value b 0 ,..., b 4 From the input value a 0 ,..., a 4 Derived from the relationships shown in formulas (76) to (80), such that the output value is determined from the input value by exclusive - or operation. Here, the symbol "+" represents addition modulo 2 (exclusive - or operation). Correspondingly, a constant multiplier can be implemented by means of exclusive - or gates.

[0508] Description of a byte error position signal former for forming a byte error position signal

[0509] Figure 1 Shows an exemplary circuit arrangement for determining a byte error position signal. Exemplarily, consider an error code for 2 - byte error correction with a codeword consisting of n bytes, where each byte has m bits respectively.

[0510] The circuit arrangement has N byte error position signal formers 10, 11,..., li,..., 1N - 1, which provide binary byte error position signals BPs via their respective 1 - bit - wide output terminals 0 , BPs 1 ,..., BPs i ,..., BPs N-1 .

[0511] The 4·m - bit - wide syndrome provided by the syndrome generator ( Figure 1 not shown in the figure)

[0512] s = s 1 , s 2 , s 3 , s 4

[0513] Is applied at the respective 4·m - bit - wide input terminals of the N byte error position signal formers 10, 11,..., 1i,..., 1N - 1. The syndrome consists of syndrome components s 1 , s 2 , s 3 , s 4 constituting it.

[0514] If all bytes are corrected in case of an error, then N = n applies. If less than n bytes are corrected in case of an error, then N < n applies. For example, it is feasible that: only data bytes are corrected in case of an error. In such an example, parity bytes may not be corrected.

[0515] The byte error position signal former 10 is designed, for example, as

[0516] - such that if

[0517]

[0518] it applies, the byte error position signal former outputs a byte error position signal BPs 0 = 1,

[0519] - such that if

[0520]

[0521] it applies, the byte error position signal former outputs a byte error position signal BPs 0 = 0.

[0522] The byte error position signal former 11 is designed, for example, as follows:

[0523] - such that if

[0524]

[0525] it applies, the byte error position signal former outputs a byte error position signal BPs 1 = 1,

[0526] - such that if

[0527]

[0528] it applies, the byte error position signal former outputs a byte error position signal BPs 1 = 0.

[0529] The byte error position signal former 1i is designed, for example, as follows:

[0530] - such that, if

[0531]

[0532] it applies, the byte error position signal former outputs a byte error position signal BPs i = 1,

[0533] - such that, if

[0534]

[0535] it applies, the byte error position signal former outputs a byte error position signal BPs i = 0.

[0536] The byte error position signal former 1N-1 is designed, for example, as

[0537] - such that, if

[0538]

[0539] applicable, the byte error position signal former outputs a byte error position signal BPs N-1 = 1,

[0540] - such that, if

[0541]

[0542] applicable, the byte error position signal former outputs a byte error position signal BPs N-1 = 0.

[0543] Here, the corresponding exponent of α modulo 2 m - 1 needs to be explained.

[0544] If there are 2-byte errors and the j-th byte and the k-th byte are in error, then for i = j and for i = k, the byte error position signal BPs i equals 1, while all the remaining byte error position signals BPs l equal 0, where l ≠ j, k, where applicable:

[0545] 0 ≤ i, j, k, l ≤ N - 1,

[0546] α 0 = 1 and

[0547] 1 is the identity element of the Galois field GF(2 m ).

[0548] According to Figure 2 the byte error position signal former

[0549] Figure 2 shows a circuit arrangement, which represents Figure 1 a possible design of the circuit arrangement shown in

[0550] Figure 1 The byte error position signal former 10 shown in

[0551] - a sub-circuit 210, having a 4·m-bit-wide input terminal for inputting error correction sub-s = s 1 、s 2 、s 3 、s 4 components s 1 、s 2 、s 3 and s 4 and three output terminals each of m-bit width,

[0552] - A constant multiplier 220, having an input terminal with a first m-bit width, an input terminal with a second m-bit width, and an output terminal with an m-bit width,

[0553] - A constant multiplier 230, having an input terminal with a first m-bit width, an input terminal with a second m-bit width, and an output terminal with an m-bit width,

[0554] - An exclusive-OR circuit 240, having three input terminals each with an m-bit width and an output terminal with an m-bit width, and

[0555] - A NOR circuit 250, having an input terminal with an m-bit width and a binary output terminal with a 1-bit width.

[0556] The sub-circuit 210 is designed such that when the sub-circuit inputs an error correction sub-s,

[0557] - outputs s at the first output terminal 1 ·s 4 +s 2 ·s 3 ,

[0558] - outputs at the second output terminal and

[0559] - outputs at the third output terminal

[0560] The first output terminal of the sub-circuit 210 is connected to the first input terminal of the constant multiplier 220. The constant α 0 = 1 is applied at the second input terminal of the constant multiplier 220, such that at the output terminal of the constant multiplier 220, there is provided

[0561] α 0 (s 1 ·s 4 +s 2 ·s 3 ) = s 1 ·s 4 +s 2 ·s 3 .

[0562] The output terminal of the constant multiplier 220 is connected to the first input terminal of the exclusive-OR circuit 240.

[0563] The second output terminal of the sub-circuit 210 is connected to the first input terminal of the constant multiplier 230. The constant α 2·0 = α 0 is applied at the second input terminal of the constant multiplier 230, such that at the output terminal of the constant multiplier 230, there is provided

[0564]

[0565] The output terminal of the constant multiplier 230 is connected to the second input terminal of the exclusive - OR circuit 240.

[0566] The third output terminal of the sub - circuit 210 is connected to the third input terminal of the exclusive - OR circuit 240.

[0567] For example, the exclusive - OR circuit 240 forms a bit - by - bit exclusive - OR operation on the values of each m - bit width applied at its three input terminals and provides a value at its m - bit width output terminal

[0568]

[0569] which is fed to the input terminal of the NOR circuit 250. The NOR circuit 250 at its output terminal

[0570] - If v 0 = 0 applies, it provides the binary value BP S0 = 1, and

[0571] - If v 0 ≠ 0 applies, it provides the binary value BP S0 = 0.

[0572] Figure 1 The byte error position signal former 11 shown in

[0573] - The sub - circuit 211, having a 4·m - bit width input terminal for the input error correction sub - s = s 1 、s 2 、s 3 、s 4 components s 1 、s 2 、s 3 、s 4 and three m - bit width output terminals,

[0574] - The constant multiplier 221, having a first m - bit width input terminal, a second m - bit width input terminal, and an m - bit width output terminal,

[0575] - The constant multiplier 231, having a first m - bit width input terminal, a second m - bit width input terminal, and an m - bit width output terminal,

[0576] - The exclusive - OR circuit 241, having three m - bit width input terminals and an m - bit width output terminal, and

[0577] - The NOR circuit 251, having an m - bit width input terminal and a 1 - bit width binary output terminal.

[0578] The sub - circuit 211 is designed such that when the sub - circuit receives the input error correction sub - s

[0579] - Output s at the first output terminal 1 ·s 4 +s 2 ·s 3 ,

[0580] - Output at the second output terminal and

[0581] - Output at the third output terminal

[0582] The first output terminal of sub - circuit 211 is connected to the first input terminal of constant multiplier 221. The constant α 1 is applied at the second input terminal of constant multiplier 221, such that at the output terminal of constant multiplier 221 there is provided

[0583] α 1 (s 1 ·s 4 +s 2 ·s 3 ).

[0584] The output terminal of constant multiplier 221 is connected to the first input terminal of exclusive - OR circuit 241.

[0585] The second output terminal of sub - circuit 211 is connected to the first input terminal of constant multiplier 231. The constant α 2 is applied at the second input terminal of constant multiplier 231, such that at the output terminal of constant multiplier 231 there is provided

[0586]

[0587] The output terminal of constant multiplier 231 is connected to the second input terminal of exclusive - OR circuit 241.

[0588] The third output terminal of sub - circuit 211 is connected to the third input terminal of exclusive - OR circuit 241.

[0589] For example, exclusive - OR circuit 241 forms a bit - by - bit exclusive - OR operation of the values of each m - bit width applied at the three input terminals of the exclusive - OR circuit, and provides at its m - bit - wide output terminal a value

[0590]

[0591] The value is fed to the input terminal of NOR circuit 251. NOR circuit 251 at its output terminal

[0592] - If v 1 = 0 applies, provides the binary value BP S1 = 1, and

[0593] - If v1 If ≠0 applies, a binary value BP is provided S1 = 0.

[0594] Figure 1 The byte error position signal former 1i shown in

[0595] - Sub - circuit 21i, having an input terminal with a width of 4m bits and three output terminals each with a width of m bits, the input terminal being for inputting the error correction sub - s = s 1 , s 2 , s 3 , s 4 components s 1 , s 2 , s 3 and s 4 .

[0596] - Constant multiplier 22i, having a first input terminal with a width of m bits, a second input terminal with a width of m bits, and an output terminal with a width of m bits,

[0597] - Constant multiplier 23i, having a first input terminal with a width of m bits, a second input terminal with a width of m bits, and an output terminal with a width of m bits,

[0598] - Exclusive - OR circuit 24i, having three input terminals each with a width of m bits and an output terminal with a width of m bits,

[0599] - NOR circuit 25i, having an input terminal with a width of m bits and an output terminal with a width of 1 - bit binary.

[0600] Sub - circuit 21i is designed such that when inputting the error correction sub - s

[0601] - outputs s 1 ·s 4 + s 2 ·s 3 at the first output terminal,

[0602] - outputs and

[0603] - at the third output terminal outputs

[0604] The first output terminal of sub - circuit 21i is connected to the first input terminal of constant multiplier 22i. The constant α i is applied at the second input terminal of constant multiplier 22i, such that at the output terminal of constant multiplier 22i,

[0605] α i (s 1 ·s 4 + s 2 ·s 3 ) is provided.

[0606] The output terminal of the constant multiplier 22i is connected to the first input terminal of the exclusive-OR circuit 24i.

[0607] The second output terminal of the sub-circuit 21i is connected to the first input terminal of the constant multiplier 23i. The constant α 2·i is applied at the second input terminal of the constant multiplier 23i such that at the output terminal of the constant multiplier 23i there is provided

[0608]

[0609] The output terminal of the constant multiplier 23i is connected to the second input terminal of the exclusive-OR circuit 24i.

[0610] The third output terminal of the sub-circuit 21i is connected to the third input terminal of the exclusive-OR circuit 24i.

[0611] For example, the exclusive-OR circuit 24i forms a bit-by-bit exclusive-OR operation of the values of width m applied at the three input terminals of the exclusive-OR circuit and provides at its output terminal of width m

[0612]

[0613] which is directed to the input terminal of the NOR circuit 25i. The NOR circuit 25i at its output terminal

[0614] - If v 1 = 0 applies, then the binary value BP Si = 1 is provided, and

[0615] - If v 1 ≠ 0 applies, then the binary value BP Si = 0 is provided.

[0616] Figure 1 The byte error position signal former lN-1 shown in

[0617] - A sub-circuit 21N-1 having an input terminal of width 4m and three output terminals each of width m, the input terminal being for inputting the components s = s 1 s 2 s 3 s 4 of the error correction sub s 1 s 2 s 3 and s 4 ,

[0618] - A constant multiplier 22N-1 having a first input terminal of width m, a second input terminal of width m and an output terminal of width m,

[0619] - Constant multiplier 23N-1, having an input terminal with a first m-bit width, an input terminal with a second m-bit width, and an output terminal with an m-bit width,

[0620] - Exclusive-OR circuit 24N-1, having three input terminals each with an m-bit width and an output terminal with an m-bit width,

[0621] - NOR circuit 25N-1, having an input terminal with an m-bit width and an output terminal with a 1-bit binary width.

[0622] The sub-circuit 21N-1 is designed such that when inputting the error correction sub-s

[0623] - Output s at the first output terminal 1 ·s 4 +s 2 ·s 3 ,

[0624] - Output at the second output terminal and

[0625] - Output at the third output terminal

[0626] The first output terminal of the sub-circuit 21N-1 is connected to the first input terminal of the constant multiplier 22N-1. The constant α N-l is applied at the second input terminal of the constant multiplier 22N-1, such that at the output terminal of the constant multiplier 22N-1, there is provided

[0627] α N-1 (s 1 ·s 4 +s 2 ·s 3 ).

[0628] The output terminal of the constant multiplier 22N-1 is connected to the first input terminal of the exclusive-OR circuit 24N-1.

[0629] The second output terminal of the sub-circuit 21N-1 is connected to the first input terminal of the constant multiplier 23N-1. The constant a 2·(N-l) is applied at the second input terminal of the constant multiplier 23N-1, such that at the output terminal of the constant multiplier 23N-1, there is provided

[0630]

[0631] The output terminal of the constant multiplier 23N-1 is connected to the second input terminal of the exclusive-OR circuit 24N-1.

[0632] The third output terminal of the sub-circuit 21N-1 is connected to the third input terminal of the exclusive-OR circuit 24N-1.

[0633] For example, the exclusive - OR circuit 24N - 1 forms a component - by - component exclusive - OR operation on the respective m - bit - wide values applied at the three input terminals of the exclusive - OR circuit and provides a value at its m - bit - wide output terminal.

[0634]

[0635] This value is directed to the input terminal of the NOR circuit 25N - 1. The NOR circuit 25N - 1 at its output terminal

[0636] - If v N-1 = 0 applies, it provides the binary value BP sN-1 = 1, and

[0637] - If v N-1 ≠ 0 applies, it provides the binary value BP sN-1 = 0.

[0638] Exemplary combinations of sub - circuits

[0639] Figure 2 The sub - circuits 210, 211,..., 21i,..., 21N - 1 in the combinations are functionally identical. Thus, the sub - circuits can be combined in the sub - circuit 31.

[0640] Figure 3 Figure shows such a sub - circuit 31 that combines the sub - circuits 210, 211,..., 21i,..., 21N - 1. Figure 3 The remaining circuit parts shown in Figure 2 are the same.

[0641] For example, the byte error position signal formers 10, 11,..., li,..., lN - 1 according to Figure 1 can use the common sub - circuit 31.

[0642] Exemplary implementation of the sub - circuit 31

[0643] Figure 4 Figure shows Figure 3 a possible implementation of the sub - circuit 31 shown in

[0644] The sub - circuit 31 has four input terminals each of m - bit width for inputting the components s 1 、s 2 、s 3 、s 4, the components form a syndrome s. In addition, there are four multipliers 41, 42, 44, and 47, two squarers 45 and 48, and three exclusive - OR circuits 43, 46, and 49. The multipliers each have two input terminals with an m - bit width and one output terminal with an m - bit width. The squarers each have one input terminal with an m - bit width and one output terminal with an m - bit width. The exclusive - OR circuits each have 2 input terminals with an m - bit width and 1 output terminal with an m - bit width.

[0645] The exclusive - OR circuits 43, 46, 49 respectively perform a component - by - component exclusive - OR operation on the m - component values applied at their respective input terminals. The multipliers perform multiplication in the Galois field GF(2 m ), and the squarers also square the operands applied at their input terminals in the Galois field GF(2 m ).

[0646] The input terminal of the leading component s 1 is connected to the first input terminal of the multiplier 41 and to the first input terminal of the multiplier 44.

[0647] The input terminal of the leading component s 2 is connected to the first input terminal of the multiplier 42, to the first input terminal of the multiplier 47, and to the input terminal of the squarer 45.

[0648] The input terminal of the leading component s 3 is connected to the second input terminal of the multiplier 42, to the second input terminal of the multiplier 44, and to the input terminal of the squarer 48.

[0649] The input terminal of the leading component s4 is connected to the second input terminal of the multiplier 41 and to the second input terminal of the multiplier 47.

[0650] The output terminal of the multiplier 41 is led to the first input terminal of the exclusive - OR circuit 43. The output terminal of the multiplier 42 is led to the second input terminal of the exclusive - OR circuit 43. A signal s 1 s 4 +s 2 s 3 is provided at the output terminal of the exclusive - OR circuit 43.

[0651] The output terminal of the multiplier 44 is led to the first input terminal of the exclusive - OR circuit 46. The output terminal of the squarer 45 is connected to the second input terminal of the exclusive - OR circuit 46. A signal

[0652] The output terminal of the multiplier 47 is led to the first input terminal of the exclusive - OR circuit 49. The output terminal of the squarer 48 is connected to the second input terminal of the exclusive - OR circuit 49. A signal

[0653] Byte error correction value for 2 - byte errors

[0654] Figure 5 An exemplary circuit is shown for forming a byte error correction value of a total of N bytes in the case of 2 - byte errors. The N bytes under consideration are numbered from 0 to N - 1.

[0655] Based on the current error correction syndrome s, byte position i, and byte error position signal BP Si , according to

[0656] a(i) cor = BPs i ·a(i)

[0657] to determine the byte error correction value a(i) of the i - th byte cor , where 0 ≤ i ≤ N - 1.

[0658] For example, the byte error correction values are determined for all N byte positions. For byte positions without errors, the byte error correction values are masked. For example, masking can be performed by multiplying the byte error position signal with a value of 0 by the byte error correction value.

[0659] If there are 2 - byte errors in byte positions i and j, then the i - th and j - th bytes can be corrected by performing an exclusive - OR operation component - by - component with the corresponding byte error correction values a(i) cor = a(i)≠0 or a(j) cor = a(j)≠0.

[0660] Bytes without errors are not corrected. To this end, the byte error correction value is set to 0 for the byte positions of bytes without errors (e.g., by multiplying the byte error correction value with 0 in the manner explained above), and then the correct bytes are exclusive - ORed component - by - component with the value 0. By exclusive - ORing with the value 0, the original value remains unchanged.

[0661] For the i - th erroneous byte, the byte error position signal BP Si = 1, and the following applies:

[0662] a(i) cor = BPs i ·a(i)= a(i).

[0663] For the j - th erroneous byte, the byte error position signal BP Sj = 1 and the following applies:

[0664] a(k) cor = BPs j ·a(j)= a(j).

[0665] For the k-th error-free byte, where k ≠ i, j, the byte error position signal BP Sk = 0 and applies:

[0666] a(k) cor = BPs k ·a(k) = 0.

[0667] If the k-th byte has no error, where k ≠ i, j, no correction is performed. This can be achieved in the manner shown in Figure 5 by XORing the k-th byte component-wise with the value 0, so that the value of the k-th byte remains unchanged. Thus, the byte error position signal masks the byte error correction value to 0, so that no correction is performed.

[0668] If, in the case of a 2-byte error, there is a first byte error in byte position j and a second byte error in byte position k, then the byte error correction values a(j) cor and a(k) cor are not equal to 0, while the byte error correction value a(i) cor is equal to 0 for i ≠ j, k respectively. Then, it also applies:

[0669] BP Sj = BP Sk = 1

[0670] and

[0671] BP Si = 0, where i ≠ j, k.

[0672] Figure 5 Including N byte error position signal formers 10, 11, …, 1i, …, 1N-1 to form the byte error position signals BP S0 、BP S1 、...、BP Si 、…、BP SN-1 ,The N byte error position signal formers respectively have an input end with a width of 4·m bits (or 4·m dimensions) and an output end with a width of 1 bit (or 1 dimension), where the input end is used to input the error correction sub s, and the output end is used to output the byte error position signals BP S0 、BP S1 、...、BP Si 、…、BP SN-1 。

[0673] Figure 5 There are also shown N byte error correction value formers 510, 511, …, 51i, …, 5N-l, and the N byte error correction value formers respectively have

[0674] A first input terminal with a width of -1, for inputting a byte error position signal,

[0675] A second input terminal with a width of -3·m, for inputting the components s 1 , s 2 , s 3 and

[0676] An output terminal with a width of -m, for outputting a byte error correction value a(0) at the corresponding byte position cor , a(l) cor , …, a(i) cor ,...,, a(N - 1) cor of one of them.

[0677] In addition, Figure 5 it includes N exclusive - OR circuits 520, 521,..., 52i,..., 52N - 1, and the exclusive - OR circuits respectively have

[0678] A first input terminal with a width of -m, for inputting the corresponding byte error correction value,

[0679] A second input terminal with a width of -m, for inputting the corresponding byte to be corrected, and

[0680] An output terminal with a width of -m, for outputting each corrected byte with a width of m.

[0681] Apply the current syndrome s at the 4·m - width input terminal of the byte error position signal former 10. The byte error position signal BP S0 is output at the 1 - width output terminal of the byte error position signal former 10, and this output terminal is connected to the first input terminal of the byte error correction value former 510.

[0682] The components s 1 , s 2 , s 3 of the syndrome s are applied at the 3·m - width second input terminal of the byte error correction value former 510. The byte error correction value former 510 provides the byte error correction value a(0) cor at its output terminal. The output terminal of the byte error correction value former 510 is connected to the first input terminal of the exclusive - OR circuit 520. The possibly erroneous byte value v′ 0 of the 0th byte is applied at the second input terminal of the exclusive - OR circuit 520. The exclusive - OR circuit 520 forms a bit - by - bit exclusive - OR operation of the possibly erroneous byte value v′ 0 and the byte error correction value a(0) cor , and outputs a value at the output terminal of the exclusive - OR circuit

[0683]

[0684] Byte error correction value a(0) cor

[0685] - If the 0th byte is correct and BP S0 = 0, it is equal to 0, and

[0686] - If the 0th byte is incorrect and BP S0 = 1, it is not equal to 0.

[0687] The current syndrome s is applied at the 4·m-bit-wide input of the byte error position signal former 11. The byte error position signal BP s1 is output at the 1-bit-wide output of the byte error position signal former 11, and this output is connected to the first input of the byte error correction value former 511.

[0688] The components s 1 、s 2 、s 3 of the syndrome s are applied at the 3·m-bit-wide second input of the byte error correction value former 511. The byte error correction value former 511 provides the byte error correction value a(l) cor . The output of the byte error correction value former 511 is connected to the first input of the exclusive-OR circuit 521. The possibly incorrect byte value v′1 of the 1st byte is applied at the second input of the exclusive-OR circuit 521. The exclusive-OR circuit 521 forms the component-by-component exclusive-OR operation of the possibly incorrect byte value v′1 and the byte error correction value a(1) cor and outputs the value

[0689]

[0690] byte error correction value a(1) cor

[0691] - If the 1st byte is correct and BP S1 = 0, it is equal to 0, and

[0692] - If the 1st byte is incorrect and BP S1 = 1, it is not equal to 0.

[0693] The current syndrome s is applied at the 4·m-bit-wide input of the byte error position signal former 1i. The byte error position signal BP Si is output at the 1-bit-wide output of the byte error position signal former 1i, and this output is connected to the first input of the byte error correction value former 51i.

[0694] Components s of the syndrome s 1 、s 2 、s 3 are applied at the second input of 3·m bit width of the byte error correction value former 51i. The byte error correction value former 51i provides a byte error correction value a(i) at its output cor 。The output of the byte error correction value former 51i is connected to the first input of the exclusive-OR circuit 52i. The possibly erroneous byte value v′ i of the i-th byte is applied at the second input of the exclusive-OR circuit 52i. The exclusive-OR circuit 52i forms the exclusive-OR operation of the possibly erroneous byte value v′ i and the byte error correction value a(i) cor component by component, and outputs a value at the output of the exclusive-OR circuit

[0695]

[0696] byte error correction value a(i) cor

[0697] -equals 0 if the i-th byte is correct and BP Si = 0, and

[0698] -is not equal to 0 if the i-th byte is erroneous and BP Si = 1.

[0699] The current syndrome s is applied at the 4·m bit width input of the byte error position signal former 1N-1. The byte error position signal BP SN-1 is output at the 1 bit width output of the byte error position signal former 1N-1, and this output is connected to the first input of the byte error correction value former 51N-1.

[0700] Components s of the syndrome s 1 、s 2 、s 3 are applied at the second input of 3·m bit width of the byte error correction value former 51N-1. The byte error correction value former 51N-1 provides a byte error correction value a(N-1) at its output cor 。The output of the byte error correction value former 51N-1 is connected to the first input of the exclusive-OR circuit 52N-1. The possibly erroneous byte value v′ N-1 of the (N-1)-th byte is applied at the second input of the exclusive-OR circuit 52N-1. The exclusive-OR circuit 52N-1 forms the exclusive-OR operation of the possibly erroneous byte value v′ N-1 and the byte error correction value a(N-1) cora bitwise exclusive OR operation, and outputs a value at the output of the exclusive OR circuit

[0701]

[0702] byte error correction value a(N - 1) cor

[0703] - If the (N - 1)-th byte is correct and BP SN-1 = 0, then it is equal to 0, and

[0704] - If the (N - 1)-th byte is incorrect and BP SN-1 = 1, then it is not equal to 0.

[0705] Therefore, byte corrector 530 may include byte error position signal former 10 and byte error correction value former 510, byte corrector 531 may include byte error position signal former 11 and byte error correction value former 511, byte corrector 53i may include byte error position signal former 1i and byte error correction value former 51i, and byte corrector 53N - 1 may include byte error position signal former 1N - 1 and byte error correction value former 51N - 1. Correspondingly, byte correctors 530, 531,..., 53i,..., 53N - 1 may be referred to as byte correctors for 2 - byte errors.

[0706] In the said example, the byte corrector for 2 - byte errors outputs the byte error correction values of the two byte positions with errors. For byte positions without errors, the byte error correction value is equal to 0.

[0707] For the incorrect byte position i, the following applies:

[0708] a(i) cor = a(i).

[0709] For the byte position j without errors, the following applies:

[0710] a(j) cor = 0,

[0711] Here, a(i) is the byte error correction value of the i - th byte.

[0712] For the sake of clear representation: The byte error position signal former forms corresponding byte error position signals according to the four components s 1 、s 2 、s 3 、s 4 of the error correction syndrome s, and the byte error correction value former forms the byte error correction value according to three components s 1 、s 2 、s3 Form a corresponding byte error correction value. In Figure 5 Two input lines are exemplarily shown, one input line for inputting components s 1 , s 2 , s 3 , s 4 , and the other input line for inputting components s 1 , s 2 , s 3 . The lines can also be combined for components s 1 , s 2 , s 3 .

[0713] For r = 0,..., N - 1, the byte error correction value former 51r is configured such that the byte error correction value former forms a byte error correction value at its m-bit wide output terminal connected to the m-bit wide first input terminal of the exclusive OR circuit 52r in the case of a 2-byte error, such that the following applies:

[0714]

[0715] If, in the case of a 2-byte error, the j-th and k-th bytes have errors, the byte error correction value former 51j outputs a byte error correction value

[0716]

[0717] and the byte error correction value former 51k outputs a byte error correction value

[0718]

[0719] For all other byte error correction value formers 51r, where r ≠ j, k and 0 ≤ r ≤ N - 1, the byte error correction value is equal to a(r) cor = 0.

[0720] Byte error correction value former

[0721] Figure 6 Shows a possible design of the byte error correction value former 51r, where r can take values from 0 to N - 1.

[0722] The byte error correction value former 5lr includes

[0723] - Two multipliers 61, 66, each having a first input terminal and a second input terminal with m-bit width and an output terminal with m-bit width,

[0724] - Two exclusive OR circuits 63, 64, each having a first input terminal with m-bit width, a second input terminal with m-bit width and an output terminal with m-bit width,

[0725] - A constant multiplier 67, having first and second inputs with an m-bit width and an output with an m-bit width, where a constant value α 2r is applied at the second input,

[0726] - A squarer 62, having an input with an m-bit width and an output with an m-bit width,

[0727] - A reciprocal circuit 65, having an input with an m-bit width and an output with an m-bit width, and

[0728] - An AND circuit 68, having a first input with a 1-bit width, a second input with an m-bit width, and an output with an m-bit width.

[0729] Component s 1 The value of is applied at the first input of multiplier 61 and component s 3 The value of is applied at the second input of multiplier 61. Multiplier 61 forms the value s m in the Galois field GF(2 1 ·s 3 and outputs the value s 1 ·s 3 at its output. The output of multiplier 61 is connected to the first input of XOR circuit 63.

[0730] The second input of XOR circuit 63 is connected to the output of squarer 62, at which the value of component s 2 is applied. Thus, squarer 62 outputs the value XOR circuit 63 forms the bitwise XOR operation of the values applied at its two inputs and outputs the value The output of XOR circuit 63 is connected to the first input of multiplier 66.

[0731] Component s 3 The value of is applied at the first input of XOR circuit 64. Component s 1 The value of is applied at the first input of constant multiplier 67, and the constant α 2r is applied at the second input of constant multiplier 67. Constant multiplier 67 implements the operation α m in the Galois field GF(2 2r ·s 1 . Constant multiplier can be implemented using XOR gates, for example.

[0732] Value s 3 +α 2r s 1 is provided at the output of XOR circuit 64 and is fed to the input of reciprocal 65. Reciprocal 65 provides the value at its output

[0733]

[0734] The output terminal of the reciprocal calculator 65 is connected to the first input terminal of the multiplier 66. Thereby, the multiplier 66 provides a value at its output terminal

[0735]

[0736] Here, a(r) is the byte error correction value of the r-th byte. The byte error position signal BP Sr is applied at the first input terminal of the AND circuit 68. The second input terminal of the AND circuit 68 is connected to the output terminal of the multiplier 66.

[0737] The AND circuit performs a bitwise AND operation on the m bits applied at its second input terminal and the byte error position signal BP Sr such that the AND circuit provides a value at its output terminal

[0738]

[0739] Byte error correction value former, alternative implementation

[0740] Figure 7 shows another possible design of the byte error correction value former 51r, which is described for the r-th byte as Figure 6 where r can take values from 0 to (N - 1).

[0741] Figure 7 The byte error correction value former 5lr shown in includes:

[0742] - Three multipliers 71, 75, 76, each having a first input terminal, a second input terminal, and an output terminal with a width of m bits,

[0743] - Two exclusive-OR circuits 72, 77, each having a first input terminal, a second input terminal, and an output terminal with a width of m bits,

[0744] - A constant multiplier 78, having a first input terminal, a second input terminal, and an output terminal with a width of m bits, where a constant value α 2r is applied at the second input terminal,

[0745] - A squarer 73, having an input terminal and an output terminal with a width of m bits,

[0746] - Two reciprocal calculators 74, 79, each having an input terminal and an output terminal with a width of m bits, and

[0747] - And a circuit 710, having a first input terminal with a 1-bit width, a second input terminal with an m-bit width, and an output terminal with an m-bit width.

[0748] Component s 1 The value of is applied at the first input terminal of the multiplier 71 and the component s 3 The value of is applied at the second input terminal of the multiplier 71. The multiplier 71 forms the value s in the Galois field GF(2 m ) and provides the value s 1 ·s 3 at its output terminal. The output terminal of the multiplier 71 is connected to the first input terminal of the exclusive-OR circuit 72. 1 ·s 3 . The output terminal of the multiplier 71 is connected to the first input terminal of the exclusive-OR circuit 72.

[0749] The second input terminal of the exclusive-OR circuit 72 is connected to the output terminal of the squarer 73, and the value of the component s 2 is applied at the input terminal of the squarer. Thus, the squarer 73 provides the value at its output terminal. The exclusive-OR circuit 72 forms the per-component exclusive-OR operation of the values applied at its two input terminals and provides the value at its output terminal. The output terminal of the exclusive-OR circuit 72 is connected to the input terminal of the reciprocal calculator 74. The reciprocal calculator 74 provides the value

[0750]

[0751] at its output terminal. The output terminal of the reciprocal calculator 74 is connected to the first input terminal of the multiplier 75, and the value of the component s 3 is applied at the second input terminal of the multiplier 75. In addition, the output terminal of the reciprocal calculator 74 is connected to the first input terminal of the multiplier 76, and the value of the component s 1 is applied at the second input terminal of the multiplier 76.

[0752] The multiplier 76 provides the value

[0753]

[0754] at its output terminal. The output terminal of the multiplier 76 is connected to the first input terminal of the constant multiplier 78. The value α 2r is applied at the second input terminal of the constant multiplier 78. The constant multiplier 78 provides the value

[0755]

[0756] The constant multiplier 78 multiplies the value applied at its first input terminal by the constant α m in the Galois field GF2 2rMultiply the values. The multiplication is performed by the corresponding exclusive OR operation on the bits applied at the first input. The constant α 2r is uniquely associated with the r-th byte.

[0757] The multiplier 75 provides a value at its output

[0758]

[0759] The output of the multiplier 75 is connected to the first input of the exclusive OR circuit 77.

[0760] The output of the constant multiplier 78 is connected to the second input of the exclusive OR circuit 77. The exclusive OR circuit 77 provides a value at its output

[0761]

[0762] The output of the exclusive OR circuit 77 is connected to the input of the reciprocal calculator 79.

[0763] The reciprocal calculator 79 provides a value at its output

[0764]

[0765] The output of the reciprocal calculator 79 is connected to the second input of the AND circuit 710.

[0766] The byte error position signal BP Sr is applied at the first input of the AND circuit 710. The AND circuit 710 performs a bitwise AND operation on the m bits applied at its second input and the byte error position signal BP Sr Accordingly, the AND circuit 710 provides a value at its output

[0767]

[0768] Figure 7 The part shown in, including the multipliers 71, 75, 76, the exclusive OR circuit 72 and the squarer 73, outputs values at the outputs of the multipliers 75 and 76

[0769]

[0770] and

[0771]

[0772] The said values are determined separately by the components s 1 , s 2 , s 3 and are independent of the byte position r. The said part of the circuit is for Figure 5All byte error correction value formers 510, 511, ..., 51N-1 shown in [figure] are the same. Thus, it is feasible to: set the circuit part only once and use the output signals of multipliers 71, 75, and 76 for all byte error correction value formers 510 to 51N-1. For different byte positions 0 to N-1, it is then only necessary to implement the remaining part 711 shown in [figure] separately, which includes an exclusive-OR circuit 77, a constant multiplier 78, a reciprocal calculator 79, and an AND circuit 710. Figure 7 The remaining part 711 shown in [figure], which includes an exclusive-OR circuit 77, a constant multiplier 78, a reciprocal calculator 79, and an AND circuit 710.

[0773] One option is to implement the byte error correction value former for correctable byte positions using at most three multiplications, for example, the byte error correction value former for all correctable byte positions or for a part of the correctable byte positions. Here, these three multiplications can be implemented using three multipliers. Another option is to perform further multiplications with constants, in particular, by means of a constant multiplier.

[0774] Correction of 1-byte and 2-byte errors Figure 8

[0775] Figure 8 An exemplary circuit for correcting 1-byte and 2-byte errors is shown, where the circuit can be used to determine the byte error position signal for a 2-byte error and correct the 2-byte error.

[0776] For example, Figure 8 the circuit shown in [figure] is designed such that

[0777] - if there is a 2-byte error, correct the 2-byte error,

[0778] - if there is a 1-byte error, correct the 1-byte error, and

[0779] - if there is no error, no correction is performed.

[0780] For this purpose, Figure 8 including

[0781] - N byte error correction value formers 810, ..., 81i, ..., 81N-1 for correcting 1-byte errors, each having an input terminal with a 2·m bit width for input components s 1 , s 2 and an output terminal with an m bit width for outputting a byte error correction value with an m bit width,

[0782] - N byte correctors 530, ..., 53i, ..., 53N-1 for correcting 2-byte errors, each having input terminals for input components s 1 , s 2 , s 3 , s4 a 4·m-bit wide input terminal and an m-bit wide output terminal for outputting a byte error correction value of m-bit width, as Figure 5 described in

[0783] - N multipliers 820, …, 82i, ..., 82N-1, each having

[0784] - an m-bit wide first input terminal (0 input terminal),

[0785] - an m-bit wide second input terminal (1 input terminal),

[0786] - a 1-bit wide control input terminal at which a binary control signal st can be applied, and

[0787] - an m-bit wide output terminal,

[0788] - N AND circuits 830, ..., 83i, ..., 83N-1, each having a 1-bit wide first input terminal for inputting a binary error signal E, an m-bit wide second input terminal, and an m-bit wide output terminal, and

[0789] - N exclusive-OR circuits 840, ..., 84i, …, 84N-1, each having an m-bit wide first input terminal, an m-bit wide second input terminal, and an m-bit wide output terminal.

[0790] Line 85 guides component s 1 s 2 and is connected to the corresponding input terminals of byte error correction value formers 810, ..., 81i, ..., 81N-1.

[0791] Line 86 guides component s 1 s 2 s 3 s 4 and is connected to the corresponding input terminals of byte correctors 530, ..., 53i, ..., 53N-1.

[0792] In the case of a 1-byte error occurring in byte position 0, byte error correction value former 810 provides, at its output terminal, the correct byte error correction value for the 0th byte v′ 0 of the error. This applies correspondingly to the other byte error correction value formers. Thus, in the case of a 1-byte error occurring in byte position i, byte error correction value former 81i provides, at its output terminal, the correct byte error correction value for the ith byte v′ i of the error. In the case of a 1-byte error occurring in byte position (N-1), byte error correction value former 81N-1 provides, at its output terminal, the correct byte error correction value for the (N-1)th byte v′ N-1The correct byte error correction value.

[0793] Combined with Figure 10 Explain possible implementations of a byte error correction value former for correcting 1-byte errors.

[0794] Regarding possible implementations of byte correctors 530 to 53N-1, for example, with reference to the byte error position signal former combined with Figure 2 described and the byte error correction value former combined with Figure 6 and Figure 7 described.

[0795] The output of the byte error correction value former 810 is connected to the first input of the multiplier 820. The output of the byte corrector 530 is connected to the second input of the multiplier 820. If the value of the control signal st is equal to 0, the multiplier 820 connects its 0 input (first input) to its output. If the value of the control signal st is equal to 1, the multiplier 820 connects its 1 input (second input) to its output.

[0796] The binary error signal E is applied at the first input of the AND circuit 830. The output of the multiplier 820 is connected to the second input of the AND circuit 830. The output of the AND circuit 830 is connected to the first input of the exclusive-OR circuit 840. The possibly incorrect byte v′ 0 is applied at the second input of the exclusive-OR circuit 840. The exclusive-OR circuit 840 provides the corrected byte value at its output

[0797] The AND circuit 830 can perform a bit-by-bit AND operation on the m-bit value applied at its second input and the error signal E. If the error signal E = 0, the AND circuit 830 outputs an m-component value of 0. If the error signal E = 1, the AND circuit 830 outputs the value applied at its second input.

[0798] The described implementation is correspondingly applicable to the remaining byte positions.

[0799] The output of the byte error correction value former 81i is connected to the first input of the multiplier 82i. The output of the byte error correction value former 53i is connected to the second input of the multiplier 82i. If the value of the control signal st is equal to 0, the multiplier 82i connects its 0 input (first input) to its output. If the value of the control signal st is equal to 1, the multiplier 82i connects its 1 input (second input) to its output.

[0800] The binary error signal E is applied at the first input of the AND circuit 83i. The output of the multiplier 82i is connected to the second input of the AND circuit 83i. The output of the AND circuit 83i is connected to the first input of the XOR circuit 84i. The possibly erroneous byte v′ i is applied at the second input of the XOR circuit 84i. The XOR circuit 84i provides the corrected byte value at its output

[0801] The AND circuit 83i can perform a bit-by-bit AND operation of the m-bit value applied at its second input with the error signal E. If the error signal E = 0, the AND circuit 83i outputs an m-component value of 0. If the error signal E = 1, the AND circuit 83i outputs the value applied at its second input.

[0802] The output of the byte error correction value former 81N-1 is connected to the first input of the multiplier 82N-1. The output of the byte error correction value former 53N-1 is connected to the second input of the multiplier 82N-1. If the value of the control signal st is equal to 0, the multiplier 82N-1 connects its 0 input (first input) to its output. If the value of the control signal st is equal to 1, the multiplier 82N-1 connects its 1 input (second input) to its output.

[0803] The binary error signal E is applied at the first input of the AND circuit 83N-1. The output of the multiplier 82N-1 is connected to the second input of the AND circuit 83N-1. The output of the AND circuit 83N-1 is connected to the first input of the XOR circuit 84N-1. The possibly erroneous byte v′ N-1 is applied at the second input of the XOR circuit 84N-1. The XOR circuit 84N-1 provides the corrected byte value at its output

[0804] The AND circuit 83N-1 can perform a bit-by-bit AND operation of the m-bit value applied at its second input with the error signal E. If the error signal E = 0, the AND circuit 83N-1 outputs an m-component value of 0. If the error signal E = 1, the AND circuit 83N-1 outputs the value applied at its second input.

[0805] The error signal E

[0806] - takes the value 1 if a 1-byte error or a 2-byte error occurs, or

[0807] - takes the value 0 if no error occurs.

[0808] The control signal st

[0809] - takes the value 0 if a 1-byte error occurs, and

[0810] - If a 2-byte error occurs, the value 1 is taken.

[0811] A circuit for correcting more than two byte errors

[0812] Figure 9 Shows a circuit for correcting 1-byte errors, 2-byte errors up to t-byte errors. Figure 8 The components described in can be used in the circuit accordingly.

[0813] Figure 9 The circuit shown in implements:

[0814] - If a 1-byte error exists, correct the 1-byte error,

[0815] - If a 2-byte error exists, correct the 2-byte error,

[0816] -

[0817] …

[0818] - If a t-byte error exists, correct the t-byte error, and

[0819] - If no error exists, no correction is performed.

[0820] The following situation is described by way of example: Using t-byte error correction and (t + 1)-byte error identification code, where in particular t>2 applies.

[0821] According to Figure 9 The circuit of includes

[0822] - N byte error correction value formers 810 to 81N-1 according to Figure 8 of,

[0823] - N byte correctors 530 to 53N-1 according to Figure 8 (also as described in ), up to Figure 5 of

[0824] - N byte error correction value formers 910,..., 91i,..., 91N-1 for correcting t-byte errors, each having an input terminal for input components s 1 s 2 s 2t ..., s

[0825] - N multipliers 920,..., 92i,..., 92N-l, each having

[0826] - A first input terminal (0 input terminal) with m-bit width,

[0827] - A second input terminal (1 input terminal) with an m-bit width,

[0828] - Up to the t-th input terminal ((t - 1) input terminal) with an m-bit width

[0829] - A control input terminal, where a control signal st is applied, and the control signal can take t different values, and

[0830] - An output terminal with an m-bit width.

[0831] - N AND circuits 930, …, 93i, …, 93N - 1, each having a 1-bit width first input terminal, an m-bit width second input terminal, and an m-bit width output terminal for inputting a binary error signal E, and

[0832] - N exclusive-OR circuits 940, …, 94i, …, 94N - 1, each having an m-bit width first input terminal, an m-bit width second input terminal, and an m-bit width output terminal.

[0833] When the control signal st has a value of 0, the 0 input terminal of one of the multipliers 920 to 92N - 1 is connected to its output terminal. Correspondingly, the connection between one of the input terminals 0 to (t - 1) and the output terminal can be established by setting the corresponding control signal st to a value between 0 and (t - 1). For example, if st = (t - 1) = 3 is applicable, the third input terminal (2 input terminal) of the multiplier is connected to its output terminal.

[0834] Line 95 guides component s 1 、s 2 and is connected to the corresponding input terminals of the byte error correction value formers 810, …, 81i, …, 81N - 1.

[0835] Line 96 guides component s 1 、s 2 、s 3 、s 4 and is connected to the corresponding input terminals of the byte correctors 530, …, 53i, …, 53N - l.

[0836] Finally, line 97 is shown, through which component s 1 、s 2 、…、s 2t is guided to the corresponding input terminals of the byte error correction value formers 910, …, 91i, …, 91N - 1.

[0837] In the case of a 1-byte error occurring in byte position 0, the byte error correction value former 810 provides the 0-th byte v′ for the error at its output terminal 0The correct byte error correction value. This correspondingly applies to other byte error correction value formers. Thus, in the case of a 1-byte error occurring at byte position i, the byte error correction value former 81i provides at its output the correct byte v′ for the error at the i-th byte i The correct byte error correction value. In the case of a 1-byte error occurring at byte position (N - 1), the byte error correction value former 81N-1 provides at its output the correct byte v′ for the error at the (N - 1)-th byte N-1 The correct byte error correction value.

[0838] In the case of a 2-byte error, the byte corrector 530 provides at its output the correct byte v′ for the error at the 0-th byte 0 The correct byte error correction value. This correspondingly applies to other byte error correction value formers. Thus, in the case of a 2-byte error, the byte error correction value former 53i provides at its output the correct byte v′ for the error at the i-th byte i The correct byte error correction value. In the case of a 2-byte error, the byte error correction value former 53N-1 provides at its output the correct byte v′ for the error at the (N - 1)-th byte N-1 The correct byte error correction value.

[0839] In the case of a t-byte error, the byte error correction value former 910 provides at its output the correct byte v′ for the error at the 0-th byte 0 The correct byte error correction value. This correspondingly applies to other byte error correction value formers. Thus, in the case of a t-byte error, the byte error correction value former 91i provides at its output the correct byte v′ for the error at the i-th byte i The correct byte error correction value. In the case of a t-byte error, the byte error correction value former 91N-1 provides at its output the correct byte v′ for the error at the (N - 1)-th byte N-1 The correct byte error correction value.

[0840] For bytes without errors, the byte error correction values associated with the byte positions are masked by the value 0 respectively.

[0841] The output of the byte error correction value former 810 is connected to the first input terminal (0 input terminal) of the multiplier 920. The output of the byte corrector 530 is connected to the second input terminal (1 input terminal) of the multiplier 920. Correspondingly, the output of the byte error correction value former 910 is connected to the t-th input terminal ((t - 1) input terminal) of the multiplier 920.

[0842] The binary error signal E is applied at the first input of the AND circuit 930. The output of the multiplier 920 is connected to the second input of the AND circuit 930. The output of the AND circuit 930 is connected to the first input of the XOR circuit 940. The possibly erroneous byte v′ 0 is applied at the second input of the XOR circuit 940. The XOR circuit 940 provides the corrected byte value at its output

[0843] The AND circuit 930 can perform a bit-by-bit AND operation of the m-bit value applied at its second input and the error signal E. If the error signal E = 0, the AND circuit 930 outputs the m-component value 0. If the error signal E = 1, the AND circuit 930 outputs the value applied at its second input.

[0844] The described implementation is correspondingly applicable to the remaining byte positions.

[0845] The output of the byte error correction value former 8li is connected to the first input (0 input) of the multiplier 92i. The output of the byte error correction value former 53i is connected to the second input (1 input) of the multiplier 92i. Correspondingly, the output of the byte error correction value former 91i is connected to the t-th input ((t - 1) input) of the multiplier 92i.

[0846] The binary error signal E is applied at the first input of the AND circuit 93i. The output of the multiplier 92i is connected to the second input of the AND circuit 93i. The output of the AND circuit 93i is connected to the first input of the XOR circuit 94i. The possibly erroneous byte v′ i is applied at the second input of the XOR circuit 94i. The XOR circuit 94i provides the corrected byte value at its output

[0847] The AND circuit 93i can perform: a bit-by-bit AND operation of the m-bit value applied at its second input and the error signal E. If the error signal E = 0, the AND circuit 93i outputs the m-component value 0. If the error signal E = 1, the AND circuit 93i outputs the value applied at its second input.

[0848] The output of the byte error correction value former 81N - 1 is connected to the first input (0 input) of the multiplier 92N - 1. The output of the byte error correction value former 53N - 1 is connected to the second input (1 input) of the multiplier 92N - 1. Correspondingly, the output of the byte error correction value former 91N - 1 is connected to the t-th input ((t - 1) input) of the multiplier 92N - 1.

[0849] The binary error signal E is applied at the first input of the AND circuit 93N-1. The output of the multiplier 92N-1 is connected to the second input of the AND circuit 93N-1. The output of the AND circuit 93N-1 is connected to the first input of the XOR circuit 94N-1. The possibly incorrect byte v′ N-1 is applied at the second input of the XOR circuit 94N-1. The XOR circuit 94N-1 provides a corrected byte value at its output

[0850] The AND circuit 93N-1 is capable of performing: a bit-by-bit AND operation of the m-bit value applied at its second input with the error signal E. If the error signal E = 0, the AND circuit 93N-1 outputs an m-bit value of 0. If the error signal E = 1, the AND circuit 93N-1 outputs the value applied at its second input.

[0851] The error signal E

[0852] - takes the value 1 if a 1-byte error or a 2-byte error, …, or a t-byte error occurs, or

[0853] - takes the value 0 if no error occurs.

[0854] The control signal st

[0855] - takes the value 0 if a 1-byte error occurs,

[0856] - takes the value 1 if a 2-byte error occurs,

[0857] - and so on,

[0858] - takes the value (t - 1) if a t-byte error occurs.

[0859] Byte error corrector for 1-byte error

[0860] Figure 10 Shows an exemplary circuit of the byte error correction value former 81i for the i-th byte, as explained for example with reference to Figure 8 Explanation.

[0861] The byte error correction value former 81i includes

[0862] - a constant multiplier 101, which has

[0863] - a first input with an m-bit width,

[0864] - a second input with an m-bit width, to which the constant value α i is applied at the second output, and

[0865] - an output with an m-bit width,

[0866] - An exclusive - OR circuit 102, having a first input terminal with an m - bit width, a second input terminal with an m - bit width, and an output terminal with an m - bit width,

[0867] - A NOR circuit 103, having an input terminal with an m - bit width and an output terminal with a 1 - bit width,

[0868] - An AND circuit 104, having a first input terminal with a 1 - bit width, a second input terminal with an m - bit width, and an output terminal with an m - bit width.

[0869] In addition, Figure 10 is shown Figure 8 (and Figure 5 ) the multiplier 82i and the byte error correction value former 53i in.

[0870] The constant multiplier 101, the exclusive - OR circuit 102, and the NOR circuit 103 form a byte error correction value former 105 and are used, for example, to form a byte error position signal The byte error position signal indicates whether there is a 1 - byte error in the i - th byte position.

[0871] If a 1 - byte error occurs in byte position i, an m - dimensional byte error correction value a(i) is provided at the output terminal of the AND circuit 104 cor . If a 1 - byte error occurs in a byte position j different from i, the byte error position signal BP Si = 0, and thus a value of 0 is also applied at the output terminal of the AND circuit 104.

[0872] Component s 1 is applied at the first input terminal of the constant multiplier 101, and the constant α i is applied at the second input terminal of the constant multiplier 101. The output terminal of the constant multiplier 101 is connected to the first input terminal of the exclusive - OR circuit 102. Component s 2 is applied at the second input terminal of the exclusive - OR circuit 102. The output terminal of the exclusive - OR circuit 102 is connected to the input terminal of the NOR circuit 103. The output terminal of the NOR circuit 103 is connected to the first input terminal of the AND circuit 104. Component s 1 is applied at the second input terminal of the AND circuit 104. The output terminal of the AND circuit 104 is connected to the first input terminal of the multiplier 82i.

[0873] The second input terminal of the multiplier 82i is connected to the output terminal of the byte error correction value former 53i.

[0874] Therefore, a byte error correction value for a 1 - byte error is provided at the first input terminal of the multiplier 82i, and a byte error correction value for a 2 - byte error is provided at the second input terminal of the multiplier 82i.

[0875] Correspondingly, the control signal st for the multiplier 82i is

[0876] - if there is a 1-byte error, then equal to 0, so that the first input (0 input) of multiplier 82i is connected to its output, or

[0877] - if there is a 2-byte error, equal to 1, so that the second input terminal (1 input terminal) of the multiplier 82i is connected to its output terminal.

[0878] If there is no error, the value of the control signal st is arbitrary. For example, the value can be set to 0, as described exemplarily below.

[0879] If there is no error, the value of the error signal E is equal to 0. This has been combined with Figure 8 The AND circuit 83i connected downstream, which logically ANDs the signal at the output of the multiplier 82i component by component with the error signal E, ensures that, in the case of error signal E=0 (i.e., when no error is present), the value 0 is provided at the output of the AND circuit 83i, more precisely independently of the signal at the output of the multiplier 82i. Therefore, no correction is performed on the i-th byte.

[0880] Circuit for determining error signals

[0881] Figure 11 For example, in Figure 8 An exemplary circuit for determining the error signal E is used in the circuit shown in .

[0882] Figure 11 The device shown in the

[0883] a multiplier 111 having a first input terminal of m bits width, a second input terminal of m bits width and an output terminal of m bits width,

[0884] - an XOR circuit 113 having a first input terminal with a width of m bits, a second input terminal with a width of m bits and an output terminal with a width of m bits,

[0885] - a squarer 112 having an input terminal with a width of m bits and an output terminal with a width of m bits,

[0886] - an OR circuit 114 (OR circuit) having an input terminal with a width of m bits and an output terminal with a width of 1 bit,

[0887] -OR circuit 116, having an m-bit wide input and a 1-bit wide output, and

[0888] An OR circuit 115 having a first binary input, a second binary input and a binary output.

[0889] Quantity1 The value is applied at the first input terminal of multiplier 111. Component s 3 The value is applied at the second input terminal of multiplier 111. The output terminal of multiplier 111 is connected to the first input terminal of exclusive - OR circuit 113.

[0890] Component s 1 is also applied at the input terminal of OR circuit 116. The output terminal of OR circuit 116 is connected to the second input terminal of OR circuit 115.

[0891] Component s 2 is applied at the input terminal of squarer 112. The output terminal of squarer 112 is connected to the second input terminal of exclusive - OR circuit 113.

[0892] The output terminal of exclusive - OR circuit 113 is connected to the input terminal of OR circuit 114, and the output terminal of OR circuit 114 is connected to the first input terminal of OR circuit 115.

[0893] The control signal st is provided at the output terminal of OR circuit 114, and the error signal E is provided at the output terminal of OR circuit 115.

[0894] If the following conditions are applicable, the control signal st takes the value 0:

[0895]

[0896] Correspondingly, if the following conditions are applicable, the control signal st takes the value 1:

[0897]

[0898] If the control signal st is equal to 0 and if component s 1 has a value equal to 0, the error signal E takes the value 0. In this case, neither a 1 - byte error nor a 2 - byte error exists.

[0899] If the value of the control signal st is equal to 1, 2 - byte correction is performed in the circuit according to Figure 8 using byte correctors 530 to 53N - 1.

[0900] If the value of the control signal st is equal to 0, first 1 - byte correction is performed in the circuit according to Figure 8 using byte error correction value formers 810 to 81N - 1. If the error signal E is also equal to 0, such that neither a 1 - byte error nor a 2 - byte error exists, all AND circuits 830 to 83N - 1 output a value of 0, such that no correction is made to bytes v′ 0 to v′ N-1 is made.

[0901] If a 3-byte error is detected, error correction can be interrupted, for example. This interruption of error correction can be performed at the system level.

[0902] A circuit for detecting a 3-byte error

[0903] Figure 12 An exemplary circuit for detecting a 3-byte error is shown. To this end, the circuit includes

[0904] - Four multipliers 121, 122, 123, 124, each having a first input terminal with a width of m bits, a second input terminal with a width of m bits, and an output terminal with a width of m bits,

[0905] - Three squarers 125, 126, 127, each having an input terminal with a width of m bits and an output terminal with a width of m bits,

[0906] - Three exclusive-OR circuits 128, 129, 1210, each having a first input terminal with a width of m bits, a second input terminal with a width of m bits, and an output terminal with a width of m bits, and

[0907] - An OR circuit 1211, having an input terminal with a width of m bits and a binary output terminal, wherein the OR circuit 1211 performs a bit-by-bit OR operation on the m bits applied at its input terminal.

[0908] Component s 1 The value is applied to the first input terminal of the multiplier 121 and the second input terminal of the multiplier 123.

[0909] Component s 2 The value is applied to the input terminal of the squarer 126.

[0910] Component s 3 The value is applied to the input terminal of the squarer 125 and the second input terminal of the multiplier 122.

[0911] Component s 4 The value is applied to the input terminal of the squarer 127.

[0912] Component s 5 The value is applied to the second input terminal of the multiplier 121 and the first input terminal of the multiplier 124.

[0913] The output terminal of the multiplier 121 is connected to the first input terminal of the exclusive-OR circuit 128. The output terminal of the squarer 125 is connected to the second input terminal of the exclusive-OR circuit 128. The output terminal of the exclusive-OR circuit 128 is connected to the first input terminal of the multiplier 122. The output terminal of the multiplier 122 is connected to the first input terminal of the exclusive-OR circuit 129.

[0914] The output terminal of squarer 127 is connected to the first input terminal of multiplier 123. The output terminal of multiplier 123 is connected to the first input terminal of exclusive-OR circuit 1210.

[0915] The output terminal of squarer 126 is connected to the second input terminal of multiplier 124, and the output terminal of multiplier 124 is connected to the second input terminal of exclusive-OR circuit 1210. The output terminal of exclusive-OR circuit 1210 is connected to the second input terminal of exclusive-OR circuit 129. The output terminal of exclusive-OR circuit 129 is connected to the input terminal of OR circuit 1211, and signal Err3 is provided at the output terminal of OR circuit 1211. According to this signal, a 3-byte error can be determined.

[0916] If the following conditions are applicable, signal Err3 takes the value 1:

[0917]

[0918] Correspondingly, if the following conditions are applicable, signal Err3 takes the value 0:

[0919]

[0920] Alternative determination of byte error correction value

[0921] An alternative effective variant for determining the byte error correction value is described below.

[0922] For example, consider the correction of a 2-byte error.

[0923] The byte error correction value a(k) for the k-th byte position is determined according to formula (50) as

[0924]

[0925] Therefore, for each byte position k to be corrected, in the Galois field GF(2 m ) the value determined from the syndrome components s 1 , s 2 , s 3 is

[0926]

[0927] divided by

[0928] s 3 + α 2k s 1 .

[0929] The divisor is related to the byte position k and is different for each byte position. Therefore, a separate division is required for each byte position.

[0930] For example, the division can be implemented by first using a reciprocal calculator in the Galois field GF(2 m ) to form the reciprocal value of the divisor

[0931]

[0932] and then using a multiplier to multiply the reciprocal value by the term .

[0933] Here, for example, a reciprocal calculator and a multiplier are required for each byte position to be corrected.

[0934] By first determining

[0935]

[0936] in place of α(k), the implementation workload can be reduced. The reciprocal is obtained by taking the reciprocal

[0937]

[0938] Here, the terms

[0939]

[0940] and the terms

[0941]

[0942] can be formed centrally and provided for all byte positions to be corrected.

[0943] For the k-th byte position, the terms

[0944]

[0945] can be multiplied by α 2k . This multiplication for each byte position is a multiplication by a constant corresponding to that byte position.

[0946] With a reciprocal calculator in the Galois field GF(2 m ), the reciprocal value of

[0947]

[0948] is determined in parallel or at least partially in parallel or at least partially simultaneously (i.e., with partial temporal overlap). Here, k takes on all values of the byte positions to be corrected when a byte error occurs. The disadvantage here is that for each byte position to be corrected, a reciprocal calculator in the Galois field GF(2m) is required in the case of (at least partial) parallel processing.

[0949] Next, an example will be given to explain based on the correction of 2-byte errors: how to effectively determine the byte error correction value.

[0950] Here, it is advantageous that the coefficients of the locator polynomial are symmetric functions of the incorrect byte positions and can be determined as functions of the components of the error syndrome by solving a system of linear equations.

[0951] In the case of 2-byte errors in byte positions α i and α j the coefficients of the locator polynomial

[0952] L 2 (x) = x 2 + x·σ 1 + σ 2 = (x + α i )(x + α j )

[0953] are determined as

[0954] σ 1 = α i + α j and σ 2 = α i ·α j .

[0955] Here, σ 1 and σ 2 are symmetric functions of byte positions α i and α j where σ 1 is the coefficient of the linear term x of the locator polynomial L 2 (x) and is the sum of α i and α j .

[0956] There is the following relationship between the coefficients σ 1 and σ 2 of the locator polynomial and the syndrome components s 1 , s 2 , s 3 , s 4 which can be obtained by substituting the values

[0957]

[0958] This can be achieved by substituting the values

[0959] s 1 = a + b,

[0960] s 2 = α i a + α j b,

[0961] s 3 = α 2i a + α 2j b,

[0962] s 4 = α 3i a + α 3j b,

[0963] σ 1 = α i + α j ,

[0964] σ 2 = α i ·α j

[0965] to verify.

[0966] Equation (81) is a system of linear equations that allows: the coefficients σ 1 and σ 2 to be determined as functions of the syndrome components s 1 , s 2 , s 3 , s 4 as

[0967]

[0968] and

[0969]

[0970] For example, in the case of a 2-byte error, the byte error correction value can advantageously be determined according to the coefficients σ 2 of the linear part of the locator polynomial L 1 (x) such that a simple implementation for determining the byte error correction value is obtained.

[0971] For the byte positions where correction may be considered, the potential byte error correction values for the erroneous byte positions and the error-free byte positions are determined. If there is a 2-byte error and one byte position is in error, the byte position can be corrected with the aid of the byte error correction value. If the byte position is error-free, the byte position correction value can take any value for that byte position.

[0972] Here, it should be noted that the term "error" assumes that an error is recognized for that byte position. In addition, there is the possibility that there are errors that are not recognized and thus not corrected. In this context, this situation is not covered by the term "error". When currently referring to "error-free", the corresponding applies.

[0973] Using the locator polynomial L 2(x), a byte error position signal for determining the byte positions of errors and error - free bytes. Here, when L 2 (α i ) = 0 and the byte has an error, the byte error position signal of byte position α i takes a first value, and when L 2 (α i ) ≠ 0 and the byte has no error, this byte error position signal takes a second value different from the first value.

[0974] If the byte at byte position α i has an error and thus L 2 (α i ) = 0 applies, the potential byte error correction value determined for the byte position is used to correct the byte identified as having an error. If the byte at byte position α i has no error and thus L 2 (α i ) ≠ 0 applies, the potential byte error correction value determined for this byte position is not used for correction.

[0975] Using the byte error position signal determined for the corresponding byte position, it is possible to determine whether the potential byte error value determined for the byte position is used for correction.

[0976] Exemplarily, a Reed - Solomon code in the Galois field GF(2 m ) with four syndrome components s 1 , s 2 , s 3 , s 4 is used.

[0977] As in formulas (3) and (4), first, an H matrix is used. The first row of the H matrix is α 0 , α 0 ,..., α 0 . The H matrix HByte used in formulas (3) and (4) has 3 rows and 5 columns.

[0978] The H matrix H exemplarily used in this section of the Reed - Solomon code has 4 rows:

[0979]

[0980] The H matrix H according to formula (82) is obtained from the H matrix HByte according to formula (4) by deleting the last row.

[0981] If there is a 2 - byte error with byte error values a and b at byte positions i and j, the syndrome components s 1 , s 2 , s3 , s 4 is obtained according to formula (6) as

[0982] s 1 = a + b

[0983] s 2 = α i a + α j b

[0984] s 3 = α 2i α + α 2j b

[0985] s 4 = α 3i a + α 3j b (83)

[0986] Locator polynomial L 2 (x), which is in the

[0987] L 2 (x) = x 2 + σ 1 x + σ 2 (84)

[0988] in the form of, where

[0989]

[0990] For example, it is determined in the following way: Divide the left side of formula (84) by such that

[0991]

[0992] is applicable.

[0993] If there is a 2 - byte error with byte error values a and b at byte positions i and j, then the syndrome components s 1 to s 4 are determined according to formula (83). With the help of the syndrome components s 1 to s4 the following is applicable:

[0994] s 1 · s 4 + s 2 · s 3 = (α + b)(α 3i a + α 3j b)+(α i a + α j b)(α 2i a + α 2j b)=

[0995] = α 3i a 2 + α 3i ab + α 3j ab + α 3j b 2 +

[0996] + α 3i a 2 + α 2i α j ab + α i α 2j ab + α 3j b 2 =

[0997] = ab(α 3i + α 3j + α i α 2j + α j α 2i )

[0998] and

[0999]

[1000] It follows that:

[1001]

[1002] In the Galois field GF(2m), it holds that: The sum of two equal expressions gives the value 0.

[1003] Thus, for example

[1004] α 3i a 2 + α 3i a 2 = 0.

[1005] Furthermore, it holds that:

[1006] L 2 (α i ) = L 2 (α j ) = 0 and L 2 (x) ≠ 0, where x ≠ α i , α j .

[1007] One option is that: σ1 is determined as the component-wise exclusive OR sum

[1008]

[1009] where

[1010]

[1011] σ 1 Determined as the exclusive-or sum of two values in the Galois field GF(2 m ) according to formulas (88) and (89), the two values corresponding to two zeros of the locator polynomial L 2 (x).

[1012] One option is: instead of the locator polynomial in formula (84)

[1013] L 2 (x) = x 2 + σ 1 x + σ 2

[1014] use the locator polynomial

[1015] L′ 2 (y) = y 2 σ 2 + yσ 1 + 1. (90)

[1016] By substituting

[1017]

[1018] into formula (84), formula (90) is obtained. When the zeros of L 2 (x) are equal to α i and α j , the zeros of L′ 2 (y) are α -i and α -j .

[1019] For the byte positions corrected in the case of byte errors, determine the byte error correction values. For example, if the byte positions from 0 to n - 1 are the byte positions to be corrected, then for k (where 0 ≤ k ≤ n - 1), determine the byte error value a(k) such that the following applies:

[1020]

[1021] If there is a 2-byte error with the byte error correction value a in the byte position α i and the byte error correction value b in the byte position α j , then for the i-th byte position with k = i, the following applies according to formula (91): i j

[1022]

[1023] ​​And it applies to the j-th byte position with k = j:

[1024]

[1025] In byte positions where there are no byte errors, the byte error correction value determined according to formula (91) is not used for correction. If there are errors in the values at byte positions i and j in the case of a 2-byte error, the values determined for k ≠ i and k ≠ j are not used for error correction. At byte positions k = i and k = j, the byte error correction values a or b required for correction are provided respectively: In the case of a 2-byte error at byte positions α i and α j at,

[1026] s 1 = a + b,

[1027] s 2 = α i a + α j b

[1028] σ 1 = α i + α j

[1029] Substitute into formula (91) and obtain:

[1030]

[1031] Advantageously, the technical implementation of the relationship described in formula (91) can achieve significant simplification and thus higher efficiency. Therefore, for example, the values

[1032]

[1033] and

[1034]

[1035] can be formed centrally (in advance) and, if necessary, only once respectively, and then used to determine all byte positions to be corrected.

[1036] For example, for each byte position k to be corrected, the value

[1037]

[1038] can be multiplied by the constant value α k known for byte position k. Multiplying by the value α k known for the byte position is multiplying by a constant, and can be implemented by means of a simple constant multiplier.

[1039] Then, the value

[1040] and

[1041] perform an exclusive OR operation component by component.

[1042] Therefore, different from the previously known methods, taking the reciprocal of each byte in the Galois field GF(2m) can be omitted.

[1043] One option is: use the H matrix H*

[1044]

[1045] The H matrix H* according to formula (94) has four rows, while the H matrix according to formula (2) only includes three rows.

[1046] If there is a 2-byte error with byte error values a and b at byte positions i and j, the syndrome components s 1 to s 4 are

[1047] s 1 = α i a + α j b

[1048] s 2 = α 2i a + α 2j b

[1049] s 3 = α 3i a + α 3j b

[1050] s 4 = α 4i a + α 4j b (95)

[1051] With the H matrix H* according to formula (94) and the syndrome components according to formula (95), the byte error correction value a(k) of the k-th byte is determined as follows:

[1052]

[1053] If there is a 2-byte error with byte error values a and b at byte positions i and j, then a(i) = a and a(j) = b apply. This is obtained by substituting the syndrome components s 1 to s 4 into formula (85) and formula (96).

[1054] The implementation according to formula (96) enables a simplification compared to the previously known solutions. Thus, for example, the values

[1055]

[1056] and

[1057]

[1058] can be formed centrally (in advance), and if necessary, only once each, and then used to determine all byte positions to be corrected.

[1059] For example, for each byte position k to be corrected, the values

[1060]

[1061] can be multiplied by the constant value α -k known for the byte position k, for example, by means of a constant multiplier.

[1062] Then, the values

[1063] and

[1064] can be XORed component-wise.

[1065] Therefore, different from the previously known methods, taking the reciprocal of each byte in the Galois field GF(2 m ) can be omitted.

[1066] In the case of a 2-byte error with a byte error value a at the byte position α i and a byte error value b at the byte position a j , regardless of a and b, the following applies:

[1067]

[1068] This can be verified by substituting the syndrome component s 1 according to formula (95) into s 4 :

[1069]

[1070] Even when using the H matrix H* according to formula (94), one option is to determine σ 1 as the component-wise XOR sum

[1071]

[1072] , where the following applies:

[1073]

[1074] In the case of a 2 - byte error in byte positions i and j, the locator polynomial L 2 (x) takes the value 0 for x = α i and x = α j and is non - zero in all other byte positions, such that in the case of a 2 - byte error at byte positions i and j, the following applies according to formula (101):

[1075] σ 1 = α i + α j .

[1076] Figure 14 Shows an exemplary design for forming the coefficients σ m and σ 1 to s 4 from the syndrome components s 1 and σ 2 according to formula (85) by means of Galois - field multipliers 1401 to 1406, adders (bit - by - bit exclusive - OR operations) 1407 to 1409, squarers 1410, 1411, and a reciprocal calculator 1412 (in the Galois field GF(2 m ).

[1077] Figure 15 Shows an exemplary design for forming the term which is the input signal of the circuit shown in Figure 18 . According to formula (85)

[1078]

[1079] Thus,

[1080]

[1081] For this purpose, Figure 15 the circuit shown in

[1082] Figure 16 Shows an exemplary design for forming the term which is the input signal of the circuit shown in Figure 18 . Substituting with formula (85) gives again:

[1083]

[1084] For this purpose, Figure 16The circuit shown in the figure includes Galois field multipliers 1601 to 1604, adders 1605 and 1606, squarers 1607 and cube formers 1608, and a reciprocal calculator 1609.

[1085] Figure 17 Shows the coefficients σ for byte positions i and j according to the locator polynomial 1 and σ 2 An exemplary design for forming the value of the locator polynomial. If in formula (84) x is replaced by α k then there is:

[1086] L 2 (α k ) = α 2k + σ 1 ·α k + σ 2 . (102)

[1087] In Figure 17 , for k = i, j, shows the determination of the locator polynomial according to formula (102). For this purpose, for example, constant multipliers 1701 and 1702, adders 1703 to 1706, and OR gates 1707 and 1708 are used. The OR gates 1707, 1708 perform an OR operation on the signals applied at the m input terminals, such that only when the value 0 is applied at all input terminals, the value 0 is applied at the output terminal. Therefore, the value 0 at the output terminal of the corresponding OR gate indicates whether the condition

[1088] L 2 (α k ) = 0 (103)

[1089] As explained above, when the said condition is satisfied, there is an error.

[1090] Figure 18 Shows for based on

[1091] - According to Figure 17 Determine and provide the locator polynomial L 2 (α k ),

[1092] - According to Figure 16 Determine the term s 2 / σ 1 + s 1 and

[1093] - According to Figure 15 Determine the term s 1 / σ 1

[1094] An exemplary design for forming the byte error correction value a(k) at byte positions i and j.

[1095] For this purpose, in Figure 18 constant multipliers 1801 and 1802, adders 1803 to 1804, and AND gates 1805 and 1806 are exemplarily used, where one of the input terminals of the respective AND gate is inverted.

[1096] As Figure 17 explained in

[1097] L 2 (α k )≠0,

[1098] then no error is determined at byte position k. Correspondingly, the inverted value is applied to the input terminals of the AND gates 1805, 1806, and thus the byte error correction value according to formula (91) is provided at the output terminals of the AND gates 1805, 1806 only when a byte error is confirmed at byte position k by means of the locator polynomial.

[1099]

Claims

1. A circuit arrangement for correcting at least one byte error in a binary sequence comprising a plurality of bytes, wherein in the error-free case the binary sequence is a codeword of an error code, wherein the circuit arrangement is designed - for determining at least one byte error position signal, the byte error position signal indicating whether a byte of the binary sequence is erroneous, for determining at least one byte error correction value, according to which an erroneous byte position identified by means of the byte error position signal can be corrected, - wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of the at least three byte positions according to coefficients of a locator polynomial, - for correcting the at least one byte error based on the at least one byte error correction value.

2. The circuit arrangement according to claim 1 , wherein the first value comprises: The correction value A is multiplied by a first constant, wherein the first constant is determined by the byte position of the error.

3. The circuit arrangement according to claim 1 , wherein the third value comprises: The correction value C is multiplied by a second constant, wherein the second constant is determined by the byte position of the error. 4 . The circuit arrangement according to claim 1 , wherein the multiplication with the constant is a multiplication in a Galois field GF(2m), where m≧2.

5. The circuit arrangement according to claim 1 , wherein the byte error correction value is determined according to the following formula: v(L)α (104) in a L represents the first constant, a 2L represents the second constant, A and C represent the correction values, B represents the second value and + denotes addition in the Galois field GF(2m), where m≥2. 6 . The circuit arrangement as claimed in claim 3 , wherein the correction values ​​A and C and the second value are identical for different byte positions. 7 . The circuit arrangement according to claim 3 , wherein the second constant is the square of the first constant. 8 . The circuit arrangement as claimed in claim 1 , wherein a correction is performed for byte positions in which the byte position error correction value is not zero. 9 . The circuit arrangement as claimed in claim 1 , wherein a 3-byte error can be corrected by means of three byte error location signals. 10 . The circuit arrangement as claimed in claim 1 , wherein the byte error correction values ​​are determined at least partially overlapping in time.

11. The circuit arrangement as claimed in claim 1, wherein the byte error position signal can be determined using components of an error syndrome of the error code. 12 . The circuit arrangement as claimed in claim 1 , wherein at least one of the byte error correction values ​​is determined for at least one correct byte.

13. The circuit arrangement as claimed in claim 1, wherein 3-byte errors are corrected.

14. The circuit arrangement according to claim 1 , wherein the error code is a Galois field GF(2 m ) wherein m≥2, the Reed-Solomon code being capable of correcting at least 3-byte errors.

15. A method for correcting at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence is a codeword of an error code in the absence of an error, the method comprising the following steps: - determining at least one byte error position signal, which indicates whether a byte of the binary sequence is erroneous, - determining at least one byte error correction value, according to which an erroneous byte position identified by means of the byte error position signal can be corrected, - wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of the at least three byte positions according to coefficients of a locator polynomial, - correcting the at least one byte error according to the at least one byte error correction value.

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