Verification system of AI accelerator based on UVM and python
By using Python on the UVM verification platform to build a reference model for AI accelerator and implementing communication between SystemVerilog and Python through C language, the problem of difficult and low accuracy in traditional verification methods is solved, and a more efficient and accurate verification process is achieved.
Patent Information
- Application Number
- CN202510222158.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-05-30
AI Technical Summary
In the existing verification methods, the construction of reference models is difficult, long cycles and error-prone. Especially when dealing with neural network algorithms, the traditional verification method based on SystemVerilog requires the construction of a huge reference model, resulting in large workload and low accuracy.
The AI accelerator verification system based on UVM and Python is adopted, and the reference model built by traditional SystemVerilog is abandoned, and the reference model is built using Python, and the communication between SystemVerilog and Python is realized through C language as a bridge, reducing the difficulty and error rate of the reference model construction.
It significantly reduces the difficulty and time of building a reference model, improves the accuracy and efficiency of verification, reduces the coupling with the verification platform, is easy to maintain, and uses the off-the-shelf neural network algorithm library to improve code readability.
Smart Images
Figure CN120068744A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of digital integrated circuit (IC) verification, and in particular relates to a verification system for an AI accelerator based on UVM and Python. Background Art
[0002] With the rapid improvement of computing efficiency, artificial intelligence technology has developed rapidly and has been applied to many fields so far. Convolutional neural network (CNN) has become a mainstream neural network due to its mature training methods and rich data sets. CNN mainly includes convolutional layer, pooling layer and fully connected layer; convolutional layer is used to extract features, pooling layer is used to reduce the amount of data, and fully connected layer is used for classification, among which the most core is convolutional layer.
[0003] The implementation of neural network algorithms requires hardware support, and the relevant hardware is called DLP (Deep Learning Processor). The traditional CPU structure is highly versatile and can perform various tasks, including neural network calculations. In addition, the CPU has a mature programming model and tool chain, and developers are familiar with its operation and have debugged and optimized it. However, the lack of computational parallelism and data bandwidth limitations make it unable to meet the computational processing of intensive data in neural networks. Compared with specialized hardware accelerators, CPUs are less efficient when performing large-scale neural network calculations. Although GPUs have excellent parallel processing capabilities, due to the limitations of their physical structure, their memory is usually very small, while some large neural networks have wider and deeper structures and contain a huge amount of parameters. In addition, GPUs are very expensive and are not applicable in many scenarios. Therefore, designing dedicated neural network accelerators has become a widely used solution for hardwareizing neural networks.
[0004] Today's integrated circuit development still follows Moore's Law, which makes the number of transistors on a single integrated circuit grow almost exponentially. At the same time, the area of a single transistor is also decreasing rapidly. It is the increase in the number of transistors and the reduction in size that have brought amazing performance to today's SOC (System on Chip) chips, but along with it comes the problem of how to design and manufacture highly integrated chips.
[0005] During the entire chip design process, verification plays a very important role and almost runs through the entire process before tape-out. Verification is an important means to ensure the correct functionality of the chip before manufacturing. The workload and difficulty of chip verification increase exponentially with the increase in design complexity. For current chips with hundreds of millions of transistors, functional verification has become the most time-consuming, labor-intensive, and resource-consuming issue in the entire chip design process. Moreover, incomplete and incorrect verification will lead to functional errors in the final chip. The current mainstream verification method is UVM (Universal Verification Methodology) introduced by Accellera in 2011. Based on the SystemVerilog language, it provides many excellent mechanisms and verification ideas, greatly improving the verification efficiency. However, as mentioned above, neural network algorithms have extremely large amounts of computation, involving very complex operations such as data access, data rearrangement, data reuse, matrix multiply-add operations, activation operations, and pooling operations. Correspondingly, traditional verification work based on systemverilog requires building a huge reference model to simulate the behavior of the hardware. That is, after the reference model RM obtains the input data, it simulates the behavior of the neural network algorithm, manually constructs a large number of multi-dimensional arrays, and performs complex rearrangement and reuse operations on these arrays to obtain the final operation result. This approach has a very large workload and is very error-prone.
[0006] Therefore, it is particularly important to build a simpler and more accurate reference model to replace the reference model in the traditional verification platform. Summary of the Invention
[0007] In view of the above problems or deficiencies, to solve the problems of the large difficulty, long cycle, and easy error in building the reference model RM in the existing verification methods, the present invention provides a verification system for an AI accelerator based on UVM and Python. The verification method proposed by the present invention abandons the reference model RM built with Systemverilog in the traditional verification platform, no longer requires manually constructing a large number of multi-dimensional arrays and performing numerous complex operations on them, and instead selects to build the reference model using Python. Due to the far greater flexibility of Python than Systemverilog and the existing algorithm libraries related to neural networks, it can significantly reduce the difficulty of building the reference model and greatly ensure the accuracy of the reference model.
[0008] The technical solution adopted by the present invention is as follows:
[0009] A verification system for an AI accelerator based on UVM and Python, based on the UVM verification platform, includes an excitation generation part, a reference model part, and a scoreboard part.
[0010] The excitation generation (inputagent) part simulates the actual usage scenario, generates the excitation corresponding to the DUT (Design Under Test) to be tested, and transmits it to the DUT to be tested and the reference model. This is because the verification is for a specific DUT to be tested, and this DUT needs to obtain input data from the outside to start normal operation. Therefore, the inputagent needs to simulate the actual usage scenario and generate the corresponding excitation.
[0011] The reference model part is built with Python, which passes multi-dimensional arrays and is responsible for simulating the functions of the DUT to be tested, operating on the excitation input by the excitation generation part (the same as the excitation received by the DUT to be tested), and generating the operation results. The traditional reference model is directly built with Systemverilog. In the present invention, the reference model is built with Python. Therefore, the core problem is the communication between the native Systemverilog components other than the reference model in the UVM verification platform and the Python reference model. The present invention uses C language as a bridge to build a communication channel between Systemverilog and Python.
[0012] Among them, C language is used as a bridge to build a communication channel between the native Systemverilog components other than the reference model in the UVM verification platform and the Python reference model, making the reference model built with Python available;
[0013] The scoreboard part is responsible for collecting the operation results of the DUT to be tested and the reference model, and comparing these two results to complete the verification.
[0014] Furthermore, the communication between the C language and the native Systemverilog components is specifically as follows: communicate with the C language by introducing the Direct Programming Interface (DPI) in Systemverilog.
[0015] Furthermore, for the communication between the C language and the native Systemverilog components, as long as a C language program is declared in Systemverilog through syntax, it can be imported and used like a function written in native Systemverilog code. The first problem in the communication between Systemverilog and C language is the data type problem, and the specific solution methods are:
[0016] During the verification process of the present invention, a multi-dimensional array is passed. At this time, an open array is needed to share the multi-dimensional array. The open array is represented by blank square brackets after the import statement on the Systemverilog side, and the number of dimensions is equal to the number of square brackets; on the C language side, a handle of the svOpenArrayHandle type is used to reference the open array. By using multiple DPI methods provided in the DPI header file to access the content of the open array, the open array can fully realize the transfer of the multi-dimensional array between Systemverilog and C language.
[0017] Furthermore, the multiple DPI methods in the DPI header file to access the content of the open array include accessing the number of dimensions of the open array, the upper and lower boundaries of each dimension, the array size, and the elements at each position of the array.
[0018] Furthermore, the communication between the Python reference model and C language is implemented by using the Python interface Python / CAPI of Python.
[0019] Furthermore, the communication between the Python reference model and C language is specifically as follows:
[0020] The essence of calling Python in C language by using Python / CAPI is to embed a Python interpreter in the C language code; during the execution of Python code by the Python interpreter, each Python object is represented as a structure called PyObject, which contains the reference count and type object of the object; the type object specifies the operable methods, memory size, and name information of the object; by using the methods provided by Python / CAPI, the data types in Python can be directly declared, defined, and used in C language.
[0021] Furthermore, the verification system of the above-mentioned AI accelerator based on UVM and Python has the following specific working process:
[0022] Step 1: The stimulus generation part generates the input stimulus corresponding to the DUT under test according to the actual usage situation, and sends it to the DUT under test and the reference model respectively.
[0023] Among them, the traditional communication method provided by Systemverilog is used to send it to the DUT under test, and a communication channel between Systemverilog and the Python reference model is built through C language as a bridge and sent to the reference model.
[0024] The entire interaction process is initiated by Systemverilog. Multidimensional arrays are defined and allocated memory in Systemverilog. Then, C language uses the svopenarrayhandle handle to obtain the memory location of the open array and uses DPI functions to obtain the element values at any position of the open array.
[0025] In C language, these elements are stored in the svBitvecVal type. The valid part of the data is cut into portions of every 8 bits and collected using Pylist. Then, starting from the low dimension to the high dimension, new Pylists are used to collect them in sequence.
[0026] Step 2: After the reference model receives the input stimulus, it starts working and generates the operation result to be sent to the scoreboard.
[0027] On the Python reference model side, due to the cutting operation in the above Step 1, this list needs to be parsed and reassembled into the original array, and then sent to the reference model as an array-type stimulus.
[0028] After the Python reference model finishes the operation, the completely opposite idea is used: First, the high-dimensional operation result is encoded into a one-dimensional list and sent into C language. C language converts it into the svBitVecVal type for storage, and then uses the functions provided by DPI to pass it to Systemverilog.
[0029] Ultimately, the entire C language communication structure uses DPI and Python / CAPI to achieve two-way interaction of multidimensional arrays between Systemverilog and Python.
[0030] Step 3: In the scoreboard, the output results of the DUT under test and the Python reference model are compared. If the comparison fails, start analyzing the problems in the DUT under test code and make modifications until the results on both sides are successfully compared.
[0031] In summary, the present invention has the following advantageous effects: (1) The present invention uses the method of building a reference model with Python to replace the traditional method of building a reference model with Systemverilog, solving the problems of large workload and low accuracy of the traditional method. (2) Using Python to build a reference model and communicating with Systemverilog through C language reduces the coupling degree between the reference model and the verification platform and is easy to maintain. (3) Because ready-made neural network-related algorithm libraries are used on the Python side, the code readability is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of the basic structure of the img2col module.
[0033] Figure 2 It is a schematic diagram of a traditional verification platform.
[0034] Figure 3 It is a schematic diagram of the verification platform of the present invention.
[0035] Figure 4 It is a schematic diagram of the verification process.
[0036] Figure 5 It is a schematic diagram of the communication between Systemverilog and Python. Specific implementation manners
[0037] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings, taking the img2col module as an example.
[0038] This embodiment takes a specific DUT img2col module as an example.
[0039] Figure 1 It is a schematic diagram of the basic structure of the img2col module. The img2col is responsible for rearranging and multiplexing the data fetched from the BUFFER within multiple cycles (how to do it depends on the instruction, and the instruction is configured via APB). For example, for 3x3 convolution, 1x1 convolution, and RGB3x3 convolution, since the ways they are arranged in the BUFFER are different, and the ways they need to be arranged to enter the 16 PEArrays in the systolic are also different, the rearrangement forms they need to do in this module are also different. When this function is mapped to the verification platform, a multi-dimensional array needs to be defined in the reference model and multiple complex operations need to be performed on it.
[0040] Figure 2 It is a schematic diagram of a traditional verification platform. In the traditional construction method, after using Systemverilog to build the reference model, the input agent generates stimuli corresponding to the target DUT and sends them to the target DUT and the reference model. After each path works independently, the corresponding operation results are generated and sent to the scoreboard for comparison.
[0041] Figure 3 It is a schematic diagram of the verification platform of the present invention. The reference model is built using Python instead of the traditional Systemverilog. In the sequence related to the input agent, the reference model is called through C language to generate output results, which are sent to the scoreboard and compared with the results of the target DUT.
[0042] Combined with Figure 4 , the specific working process of this embodiment is as follows:
[0043] Step 1, the input agent generates the input stimuli corresponding to the target DUT according to the actual usage and sends them to the target DUT and the reference model respectively. Among them, the traditional communication method provided by Systemverilog is used to send to the target DUT, while a communication channel between Systemverilog and Python needs to be built through C language as a bridge when sending to the reference model.
[0044] Step 2, after receiving the input stimuli, the reference model starts to work and sends the operation results to the scoreboard.
[0045] Step 3, in the scoreboard, the output results of the target DUT and the Python reference model are compared. If the comparison fails, start to analyze the problems in the target DUT code and make modifications until the results on both sides are successfully compared.
[0046] Among them, the input stimuli involved in the verification of this module include: (1) APB configuration parameters; (2) input data, that is, the three-dimensional feature map pre-stored in the BUFFER.
[0047] Taking the RGB mode as an example, a three-dimensional array of 3x32x8 is input. At this time, for the communication between Systemverilog and C language. Systemverilog uses DPI to communicate with C language. A C function can be imported by declaring it in Systemverilog through the statement import DPI-C function, and it can be used just like a function written in native Systemverilog code. The core issue of the communication between Systemverilog and C language is the data type issue. In the present invention, it is aimed at arrays. At this time, open arrays are needed to share multi-dimensional arrays. The open array is represented by blank square brackets after the import statement on the Systemverilog side, that is, the bit dataout[][][] statement; on the C language side, an svOpenArrayHandle type handle is used to reference the open array; the use of open arrays can fully realize the transfer of multi-dimensional arrays between Systemverilog and C.
[0048] In this embodiment, the native Python / CAPI is used to implement the communication between Python and C language. The essence of calling Python in C language using Python / CAPI is to embed a Python interpreter in the C code. During the execution of Python code by the Python interpreter, each Python object is represented as a structure called PyObject, which contains the reference count of the object and the type object. The type object specifies the operable methods, memory size, and name information of the object. By using the methods provided by Python / CAPI, data types in Python can be directly declared, defined, and used in C language.
[0049] The entire C language communication structure uses the above DPI functions and Python / CAPI to achieve two-way interaction between Systemverilog and Python. The entire interaction process is initiated by Systemverilog in the sequence related to inputagent. A three-dimensional array of 3x32x8 is defined and allocated memory in Systemverilog, and then the imported C function is called in the sequence. The three-dimensional array is passed to the C language through the function call. The C language uses the svopenarrayhandle handle to obtain the memory location of the open array. In the C language, the array is stored in the svBitvecVal type. The valid part of the data is cut into portions of every 8 bits and collected using Pylist. Then, from the low dimension to the high dimension, new Pylists are used to collect them in turn. On the Python side, this list is parsed and reassembled into the original array, and then sent to the reference model as an array-type stimulus. After the reference model finishes the operation, using the completely opposite idea, that is, first encoding the high-dimensional operation result into a one-dimensional list and sending it into the C language. The C language converts it into the svBitVecVal type for storage, and then uses the functions provided by DPI to pass it to Systemverilog.
[0050] Based on the above principle, as Figure 5 shown, the input three-dimensional array generated by inputagent is sent to the C language through DPI. The C language then sends it to the Python side through Python / C API for operation. After the operation is completed, it returns to the Systemverilog side through the opposite route. In the scoreboard, the output results of the target DUT and the reference model are compared. If the comparison fails, start analyzing the problems in the DUT code and make modifications until the results of both sides are successfully compared.
[0051] As can be seen from the above embodiments, the present invention is based on the UVM verification platform and uses the method of building a reference model with Python to replace the traditional method of building a reference model with SystemVerilog, solving the problems of large workload and low accuracy of the traditional method; supplemented by C language as a bridge to build a communication channel between the native SystemVerilog components other than the reference model in the UVM verification platform and the Python reference model, making the Python reference model available and reducing the coupling degree between the reference model and the verification platform, which is easy to maintain; because the Python side uses the ready-made algorithm libraries related to neural networks, the code readability is improved. The present invention no longer needs to manually construct a large number of multi-dimensional arrays and perform many complex operations on them, and can significantly reduce the difficulty of building the reference model, and greatly ensure the accuracy of the reference model; it solves the problems of large workload and low correct rate when the traditional verification method performs complex operations on multi-dimensional arrays.
Claims
1. A verification system for AI accelerator based on UVM and python, characterized by: Based on the UVM verification platform, it includes stimulus generation, reference model and scoreboard. The stimulus generation part simulates the actual usage situation, generates the stimulus corresponding to the DUT to be tested and transmits it to the DUT to be tested and the reference model; The reference model part is built with Python, passing multidimensional arrays, responsible for simulating the functions of the DUT to be tested, operating the stimuli input by the stimulus generation part, and generating operation results. Among them, C language is used as a bridge to build a communication channel between the native SystemVeri log component outside the reference model in the UVM verification platform and the Python reference model, making the reference model built in Python available. The scoreboard part is responsible for collecting the operating results of the DUT to be tested and the reference model, and comparing the two results to complete the verification.
2. The verification system of the AI accelerator based on UVM and python as claimed in claim 1, characterized in that: The communication between the C language and the native SystemVerilog component is specifically as follows: the direct programming interface DPI is introduced in SystemVeri log to communicate with the C language.
3. The verification system of the AI accelerator based on UVM and python as claimed in claim 2, characterized in that, The communication between the C language and the native SystemVeri log component is as follows: Use open arrays to share multidimensional arrays. Open arrays are represented by blank square brackets after the import statement on the SystemVerilog side, and the number of dimensions is equal to the number of square brackets. On the C language side, a handle of type svOpenArrayHandle is used to reference the open array. Using multiple DPI methods provided in the DPI header file to access the content of the open array, open arrays can fully realize the transfer of multidimensional arrays between SystemVeri log and C language.
4. The verification system of the AI accelerator based on UVM and python as claimed in claim 3, characterized in that, The DPI method for accessing the content of an open array specifically includes: accessing the number of dimensions of the open array, the upper and lower boundaries of each dimension, the array size, and the elements at each position of the array.
5. The verification system of the AI accelerator based on UVM and python as claimed in claim 1, characterized in that: The communication between the Python reference model and the C language is implemented using the Python interface Python / CAPI.
6. The verification system of the AI accelerator based on UVM and python as claimed in claim 5, characterized in that, The communication between the Python reference model and the C language is specifically as follows: Embed the Python interpreter in the C language code; when the Python interpreter executes the Python code, each Python object is represented as a structure called PyObject, which contains the object's reference count and type object; the type object specifies the object's operable methods, memory size, and name information; By using the methods provided by Python / CAPI, you can directly declare, define and use data types in Python in C language.
7. The verification system of the AI accelerator based on UVM and python as claimed in claim 1, characterized in that: The communication between the C language and the native SystemVerilog component is specifically as follows: introducing a direct programming interface DPI in SystemVeri log to communicate with the C language; The communication between the Python reference model and the C language is implemented using the Python interface Python / CAPI.
8. The verification system of the AI accelerator based on UVM and python as claimed in claim 7, characterized in that, The specific workflow is: Step 1: The stimulus generation part generates the input stimulus corresponding to the DUT under test according to the actual use situation, and sends it to the DUT under test and the reference model respectively; Among them, the communication method provided by the traditional Systemveri log is used when sending to the DUT under test, while the communication channel between Systemveri log and the python reference model is built by using C language as a bridge when sending to the reference model; The whole interaction process is initiated by Systemverilog. The multidimensional array is defined and memory is allocated in Systemveri log. Then the C language uses the svopenarrayhandle handle to obtain the memory location of the open array and the DPI function to obtain the element value at any position of the open array. In C language, these elements are stored as svBitvecVal type, and the valid part of the data is cut into 8 bits each, collected with Pylist, and then collected with new Pylist from low dimension to high dimension. Step 2: After receiving the input stimulus, the reference model starts to work and generates the calculation results and sends them to the scoreboard; On the Python reference model side, due to the splitting operation in step 1 above, the list needs to be parsed and reassembled into the original array, and then sent to the reference model as an array-type stimulus; After the Python reference model operation is completed, the opposite idea is used: first, the high-dimensional operation result is encoded into a one-dimensional list and sent to the C language. The C language converts it into the svBitVecVal type for storage, and then uses the function provided by DPI to pass it to Systemveri log; Finally, the entire C language communication structure uses DPI and Python / CAPI to realize the bidirectional multi-dimensional array interaction between Systemveri log and Python; Step 3: Compare the output results of the DUT to be tested and the Python reference model in the scoreboard. If the comparison fails, start analyzing the problem of the DUT code to be tested and modify it until the results on both sides are successfully compared.