Integrated circuit test set generation method based on community division and greedy optimization

Abstract

The invention provides an integrated circuit test set generation method based on community division and greedy optimization, and belongs to the technical field of integrated circuit test. According to the method, logic relevance between faults is quantized by constructing a fault incidence matrix, a fault set is divided into high-cohesiveness communities in combination with an improved Louvain community division algorithm, and a minimum test set is generated based on a community structure and a greedy strategy. The method is characterized by comprising the following steps: 1) analyzing and constructing a fault incidence matrix through a gate-level circuit, and defining high, middle and low three-level correlation weights; 2) dynamically adjusting resolution parameters of community division to adapt to topological characteristics of circuits of different scales; and 3) adopting a two-stage test set generation strategy, preferentially covering a high-weight fault in the community, and performing global optimization in combination with a greedy algorithm. Experiments of the method on an ISCAS85 reference circuit show that the scale of a test set is reduced by 35%-48% compared with that of a traditional greedy algorithm, and the test cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to integrated circuit testing technology, and in particular, to a method for generating an integrated circuit test set based on community division and greedy optimization, which is applicable to the optimization of the scale of the fault test set and the control of test costs for very large scale integrated circuits (VLSIs). Background Art

[0002] With the continuous development of integrated circuit technology, the complexity of chip manufacturing processes has increased significantly, resulting in an increasing variety and quantity of chip defects. These defects not only affect the performance and reliability of the chips but also pose higher requirements for chip testing. Chip testing is a key link to ensure chip quality, and the design and optimization of the test set are the core to improve test efficiency and coverage. However, there are still many challenges in current chip testing and test sets.

[0003] First of all, with the continuous increase in the complexity of chip design, traditional testing methods and test set designs are no longer sufficient to meet the requirements. Early testing methods mainly relied on manually designed test cases, but this method was inefficient and difficult to handle complex chip designs. In recent years, although automated testing methods based on simulation have been widely used, there are still problems of insufficient test coverage and high test costs in the face of increasingly complex chip designs.

[0004] Secondly, the design of chip test sets also faces the problem of being disconnected from the actual application scenarios. Current test sets are often generated based on theoretical models or historical data and are difficult to fully cover all situations that chips may encounter in actual applications. This results in the fact that even chips that pass the test may still malfunction in actual use, affecting product reliability and user experience.

[0005] At the same time, with the development of artificial intelligence and deep learning technologies, testing methods based on machine learning and deep learning have gradually emerged, but these methods still face problems such as insufficient dataset scale and limited model generalization ability in actual applications. For example, although the deep learning model based on YOLOv8 shows high accuracy and efficiency in chip defect detection, the construction and annotation of its dataset still require a large amount of manpower and time.

[0006] In summary, current chip testing and test set design face multiple challenges such as complex defect types, low efficiency of traditional methods, disconnection between test sets and actual applications, and limited application of emerging technologies. Future research needs to conduct in-depth exploration in aspects such as intelligent design of test sets, high efficiency of defect detection, and close combination of testing methods and actual applications to improve the overall level and efficiency of chip testing.

[0007] In view of this, the present invention is proposed to solve the problems of low efficiency and long test time in traditional methods, and a new optimization direction is proposed. By using a modularity-based clustering algorithm to automatically divide fault communities without manual intervention, it reduces the dependence on human experience; dynamically adjusts the resolution parameter of community division according to the fault scale to adapt to the topological characteristics of circuits of different scales; dynamically adjusts the resolution parameter of community division according to the fault scale to adapt to the topological characteristics of circuits of different scales; combines the greedy algorithm and community division, significantly reducing the time complexity of the algorithm and being applicable to the test of very large scale integrated circuits. Summary of the Invention

[0008] The object of the present invention is to provide an efficient and optimized method for generating a test set for integrated circuit fault detection, aiming to solve the problems of increased test time, increased storage burden of test equipment, and increased test cost caused by a large amount of test data in existing integrated circuit tests. By optimizing the generation process of the test set, reducing the amount of test data, reducing the test time and storage cost, and at the same time improving the test coverage, this method has wide applicability.

[0009] To achieve the above object, the present invention proposes a method for generating a test set for integrated circuits based on community division and greedy optimization. By parsing the circuit description file, constructing a fault correlation matrix, and using two algorithms, the Louvain algorithm and the greedy algorithm, in combination with the optimized GCRL-TC algorithm for test set generation, it is applicable to the field of integrated circuit fault detection.

[0010] Step 1: Netlist parsing. According to the parsed nodes and fault information, generate a fault list.

[0011] Step 2: Fault correlation matrix construction. Traverse the fault list and set different weights according to the correlation between different faults, thereby generating a fault correlation matrix.

[0012] Step 3: Implementation of the Louvain algorithm, including matrix transformation, community division, and dynamic resolution adjustment.

[0013] Step 4: Generation of test vectors within the community. After obtaining the community division result, traverse the communities in descending order of community weight. According to the optimized greedy algorithm, select 2-3 faults with the highest total fault weight in each community to form a test vector.

[0014] Step 5: Redundancy elimination. After generating the preliminary test set, count the number of faults directly covered by the test set, and use the backpropagation algorithm to eliminate redundant test vectors to generate an optimized test set.

[0015] Step 6: Determine whether the termination condition is met. The termination condition is that all traversals are completed. If the termination condition is not met, continue with iterative optimization and return to Step 1. Otherwise, end the search process, output the optimal test set, and obtain the final result.

[0016] Further, since the construction of the fault correlation matrix is based on the logical structure of the circuit, the correlation between faults is divided into high correlation, medium correlation, and low correlation, which are represented by different weights: high correlation weight is 0.6 - 0.9, medium correlation weight is 0.3 - 0.5, and low correlation weight is 0.1 - 0.2.

[0017] Further, since the community partitioning algorithm uses the Louvain algorithm, its resolution parameter is dynamically adjusted according to the number of faults: when the number of faults > 100, the resolution = 1.5 × the reference resolution; when the number of faults ≤ 100, the resolution = the reference resolution.

[0018] Further, the calculation method of community weight is: community weight = Σ (fault weights within the community) × log2 (community size); fault weight = Σ (non - zero element values in the corresponding row of the fault correlation matrix).

[0019] Beneficial effects:

[0020] 1. Fault correlation modeling:

[0021] Construct a fault correlation matrix through gate - level netlist parsing to quantify the logical coupling strength between faults;

[0022] Define three - level correlation weights to accurately reflect the circuit topology characteristics.

[0023] 2. Dynamic community partitioning:

[0024] Adopt an improved Louvain algorithm to dynamically adjust the resolution parameter according to the circuit scale;

[0025] Introduce a weight threshold to filter out noise edges and enhance community cohesion.

[0026] 3. Hierarchical test generation:

[0027] Generate high - density test vectors within the community to preferentially cover critical faults;

[0028] Use a global greedy strategy to supplement the coverage of marginal faults and balance efficiency and coverage. Description of the Drawings

[0029] In order to further elaborate on the content described in the present invention, the following further details the specific implementation manners of the present invention with reference to the accompanying drawings. It should be understood that these drawings are only typical examples and should not be regarded as limiting the scope of the present invention.

[0030] Figure 1 : Overall flow chart, briefly illustrating the implementation steps of the entire method.

[0031] Figure 2 : Flow chart for constructing the fault correlation matrix, showing the steps from netlist parsing to matrix generation.

[0032] Figure 3 : Flow chart of the dynamic community partitioning algorithm, highlighting the resolution adjustment and weight filtering modules.

[0033] Figure 4 : Schematic diagram of two-stage test generation, comparing the complementarity of in-community generation and global greedy.

[0034] Figure 5 : Flow chart of backpropagation redundancy elimination, showing the iterative process of redundancy determination and elimination. Specific implementation manner

[0035] In order to make the objectives, technical solutions and beneficial effects of the present application clearer and more understandable, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present invention.

[0036] In order to illustrate the technical solutions described in the present invention, the following is illustrated through specific embodiments.

[0037] Please refer to Figures 1 - 5 ; The present invention provides a method for generating an integrated circuit test set based on community partitioning and greedy optimization. Step 1: Parse the circuit description file. Step 2: Construct a fault correlation matrix according to the fault list generated by the parsing in Step 1. Step 3: Implement the Louvain algorithm according to the fault correlation matrix in Step 2. Step 4: Generate in-community test vectors according to the algorithm in Step 3. Step 5: Perform redundancy elimination, and generate an optimized test set according to the optimized model in Step 4.

[0038] Step 1: Netlist parsing. Generate a fault list according to the parsed node and fault information. Parse the circuit description file, that is, read the.bench file and parse the input, output nodes and logic gate information in the circuit, extract all nodes in the circuit, and generate a fault list with the two fault states of 0 and 1 corresponding to each node.

[0039] Step 2: Fault correlation matrix construction. Traverse the fault list, and set different weights according to the correlation between different faults, thereby generating a fault correlation matrix. First, initialize a sparse matrix fault_matrix to store the correlation strength between faults. Set the correlation values in the matrix according to the relationship between fault nodes:

[0040] High correlation (weight 0.6 - 0.9): Among multiple input node faults of the same logic gate.

[0041] Medium correlation (weight 0.3 - 0.5): Between directly connected input-output node faults.

[0042] Low correlation (weight 0.1 - 0.2): Between node faults without direct logical connection.

[0043] Self-correlation (weight 0): The correlation of the same fault itself, to avoid self-overlap.

[0044] Step 3: Implementation of the Louvain algorithm, including matrix transformation, community division, and dynamic resolution adjustment. Community detection is initialized by converting the fault correlation matrix into a graph structure, then community division is performed on the fault correlation graph, and the resolution parameter is dynamically adjusted to adapt to fault matrices of different scales.

[0045] The purpose of community division is to divide fault nodes into multiple subsets, and the fault nodes within each subset have a high degree of correlation. Specifically, when implementing, each node in the graph is initialized as an independent community, and the initial number of communities is the same as the total number of nodes. For each node, it is sequentially tried to assign the node to the community where each of its neighbor nodes is located, calculate the change in modularity before and after the assignment, and assign the node to the community with the largest modularity gain. If the modularity gain is zero or negative when the node is assigned to the community where its neighbor node is located, the node remains in the original community. Repeat the above steps until the communities to which all nodes belong no longer change. Since the communities to which the nodes belong have changed, the graph needs to be reconstructed. The communities obtained in the previous step are folded, each community is folded into a node, the weights of the edges between the nodes within the community are updated to the weights of the loops of the new node, and the weights of the edges between the communities are updated to the weights of the edges between the new nodes, and then return to perform the node transfer operation between the communities.

[0046] Step 4: Generation of test vectors within the community. After obtaining the community division result, traverse the communities in descending order of community weight. According to the optimized greedy algorithm, select 2 - 3 faults with the highest total fault weight within each community to form a test vector. Select the top 20 faults with the highest weight from the uncovered faults as candidates. For each candidate fault, select the faults with an association strength greater than 0.4 with it to form a test set, and each test contains at most 2 faults. If there are no suitable fault pairs in the candidate set, generate a test separately.

[0047] Step 5: Redundancy elimination. After generating the preliminary test set, count the number of faults directly covered by the test set, and use the backpropagation algorithm to eliminate redundant test vectors to generate an optimized test set. Compare the results by counting the sizes of the test sets of the two algorithms. Use the backpropagation algorithm to eliminate redundant test vectors, and judge whether a fault is redundant by the number of times the fault is covered, so as to optimize the test set and finally generate the optimal test set.

[0048] Step 6: Judge whether the termination condition is met. The termination condition is full traversal. If the termination condition is not met, continue iterative optimization and return to Step 1. Otherwise, end the search process, output the optimal test set, and obtain the final result.

[0049] The integrated circuit test set generation method based on community partitioning and greedy optimization proposed by the present invention efficiently constructs a fault association graph and performs community partitioning through a fault association matrix parsing and community detection module; through a test set generation and optimization module, an optimized test set is generated and the structure of the test set is further optimized. The method can significantly reduce the amount of test data, reduce the test time and storage cost, and at the same time improve the test coverage rate. It is applicable to the fault detection processes of most integrated circuits and has wide applicability and practical application value.

[0050] Finally, it should be noted that the above embodiments are only presented as illustrations of the present application and not as limitations. Those skilled in the relevant art can implement all or part of the above embodiments, and can make various combinations, variations and changes without departing from the spirit and scope of the present invention. And the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A method for generating an integrated circuit test set based on community partitioning and greedy optimization, comprising the following steps: Step 1: Netlist analysis: Generate a fault list based on the analyzed nodes and fault information; Step 2: construct the fault correlation matrix. Traverse the fault list and set different weights according to the correlation between different faults to generate the fault correlation matrix. Step 3: Implementation of Louvain algorithm, including matrix transformation, community division and dynamic resolution adjustment; Step 4: Generate test vectors within the community. After obtaining the community division results, traverse the communities in descending order of community weights. Based on the optimized greedy algorithm, select 2-3 faults with the highest total fault weights in each community to form a test vector. Step 5: Redundancy elimination: After generating the preliminary test set, count the number of faults directly covered by the test set, use the back propagation algorithm to eliminate redundant test vectors, and generate an optimized test set. Step 6: Determine whether the termination condition is met. The termination condition is all traversals. If the termination condition is not met, continue iterative optimization and return to step 1. Otherwise, end the search process, output the optimal test set, and obtain the final result.

2. The integrated circuit test set generation method based on community partitioning and greedy optimization according to claim 1, characterized in that: In the step 2, the construction of the fault correlation matrix is ​​based on the logical structure of the circuit, and the correlation between faults is divided into high correlation, medium correlation and low correlation, which are represented by different weights: high correlation weight 0.6-0.9, medium correlation weight 0.3-0.5, low correlation weight 0.1-0.

2.

3. The integrated circuit test set generation method based on community partitioning and greedy optimization according to claim 1, characterized in that: In the step 3, the community division algorithm adopts the Louvain algorithm, and its resolution parameter is dynamically adjusted according to the number of faults: when the number of faults is greater than 100, the resolution = 1.5 × the benchmark resolution; when the number of faults is less than or equal to 100, the resolution = the benchmark resolution.

4. The integrated circuit test set generation method based on community partitioning and greedy optimization according to claim 1, characterized in that: The community weight calculation method in step 4 is: Community weight = Σ(fault weight within the community) × log2(community size); fault weight = Σ(non-zero element value of the corresponding row in the fault association matrix).

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