Sampling rate dynamic configuration platform and configuration method based on radio frequency FPGA

Abstract

The embodiment of the invention discloses a sampling rate dynamic configuration platform and method based on a radio frequency FPGA. The configuration platform comprises the radio frequency FPGA, an upper computer for obtaining a target sampling rate and an external clock for generating clock information. The radio frequency FPGA comprises a register module, a configuration module and a radio frequency data conversion module which is used for receiving analog signals and comprises a plurality of asynchronous sampling units; the register module is used for storing a target sampling rate obtained based on the upper computer as a system sampling rate; the configuration module is used for outputting clock frequency and sampling frequency corresponding to each sampling unit based on the system sampling rate; and the sampling unit is used for sampling the received analog signal to obtain a digital signal based on the sampling frequency corresponding to the sampling unit and clock information generated by an external clock according to the clock frequency. A platform design idea is adopted, and a plurality of ADCs are integrated in the FPGA, so that the working difficulty of PCB design is reduced, and the modification process of the sampling rate is greatly simplified.

Description

Technical Field

[0001] Multiple embodiments of this specification relate to the technical field of communication data acquisition, and specifically relate to a sampling rate dynamic configuration platform and configuration method based on a radio frequency FPGA. Background Art

[0002] With the development of microwave technology, the operating frequency bands of radar and communication devices are continuously expanding, and the covered frequency bands are also continuously increasing, making the bandwidth of the radio frequency front-end received signals continuously increase. This also continuously raises the requirements for the ADC sampling rate, which has now rapidly expanded to 1 Gsps, 10 Gsps, or even dozens of Gsps. Usually, imported ultra-high-speed ADC chips are selected, and the architecture of an ADC chip plus an FPGA chip is used for signal acquisition and processing, and the JESD204B interface is used to realize the transfer of the acquired data between the ADC chip and the FPGA chip, as Figure 1 shown.

[0003] The existing patent with the application number 202223101962.5 discloses an ADC interleaved acquisition device based on the JESD204B bus. This technical solution realizes the stable sampling timing of each ADC sub-module through the sampling clock of the clock circuit, fine-tunes the delay parameters of each ADC sub-module to achieve multi-channel equidistant sampling, and with the help of the JESD204B protocol, controls the SYNC_N signal through the FPGA module to realize the synchronization of the initialization moments of each ADC sub-module, and realizes the alignment of the sampled data transmission of each ADC sub-module through the SYSREF signal with the same source and fixed relative phase, so as to realize high-quality signal interleaved acquisition.

[0004] However, in actual use, in order to acquire signals with different bandwidths, the ADC chip needs to be configured with different sampling rates. It is necessary to modify the JESD204B interface parameters, and at the same time modify the clock and ADC register configurations. After the modification, the FPGA needs to be recompiled and solidified. The modification process is cumbersome and consumes a large amount of labor costs and time costs. Summary of the Invention

[0005] Embodiments of this specification provide a sampling rate dynamic configuration platform and configuration method based on a radio frequency FPGA. Adopting the platform design concept, multiple ADCs are integrated in the FPGA, and the analog part of the circuit only includes a clock chip, reducing the PCB design workload and difficulty; modifying the sampling rate does not require debugging the JESD204B interface, greatly simplifying the modification process and saving a large amount of labor costs and time costs.

[0006] The technical solution is as follows: In a first aspect, an embodiment of this specification provides a sampling rate dynamic configuration platform based on a radio frequency FPGA, including: a radio frequency FPGA, a host computer for obtaining a target sampling rate, and an external clock for generating clock information; The radio frequency FPGA includes a register module, a configuration module 212, and a radio frequency data conversion module that receives an analog signal and includes a sampling unit with multiple asynchronous samplings. The register module stores the target sampling rate obtained from the host computer as the system sampling rate. The configuration module 212 outputs a clock frequency and the sampling frequencies corresponding to each of the sampling units based on the system sampling rate. The sampling unit samples the received analog signal to obtain a digital signal based on the sampling frequency corresponding to it and the clock information generated by the external clock according to the clock frequency.

[0007] As a preferred solution, the register module includes a register unit and a judgment unit. The register unit updates the system sampling rate with the target sampling rate obtained from the host computer. The judgment unit obtains determination information indicating whether the system sampling rates before and after the update are the same. The determination information includes the same sampling rate and different sampling rates. The configuration module 212 outputs a clock frequency and the sampling frequencies corresponding to each of the sampling units based on the updated system sampling rate when the determination information is different sampling rates; when the determination information is the same sampling rate, it does not output the clock frequency and the sampling frequencies corresponding to each of the sampling units.

[0008] As a preferred solution, the configuration module 212 includes a counting unit and a first configuration unit. The counting unit counts the number of configurations after each startup of the configuration module 212. The first configuration unit outputs a clock frequency and the sampling frequencies corresponding to each of the sampling units based on the updated system sampling rate when the determination information is the same sampling rate and the number of configurations is zero.

[0009] As a preferred solution, the host computer includes an acquisition unit and a feedback unit. The acquisition unit acquires configuration status information indicating whether the external clock configuration is successful when the number of configurations changes. The configuration status information includes configuration success and configuration failure. The feedback unit outputs feedback information based on the configuration status information.

[0010] As a preferred solution, the configuration module further includes a second configuration unit: The second configuration unit outputs a clock frequency and the sampling frequencies corresponding to each of the sampling units again based on the updated system sampling rate when the configuration status information is configuration failure. When the configuration status information fails to be configured for a preset number of consecutive times, the feedback unit outputs configuration feedback information indicating configuration failure.

[0011] As a preferred solution, the configuration module includes a decision-making unit and a third configuration unit; The decision-making unit obtains the maximum sampling rate corresponding to each of the sampling units, and based on the maximum sampling rate corresponding to each of the sampling units and the system sampling rate, obtains the sampling units for performing sampling work; The third configuration unit outputs the clock frequency and the sampling frequency corresponding to each of the sampling units for performing sampling work based on the system sampling rate.

[0012] As a preferred solution, the decision-making unit: obtains the maximum sampling rate corresponding to each of the sampling units, the historical working data of all sampling units, and based on the maximum sampling rate corresponding to each of the sampling units, the historical working data of all sampling units, and the system sampling rate, obtains the sampling units for performing sampling work.

[0013] As a preferred solution, the decision-making unit includes a first acquisition subunit, a first decision-making subunit, and a second decision-making subunit; The first acquisition subunit obtains the maximum sampling rate corresponding to each of the sampling units and the historical working data of all sampling units; The first decision-making subunit obtains the minimum number of sampling units required to meet the system sampling rate based on the maximum sampling rate corresponding to each of the sampling units and the system sampling rate; The second decision-making subunit obtains the sampling units for performing sampling work based on the minimum number of sampling units required to meet the system sampling rate and the historical working data of all sampling units.

[0014] As a preferred solution, the decision-making unit includes a second acquisition subunit and a third decision-making subunit; The second acquisition subunit obtains the maximum sampling rate corresponding to each of the sampling units and the power consumption - sampling frequency curve corresponding to each of the sampling units; The third decision-making subunit obtains multiple configuration schemes that meet the system sampling rate based on the maximum sampling rate corresponding to each of the sampling units and the system sampling rate. The configuration scheme includes at least one sampling unit for performing sampling work and the sampling frequency corresponding to each of the at least one sampling unit for performing sampling work, and obtains the power consumption value corresponding to each configuration scheme based on the power consumption - sampling frequency curve corresponding to each of the sampling units; The third configuration unit outputs the clock frequency and the sampling frequency corresponding to each of the sampling units for performing sampling work based on the system sampling rate, multiple configuration schemes, and the power consumption value corresponding to each configuration scheme.

[0015] In a second aspect, an embodiment of this specification provides a method for dynamically configuring a sampling rate, including: Obtaining a target sampling rate and using it as the system sampling rate; Outputting a clock frequency and a sampling frequency corresponding to each of the sampling units based on the system sampling rate; Obtaining clock information based on the clock frequency; Collecting an analog signal and asynchronously sampling the analog signal based on the clock information and the sampling frequency corresponding to each of the sampling units to obtain a digital signal.

[0016] In a third aspect, an embodiment of this specification provides an electronic device, including a processor and a memory; the processor is connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory to execute the steps described in the second aspect of the above embodiment.

[0017] In a fourth aspect, an embodiment of this specification provides a computer storage medium, which stores multiple instructions, and the instructions are suitable for being loaded and executed by a processor to execute the steps described in the second aspect of the above embodiment.

[0018] The beneficial effects brought by the technical solutions provided by some embodiments of this specification at least include: 1. Each sampling unit completes an ADC acquisition task. Integrating multiple ADC chips in the RF FPGA greatly reduces the PCB design workload and difficulty. After the host computer receives the sampling rate adjustment command issued by the user device, it extracts the target sampling rate to the RF FPGA. The register module overwrites the old target sampling rate with the new target sampling rate, and the configuration module automatically generates the sampling frequency and the clock frequency with the new target sampling rate and outputs them, respectively configuring each sampling unit and the external clock to achieve fast adjustment of the sampling rate and meet the sampling rate modification requirements with high timeliness. Since the ADC is integrated in the FPGA, the analog part of the circuit only includes a clock chip, reducing the PCB design workload and difficulty, reducing the board area to a certain extent, and the collected data is directly sent to the internal logic of the FPGA through the AXI bus without passing through the JESD204B interface. If dynamic sampling rate configuration is performed, only the clock chip register and the RF Data Convert IP core need to be configured, without calculating the line rate of the JESD204B interface, reducing the FPGA code design and debugging workload, and the development designers and debuggers no longer need to spend energy understanding the underlying principle of wideband acquisition of the JESD204B protocol.

[0019] 2. When the target sampling rate, i.e., the current system sampling rate, is low, only select some sampling units to perform the sampling work under the condition of meeting the sampling requirements, which can greatly reduce the difficulty of interleaving the data collected by each acquisition unit.

[0020] 3. Select the sampling units for sampling work according to the historical working data, which can average the states or working intensities of each sampling unit, etc., make the service lives of each sampling unit similar, and thus increase the total service life of the configuration platform.

[0021] 4. Obtain multiple configuration schemes that meet the system sampling rate in advance, calculate the power consumption values corresponding to each configuration scheme according to the power consumption - sampling frequency curves corresponding to each sampling unit, and further select and implement the optimal configuration scheme. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0023] Figure 1 is a schematic structural diagram of a common signal acquisition and processing solution; Figure 2 is a schematic structural diagram of a sampling rate dynamic configuration platform based on a radio frequency FPGA provided in Embodiment 1 of this specification; Figure 3 is a schematic structural diagram of a configuration module of a sampling rate dynamic configuration platform based on a radio frequency FPGA provided in Embodiment 2 of this specification; Figure 4 is a flowchart of a sampling rate dynamic configuration method provided in the embodiments of this specification; Figure 5 is a schematic structural diagram of an electronic device provided in the embodiments of this specification. Detailed Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of this specification with reference to the drawings in the embodiments of this specification.

[0025] In the description, claims, and the above-mentioned drawings of this specification, the terms "first", "second", "third", etc. are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0026] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes can be made to the functions and arrangements of the described elements without departing from the scope of the content of this specification. Various processes or components can be appropriately omitted, substituted, or added to each example. For example, the described method can be executed in a different order from the described order, and various steps can be added, omitted, or combined. In addition, the features described for some examples can be combined into other examples.

[0027] Referring to the attached Figure 1 , Figure 1 is a schematic diagram of the architecture of a commonly used signal acquisition and processing solution. The data interface between the FPGA and the ADC uses the JESD204B protocol. When multiple low-speed ADCs are used to replace a high-speed ADC, in order to modify the system sampling rate, a dedicated IP core needs to be added on the FPGA side for adaptation, and the registers related to JESD204B on the ADC side also need to be configured to ensure the stability of the link, which increases the code logic and debugging workload. Therefore, a sampling rate dynamic configuration platform and configuration method based on a radio frequency FPGA are provided.

[0028] Embodiment 1 Referring to Figure 2 , Figure 2 is a schematic diagram of the structure of a sampling rate dynamic configuration platform based on a radio frequency FPGA provided by this specification.

[0029] The configuration platform 200 includes a radio frequency FPGA 210, a host computer 220 for obtaining a target sampling rate, and an external clock 230 for generating clock information; The radio frequency FPGA 210 includes a register module 211, a configuration module 212, and a radio frequency data conversion module 213 including a sampling unit 2131 with multiple asynchronous samplings for receiving analog signals; The register module 211 stores the target sampling rate obtained from the host computer 220 as the system sampling rate; The configuration module 212 outputs the clock frequency and the sampling frequency corresponding to each sampling unit 2131 based on the system sampling rate; The sampling unit 2131 samples the received analog signal to obtain a digital signal based on the sampling frequency corresponding thereto and the clock information generated by the external clock 230 according to the clock frequency.

[0030] Illustratively, the external clock 230 is preferably a combination of a reference crystal oscillator and a phase-locked loop chip. The phase-locked loop chip can generate clock signals of multiple frequencies through programming. Only the settings of the phase-locked loop need to be changed, without the need to replace the crystal oscillator, which can adapt to different working modes and frequency requirements. The host computer 220 can be a processor or a field programmable gate array.

[0031] Explanatorily, to implement a high-sampling-rate data acquisition and processing method that is convenient to adjust, multiple ADC chips are integrated in the radio frequency FPGA 210 for asynchronous interleaved acquisition and processing. Each sampling unit 2131 completes the acquisition and processing task of one ADC, greatly reducing the workload of PCB design and the working difficulty. After the host computer 220 receives the sampling rate adjustment command issued by the user device, it extracts the target sampling rate to the radio frequency FPGA 210. The register module 211 overwrites the old target sampling rate with the new target sampling rate as the system sampling rate. The configuration module 212 generates the sampling frequencies and clock frequencies of each ADC chip based on the system sampling rate, and configures each sampling unit 2131 and the external clock 230 to achieve rapid adjustment of the sampling rate and meet the sampling rate modification requirements with high timeliness requirements.

[0032] In addition, since the ADC is integrated in the FPGA, the analog part of the circuit only includes a clock chip, reducing the workload of PCB design and the working difficulty, reducing the board area to a certain extent, and the acquired data is directly sent to the internal logic of the FPGA through the AXI bus without passing through the JESD204B interface. If dynamic sampling rate configuration is performed, only the clock chip register and the RF DataConvert IP core need to be configured, without calculating the line rate of the JESD204B interface, reducing the workload of FPGA code design and debugging. Development designers and debuggers also do not need to spend energy understanding the underlying principle of wideband acquisition of the JESD204B protocol.

[0033] In some embodiments, the register module 211 includes a register unit and a judgment unit; The register unit updates the system sampling rate with the target sampling rate obtained by the host computer 220; The judgment unit obtains determination information indicating whether the system sampling rates before and after the update are the same. The determination information includes the same sampling rate and different sampling rates; The configuration module 212 outputs the clock frequency and the sampling frequencies corresponding to each sampling unit 2131 based on the updated system sampling rate when the determination information indicates different sampling rates; when the determination information indicates the same sampling rate, it does not output the clock frequency and the sampling frequencies corresponding to each sampling unit 2131.

[0034] Illustratively, whenever the system sampling rate is readjusted, the determination unit compares whether the system sampling rates before and after the update are the same. If they are the same, the configuration module 212 does not perform the configuration, which can avoid meaningless repeated configurations.

[0035] In some embodiments, the configuration module 212 includes a counting unit and a first configuration unit; The counting unit counts the number of configurations each time the configuration module 212 is started; The first configuration unit outputs the clock frequency and the sampling frequencies corresponding to each sampling unit 2131 based on the updated system sampling rate when the determination information indicates the same sampling rate and the number of configurations is zero.

[0036] Illustratively, each time the configuration module 212 is started, that is, each time the configuration platform 200 is powered on, when no reconfiguration is performed, the configuration module 212 automatically performs the initialization configuration to avoid the sampling rate being inaccurate after the configuration platform 200 is started. If the updated system sampling rate is the same as the system sampling rate before the update, the initialization configuration will be skipped.

[0037] In some embodiments, the host computer 220 includes an acquisition unit and a feedback unit; The acquisition unit acquires the configuration status information indicating whether the external clock 230 is successfully configured when the number of configurations changes. The configuration status information includes configuration success and configuration failure; The feedback unit outputs feedback information based on the configuration status information.

[0038] Illustratively, each time the configuration module 212 performs a configuration action, the configuration status information of the external clock 230 configuration is acquired. For example, it is determined whether the external clock 230 is locked by reading the phase-locked loop chip register. If it is locked, the configuration is successful; otherwise, the configuration is failed. The host computer 220 sends the feedback information to the user device, which can help the user confirm the sampling rate adjustment situation and whether the collected data is available.

[0039] In some embodiments, the configuration module 212 further includes a second configuration unit: The second configuration unit outputs the clock frequency and the sampling frequencies corresponding to each sampling unit 2131 again based on the updated system sampling rate when the configuration status information indicates configuration failure; The feedback unit outputs the configuration feedback information indicating configuration failure when the configuration status information is configuration failure for a preset number of consecutive times.

[0040] The configuration fails to be automatically reconfigured. When the configuration still fails after multiple attempts, the configuration feedback information of the configuration failure is output.

[0041] Illustratively, in the case where the configuration of the configuration platform 200 occasionally fails, the configuration platform 200 can automatically retry when the configuration fails, and output the information of the configuration failure only after multiple attempts, improving the fault tolerance of the configuration platform 200 and reducing the operation burden of users.

[0042] Embodiment 2 Refer to Figure 3 , Figure 3 is a schematic structural diagram of the configuration module 212 of the configuration platform 200. The difference between this embodiment and Embodiment 1 is that the configuration module 212 includes a decision-making unit 2121 and a third configuration unit 2122; The decision-making unit 2121 obtains the maximum sampling rate corresponding to each sampling unit 2131, and obtains the sampling unit 2131 for performing sampling work based on the maximum sampling rate corresponding to each sampling unit 2131 and the system sampling rate; The third configuration unit 2122 outputs the clock frequency and the sampling frequency corresponding to each sampling unit 2131 for performing sampling work based on the system sampling rate.

[0043] Illustratively, the maximum sampling rate of each sampling unit 2131 is the rated sampling rate corresponding in the specification sheet. The multiple sampling units 2131 can be the same or different, and the maximum sampling rates corresponding to them can also be the same or different. Usually, they are multiple identical low-speed ADC chips. The maximum sampling frequency that can be achieved by the interleaved acquisition of multiple sampling units 2131 is the maximum system sampling rate of the configuration platform 200. When the target sampling rate corresponding to the adjustment command issued by the user device is much lower than the maximum system sampling rate of the configuration platform 200, only some sampling units 2131 can be selected for interleaved acquisition to achieve the target sampling rate.

[0044] Exemplarily, if the target sampling rate is 9, it can be understood that sampling is performed 9 times per unit time. The configuration platform 200 has a total of 4 sampling units 2131, and the maximum sampling rate of each is 4. At this time, only 3 of the sampling units 2131 can be called and configured to perform this sampling work. And the sampling frequency of each sampling unit 2131 can be configured to 3. The clock frequency is configured to 9, which can be understood as being evenly divided into 9 sampling moments per unit time. The first sampling unit 2131 samples at the 1st, 4th, and 7th sampling moments per unit time, the first sampling unit 2131 samples at the 2nd, 5th, and 8th sampling moments per unit time, and the first sampling unit 2131 samples at the 3rd, 6th, and 9th sampling moments per unit time. In this way, the sampling requirements of the target sampling rate can be met.

[0045] Explanatory, when the target sampling rate, i.e., the current system sampling rate, is low, and under the condition of meeting the sampling requirements, only some sampling units 2131 are selected to perform the sampling work, which can greatly reduce the difficulty of interleaving the data collected by each acquisition unit.

[0046] In some embodiments, the decision-making unit 2121: obtains the maximum sampling rate corresponding to each sampling unit 2131, the historical working data of all sampling units 2131, and obtains the sampling units 2131 for performing the sampling work based on the maximum sampling rate corresponding to each sampling unit 2131, the historical working data of all sampling units 2131, and the system sampling rate.

[0047] Explanatory, the historical working data can be status information in multiple dimensions such as the cumulative working duration, cumulative working intensity, and real-time temperature of each sampling unit 2131. The sampling units 2131 for performing the sampling work are selected according to the historical working data. For example, if it is currently necessary to select three out of four sampling units 2131 to perform the sampling work according to the system sampling rate, the three sampling units 2131 with shorter cumulative working durations are preferentially selected to perform the sampling work. This can average the status or working intensity of each sampling unit 2131, make the service lives of each sampling unit 2131 similar, and thus increase the total service life of the configuration platform 200.

[0048] In some embodiments, the decision-making unit 2121 includes a first acquisition subunit, a first decision-making subunit, and a second decision-making subunit; The first acquisition subunit obtains the maximum sampling rate corresponding to each sampling unit 2131 and the historical working data of all sampling units 2131; The first decision-making subunit obtains the minimum number of sampling units 2131 required to meet the system sampling rate based on the maximum sampling rate corresponding to each sampling unit 2131 and the system sampling rate; The second decision-making subunit obtains the sampling units 2131 for performing the sampling work based on the minimum number of sampling units 2131 required to meet the system sampling rate and the historical working data of all sampling units 2131.

[0049] Illustrative, set the priority of the sampling units 2131 selected to perform the sampling work, preferentially use the least number of sampling units 2131 to perform the sampling work, minimize the data interleaving difficulty, and then select specific sampling units 2131 to perform the sampling work according to the historical working data to ensure the data quality of the data collected by the configuration platform 200.

[0050] Exemplarily, when there are a total of 5 sampling units 2131 and the maximum sampling rates of multiple acquisition units are not the same, where the maximum sampling rates of two sampling units 2131 are 3, and the maximum sampling rates of the other three sampling units 2131 are 2, three options can be selected to perform the sampling work: two sampling units 2131 with a maximum sampling rate of 3, or three sampling units 2131 with a maximum sampling rate of 2, or one sampling unit 2131 with a maximum sampling rate of 3 and one sampling unit 2131 with a maximum sampling rate of 2. It is preferred to use the fewest sampling units 2131 to perform the sampling work, that is, to select the two options of two sampling units 2131 with a maximum sampling rate of 3 or one sampling unit 2131 with a maximum sampling rate of 3 and one sampling unit 2131 with a maximum sampling rate of 2, and then determine which one of the two options to finally select based on historical work data.

[0051] In some embodiments, the decision-making unit 2121 includes a second acquisition subunit and a third decision-making subunit; The second acquisition subunit acquires the maximum sampling rate corresponding to each sampling unit 2131 and the power consumption - sampling frequency curve corresponding to each sampling unit 2131; The third decision-making subunit obtains multiple configuration schemes that meet the system sampling rate based on the maximum sampling rate corresponding to each sampling unit 2131 and the system sampling rate. The configuration scheme includes at least one sampling unit 2131 that performs the sampling work and the sampling frequency corresponding to each sampling unit 2131 that performs the sampling work, and obtains the power consumption value corresponding to each configuration scheme based on the power consumption - sampling frequency curve corresponding to each sampling unit 2131; The third configuration unit 2122 outputs the clock frequency and the sampling frequency corresponding to each sampling unit 2131 that performs the sampling work based on the system sampling rate, multiple configuration schemes, and the power consumption value corresponding to each configuration scheme.

[0052] Illustratively, for a single ADC chip, as the sampling rate increases, the power consumption of the ADC chip will increase, and this increase is not linear. At low sampling rates, the power consumption may be relatively low and change little, while at high sampling rates, the power consumption may increase significantly. The relationship between the sampling rate and power consumption of the ADC chip can be understood by referring to the data manual or technical specifications of the ADC chip to obtain the relationship curve or table of power consumption and sampling rate. When the system sampling rate is low, the number of sampling units 2131 selected to perform the sampling work is different, and the sampling frequencies corresponding to the sampling units 2131 are also different, so that multiple configuration schemes for selecting sampling units 2131 can be obtained. The maximum sampling frequencies of the respective sampling units 2131 that perform the sampling work are different, and more configuration schemes will be obtained for the platform to choose from. Estimate the corresponding power consumption values respectively.

[0053] Exemplarily, for a configuration scheme where all three sampling units 2131 sample at the same relatively low sampling frequency, and a configuration scheme where one sampling unit 2131 samples at a relatively high sampling frequency and another sampling unit 2131 samples at a relatively low sampling frequency, the power consumption value of the latter configuration scheme may be higher, but the latter configuration scheme uses fewer sampling units 2131 and has a lower data interleaving difficulty. A configuration scheme with the minimum power consumption value can be selected for configuration, or further, a configuration scheme with fewer required sampling units 2131 and a relatively low power consumption value can be selected for configuration.

[0054] The specific embodiments of this specification have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0055] Next, please refer to Figure 4 , Figure 4 which is a schematic flowchart of a sampling rate dynamic configuration method provided by an embodiment of this specification. The configuration method is based on the above configuration platform, and the configuration method can at least include the following steps: Step 202, obtain the target sampling rate and use it as the system sampling rate; Step 204, output the clock frequency and the sampling frequency corresponding to each sampling unit based on the system sampling rate; Step 206, obtain the clock information based on the clock frequency; Step 208, collect the analog signal, and perform asynchronous sampling on the analog signal based on the clock information and the sampling frequency corresponding to each sampling unit to obtain a digital signal.

[0056] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the embodiment of the configuration method, since it is basically similar to the embodiment of the configuration platform, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the configuration platform embodiment.

[0057] Please refer to Figure 5 which shows a schematic structural diagram of an electronic device provided by an embodiment of this specification.

[0058] As Figure 5As shown, the electronic device 600 may include: at least one processor 601, at least one network interface 604, a user interface 603, a memory 605, and at least one communication bus 602.

[0059] Among them, the communication bus 602 can be used to realize the connection and communication of the above-mentioned various components.

[0060] Among them, the user interface 603 may include buttons, and the optional user interface may further include a standard wired interface and a wireless interface.

[0061] Among them, the network interface 604 can but is not limited to include a Bluetooth module, an NFC module, a Wi-Fi module, etc.

[0062] Among them, the processor 601 may include one or more processing cores. The processor 601 connects various parts within the entire electronic device 600 through various interfaces and lines. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 605, and by calling the data stored in the memory 605, the processor 601 executes various functions of the electronic device 600 and processes data. Optionally, the processor 601 can be implemented in at least one of the hardware forms of DSP, FPGA, and PLC. The processor 601 can integrate one or several combinations of CPU, GPU, and modem, etc. Among them, the CPU mainly processes the operating system, the user interface, and application programs, etc.; the GPU is responsible for the rendering and drawing of the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 601 and can be implemented separately through a single chip.

[0063] Among them, the memory 605 may include RAM and may also include ROM. Optionally, the memory 605 includes a non-transitory computer-readable medium. The memory 605 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 605 may include a program storage area and a data storage area. Among them, the program storage area can store instructions for implementing the operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store the data involved in the above-mentioned various method embodiments. Optionally, the memory 605 can also be at least one storage device located far from the aforementioned processor 601. As a computer storage medium, the memory 605 may include an operating system, a network communication module, a user interface module, and a sampling rate dynamic configuration application program. The processor 601 can be used to call the sampling rate dynamic configuration application program stored in the memory 605 and execute the steps of the sampling rate dynamic configuration method mentioned in the foregoing embodiments.

[0064] The embodiments of this specification also provide a computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions run on a computer or a processor, the computer or the processor is caused to execute one or more steps in the above embodiments of the sampling rate dynamic configuration method. If each component module of the above electronic device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0065] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of this specification are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a Digital Versatile Disc (DVD)), or a semiconductor medium (such as a SolidState Disk (SSD)), etc.

[0066] Those of ordinary skill in the art can understand that all or part of the processes in the above embodiments of the method can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above embodiments of each method. The foregoing storage medium includes various media that can store program codes, such as ROM, RAM, magnetic disks, or optical discs. Without conflict, the technical features in this embodiment and the implementation solutions can be combined arbitrarily.

[0067] The above embodiments are only described in the preferred implementation manners of this specification, and do not limit the scope of this specification. Without departing from the design spirit of this specification, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of this specification shall fall within the protection scope determined by the claims of this specification.

Claims

1. A sampling rate dynamic configuration platform based on radio frequency FPGA, characterized by: It includes a radio frequency FPGA, a host computer for obtaining a target sampling rate, and an external clock for generating clock information; The radio frequency FPGA includes a register module, a configuration module, and a radio frequency data conversion module including a plurality of asynchronous sampling sampling units for receiving analog signals; The storage module stores the target sampling rate obtained by the host computer as the system sampling rate; The configuration module outputs a clock frequency and a sampling frequency corresponding to each of the sampling units based on a system sampling rate; The sampling unit samples the received analog signal to obtain a digital signal based on the sampling frequency corresponding to the sampling unit and the clock information generated by the external clock according to the clock frequency.

2. A sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 1, characterized in that: The storage module includes a storage unit and a judgment unit; The storage unit updates the system sampling rate with the target sampling rate obtained by the host computer; The judgment unit obtains judgment information indicating whether the system sampling rates before and after the update are the same, wherein the judgment information includes whether the sampling rates are the same or different; The configuration module, when the determination information is that the sampling rates are different, outputs the clock frequency and the sampling frequencies corresponding to each of the sampling units based on the updated system sampling rate; when the determination information is that the sampling rates are the same, does not output the clock frequency and the sampling frequencies corresponding to each of the sampling units.

3. A sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 2, characterized in that: The configuration module includes a counting unit and a first configuration unit; The counting unit counts the number of configurations after each startup of the configuration module; When the determination information indicates that the sampling rates are the same and the number of configurations is zero, the first configuration unit outputs the clock frequency and the sampling frequencies corresponding to the sampling units based on the updated system sampling rate.

4. A sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 3, characterized in that: The host computer includes an acquisition unit and a feedback unit; The acquisition unit acquires configuration status information indicating whether the external clock configuration is successful when the configuration times change, wherein the configuration status information includes whether the configuration is successful or not; The feedback unit outputs feedback information based on the configuration status information.

5. A sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 4, characterized in that: The configuration module also includes a second configuration unit: The second configuration unit, when the configuration status information indicates that the configuration is unsuccessful, re-outputs the clock frequency and the sampling frequencies corresponding to the respective sampling units based on the updated system sampling rate; The feedback unit outputs configuration feedback information indicating configuration failure when the configuration status information indicates configuration failure for a preset number of consecutive times.

6. The sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 1, characterized in that: The configuration module includes a decision unit and a third configuration unit; The decision unit obtains the maximum sampling rate corresponding to each sampling unit, and obtains the sampling unit that performs the sampling work based on the maximum sampling rate corresponding to each sampling unit and the system sampling rate; The third configuration unit outputs a clock frequency based on the system sampling rate and a sampling frequency corresponding to each sampling unit performing sampling work.

7. A sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 6, characterized in that: The decision unit obtains the maximum sampling rate corresponding to each sampling unit and the historical working data of all sampling units, and obtains the sampling unit that performs the sampling work based on the maximum sampling rate corresponding to each sampling unit, the historical working data of all sampling units and the system sampling rate.

8. The sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 7, characterized in that: The decision unit includes a first acquisition subunit, a first decision subunit and a second decision subunit; The first acquisition subunit acquires the maximum sampling rate corresponding to each of the sampling units and the historical working data of all the sampling units; The first decision subunit acquires the minimum number of sampling units required to meet the system sampling rate based on the maximum sampling rate corresponding to each of the sampling units and the system sampling rate; The second decision subunit acquires the sampling unit that performs the sampling work based on the minimum number of sampling units required to meet the system sampling rate and the historical work data of all the sampling units.

9. The sampling rate dynamic configuration platform based on radio frequency FPGA according to claim 6, characterized in that: The decision unit includes a second acquisition subunit and a third decision subunit; The second acquisition subunit acquires the maximum sampling rate corresponding to each of the sampling units and the power consumption-sampling frequency curve corresponding to each of the sampling units; The third decision subunit acquires a plurality of configuration schemes satisfying the system sampling rate based on the maximum sampling rate and the system sampling rate corresponding to each of the sampling units, wherein the configuration schemes include at least one sampling unit that performs a sampling operation and a sampling frequency corresponding to each of the at least one sampling unit that performs a sampling operation, and acquires a power consumption value corresponding to each configuration scheme based on a power consumption-sampling frequency curve corresponding to each of the sampling units; The third configuration unit outputs a clock frequency and a sampling frequency corresponding to each sampling unit performing sampling work based on a system sampling rate, a plurality of configuration schemes and a power consumption value corresponding to each configuration scheme.

10. A method for dynamic configuration of sampling rate, characterized in that: Based on a sampling rate dynamic configuration platform based on a radio frequency FPGA as described in any one of claims 1 to 9, the configuration method includes: Get the target sampling rate and use it as the system sampling rate; Output clock frequency based on system sampling rate and sampling frequency corresponding to each sampling unit; Obtain clock information based on clock frequency; The analog signal is collected, and based on the clock information and the sampling frequencies corresponding to the sampling units, the analog signal is asynchronously sampled to obtain a digital signal.

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