2D NC-FET device capacitance characteristic simulation model and establishment method and application thereof

Abstract

A 2D NC-FET device capacitance characteristic simulation model disclosed by the present invention comprises an intrinsic 2D FET equivalent capacitance network and a nonlinear ferroelectric capacitor CFE, the intrinsic 2D FET equivalent capacitance network comprises three ports, the three ports are respectively a source electrode, a drain electrode and an internal grid electrode, the negative electrode of the nonlinear ferroelectric capacitor CFE is connected with the internal grid electrode, and the negative electrode of the nonlinear ferroelectric capacitor CFE is connected with the internal grid electrode. The positive electrode of the nonlinear ferroelectric capacitor (CFE) is the gate electrode of the 2D NC-FET device. The invention also discloses an establishment method of the 2D NC-FET device capacitance characteristic simulation model. The method comprises a completely explicit 2D NC-FET device port total charge and transmission capacitance mathematical expression, meanwhile, the simulation speed and precision of the model are improved, the application range of the model is widened, and the blank that no capacitance characteristic simulation model of the two-dimensional semiconductor negative capacitance field effect transistor exists at present is filled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device modeling, and particularly to a simulation model for the capacitance characteristics of a 2D NC-FET device, a method for establishing the same, and an application thereof. Background Art

[0002] As integrated circuits enter the post-Moore era, excessive static power consumption has become the main factor restricting the further reduction of the size of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). Reducing the operating voltage of transistors is the core way to reduce the dynamic and static power consumption of transistors. However, the minimum operating voltage (V dd,min ) of a field-effect transistor is limited by the subthreshold swing (SS): V dd,min = SS·log 10 (I on / I off ). Here, I on and I off are the on-state and off-state currents of the transistor, respectively. In traditional MOSFET devices, since carriers follow the Boltzmann distribution mechanism, at room temperature, the minimum value of the subthreshold swing SS is about 60 mV / dec. Moreover, as the MOSFET gate length continues to shorten, the short-channel effect becomes more significant. This effect causes the subthreshold swing SS to continuously increase as the transistor size is scaled down. Two-dimensional semiconductor materials, such as MoS 2 , WSe 2, such as graphene, has an atomic layer thickness, a clean and smooth surface, and a high carrier mobility. The ultra-thin channel means that the gate has extremely strong control over the channel, that is, it has a strong ability to resist the short-channel effect. Therefore, two-dimensional semiconductor materials have great application potential in the field of low-power and high-performance transistors. In addition, in 2008, Sayeef Salahuddin et al. from Purdue University in the United States proposed the concept of a negative capacitance transistor (Negative Capacitance Transistor, hereinafter simply referred to as NC-FET) (Nano letters, 2008, 8(2): 405-410.). The NC-FET is extremely similar to the traditional MOSFET device in terms of geometric structure. The main difference is that the NC-FET replaces the gate oxide layer in the traditional MOSFET with a ferroelectric material with negative capacitance effects, such as hafnium zirconium oxide (HZO), strontium bismuth titanate (SBT), lead zirconate titanate (PZT), etc. Because of this, the NC-FET can overcome the Boltzmann bottleneck faced by the traditional MOSFET. That is to say, the subthreshold swing (SS) value of the NC-FET device at room temperature can be lower than 60 mV / dec, thus achieving a lower operating voltage and off-state current. The two-dimensional semiconductor negative capacitance field effect transistor (hereinafter simply referred to as 2D NC-FET) uses a two-dimensional semiconductor as the channel and a ferroelectric material with negative capacitance effects as the gate dielectric. This combination gives it the advantages of ultra-low power consumption, high performance, and compatibility with traditional CMOS processes. The compact model of the device, usually covering the current characteristic (I-V) model and the capacitance characteristic (C-V) model, is an important bridge connecting chip designers and chip manufacturing engineers. At present, researchers at home and abroad mainly focus on the DC current model of 2D NC-FET devices, and there is no relevant report on the capacitance characteristic model of 2D NC-FET devices.

[0003] However, a capacitance characteristic model with high precision and fast simulation speed plays a crucial role in the simulation of the AC small-signal electrical characteristics and dynamic electrical characteristics of 2D NC-FET-based chips. It is an important technical problem that any new transistor technology must overcome before moving towards industrialization. Summary of the Invention

[0004] To solve the above problem of the lack of a high-precision and efficient capacitance characteristic model for 2D NC-FET, the present invention aims to provide a capacitance characteristic simulation model for 2D NC-FET devices, including a mathematical expression for the total port charge and transfer capacitance of 2D NC-FET devices that is completely explicit. At the same time, the simulation speed, precision, and applicable range of the model are improved, filling the gap in the capacitance characteristic simulation model for two-dimensional semiconductor negative capacitance field effect transistors that is currently lacking.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] The capacitance characteristic simulation model of the 2D NC-FET device includes an intrinsic 2D FET equivalent capacitance network and a non-linear ferroelectric capacitor C FE The intrinsic 2D FET equivalent capacitance network includes three ports, namely the source, the drain, and the internal gate. The negative electrode of the non-linear ferroelectric capacitor C FE is connected to the internal gate, and the positive electrode of the non-linear ferroelectric capacitor C FE is the gate of the 2D NC-FET device.

[0007] Preferably, the intrinsic 2D FET equivalent capacitance network includes a transfer capacitance C gs connected between the internal gate and the source, a transfer capacitance C gd connected between the internal gate and the drain, and a transfer capacitance C ds connected between the drain and the source.

[0008] The present invention also discloses a method for establishing the capacitance characteristic simulation model of the 2D NC-FET device, including the following steps:

[0009] S1. Set the process parameters of the intrinsic 2D FET device and the bias voltages of each port;

[0010] S2. Based on the process parameters and bias voltages, calculate the source-end electrostatic potential and the drain-end electrostatic potential of the intrinsic 2D FET device;

[0011] S3. Based on the process parameters, the source-end electrostatic potential, and the drain-end electrostatic potential, obtain the gate-end charge, the drain-end charge, and the source-end charge of the intrinsic 2D FET device;

[0012] S4. According to the gate-end charge, the drain-end charge, and the source-end charge, calculate the transfer capacitance between each port of the intrinsic 2D FET device;

[0013] S5. According to the bias voltage of the intrinsic 2D FET device and the gate-end charge, obtain the total gate voltage of the 2D NC-FET device;

[0014] S6. Based on the transfer capacitance between each port of the intrinsic 2D FET device and the total gate voltage, construct the capacitance characteristic simulation model of the 2D NC-FET device.

[0015] Preferably, in step S2, the method for calculating the source-end electrostatic potential and the drain-end electrostatic potential is as follows:

[0016]

[0017] Where: φs is the source - side electrostatic potential, φ d is the drain - side electrostatic potential, V s is the bias voltage of the source electrode, V d is the bias voltage of the drain electrode, V g is the bias voltage of the internal gate, V TH0 is the threshold voltage of the long - channel 2D FET device, v th is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary electronic charge, C ox is the capacitance per unit area of the gate oxide layer, N 2D is the effective density of states of the two - dimensional semiconductor material, W 0 (x) is the principal - branch Lambert W function.

[0018] Preferably, in step S3, the method for obtaining the gate - terminal charge Q g of the drain - terminal charge Q d and the source - terminal charge Q s is as follows:

[0019]

[0020] ω = V g - V TH0 +v th

[0021]

[0022] Q s =-Q g - Qx

[0023] where, is an intermediate variable, and the expression is as follows:

[0024]

[0025] Preferably, in step S4, the method for calculating the transfer capacitance between ports is as follows:

[0026]

[0027] where: i and j = s, d or g.

[0028] Preferably, in step S5, the method for obtaining the total gate voltage of the 2D NC - FET device is: using the Landau - Khalatnikov equation to calculate the total gate voltage V g,ext and the ferroelectric layer capacitance C FE , and the calculation method is as follows:

[0029]

[0030]

[0031] where: t f is the thickness of the ferroelectric layer, and α, β, and γ are the Landau parameters of a specific ferroelectric material, usually extracted from the polarization charge - electric field (i.e., P - E) curve of the measured material, and Q av represents the average gate surface charge density.

[0032] Preferably, in step S6, the capacitance characteristic simulation model of the 2D NC - FET device includes the mathematical relationship between the transfer capacitance between ports and the source - side bias voltage, drain - side bias voltage, and total gate voltage.

[0033] The present invention also discloses the application of the capacitance characteristic simulation model of such a 2D NC - FET device. The capacitance characteristic simulation model of the 2D NC - FET device is expressed in Verilog - A language and is used for circuit simulation design.

[0034] Preferably, the application includes being compatible with circuit simulation tools Hspice and / or Cadence Spectre for circuit simulation design.

[0035] The present invention proposes a capacitance characteristic simulation model and its establishment method for a two - dimensional semiconductor negative capacitance field - effect transistor (2D NC - FET). The capacitance characteristic simulation model of the 2D NC - FET device is composed of two parts in series: an intrinsic 2D FET equivalent capacitance network and a non - linear ferroelectric capacitor. The modeling process is as follows: First, set the process parameters of the intrinsic 2D FET device and the bias voltages of each port (gate, drain, and source). Then, based on the set port bias voltages, calculate the source - side electrostatic potential and drain - side electrostatic potential of the intrinsic 2D FET. Next, according to the source - side electrostatic potential and drain - side electrostatic potential, obtain the gate - terminal charge, drain - terminal charge, and source - terminal charge of the intrinsic 2D FET. Then, based on the gate - terminal charge, drain - terminal charge, and source - terminal charge, calculate the transfer capacitance between ports. After that, according to the bias voltage of the intrinsic 2D FET device and the gate - terminal charge, calculate the total gate voltage of the entire 2D NC - FET. Finally, based on the transfer capacitance between ports and the total gate voltage, construct a complete capacitance characteristic simulation model of the 2D NC - FET device.

[0036] Starting from the current continuity equation and the Landau - Khalatnikov equation, the present invention uses the Lambert W function and the Ward - Dutton charge splitting method to obtain physically - based, continuous, and analytical mathematical expressions for the terminal charge and transfer capacitance. After being implemented through the Verilog - A programming language, the model is compatible with current mainstream circuit simulators.

[0037] The present invention provides fully-analyzed expressions for terminal charges and transfer capacitances, which have the advantages of good convergence, fast simulation speed, and wide parameter applicability range.

[0038] The capacitance characteristic simulation model of the 2D NC-FET proposed by the present invention can correctly reflect the true physical working mechanism of the 2D NC-FET (two-dimensional semiconductor negative capacitance field-effect transistor).

[0039] Starting entirely from physics and without using any fitting parameters, the present invention has obtained fully explicit mathematical expressions for the total terminal charges and transfer capacitances of 2D NC-FET devices. At the same time, the simulation speed, accuracy, and applicability range of the model have been improved, filling the gap that there is currently no capacitance characteristic simulation model for two-dimensional semiconductor negative capacitance field-effect transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is the capacitance characteristic simulation macro model of the 2D NC-FET device proposed by the present invention.

[0041] Figure 2 is the flowchart of the modeling method for the capacitance characteristic simulation model of the 2D NC-FET device proposed by the present invention.

[0042] Figure 3 is the curve of the normalized terminal charge of the 2D NC-FET device varying with the gate voltage.

[0043] Figure 4 is the curve of the normalized terminal charge of the 2D NC-FET device varying with the drain voltage.

[0044] Figure 5 is the curve of the normalized transfer capacitance of the 2D NC-FET device varying with the gate voltage.

[0045] Figure 6 is the curve of the normalized transfer capacitance of the 2D NC-FET device varying with the drain voltage. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] In order to make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings.

[0047] Embodiment 1

[0048] This embodiment discloses a capacitance characteristic simulation model of a 2D NC-FET device, specifically as Figure 1 shown. This capacitance characteristic simulation model of the 2D NC-FET device consists of an intrinsic 2D FET equivalent capacitance network and a non-linear ferroelectric capacitor C FE and has three ports s, d, and g ext connected to the outside.

[0049] Wherein:

[0050] The equivalent capacitance network of the intrinsic 2D FET includes three ports: source s, drain d, and internal gate g, and three transfer capacitances C gs , C ds and C gd . The transfer capacitance C gs is connected between the internal gate g and the source s, C gd is connected between the internal gate g and the drain d, and C ds is connected between the drain d and the source s.

[0051] The negative electrode of the nonlinear ferroelectric capacitor C FE is connected to the internal gate g of the equivalent capacitance network of the intrinsic 2D FET, and the positive electrode of the nonlinear ferroelectric capacitor C FE serves as the gate g of the entire 2D NC-FET device ext .

[0052] Embodiment 2

[0053] Based on Embodiment 1, this embodiment discloses a method for establishing a capacitance characteristic simulation model of the 2D NC-FET device, as shown in Figure 2 and specifically includes the following steps:

[0054] S1: Set the process parameters of the intrinsic 2D FET device, including gate length, gate width, oxide layer thickness, channel doping concentration, etc., and bias voltages V s , V d , V g , where V s is the bias voltage of the source s, V d is the bias voltage of the drain d, and V g is the bias voltage of the internal gate g;

[0055] S2: Based on the process parameters and bias voltages, calculate the source-end electrostatic potential φ s and the drain-end electrostatic potential φ d .

[0056] Specifically, the calculation formulas for the source-end electrostatic potential and the drain-end electrostatic potential are:

[0057]

[0058] In Formulas (1)-(2), V TH0 is the threshold voltage of the long-channel 2D FET device, v th is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary electronic charge, C oxis the capacitance per unit area of the gate oxide layer, N 2D is the effective density of states of the two-dimensional semiconductor material, W 0 (x) is the main branch Lambert W function.

[0059] S3: Based on the device process parameters, the source terminal electrostatic potential, and the drain terminal electrostatic potential, obtain the gate terminal charge Q of the intrinsic 2D FET according to the Ward-Dutton charge splitting method g 、the drain terminal charge Q d and the source terminal charge Q s .

[0060] Specifically, the calculation formulas for the gate terminal charge Q g 、the drain terminal charge Q d and the source terminal charge Q s are as follows:

[0061]

[0062] In the above formula, is an intermediate variable, and the expression is as follows:

[0063]

[0064] Q s =-Q g -Q d (9).

[0065] S4: Take the derivative of the gate terminal charge Q g 、the drain terminal charge Q d and the source terminal charge Q s with respect to the bias voltage to obtain the transfer capacitances C gs , C ds and C gd .

[0066] Specifically, the calculation formulas for the transfer capacitances between ports are as follows:

[0067]

[0068] where i and j = s, d, or g.

[0069] S5: Based on the gate terminal charge and the ferroelectric insulating layer process parameters, obtain the total gate voltage V g,ext of the entire 2D NC-FET and the value of the nonlinear ferroelectric capacitor C FE .

[0070] Specifically, the calculation formulas for the total gate voltage and the non-ferroelectric layer capacitance of the 2D NC-FET are as follows:

[0071]

[0072] In the above equation, t f is the thickness of the ferroelectric layer, and α, β, and γ are the Landau parameters of a specific ferroelectric material, usually extracted from the polarization charge - electric field (i.e., P - E) curve of the measured material through experiments. Q av represents the average gate surface charge density.

[0073] Step 6: Based on the mathematical expressions of the transmission capacitances of the respective ports and the total gate voltage, construct a simulation model for the capacitance characteristics of the entire 2DNC - FET device, that is, the mathematical relationship between the transmission capacitances between the respective ports, the source - end bias voltage, the drain - end bias voltage, and the total gate voltage V g,ext therebetween.

[0074] Embodiment 3

[0075] Based on Embodiment 2, the present invention also discloses an application method of the simulation model for the capacitance characteristics of the 2D NC - FET device. The simulation model for the capacitance characteristics of the 2D NC - FET device can be implemented by Verilog - A language to achieve compatibility with mainstream circuit simulation design software such as Hspice and Cadence Spectre.

[0076] Embodiment 4

[0077] Based on Embodiments 1 and 2, this embodiment provides a verification example of the simulation model for the capacitance characteristics of the 2D NC - FET device. Specifically:

[0078] The curve of the normalized terminal charge of the 2D NC - FET device calculated by using the model proposed by the present invention with respect to the gate voltage is as Figure 3 shown, which correctly reflects the fact that when the device operates in the fully depleted region, the ionized donor charges dominate, while the mobile charges can be ignored.

[0079] The curve of the normalized terminal charge of the 2D NC - FET device calculated by using the model proposed by the present invention with respect to the drain voltage is as Figure 4 shown. It can be seen that as the drain voltage increases, the depletion region between the drain end and the channel becomes wider and wider, resulting in the total terminal charge (Q g ) controlled by the gate becoming smaller and smaller.

[0080] The curve of the normalized transmission capacitance of the 2D NC - FET device calculated by using the model proposed by the present invention with respect to the gate voltage is as Figure 5 shown. When the total gate voltage reaches the threshold voltage and the flat - band voltage, there are two relatively large growth slopes in the transmission capacitances between the respective ports, dividing the working region of the entire device into a fully depleted region, a partially depleted region, and an accumulation region.

[0081] The variation curve of the normalized transmission capacitance of the 2D NC-FET device calculated by the model proposed in the present invention with respect to the drain voltage is as Figure 6 shown.

[0082] In summary, the capacitance characteristic simulation model of the 2D NC-FET device proposed in the present invention can correctly reflect the true physical working mechanism of the two-dimensional semiconductor negative capacitance field-effect transistor.

[0083] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention. However, these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.

Claims

1. 2D NC-FET device capacitance characteristic simulation model, characterized by: Including the intrinsic 2D FET equivalent capacitance network and the nonlinear ferroelectric capacitor C FE The intrinsic 2D FET equivalent capacitance network includes three ports, which are a source, a drain and an internal gate. The nonlinear ferroelectric capacitor C FE The negative electrode of the nonlinear ferroelectric capacitor C FE The anode of is the gate of the 2D NC-FET device.

2. The 2D NC-FET device capacitance characteristic simulation model according to claim 1, characterized in that: The intrinsic 2DFET equivalent capacitance network includes a transfer capacitor C connected between the internal gate and the source. gs , connected to the transfer capacitor C between the internal gate and drain gd , connected to the transfer capacitor C between the drain and source ds .

3. The method for establishing a 2D NC-FET device capacitance characteristic simulation model according to claim 2, characterized in that: The following steps are involved: S1, setting the process parameters of the intrinsic 2D FET device and the bias voltage of each port; S2. Calculating the source electrostatic potential and the drain electrostatic potential of the intrinsic 2D FET device based on the process parameters and the bias voltage; S3, based on the process parameters, the source end electrostatic potential and the drain end electrostatic potential, obtaining the gate end charge, the drain end charge and the source end charge of the intrinsic 2D FET device; S4, calculating the transfer capacitance between each port of the intrinsic 2D FET device according to the gate terminal charge, the drain terminal charge and the source terminal charge; S5, obtaining a total gate voltage of the 2D NC-FET device according to the bias voltage and gate terminal charge of the intrinsic 2D FET device; S6. Based on the transfer capacitance and total gate voltage between the ports of the intrinsic 2D FET device, a capacitance characteristic simulation model of the 2D NC-FET device is constructed.

4. The establishment method according to claim 3, characterized in that: In step S2, the method for calculating the source end electrostatic potential and the drain end electrostatic potential is as follows: v th =k B T / q Where: φ s is the electrostatic potential at the source, φ d is the electrostatic potential at the drain terminal, V s is the source bias voltage, V d is the drain bias, V g is the internal gate bias, V TH0 is the long channel 2D FET device threshold voltage, v th is the thermal voltage, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary electron charge, C ox is the capacitance per unit area of ​​the gate oxide layer, N 2D is the effective density of states of the two-dimensional semiconductor material, and W0(x) is the main branch Lambertian W function.

5. The establishment method according to claim 4, characterized in that: In step S3, the gate terminal charge Q of the intrinsic 2DFET device is obtained. g , drain terminal charge Q d , source terminal charge Q s The method is as follows: ω=V g -V TH0 +v th Q s =-Q g -Q d in, is an intermediate variable, and the expression is as follows:

6. The establishment method according to claim 5, characterized in that: In step S4, the method for calculating the transmission capacitance between the ports is as follows: Where: i and j = s, d or g.

7. The establishment method according to claim 6, characterized in that: In step S5, the method for obtaining the total gate voltage of the 2D NC-FET device is: using the Landau-Khalatnikov equation to calculate the total gate voltage V of the 2D NC-FET device g,ext and the ferroelectric layer capacitance C FE , the calculation method is as follows: Where: t f is the thickness of the ferroelectric layer, α, β and γ are the Landau parameters of a specific ferroelectric material, usually extracted from the experimentally measured polarization charge-electric field curve of the material, and Q av Represents the average gate surface charge density.

8. The establishment method according to claim 7, characterized in that: In step S6, the capacitance characteristic simulation model of the 2DNC-FET device includes the mathematical relationship between the transfer capacitance between each port and the source bias voltage, the drain bias voltage and the total gate voltage.

9. Application of the 2DNC-FET device capacitance characteristic simulation model constructed by the establishment method as claimed in claim 8, characterized in that: The capacitance characteristic simulation model of the 2D NC-FET device is expressed in Verilog-A language and is used for circuit simulation design.

10. The use according to claim 9, characterized in that: Includes compatibility with circuit simulation tools Hspice and / or Cadence Spectre for circuit simulation design.

Images