PCB three-dimensional area wiring method based on improved A* algorithm

Abstract

The invention relates to a PCB three-dimensional area wiring method based on an improved A * algorithm, and belongs to the technical field of electronic design automation. According to the method, network wiring is sorted according to the estimated network cost. And according to an ordered escape wiring result, constructing a hanan grid chart by taking an escape wiring region, a bonding pad, a through hole and the like as obstacles, and converting a region wiring problem into a path search problem. In the path search, the path search is divided into 2D path search and 3D path search according to whether the network nodes needing to be connected are in the same layer or not. And searching the 2D path search failure line network and the 3D path search line network by using a 3D A * improved algorithm. And finally, detailed wiring is carried out, and 2D path search and 3D path search are legalized to meet DRC constraints. The PCB area wiring problem can be solved, and the PCB area wiring efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and particularly relates to a three-dimensional area routing method for PCB based on an improved A* algorithm. Background Art

[0002] With the development of integrated circuit technology, there are more and more multi-chip modules, I / O pins and bus structures on PCB boards, and the efficiency of manual wiring is low, making it increasingly difficult to meet the wiring requirements. Therefore, an automatic bus routing algorithm with high efficiency, high routing rate and stability has become an urgent need in the industry.

[0003] PCB area routing refers to making corresponding connections to escape traces outside components to ensure the integrity of the traces. Inside the bus, it is expected that a group of nets can maintain a relatively consistent topological structure and trace length. To avoid unnecessary interference, usually, the turning angle of the traces should not be less than 135 degrees. On the premise of meeting all wiring rules, the trace length should be shortened as much as possible to reduce problems such as delay caused by too long length.

[0004] Most of the existing area routing path search algorithms focus on routability, while ignoring equally critical constraints such as topological matching, trace length matching and congestion, which makes it very difficult to perform detailed routing on legalized routing paths. Summary of the Invention

[0005] The purpose of the present invention is to provide a three-dimensional area routing method for PCB based on an improved A* algorithm in view of the defects and deficiencies existing in the prior art. For the general application scenarios of area routing, an automatic area routing algorithm is designed to solve the area routing problem of PCB boards, thereby improving the efficiency of area routing of PCB boards.

[0006] To achieve the above purpose, the technical solution of the present invention is: a three-dimensional area routing method for PCB based on an improved A* algorithm, including:

[0007] Step S1, construct a routing queue according to the ordered escape routing result and determine the routing order;

[0008] Step S2, construct a Hanan grid graph according to the ordered escape routing result, initialize the obstacles on the PCB board; convert the area routing problem into an area routing path search problem;

[0009] Step S3, search for the escape routing nets on the same layer using the improved 2D A* algorithm;

[0010] Step S4, search for the escape routing nets on the same layer and the cross-layer escape routing nets with failed search paths using the improved 3D A* algorithm.

[0011] In an embodiment of the present invention, in step S1, a cost estimation function is used to calculate the routing order priority of each net.

[0012] In an embodiment of the present invention, the specific calculation method for calculating the routing order priority of each net using a cost estimation function is as follows:

[0013] P N = ω * D N + γP b

[0014]

[0015] Wherein, P N is the routing order priority of the net, D N is the estimated cost distance between the estimated starting point v s of the net area routing and the estimated ending point v t of the net area routing, P b is the number of nets in the group where the net is located, and the more the number of nets in the group, the higher the priority; d max (v s , v t ) represents the larger value of the horizontal and vertical distances between the estimated starting point of the area routing and the estimated ending point of the area routing, d min (v s , v t ) represents the smaller value of the horizontal and vertical distances between the estimated starting point of the area routing and the estimated ending point of the area routing, min represents taking the smaller value, max represents taking the larger value, respectively represent the horizontal and vertical coordinates of v s , respectively represent the horizontal and vertical coordinates of v t ; ω and γ are respectively set fixed weights used to balance the importance of the two parameters in determining the final routing order priority of the net.

[0016] In an embodiment of the present invention, in step S2, for the obstacles on the PCB board, after considering the minimum distance between the obstacles and the traces, they are reflected in the form of a rectangular bounding box; then each point of the obstacle rectangle is extended horizontally or vertically until the extension line touches the boundary of other obstacle rectangular bounding boxes or the boundary of the PCB board; the intersection of the extension lines generates initial edges and initial faces; then the initial faces are merged or divided to eliminate the too large, too small, and narrow initial faces, and the edges of the merged or divided faces are used for subsequent routing; for the edges in the layout, if the edge is on the obstacle rectangular bounding box, it is marked as an obstacle edge, otherwise its flux is calculated normally and it is marked as a non-obstacle edge, and the flux of the remaining edges is calculated normally, and the size of the flux is the Euclidean distance between the endpoints of the edge.

[0017] In an embodiment of the present invention, the obstacles on the PCB board include devices, pads, and vias.

[0018] In an embodiment of the present invention, when searching for the area routing path of a net, if it is detected that the corresponding net and the adjacent escape routing net belong to the same group, the two nets are merged for path search.

[0019] In an embodiment of the present invention, the 2DA* algorithm is improved as follows:

[0020] f(x) = g(x) + h(x)

[0021] The estimated cost h(x) to the target point is calculated as follows:

[0022]

[0023] where v x is the current node, and v t is the target node; d max (v x , v t ) represents the larger value of the horizontal and vertical distances between the current node of the area routing and the target node of the area routing, and d min (v x , v t ) represents the smaller value of the horizontal and vertical distances between the current node of the area routing and the target node of the area routing. min represents taking the smaller value, and max represents taking the larger value. respectively represent the horizontal and vertical coordinates of v x , respectively represent the horizontal and vertical coordinates of v t ;

[0024] The actual cost g(x) is calculated as follows:

[0025]

[0026] where ε, η, and μ are weights defined by the algorithm, C w1 is the cost of the accumulated routed wire length, which is the sum of the Euclidean distances of the routed nodes, C bend is the cost proportional to the number of routing corners. len is the length of the current channel. To prevent routing congestion, it is set to preferentially route through the channel with a larger len value. C direction represents the cost of the current node in different directions, and it is set to preferentially select the node tending to the direction of the target point;

[0027] In the improved 2D A* algorithm for searching paths, if there is an intersection with existing routing lines when reaching the next node, the improved 2D A* algorithm does not directly abandon the corresponding path. Instead, it maintains an intersection judgment stack for the corresponding path to handle intersections, perform dynamic wire breaking and re - routing, and determine whether the path search result meets the requirements.

[0028] In an embodiment of the present invention, the specific operation method of maintaining an intersection judgment stack for the corresponding path to handle intersections, perform dynamic wire breaking and re - routing, and determine whether the path search result meets the requirements is as follows:

[0029] If the current stack is empty or the wire net of the existing routed line being intersected is different from the wire net of the intersection path recorded at the top of the stack, record the wire net of the existing routed line being intersected and push it onto the stack; if it is the same as the wire net of the intersection path recorded at the top of the stack, pop the wire net of the intersection path recorded at the top of the stack. If the search is successful in the end, update the corresponding wire net and the path between the two intersections of the wire being intersected; when the target node is searched, if the stack is empty, it means the path to the target node is successfully searched; limit the stack capacity to control the search scope and complexity, and the stack capacity size will affect the path search result and the path search time.

[0030] In an embodiment of the present invention, in step S4, the improved 3D A* algorithm performs cross - layer path search by dynamically inserting vias.

[0031] In an embodiment of the present invention, in step S4, the cost estimation function of the improved 3D A* algorithm is calculated as follows:

[0032]

[0033] Z(v x ,v t )=C l (lay x -lay t |)

[0034] Where h(x) represents the estimated cost to the target point, v x is the current node, v t is the target node, d max (v x ,v t ) represents the larger value of the horizontal and vertical distances between the current node of the regional routing and the target node of the regional routing, d min (v x ,v t ) represents the smaller value of the horizontal and vertical distances between the current node of the regional routing and the target node of the regional routing, Z(v x ,v t ) represents the estimated cross - layer cost, lay x and lay trespectively represent the layer where the current node is located and the layer where the target node is located, C l Define weights for the algorithm; after cross-layer, the improved 2DA* algorithm is used for in-layer search.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] (1) Different from the traditional uniform grid; this algorithm uses the hanan grid, which can better reflect the distribution of obstacles and has fewer grid numbers, thus accelerating the path search speed.

[0037] (2) If the adjacent escape traces are in the same group, they are merged for search to obtain better topological similarity and wire length matching.

[0038] (3) A new improved heuristic function based on historical cost is proposed to optimize routability while considering wiring congestion;

[0039] (4) When the heuristic algorithm expands the wiring nodes, it maintains a cross judgment stack to increase the solution search space and better update the search path.

[0040] Experimental results show that this algorithm can obtain better wiring results in a relatively short time and has good generality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is the flowchart of the method of the present invention.

[0042] Figure 2 is the schematic diagram of the merged search of the same group of nets.

[0043] Figure 3 is the schematic diagram of the crossing in the 2D path search.

[0044] Figure 4 is the effect diagram of the dynamic wire breaking and re-routing of the cross judgment stack.

[0045] Figure 5 is the schematic diagram of the 3D path search result. DETAILED DESCRIPTION OF THE INVENTION

[0046] The technical solution of the present invention will be specifically described below in conjunction with the drawings.

[0047] The present invention provides a 3D area wiring method for PCB based on an improved A* algorithm, including:

[0048] Step S1, construct a wiring queue according to the ordered escape wiring result to determine the wiring order;

[0049] Step S2: Construct a Hanan grid graph based on the ordered escape routing result, and initialize the obstacles on the PCB board; convert the area routing problem into an area routing path search problem;

[0050] Step S3: Use the improved 2DA* algorithm to search for the escape routing nets on the same layer;

[0051] Step S4: Use the improved 3DA* algorithm to search for the escape routing nets on the same layer and the cross-layer escape routing nets that fail to find a search path.

[0052] The following is the specific implementation process of the present invention.

[0053] As Figure 1 shown, this embodiment provides a 3D area routing method for PCB based on the improved A* algorithm, including the following steps:

[0054] Step S1: Construct a routing queue according to the ordered escape routing result, and determine the routing order;

[0055] Step S2: Construct a Hanan grid graph according to the ordered escape routing result, and initialize the obstacles. Convert the area routing problem into a path search problem;

[0056] Step S3: Use the improved 2DA* algorithm to search for the escape routing nets on the same layer;

[0057] Step S4: Use the improved 3DA* algorithm to search for the escape routing nets on the same layer and the cross-layer escape routing nets that fail to find a search path.

[0058] Furthermore, in step S1,

[0059] Use a cost estimation function to calculate the routing order priority of each net. The calculation method is as follows:

[0060] P N = ω * D N + γP b

[0061]

[0062] Wherein, P N is the routing order priority of the net, D N is the estimated cost distance between the estimated starting point v s and the estimated ending point v t of the net area routing, P b is the number of nets in the group where the net is located. The more the number of nets in the group, the higher the priority; d max (v s , v t) represents the larger value of the horizontal and vertical distances between the estimated starting point and the estimated ending point of the regional routing, d min (v s ,v t ) represents the smaller value of the horizontal and vertical distances between the estimated starting point and the estimated ending point of the regional routing, min represents taking the smaller value, and max represents taking the larger value. respectively represent the s horizontal and vertical coordinates of v respectively represent the t horizontal and vertical coordinates of v

[0063] Further, in step S2,

[0064] For obstacles on the PCB board such as devices, pads, vias, etc., after considering the minimum distance between the obstacle and the trace, they are represented in the form of a rectangular bounding box. Then, each point of the obstacle rectangle is extended horizontally or vertically until the extension line touches the boundary of other devices or the boundary of the PCB board. The intersection of the extension lines generates the initial edges and the initial surface. Then, the initial surface is merged or divided to eliminate the too large, too small, and narrow initial surfaces. The edges of the surface after merging or dividing are used for subsequent routing. For the edges on the obstacle rectangle, they are marked as obstacle edges, and the fluxes of the remaining edges are calculated normally. The flux size is the Euclidean distance between the endpoints of the edge.

[0065] Further, in step S3,

[0066] When searching for the regional routing path of the escape result, if it is detected that the trace of the net is in the same group as the adjacent escape trace net, the traces of the two nets are merged for path search, so as to better meet the wire length matching constraint and the topological similarity constraint. As Figure 2 shown, the escape routing search paths of n1, n2, and n3 are adjacent and belong to the same group of nets, and the escape routing search paths of n4, n5, and n6 are adjacent and belong to the same group of nets. Then, n1, n2, and n3 can be merged for path search, and n4, n5, and n6 can be merged for path search.

[0067] The improved 2DA* algorithm is used for 2D path search. The calculation method is as follows:

[0068] f(x) = g(x) + h(x)

[0069] The estimated cost h(x) to the target point is calculated as follows:

[0070]

[0071] where, vx is the current node, v t is the target node; d max (v x , v t ) represents the larger value of the horizontal and vertical distances between the current node of the regional routing and the target node of the regional routing, d min (v x , v t ) represents the smaller value of the horizontal and vertical distances between the current node of the regional routing and the target node of the regional routing, min represents taking the smaller value, and max represents taking the larger value. respectively represent the x horizontal and vertical coordinates of v respectively represent the t horizontal and vertical coordinates of v

[0072] The actual usage cost g(x) is calculated as follows:

[0073]

[0074] Among them, ε, η, μ are weights defined by the algorithm, C w1 is the cost of the cumulative routed wire length, which is the sum of the Euclidean distances of the routed nodes, C bend is the cost proportional to the number of routing corners. len is the length of the current channel. To prevent routing congestion, it is set to preferentially route through the channel with a larger len value, C direction represents the cost of the current node in different directions. It is set to preferentially select the node tending to the direction of the target point.

[0075] In the improved 2D A* algorithm for searching paths, if there is an intersection with the existing routed wires when reaching the next node, the improved 2D A* algorithm will not directly abandon the path, but maintain an intersection judgment stack for this path to handle intersections and perform dynamic wire breaking and re-routing and judge whether the path search result meets the requirements. The operation method is as follows: If the current stack is empty or the wire network of the existing routed wire being crossed is different from the wire network of the crossed path recorded at the top of the stack, then record the wire network of the existing routed wire being crossed and push it onto the stack. If it is the same as the wire network of the crossed path recorded at the top of the stack, then pop the wire network of the crossed path recorded at the top of the stack. If the search is successful finally, update the path between the two intersections of this wire network and the wire network being crossed. When the target node is searched, if the stack is empty, it means that the path to the target node is successfully searched. The stack capacity can be limited to control the search scope and complexity. The size of the stack capacity will affect the path search result and path search time to a certain extent. Such as Figure 3As shown, n3 is the wire routing path that has been successfully searched. When n2 is searched, it crosses the n2 path for the first time on the left. At this time, the intersection judgment stack is empty. Therefore, n2 is pushed onto the stack, and the intersection point is recorded. When searching for the right intersection, the wire routing network that has been crossed at this time is n2, which is the same as the network at the top of the stack. Then, the top of the stack is popped. After the path search is successful, the paths of n2 and n3 between the two intersections are swapped. This operation is the dynamic wire breaking and rerouting technology. After the swap, the Figure 4 path search effect shown is obtained.

[0076] Furthermore, in step S4;

[0077] For the nodes where the search fails or the cross-layer connection nodes in step S3, the improved 3D A* algorithm is used for search. The improved 3D A* algorithm uses the method of dynamically inserting vias to search for the cross-layer path. Its cost estimation function is calculated as follows:

[0078]

[0079] Z(v c ,v t )=C l (lay c -lay t |)

[0080] where h(x) represents the estimated cost to the target point, v x is the current node, v t is the target node, d max (v x ,v t ) represents the larger value of the horizontal and vertical distances between the current node of the regional wiring and the target node of the regional wiring, d min (v x ,v t ) represents the smaller value of the horizontal and vertical distances between the current node of the regional wiring and the target node of the regional wiring, Z(v x ,v t ) represents the estimated cross-layer cost, lay x and lay t represent the layer where the current node is located and the layer where the target node is located respectively, C l is the weight defined by the algorithm; the improved 2D A* algorithm is used for the same-layer search after cross-layer

[0081] . The same-layer search after cross-layer adopts the same process as in step S3. In Figure 5 , the path of wire network n3 has been successfully searched. The wire network n1 is the cross-layer connection node to be connected, and the wire network n2 is the same-layer connection node where the search path fails. The search path results of n1 and n2 using the improved 3D A* algorithm are as Figure 5 shown.

[0082] The above are the preferred embodiments of the present invention. All changes made according to the technical solution of the present invention, as long as the functions and effects produced do not exceed the scope of the technical solution of the present invention, shall fall within the protection scope of the present invention.

Claims

1. A PCB three-dimensional area wiring method based on an improved A* algorithm, characterized in that: include: Step S1, constructing a routing queue and determining a routing order according to the orderly escape routing result; Step S2, constructing a Hanan grid map according to the orderly escape routing results, and initializing obstacles on the PCB board; converting the regional routing problem into a regional routing path search problem; Step S3, using the improved 2D A* algorithm to search for escape wiring nets located on the same layer; Step S4: Use the improved 3D A* algorithm to search for the same-layer escape routing nets and cross-layer escape routing nets for which the search path fails.

2. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1, characterized in that: In step S1, a cost estimation function is used to calculate the routing order priority of each net.

3. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 2, characterized in that: The specific calculation method for calculating the wiring order priority of each network using the cost estimation function is as follows: P N =ω*D N +γP b Among them, P N is the wiring order priority of the wire net, D N Estimated starting point v for wiring in the network area s And the estimated termination point of the wire net area wiring v t The estimated cost distance between b The number of networks in the group to which the network belongs. The more networks there are in the group, the higher the priority. max (v s ,v t ) represents the larger value of the horizontal and vertical distances between the estimated starting point of the area wiring and the estimated ending point of the area wiring, d min (v s ,v t ) represents the smaller value of the horizontal and vertical distances between the estimated starting point of the area wiring and the estimated ending point of the area wiring. Min represents the smaller value, and max represents the larger value. Respectively represent v s The horizontal and vertical coordinates of Respectively represent v t ; ω and γ are the fixed weights set respectively, which are used to balance the importance of the two parameters in determining the final wiring order priority of the wire network.

4. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1, characterized in that: In step S2, the obstacles on the PCB are represented in the form of rectangular bounding boxes after considering the minimum spacing between the obstacles and the traces; then each point of the obstacle rectangle is extended horizontally or vertically until the extension line touches the boundary of other obstacle rectangular bounding boxes or the boundary of the PCB board; The intersection of the extended lines generates initial edges and initial faces; the initial faces are then merged or divided to eliminate initial faces that are too large, too small, or narrow, and the edges of the merged or divided faces are used for subsequent wiring; for the edges in the composition, if the edge is located on the obstacle rectangular bounding box, it is marked as an obstacle edge, otherwise its flux is calculated normally, and the flux size is the Euclidean distance between the edge endpoints.

5. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 4 is characterized in that: Obstacles on the PCB include components, pads, and through holes.

6. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1, characterized in that: When searching for a regional wiring path for a wire net, if it is detected that the corresponding wire net and the adjacent escape routing wire net belong to the same group, the two wire nets are merged for path search.

7. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1, characterized in that: Improve the 2DA* algorithm as follows: f(x)=g(x)+h(x) The estimated cost h(x) to reach the target point is calculated as follows: Among them, v x is the current node, v t is the target node; d max (v x ,v t ) represents the larger value of the horizontal and vertical distance between the current node and the target node of the regional wiring, d min (v x ,v t ) represents the smaller value of the horizontal and vertical distances between the current node and the target node of the regional wiring. Min represents the smaller value, and max represents the larger value. Respectively represent v x The horizontal and vertical coordinates of Respectively represent v t The horizontal and vertical coordinates of The actual usage cost g(x) is calculated as follows: in, ε, η, μ are weights defined by the algorithm, C w1 The cost of the accumulated route length is the sum of the Euclidean distances of the nodes that have been traveled, C bend is the cost proportional to the number of routing corners, len is the length of the current channel, and in order to prevent routing congestion, the channel with a large len value is set to take priority. direction Represents the cost of the current node in different directions, and sets the priority to select nodes that tend to the target point; When the improved 2D A* algorithm searches for a path, if it crosses an existing route when reaching the next node, the improved 2D A* algorithm will not abandon the corresponding path directly, but will maintain a cross judgment stack for the corresponding path to handle the crossover and perform dynamic line removal and rerouting and judge whether the path search result meets the requirements.

8. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 7, characterized in that: A cross judgment stack is maintained for the corresponding path to handle crossovers and perform dynamic wire removal and rerouting and to determine whether the path search results meet the requirements. The specific operation methods are as follows: If the current stack is empty or the crossed existing routing network is different from the cross-path network recorded at the top of the stack, the crossed existing routing network will be recorded and pushed into the stack; if it is the same as the cross-path network recorded at the top of the stack, the cross-path network recorded at the top of the stack will be popped out, and if the final search is successful, the path between the two intersections of the corresponding network and the crossed network will be updated; when the target node is searched, if the stack is empty, the path to the target node is successfully searched; the stack capacity is limited to control the search range and complexity. The stack capacity will affect the path search results and path search time.

9. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1, characterized in that: In step S4, the improved 3D A* algorithm uses a method of dynamically inserting vias to perform cross-layer path search.

10. The PCB three-dimensional area wiring method based on the improved A* algorithm according to claim 1 or 9, characterized in that: In step S4, the cost estimation function of the improved 3D A* algorithm is calculated as follows: Among them, h(x) represents the estimated cost to reach the target point, v x is the current node, v t is the target node, d max (v x ,v t ) represents the larger value of the horizontal and vertical distance between the current node and the target node of the regional wiring, d min (v x ,v t ) represents the smaller value of the horizontal and vertical distances between the current node and the target node of the regional wiring. Z(v x ,v t ) represents the estimated cross-layer cost, lay x and lay t Represent the layer where the current node is located and the layer where the target node is located, C l Define weights for the algorithm; the improved 2DA* algorithm is used for the same-layer search after cross-layer.

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