Method and system for checking Boolean operation, computer program product and device

Abstract

The invention relates to the technical field of semiconductor manufacturing, and provides a Boolean operation checking method and system, a computer program product and a device. The method comprises the following steps: establishing a mapping relationship between all semiconductor devices of a research and development platform and a target Mask layer, and generating a verification script; processing the original layout by adopting the Boolean operation to be inspected, and reserving or generating an identification layer for identifying the semiconductor device in the processing process; and running the verification script, and comparing all the actual Mask layers of the semiconductor device extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relation one by one so as to judge whether the Boolean operation to be checked is correct or not and judge the position where an error occurs. According to the method, whether Boolean operation is correct or not and the position where an error occurs can be accurately judged, and JDV reworking and even Mask layer reworking caused by manual misjudgment are avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method and system for verifying Boolean operations, a computer program product, and a device. Background Art

[0002] In the process of tape out of a chip, it is necessary to transfer the graphic information (CAD Layer) on the design layout to the mask layer for manufacturing the corresponding mask layer. To relieve the drawing pressure of layout designers, the foundry will use Boolean operation to generate some graphic information from the existing graphics. However, in the initial stage of platform development, the verification of Boolean operations is all carried out by human eyes. Facing the complex graphics on the layout, it is easy to check insufficiently and misjudge that the Boolean operation is correct, resulting in rework of the job deck view (JDV) or even re-generation of the mask layer. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method and system for verifying Boolean operations, a computer program product, and a device, which can accurately judge whether the Boolean operation is correct and the position where the error occurs, and avoid the occurrence of JDV rework or even mask layer re-generation caused by human misjudgment.

[0004] To solve the above problems, the present invention provides a method for verifying Boolean operations, including the following steps: establishing a mapping relationship between all semiconductor devices in the R & D platform and the target mask layer, and generating a verification script; processing the original layout with the Boolean operation to be verified, and retaining or generating an identification layer for identifying semiconductor devices during the processing; and running the verification script, comparing all the actual mask layers of the semiconductor devices extracted according to the identification layer with all the target mask layers corresponding to the semiconductor devices in the mapping relationship one by one to judge whether the Boolean operation to be verified is correct and the position where the error occurs.

[0005] To solve the above problems, the present invention also provides a system for verifying Boolean operations, including: an establishment module for establishing a mapping relationship between all semiconductor devices in the R & D platform and the target mask layer, and generating a verification script; a processing module for processing the original layout with the Boolean operation to be verified, and retaining or generating an identification layer for identifying semiconductor devices during the processing; and an inspection module for running the verification script, comparing all the actual mask layers of the semiconductor devices extracted according to the identification layer with all the target mask layers corresponding to the semiconductor devices in the mapping relationship one by one to judge whether the Boolean operation to be verified is correct and the position where the error occurs.

[0006] To solve the above problems, the present invention also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the above method of the present invention.

[0007] To solve the above problems, the present invention also provides a computer device, including a memory for storing a computer program; a processor connected to the memory for executing the computer program to implement the steps of the above method of the present invention.

[0008] In the above technical solution, by establishing a mapping relationship between all semiconductor devices on the R & D platform and the target Mask layer and generating a verification script, using the Boolean operation to be tested to process the original layout and retaining or generating an identification layer for identifying semiconductor devices during the processing, running the verification script, and comparing all the actual Mask layers of the semiconductor devices extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor devices in the mapping relationship one by one, it can accurately determine whether the Boolean operation to be tested is correct and the location where an error occurs, avoiding the occurrence of JDV rework or even Mask layer re-generation caused by human misjudgment. The method for verifying Boolean operations provided by the present invention is applicable not only to the verification of Boolean operations on an independently developed technology platform but also to the verification of Boolean operations in technology transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0010] Figure 1 It is a flowchart of the method for verifying Boolean operations provided by an embodiment of the present invention;

[0011] Figure 2 It is a schematic diagram of the system for verifying Boolean operations provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments.

[0013] Boolean Operation refers to a logical operation based on Boolean algebra. It takes logical values (true or false) as operands and performs logical operations through logical operators. Boolean operations can be applied between different geometric bodies to create new geometric bodies through logical operators. Commonly used Boolean operators include Union, Intersection, Difference, etc. Boolean operations can be used for the combination of geometric bodies. When two or more geometric bodies need to be merged into a new geometric body, the Union operation of Boolean operations can be used. Boolean operations can also be used for the division of geometric bodies. When a specific-shaped part needs to be extracted from a geometric body, the Intersection operation of Boolean operations can be used. Boolean operations can also be used for the modification of geometric bodies. When a specific-shaped part needs to be cut or removed from a geometric body, the Difference operation of Boolean operations can be used. Compared with traditional manual operations, Boolean operations have many advantages: (1) Boolean operations can quickly and efficiently achieve the combination, division, and modification of geometric bodies; (2) Boolean operations can ensure the accuracy and consistency of geometric bodies; (3) Boolean operations have good editability.

[0014] In the process of chip tape out, Boolean operations can be used to generate some graphic information (CAD Layer) from existing graphics to relieve the drawing pressure on layout designers. However, the verification method of checking Boolean operations by human eyes adopted in the initial stage of platform development is prone to insufficient inspection, resulting in rework of the view drawing file service (JDV) and even re-generation of the Mask layer. Therefore, the present invention proposes a method for verifying Boolean operations, which can accurately judge whether the Boolean operation is correct and the location where the error occurs, and avoid the occurrence of JDV rework or even Mask layer re-generation caused by human misjudgment. The method for verifying Boolean operations provided by the present invention is applicable not only to the verification of Boolean operations in an independently developed technology platform but also to the verification of Boolean operations in technology transfer.

[0015] Please refer to Figure 1 , which is a flowchart of the method for verifying Boolean operations provided by an embodiment of the present invention. As Figure 1 shown, the method for verifying Boolean operations described in this embodiment includes the following steps: S1, establish the mapping relationship between all semiconductor devices in the R & D platform and the target Mask layer, and generate a verification script; S2, process the original layout using the Boolean operation to be verified, and retain or generate an identification layer for identifying semiconductor devices during the processing; and S3, run the verification script, and compare all the actual Mask layers of the semiconductor devices extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor devices in the mapping relationship one by one to judge whether the Boolean operation to be verified is correct and the location where the error occurs.

[0016] Regarding step S1, establish the mapping relationship between all semiconductor devices on the R & D platform and the target Mask layer, and generate a verification script.

[0017] In this embodiment, the step of establishing the mapping relationship between all semiconductor devices on the R & D platform and the target Mask layer and generating a verification script specifically includes: forming a text composed of a code language based on each semiconductor device and all its corresponding target Mask layers as the verification script, and defining the corresponding relationship between each semiconductor device and all its corresponding target Mask layers in the text.

[0018] Each type of semiconductor device (or semiconductor structure) has a corresponding relationship with the target mask (Mask) layer, and the target Mask layer is directly related to the process flow of the actual process. For example, for an NMOS device, its process flow will include implanting to form a P well and implanting to form an N+ type doping, rather than implanting to form an N well and implanting to form a P+ type doping; the corresponding target Mask layer will only have NWELL and NPLUS. Both NMOS devices and PMOS devices have target Mask layers for forming active regions and polysilicon, but NMOS devices and PMOS devices will also each have their own unique target Mask layers. By summarizing all semiconductor devices on the R & D platform and all their corresponding target Mask layers, the mapping relationship between semiconductor devices and the corresponding target Mask layers can be established, and a verification script can be generated. Based on semiconductor devices and all their corresponding target Mask layers, a text composed of a code language similar to Design Rule Check (DRC), Layout versus Schematic (LVS), and Design for Manufacturing (DFM) can be made; by defining the corresponding relationship between semiconductor devices and the target Mask layer in this text, when verifying the layout by running this text, if a certain target Mask layer is missing or a certain actual Mask layer is extra, an error will be reported in the layout.

[0019] Regarding step S2, process the original layout using the Boolean operation to be tested, and retain or generate an identification layer for identifying semiconductor devices during the processing.

[0020] The original layout is a graph drawn according to a pre-provided device truth table, and each semiconductor device in the device truth table has a uniquely corresponding identification layer. In theory, after correct Boolean operation processing, the original layout can generate all the corresponding target Mask layers. For example, a designer can draw a graph according to the device truth table provided by a foundry to form the original layout at the beginning of the design. Subsequently, the foundry will process these original layouts and convert the original layouts from the layout to the corresponding actual Mask layers through Boolean operations (after correct Boolean operation processing, the actual Mask layers should be the same as the target Mask layers); various layers required to generate the target Mask layer corresponding to the semiconductor device and the relationships between layers will be defined in the Boolean operation; the identification layer of the semiconductor device can be retained or generated during the Boolean operation process. Each semiconductor device in the device truth table provided by the foundry will have a corresponding identification layer; for example, a 2.5V MOS will have a 2.5V identification layer, and a triode will have a triode identification layer. When drawing the original layout, in addition to some basic layers, a dedicated identification layer will also be covered on the semiconductor device to be used to identify the semiconductor device.

[0021] In this embodiment, the steps of using the Boolean operation to be tested to process the original layout and retaining or generating the identification layer for identifying the semiconductor device during the processing specifically include: (21) defining various layers required to generate the target Mask layer and the relationships between layers in the Boolean operation to be tested; (22) using the Boolean operation to be tested to process the original layout, converting the original layout into the actual Mask layer, and retaining or generating the identification layer during the processing.

[0022] Regarding step S3, running the verification script, all the actual Mask layers of the semiconductor device extracted according to the identification layer will be compared one by one with all the target Mask layers corresponding to the semiconductor device in the mapping relationship to determine whether the Boolean operation to be tested is correct and the location where the error occurs.

[0023] In this embodiment, the steps of running the verification script and comparing all the actual Mask layers of the semiconductor device extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relationship specifically include: (311) extracting all the actual Mask layers in the area covered by the identification layer of the semiconductor device; (312) running the verification script using an EDA tool and comparing all the actual Mask layers extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relationship one by one.

[0024] Each semiconductor device will have a corresponding target Mask layer, and these target Mask layers will determine whether the process can successfully fabricate the semiconductor device. Each semiconductor device will have a unique corresponding identification layer, and the identification layer serves as an identifier for identifying the semiconductor device. By capturing the identification layer, the actual Mask levels of the semiconductor device can be obtained; then, by running the verification script, it can be determined whether the semiconductor device has multiple or fewer layers. The verification script can be run through Calibre in the EDA tool, and the running method is similar to that of design rule check (DRC), layout versus schematic Figure 1 verification (LVS), and design for manufacturability (DFM). Calibre is a comprehensive physical verification system mainly used for the verification of integrated circuit (IC) design; Calibre is widely regarded as one of the leading design rule check (DRC), layout versus schematic Figure 1 verification (LVS), and design for manufacturability (DFM) tools.

[0025] In this embodiment, the steps of determining whether the boolean operation to be tested is correct and the location where the error occurs specifically include: (321) If all the target Mask layers of the semiconductor device have the actual Mask layers with an intersection of the first value, it means that all the target Mask layers of the semiconductor device exist, and it is determined that the boolean operation to be tested is correct; (322) If there is an intersection of the target Mask layer of the semiconductor device and all the actual Mask layers of the semiconductor device that is the second value, it means that the target Mask layer of the semiconductor device is missing, and it is determined that the boolean operation to be tested has an error and the location where the error occurs is the missing target Mask layer. Here, the second value is different from the first value; for example, the first value is 1 and the second value is 0.

[0026] The following takes the NPN bipolar junction transistor (Bipolar Junction Transistor, abbreviated as BJT, also known as a triode) as an example for further explanation. All the target Mask layers of the triode are NPLUS, PWELL, and DNW; assume that the identification layer of the triode is BJT, and an intersection of 1 represents the existence of the corresponding Mask layer, and an intersection of 0 represents the non-existence of the corresponding Mask layer.

[0027] Assume that all the actual Mask layers of the triode extracted according to the identification layer BJT have PWELL and DNW. The target Mask layer PWELL and the target Mask layer DNW of the triode both have the actual Mask layers with an intersection of 1, indicating that both the target Mask layer PWELL and the target Mask layer DNW of the triode exist; while the target Mask layer NPLUS of the triode does not have the actual Mask layers with an intersection of 1 (that is, the intersection of the target Mask layer NPLUS of the triode and all the actual Mask layers of the triode is 0), indicating that the target Mask layer NPLUS of the triode does not exist; then it is determined that the boolean operation to be tested has an error and the position where the error occurs is the missing target Mask layer NPLUS. That is, NPLUS is the target Mask layer required by the triode. When running the verification script to verify its non-existence, it is determined that the boolean operation to be tested has an error and the position where the error occurs is the missing target Mask layer NPLUS.

[0028] Continuing with the above embodiment, the step of determining whether the boolean operation to be tested is correct and the position where the error occurs further includes: (323) If there is an actual Mask layer of the semiconductor device whose intersection with all the target Mask layers of the semiconductor device is the second value, indicating that the actual Mask layer of the semiconductor device is redundant, then it is determined that the boolean operation to be tested has an error and the position where the error occurs is the redundant actual Mask layer.

[0029] Still taking the NPN-type triode as an example for further explanation. All the target Mask layers of the triode are NPLUS, PWELL, and DNW; assume that the identification layer of the triode is BJT, an intersection of 1 represents the existence of the corresponding Mask layer, and an intersection of 0 represents the non-existence of the corresponding Mask layer.

[0030] Assume that all the actual Mask layers of the triode extracted according to the identification layer BJT are LDD, PWELL, and DNW. The intersection of the actual Mask layer LDD of the triode with all the target Mask layers (NPLUS, PWELL, and DNW) of the triode is 0, indicating that the actual Mask layer LDD of the triode is redundant, then it is determined that the boolean operation to be tested has an error and the position where the error occurs is the redundant actual Mask layer LDD. That is, LDD is the actual Mask layer not required by the triode. When running the verification script to verify its existence, it is determined that the boolean operation to be tested has an error and the position where the error occurs is the redundant actual Mask layer LDD.

[0031] In this embodiment, the method further includes: S4. Obtain the hierarchical comparison difference result and generate a report or a display interface according to the hierarchical comparison difference result to show whether the Boolean operation is correct and the location where an error occurs. When running the verification script, if the intersection of the target Mask layer and the actual Mask layer is 1, no error will be reported; if the intersection of the target Mask layer and / or the actual Mask layer is 0, an error will be reported. Whether there is an error can be used to determine whether there are multiple layers or fewer layers: if the intersection of the target Mask layer is 0, it is determined that there are fewer layers; if the intersection of the actual Mask layer is 0, it is determined that there are multiple layers. Obtain the judgment result of running the verification script as the hierarchical comparison difference result, and generate a report or a display interface (such as an RVE interface) according to the hierarchical comparison difference result to visually present the correctness of the Boolean operation or the location where an error occurs.

[0032] Based on the same inventive concept, the present invention also provides a system for verifying Boolean operations, which can implement the above method for verifying Boolean operations of the present invention, accurately determine whether the Boolean operation is correct and the location where an error occurs, and avoid the occurrence of JDV rework or even the re-generation of the Mask layer caused by human misjudgment.

[0033] Please refer to Figure 2 , which is a schematic diagram of a system for verifying Boolean operations provided by an embodiment of the present invention. As Figure 2 shown, the system described in this embodiment includes: a building module 21, a processing module 22, and an inspection module 23.

[0034] Specifically, the building module 21 is used to establish the mapping relationship between all semiconductor devices on the R & D platform and the target Mask layer, and generate a verification script; the processing module 22 is used to process the original layout with the Boolean operation to be inspected, and retain or generate an identification layer for identifying semiconductor devices during the processing; the inspection module 23 is used to run the verification script, and compare all the actual Mask layers of the semiconductor devices extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor devices in the mapping relationship one by one to determine whether the Boolean operation to be inspected is correct and the location where an error occurs.

[0035] In this embodiment, the system further includes: a display module 24; the display module 24 is used to obtain the hierarchical comparison difference result and generate a report or a display interface according to the hierarchical comparison difference result to show whether the Boolean operation is correct and the location where an error occurs.

[0036] It should be noted that the above building module 21, processing module 22, inspection module 23, and display module 24 correspond to Figure 1For steps S1 to S4, the instances and application scenarios implemented by each module and the corresponding steps are the same, but are not limited to the content disclosed in the above embodiments. Each of the above modules can run in the corresponding computer terminal as a part of the system.

[0037] In the above embodiments, by establishing the mapping relationship between all semiconductor devices on the R & D platform and the target Mask layer and generating a verification script, using the boolean operation to be tested to process the original layout and retaining or generating an identification layer for identifying semiconductor devices during the processing, running the verification script, and comparing all the actual Mask layers of the semiconductor devices extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor devices in the mapping relationship one by one, it is possible to accurately determine whether the boolean operation to be tested is correct and the location where an error occurs, avoiding the occurrence of JDV rework or even Mask layer re-generation caused by human misjudgment. The method for verifying boolean operations provided by the present invention is applicable not only to the verification of boolean operations in an independently developed technology platform but also to the verification of boolean operations in technology transfer.

[0038] Based on the same inventive concept, the present invention also provides a computer program product, including a computer program, which when executed by a processor implements the steps of the method of the present invention described above.

[0039] Based on the same inventive concept, the present invention also provides a computer device, including: a memory for storing a computer program; a processor connected to the memory for executing the computer program to implement the steps of the method of the present invention described above.

[0040] Based on the same inventive concept, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the steps of the method of the present invention described above.

[0041] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus (Ram Bus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0042] It should be noted that in the above embodiments, each embodiment focuses on the differences from other embodiments. For the same / similar parts among the embodiments, reference can be made to each other.

[0043] The terms "including" and "having" and their variants involved in the documents of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context and can be used to describe a feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or features in a plural sense. The term "based on" can be understood as not necessarily aiming to express a set of exclusive factors, but instead, also at least in part depending on the context, allowing the existence of other factors that may not be explicitly described. Additionally, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention.

[0044] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A method for checking a Boolean operation, characterized in that: The steps include: Establish the mapping relationship between all semiconductor devices and the target Mask layer of the R&D platform, and generate a verification script; use the Boolean operation to be verified to process the original layout, and retain or generate an identification layer for identifying semiconductor devices during the processing; as well as Run the verification script to compare all actual Mask layers of the semiconductor device extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relationship one by one to determine whether the Boolean operation to be verified is correct and the location where the error occurs.

2. The method according to claim 1, characterized in that The steps of establishing a mapping relationship between all semiconductor devices of the R&D platform and the target Mask layer and generating a verification script specifically include: A text composed of a code language is formed based on each semiconductor device and all corresponding target Mask layers as the verification script, and the corresponding relationship between each semiconductor device and all corresponding target Mask layers is defined in the text.

3. The method according to claim 1, characterized in that The original layout is a diagram drawn according to a pre-provided device truth table, and each semiconductor device in the device truth table has a unique corresponding identification layer.

4. The method according to claim 1, characterized in that: The steps of processing the original layout using the Boolean operation to be tested and retaining or generating a marking layer for identifying the semiconductor device during the processing specifically include: In the Boolean operation to be checked, various levels and relationships between layers required to generate the target Mask layer are defined; The original layout is processed by using the Boolean operation to be checked, the original layout is converted into the actual Mask layer, and the identification layer is retained or generated during the processing.

5. The method according to claim 1, characterized in that The step of running the verification script to compare all actual Mask layers of the semiconductor device extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relationship specifically includes: Extracting all the actual Mask layers in the area covered by the identification layer of the semiconductor device; The verification script is run using an EDA tool to compare all the actual Mask layers extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor devices in the mapping relationship.

6. The method according to claim 1, characterized in that The step of determining whether the Boolean operation to be checked is correct and the location where the error occurs specifically includes: If all the target Mask layers of the semiconductor device have the actual Mask layers whose intersection is the first value, it means that all the target Mask layers of the semiconductor device exist, and it is determined that the Boolean operation to be checked is correct; If the intersection of the target Mask layer of the semiconductor device and all the actual Mask layers of the semiconductor device is a second value, indicating that the target Mask layer of the semiconductor device is missing, it is determined that an error occurs in the Boolean operation to be checked and the location where the error occurs is the missing target Mask layer, wherein the second value is different from the first value.

7. The method according to claim 6, characterized in that The step of determining whether the Boolean operation to be checked is correct and the location where the error occurs also includes: If the intersection of the actual Mask layer of the semiconductor device and all the target Mask layers of the semiconductor device is the second value, it means that the actual Mask layer of the semiconductor device is extra, then it is determined that the Boolean operation to be checked has an error and the location where the error occurs is the extra actual Mask layer.

8. The method according to claim 1, characterized in that: The method further comprises: Obtain the hierarchical comparison difference result and generate a report or a display interface according to the hierarchical comparison difference result to show whether the Boolean operation is correct and the location where the error occurs.

9. A system for checking Boolean operations, characterized in that: include: Establish a module to establish the mapping relationship between all semiconductor devices on the R&D platform and the target Mask layer, and generate a verification script; A processing module, used for processing the original layout using the Boolean operation to be checked, and retaining or generating a marking layer for identifying the semiconductor device during the processing; as well as A verification module is used to run the verification script to compare all actual Mask layers of the semiconductor device extracted according to the identification layer with all the target Mask layers corresponding to the semiconductor device in the mapping relationship one by one to determine whether the Boolean operation to be verified is correct and the location where the error occurs.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer device, characterized in that: include: Memory for storing computer programs; A processor, connected to the memory, is used to execute the computer program to implement the steps of the method according to any one of claims 1 to 8.

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