Gate driving circuit, driving method of gate driving circuit and display device

Abstract

The embodiment of the invention provides a gate driving circuit, a driving method of the gate driving circuit and a display device, the gate driving circuit comprises M stages of cascaded shift register units, and each stage of shift register unit comprises a display input sub-circuit, a first inverting sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit and an output sub-circuit; the first anti-phase sub-circuit comprises an eighteenth transistor, a thirtieth transistor, a nineteenth transistor, a twenty-seventh transistor and a twenty-eighth transistor; the second end of the twenty-seventh transistor is connected with a target signal end; wherein under the condition that the first pull-up node is high in potential, the target signal end outputs a high-potential signal to the second end of the twenty-seventh transistor, and the potential of the high-potential signal output by the target signal end is larger than that of the first constant-voltage high-potential end. The electric leakage phenomenon of the first anti-phase sub-circuit in the shift register unit is improved, and the reliability of the gate drive circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a gate driving circuit, a driving method for the gate driving circuit, and a display device. Background Art

[0002] In the current shift register unit of a gate driver on array (GOA), as Figure 1 shown, when the Q(N) point is at a high potential, there is a leakage path in the inverter sub-circuit: VDD - M18_1 - M18_2 - M27 - VGL1. At this time, M18_1, M18_2, and M27 are all in the conducting state, so there is a leakage between VDD and VGL1, and current will pass through, which may cause the burnout of the transistor. Therefore, how to improve the leakage phenomenon of the inverter sub-circuit in the shift register unit has become an urgent problem to be solved. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a gate driving circuit, a driving method for the gate driving circuit, and a display device to improve the leakage phenomenon of the first inverter sub-circuit in the shift register unit. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of the present application provide a gate driving circuit, including M cascaded shift register units, where M is an integer greater than 1, and each shift register unit includes:

[0005] a display input sub-circuit, a first inverter sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit, and an output sub-circuit;

[0006] The display input sub-circuit is configured to receive a display input signal through a display input terminal and input a display pull-up signal to a first pull-up node during a display period of one frame according to the display input signal;

[0007] The first inverter sub-circuit is configured to control the potential of a pull-down node according to the first pull-up node, so that the potential of the first pull-up node is opposite to the potential of the pull-down node;

[0008] The first pull-down sub-circuit is configured to pull down the potential of the first pull-up node under the control of the pull-down node;

[0009] The second pull-down sub-circuit is configured to pull down the potential of the output terminal of the output sub-circuit under the control of the pull-down node;

[0010] The output sub-circuit is configured to output a first shift signal through its own shift signal output terminal and output a first pixel signal through its own pixel signal output terminal under the control of the first pull-up node;

[0011] The first inverter sub - circuit includes an eighteenth transistor, a thirtieth transistor, a nineteenth transistor, a twenty - seventh transistor, and a twenty - eighth transistor;

[0012] The control terminal of the eighteenth transistor is respectively connected to the first constant - voltage high - potential terminal, the first terminal of the eighteenth transistor, and the control terminal of the thirtieth transistor. The second terminal of the eighteenth transistor is connected to the first terminal of the thirtieth transistor. The second terminal of the thirtieth transistor is respectively connected to the control terminal of the nineteenth transistor and the first terminal of the twenty - seventh transistor. The first terminal of the nineteenth transistor is connected to the first constant - voltage high - potential terminal. The second terminal of the nineteenth transistor is respectively connected to the first terminal of the twenty - eighth transistor and the pull - down node. The control terminal of the twenty - eighth transistor is connected to the first pull - up node, and the second terminal of the twenty - eighth transistor is connected to the first constant - voltage low - potential terminal. The control terminal of the twenty - seventh transistor is connected to the first pull - up node, and the second terminal of the twenty - seventh transistor is connected to the target signal terminal;

[0013] Wherein, when the first pull - up node is at a high potential, the target signal terminal outputs a high - potential signal to the second terminal of the twenty - seventh transistor, and the potential of the high - potential signal output by the target signal terminal is greater than the potential of the first constant - voltage high - potential terminal.

[0014] In a second aspect, an embodiment of the present application further provides a gate driving circuit, including M cascaded shift - register units, where M is an integer greater than 1. Each shift - register unit includes:

[0015] A display input sub - circuit, a second inverter sub - circuit, a first pull - down sub - circuit, a second pull - down sub - circuit, and an output sub - circuit;

[0016] The display input sub - circuit is configured to receive a display input signal through a display input terminal and input a display pull - up signal to the first pull - up node during the display period of one frame according to the display input signal;

[0017] The second inverter sub - circuit is configured to control the potential of the pull - down node according to the first pull - up node, so that the potential of the first pull - up node is opposite to the potential of the pull - down node;

[0018] The first pull - down sub - circuit is configured to pull down the potential of the first pull - up node under the control of the pull - down node;

[0019] The second pull - down sub - circuit is configured to pull down the potential of the output terminal of the output sub - circuit under the control of the pull - down node;

[0020] The output sub - circuit is used to output a shift signal through its own shift - signal output terminal and output a pixel signal through its own pixel - signal output terminal under the control of the first pull - up node;

[0021] The second inverter sub - circuit includes a thirty - first transistor and a thirty - second transistor;

[0022] The control terminal of the thirty - first transistor is respectively connected to the first end of the thirty - first transistor and the first constant high - voltage terminal. The second end of the thirty - first transistor is respectively connected to the first end of the thirty - second transistor and the pull - down node. The control terminal of the thirty - second transistor is connected to the first pull - up node, and the second end of the thirty - second transistor is connected to the target signal terminal;

[0023] Wherein, when the first pull - up node is at a high potential, the target signal terminal outputs a high - potential signal to the second end of the thirty - second transistor, and the potential of the high - potential signal output by the target signal terminal is greater than the potential of the first constant high - voltage terminal.

[0024] In a possible implementation manner, the target signal terminal is a shift - signal output terminal; or, the target signal terminal is a pixel - signal output terminal; or, the target signal terminal is the first pull - up node.

[0025] In a possible implementation manner, the shift - register unit further includes: a blanking input sub - circuit;

[0026] The blanking input sub - circuit is used to receive a blanking input signal through a blanking input terminal and input a blanking pull - up signal to the first pull - up node during the blanking period of one frame according to the blanking input signal;

[0027] The output sub - circuit is further used to output a second shift signal through its own shift - signal output terminal and output a second pixel signal through its own pixel - signal output terminal under the control of the first pull - up node.

[0028] In a possible implementation manner, the blanking input sub - circuit includes:

[0029] A charging module, a storage module, and an isolation module;

[0030] The charging module is used to input the blanking input signal to a blanking pull - up control node according to the blanking input signal;

[0031] The storage module is used to store the blanking pull - up signal; wherein, one end of the storage module is connected to the blanking pull - up control node;

[0032] The isolation module is used to input the blanking pull - up signal to the first pull - up node during the blanking period of one frame.

[0033] In a possible implementation, the shift register unit further includes: a display reset sub-circuit, a blanking reset sub-circuit, a third pull-down sub-circuit, and a fourth pull-down sub-circuit;

[0034] The display reset sub-circuit is configured to reset the first pull-up node under the control of a display reset control signal;

[0035] The blanking reset sub-circuit is configured to reset the first pull-up node under the control of a blanking reset control signal before the end of the blanking period of a frame;

[0036] The third pull-down sub-circuit is configured to pull down the potential of the pull-down node when the blanking pull-up signal is input to the first pull-up node;

[0037] The fourth pull-down sub-circuit is configured to pull down the potential of the pull-down node when the display pull-up signal is input to the first pull-up node.

[0038] In a possible implementation, the charging module includes a first transistor and a second transistor; the storage module includes a first capacitor; the isolation module includes a third transistor, a fourth transistor, and a fifth transistor;

[0039] The control terminal of the first transistor is respectively connected to the control signal terminal and the control terminal of the second transistor. The first terminal of the first transistor is connected to the blanking input terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor;

[0040] The second terminal of the second transistor is respectively connected to the first terminal of the first capacitor, the blanking pull-up control node, and the control terminal of the third transistor;

[0041] The first terminal of the third transistor is connected to the first clock signal terminal, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor;

[0042] The control terminal of the fourth transistor is respectively connected to the first clock signal terminal and the control terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the first terminal of the fifth transistor;

[0043] The second terminal of the fifth transistor is connected to the first pull-up node.

[0044] In a possible implementation, the display input sub-circuit includes a seventh transistor and an eighth transistor;

[0045] The control terminal of the seventh transistor is respectively connected to the display input terminal, the first terminal of the seventh transistor, and the control terminal of the eighth transistor. The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor;

[0046] The second terminal of the eighth transistor is connected to the first pull-up node.

[0047] In a possible implementation manner, the blanking reset sub-circuit includes a ninth transistor and a tenth transistor;

[0048] The control terminal of the ninth transistor is respectively connected to the blanking reset control signal terminal and the control terminal of the tenth transistor. The first terminal of the ninth transistor is connected to the first pull-up node. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor;

[0049] The second terminal of the tenth transistor is connected to the first constant low potential terminal.

[0050] In a possible implementation manner, the display reset sub-circuit includes a twelfth transistor and a thirteenth transistor;

[0051] The control terminal of the twelfth transistor is respectively connected to the display reset control signal terminal and the control terminal of the thirteenth transistor. The first terminal of the twelfth transistor is connected to the first pull-up node. The second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor;

[0052] The second terminal of the thirteenth transistor is connected to the first constant low potential terminal.

[0053] In a possible implementation manner, the first pull-down sub-circuit includes a fourteenth transistor and a fifteenth transistor;

[0054] The control terminal of the fourteenth transistor is respectively connected to the control terminal of the fifteenth transistor and the pull-down node. The first terminal of the fourteenth transistor is connected to the first pull-up node. The second terminal of the fourteenth transistor is connected to the first terminal of the fifteenth transistor;

[0055] The second terminal of the fifteenth transistor is connected to the first constant low potential terminal.

[0056] In a possible implementation manner, the second pull-down sub-circuit includes a twenty-fourth transistor and a twenty-sixth transistor;

[0057] The control terminal of the twenty-fourth transistor is connected to the pull-down node. The first terminal of the twenty-fourth transistor is connected to the shift signal output terminal. The second terminal of the twenty-fourth transistor is connected to the first constant low potential terminal;

[0058] The control terminal of the twenty-sixth transistor is connected to the pull-down node, the first terminal of the twenty-sixth transistor is connected to the pixel signal output terminal, and the second terminal of the twenty-sixth transistor is connected to the second constant low potential terminal.

[0059] In a possible implementation, the third pull-down sub-circuit includes a twentieth transistor and a twenty-first transistor;

[0060] The control terminal of the twentieth transistor is connected to the first clock signal terminal, the first terminal of the twentieth transistor is connected to the pull-down node, and the second terminal of the twentieth transistor is connected to the first terminal of the twenty-first transistor;

[0061] The control terminal of the twenty-first transistor is connected to the blanking pull-up control node, and the second terminal of the twenty-first transistor is connected to the first constant low potential terminal.

[0062] In a possible implementation, the fourth pull-down sub-circuit includes a twenty-second transistor;

[0063] The control terminal of the twenty-second transistor is connected to the display input terminal, the first terminal of the twenty-second transistor is connected to the pull-down node, and the second terminal of the twenty-second transistor is connected to the first constant low potential terminal.

[0064] In a possible implementation, the output sub-circuit includes a twenty-third transistor, a second capacitor, a twenty-fifth transistor, and a third capacitor;

[0065] The control terminal of the twenty-third transistor is respectively connected to the first pull-up node and the first terminal of the second capacitor, the first terminal of the twenty-third transistor is connected to the second clock signal terminal, and the second terminal of the twenty-third transistor is respectively connected to the second terminal of the second capacitor and the shift signal output terminal;

[0066] The control terminal of the twenty-fifth transistor is respectively connected to the first pull-up node and the first terminal of the third capacitor, the first terminal of the twenty-fifth transistor is connected to the third clock signal terminal, and the second terminal of the twenty-fifth transistor is respectively connected to the second terminal of the third capacitor and the pixel signal output terminal.

[0067] In a possible implementation, the shift register unit further includes: a first anti-leakage electronic circuit;

[0068] The first anti-leakage electronic circuit includes a thirty-third transistor; a control end of the thirty-third transistor is connected to the blanking pull-up control node, a first end of the thirty-third transistor is respectively connected to a second end of the first transistor and a first end of the second transistor, and a second end of the thirty-third transistor is connected to a second constant voltage high potential end;

[0069] The first anti-leakage electronic circuit is configured to prevent the blanking pull-up control node from leaking electricity to the blanking input end under the control of the blanking pull-up control node.

[0070] In a possible implementation manner, the shift register unit further includes: a second anti-leakage electronic circuit;

[0071] The second anti-leakage electronic circuit includes an eleventh transistor; a control end of the eleventh transistor is connected to the first pull-up node, a first end of the eleventh transistor is connected to a third constant voltage high potential end, and a second end of the eleventh transistor is respectively connected to a second end of the fourth transistor, a first end of the fifth transistor, a second end of the seventh transistor, a first end of the eighth transistor, a second end of the ninth transistor, a first end of the tenth transistor, a second end of the twelfth transistor, a first end of the thirteenth transistor, a second end of the fourteenth transistor, and a first end of the fifteenth transistor;

[0072] The second anti-leakage electronic circuit is configured to prevent the isolation module, the display input module, the display reset sub-circuit, the blanking reset sub-circuit, and the first pull-down sub-circuit from leaking electricity.

[0073] In a possible implementation manner, the output sub-circuit includes at least one pixel signal output end.

[0074] In a possible implementation manner, a blanking input end of the Nth-stage shift register unit is connected to a shift signal output end of the (N - 2)th-stage shift register unit;

[0075] A display input end of the Nth-stage shift register unit is connected to a shift signal output end of the (N - 3)th-stage shift register unit;

[0076] A display reset control signal end of the Nth-stage shift register unit is connected to a shift signal output end of the (N + 2)th-stage shift register unit;

[0077] Wherein, N ∈ M, and N is an integer greater than 3.

[0078] In a third aspect, an embodiment of the present application further provides a driving method for a gate driving circuit, which is applied to any one of the gate driving circuits in the first aspect above. The method includes:

[0079] During the display period of a frame, it includes a first pull-up stage and a first output stage;

[0080] During the first pull-up stage, the display pull-up signal is input to the first pull-up node through the display input sub-circuit;

[0081] During the first output stage, under the control of the first pull-up node, the first shift signal and the first pixel signal are output through the output sub-circuit;

[0082] During the blanking period of a frame, it includes a second pull-up stage and a second output stage;

[0083] During the second pull-up stage, the blanking pull-up signal is input to the first pull-up node through the blanking input sub-circuit;

[0084] During the second output stage, under the control of the first pull-up node, the second shift signal and the second pixel signal are output through the output sub-circuit.

[0085] In a fourth aspect, an embodiment of the present application further provides a display device, and the display device includes the gate driving circuit according to any one of the above first aspects.

[0086] Advantageous effects of the embodiments of the present application:

[0087] A gate driving circuit, a driving method of the gate driving circuit, and a display device provided by an embodiment of the present application. The gate driving circuit includes: M-stage cascaded shift register units, and each stage of shift register unit includes: a display input sub-circuit, a first inverting sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit, and an output sub-circuit; the display input sub-circuit is configured to receive a display input signal through a display input terminal, and input a display pull-up signal to a first pull-up node during a display period of one frame according to the display input signal; the first inverting sub-circuit is configured to control the potential of a pull-down node according to the first pull-up node, so that the potential of the first pull-up node is opposite to the potential of the pull-down node; the first pull-down sub-circuit is configured to pull down the potential of the first pull-up node under the control of the pull-down node; the second pull-down sub-circuit is configured to pull down the potential of an output terminal of the output sub-circuit under the control of the pull-down node; the output sub-circuit is configured to output a first shift signal through its own shift signal output terminal and output a first pixel signal through its own pixel signal output terminal under the control of the first pull-up node; the first inverting sub-circuit includes an eighteenth transistor, a thirtieth transistor, a nineteenth transistor, a twenty-seventh transistor, and a twenty-eighth transistor; a control end of the eighteenth transistor is respectively connected to a first constant high potential terminal, a first end of the eighteenth transistor, and a control end of the thirtieth transistor, and a second end of the eighteenth transistor is connected to a first end of the thirtieth transistor; a second end of the thirtieth transistor is respectively connected to a control end of the nineteenth transistor and a first end of the twenty-seventh transistor; a first end of the nineteenth transistor is connected to the first constant high potential terminal, and a second end of the nineteenth transistor is respectively connected to a first end of the twenty-eighth transistor and the pull-down node; a control end of the twenty-eighth transistor is connected to the first pull-up node, and a second end of the twenty-eighth transistor is connected to a first constant low potential terminal; a control end of the twenty-seventh transistor is connected to the first pull-up node, and a second end of the twenty-seventh transistor is connected to a target signal terminal; wherein, when the first pull-up node is at a high potential, the target signal terminal outputs a high potential signal to the second end of the twenty-seventh transistor, and the potential of the high potential signal output by the target signal terminal is greater than the potential of the first constant high potential terminal. By connecting the second end of the twenty-seventh transistor to the target signal terminal, when the first pull-up node is at a high potential, the high potential signal output by the target signal terminal is transmitted to the first end of the twenty-seventh transistor, that is, the second end of the thirtieth transistor. Moreover, the potential of the high potential signal output by the target signal terminal is greater than the potential of the first constant high potential terminal. In this way, no current passes through the thirtieth transistor, improving the leakage phenomenon of the first inverting sub-circuit in the shift register unit.

[0088] Of course, it is not necessary for any product or method implementing the present application to achieve all the above advantages simultaneously. Description of the Drawings

[0089] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0090] Figure 1 It is a schematic structural diagram of a shift register unit in the related art;

[0091] Figure 2a It is a first schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0092] Figure 2b It is a schematic structural diagram of a first inverter sub-circuit of a shift register unit provided by an embodiment of the present application;

[0093] Figure 3a It is a second schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0094] Figure 3b It is a schematic structural diagram of a second inverter sub-circuit of a shift register unit provided by an embodiment of the present application;

[0095] Figure 4 It is another schematic structural diagram of a first inverter sub-circuit of a shift register unit provided by an embodiment of the present application;

[0096] Figure 5 It is a third schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0097] Figure 6 It is a fourth schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0098] Figure 7 It is a fifth schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0099] Figure 8 It is a sixth schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0100] Figure 9 It is a seventh schematic structural diagram of a shift register unit provided by an embodiment of the present application;

[0101] Figure 10 It is based on Figure 8 The timing schematic diagram of each signal of the 5th stage shift register unit;

[0102] Figure 11The eighth structural schematic diagram of the shift register unit provided by the embodiment of the present application;

[0103] Figure 12 The ninth structural schematic diagram of the shift register unit provided by the embodiment of the present application;

[0104] Figure 13 The tenth structural schematic diagram of the shift register unit provided by the embodiment of the present application. Detailed implementation manners

[0105] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0106] First, a brief description is given to the leakage current phenomenon in the shift register unit in the related art:

[0107] In the current shift register unit of the gate driver on array (GOA), as Figure 1 shown, when the Q(N) point is at a high potential, there is a leakage path in the first inverter sub-circuit: VDD - M18_1 - M18_2 - M27 - VGL1. At this time, M18_1, M18_2, and M27 are all in the conducting state, so there is a leakage between VDD and VGL1, and current will pass through, which may cause the burning of the transistor. Therefore, how to improve the leakage phenomenon of the first inverter sub-circuit in the shift register unit becomes an urgent problem to be solved. Among them, VDD is the constant voltage high potential terminal, and VGL1 is the constant voltage low potential terminal.

[0108] To solve the above problems, the embodiments of the present application provide a gate driver circuit, a driving method of the gate driver circuit, and a display device.

[0109] Next, the gate driver circuit provided by the embodiments of the present application is described, including M - stage cascaded shift register units, where M is an integer greater than 1. Refer to Figure 2a , and each stage of the shift register unit includes:

[0110] A display input sub - circuit 11, a first inverter sub - circuit 12, a first pull - down sub - circuit 13, a second pull - down sub - circuit 14, and an output sub - circuit 15;

[0111] The display input sub - circuit 11 is configured to receive a display input signal through a display input terminal, and input a display pull - up signal to the first pull - up node Q(N) during the display period of one frame according to the display input signal;

[0112] The first inverter sub - circuit 12 is configured to control the potential of the pull - down node QB according to the first pull - up node Q(N), so that the potential of the first pull - up node Q(N) is opposite to the potential of the pull - down node QB;

[0113] The first pull - down sub - circuit 13 is configured to pull down the potential of the first pull - up node Q(N) under the control of the pull - down node QB;

[0114] The second pull - down sub - circuit 14 is configured to pull down the potential of the output terminal of the output sub - circuit 15 under the control of the pull - down node QB;

[0115] The output sub - circuit 15 is configured to output a first shift signal through its own shift - signal output terminal CR(N) and output a first pixel signal through its own pixel - signal output terminal G(N) under the control of the first pull - up node Q(N);

[0116] It can be understood that the first shift signal and the first pixel signal are display output signals.

[0117] See Figure 2b , the first inverter sub - circuit 12 includes an eighteenth transistor M18, a thirtieth transistor M30, a nineteenth transistor M19, a twenty - seventh transistor M27, and a twenty - eighth transistor M28;

[0118] The control terminal of the eighteenth transistor M18 is respectively connected to the first constant - voltage high - potential terminal VDD, the first terminal of the eighteenth transistor M18, and the control terminal of the thirtieth transistor M30. The second terminal of the eighteenth transistor M18 is connected to the first terminal of the thirtieth transistor M30. The second terminal of the thirtieth transistor M30 is respectively connected to the control terminal of the nineteenth transistor M19 and the first terminal of the twenty - seventh transistor M27. The first terminal of the nineteenth transistor M19 is connected to the first constant - voltage high - potential terminal VDD. The second terminal of the nineteenth transistor M19 is respectively connected to the first terminal of the twenty - eighth transistor M28 and the pull - down node QB. The control terminal of the twenty - eighth transistor M28 is connected to the first pull - up node Q(N). The second terminal of the twenty - eighth transistor M28 is connected to the first constant - voltage low - potential terminal VGL1. The control terminal of the twenty - seventh transistor M27 is connected to the first pull - up node Q(N). The second terminal of the twenty - seventh transistor M27 is connected to the target - signal terminal TS;

[0119] Wherein, when the first pull-up node Q(N) is at a high potential, the target signal terminal TS outputs a high-potential signal to the second terminal of the twenty-seventh transistor M27, and the potential of the high-potential signal output by the target signal terminal TS is greater than the potential of the first constant-voltage high-potential terminal VDD.

[0120] It should be noted that Q(N) represents the first pull-up node of the Nth-stage shift register unit, CR(N) represents the shift signal output terminal of the Nth-stage shift register unit, and G(N) represents the pixel signal output terminal of the Nth-stage shift register unit.

[0121] In the embodiment of the present application, by connecting the second terminal of the twenty-seventh transistor M27 to the target signal terminal TS, when the first pull-up node Q(N) is at a high potential, the high-potential signal output by the target signal terminal TS is transmitted to the first terminal of the twenty-seventh transistor M27, that is, the second terminal of the thirtieth transistor M30. In addition, the potential of the high-potential signal output by the target signal terminal TS is greater than the potential of the first constant-voltage high-potential terminal VDD. In this way, no current passes through the thirtieth transistor M30, improving the leakage phenomenon of the first inverter sub-circuit in the shift register unit and enhancing the reliability of the gate driving circuit.

[0122] The embodiment of the present application also provides a gate driving circuit, including M cascaded shift register units, where M is an integer greater than 1. Refer to Figure 3a and each stage of the shift register unit includes:

[0123] a display input sub-circuit 11, a second inverter sub-circuit 30, a first pull-down sub-circuit 13, a second pull-down sub-circuit 14, and an output sub-circuit 15;

[0124] The display input sub-circuit 11 is configured to receive a display input signal through a display input terminal and input a display pull-up signal to the first pull-up node Q(N) during the display period of one frame according to the display input signal;

[0125] The second inverter sub-circuit 30 is configured to control the potential of the pull-down node QB according to the first pull-up node Q(N) so that the potential of the first pull-up node Q(N) is opposite to the potential of the pull-down node QB;

[0126] The first pull-down sub-circuit 13 is configured to pull down the potential of the first pull-up node Q(N) under the control of the pull-down node QB;

[0127] The second pull-down sub-circuit 14 is configured to pull down the potential of the output terminal of the output sub-circuit 15 under the control of the pull-down node QB;

[0128] The output sub - circuit 15 is configured to output a shift signal through its own shift - signal output terminal and output a pixel signal through its own pixel - signal output terminal under the control of the first pull - up node Q(N).

[0129] See Figure 3b , the second inverter sub - circuit 30 includes a thirty - first transistor M31 and a thirty - second transistor M32;

[0130] The control terminal of the thirty - first transistor M31 is connected to the first terminal of the thirty - first transistor M31 and the first constant high - voltage terminal VDD respectively. The second terminal of the thirty - first transistor M31 is connected to the first terminal of the thirty - second transistor M32 and the pull - down node QB respectively. The control terminal of the thirty - second transistor M32 is connected to the first pull - up node Q(N), and the second terminal of the thirty - second transistor M32 is connected to the target signal terminal TS;

[0131] Wherein, when the first pull - up node Q(N) is at a high potential, the target signal terminal TS outputs a high - potential signal to the second terminal of the thirty - second transistor M32, and the potential of the high - potential signal output by the target signal terminal TS is greater than the potential of the first constant high - voltage terminal VDD.

[0132] In the embodiment of the present application, by connecting the second terminal of the thirty - second transistor M32 to the target signal terminal TS, when the first pull - up node Q(N) is at a high potential, the high - potential signal output by the target signal terminal TS is transmitted to the first terminal of the thirty - second transistor M32, that is, the second terminal of the thirty - first transistor M31. In addition, the potential of the high - potential signal output by the target signal terminal TS is greater than the potential of the first constant high - voltage terminal VDD. In this way, no current passes through the thirty - first transistor M31, improving the leakage phenomenon of the second inverter sub - circuit in the shift - register unit and enhancing the reliability of the gate - driving circuit.

[0133] In a possible implementation manner, see Figure 4 , the target signal terminal TS is a shift - signal output terminal CR(N); or, the target signal terminal TS is a pixel - signal output terminal G(N); or, the target signal terminal TS is the first pull - up node Q(N).

[0134] In a possible implementation manner, see Figure 5 , the shift - register unit further includes: a blanking input sub - circuit 16;

[0135] The blanking input sub - circuit 16 is configured to receive a blanking input signal through a blanking input terminal and input a blanking pull - up signal to the first pull - up node Q(N) during the blanking period of one frame according to the blanking input signal;

[0136] The output sub - circuit 15 is further configured to output a second shift signal through its own shift - signal output terminal CR(N) and output a second pixel signal through its own pixel - signal output terminal G(N) under the control of the first pull - up node Q(N).

[0137] It can be understood that the second shift signal and the second pixel signal are blanking output signals.

[0138] For the specific working process and principle of the blanking input sub - circuit, reference can be made to the prior art, and details are not described herein in the present application.

[0139] During the display period of one frame, the output sub - circuit 15 is configured to output a display output signal under the control of the first pull - up node Q(N); during the blanking period of one frame, the output sub - circuit 15 is configured to output a blanking output signal under the control of the first pull - up node Q(N).

[0140] According to the shift - register unit of the embodiment of the present application, the blanking input sub - circuit 16 and the display input sub - circuit 11 can share a first pull - up node Q(N) and the same output sub - circuit 15, so as to implement a smaller - sized shift - register unit.

[0141] In a possible implementation manner, refer to Figure 6 , the blanking input sub - circuit 16 includes:

[0142] A charging module 161, a storage module 162, and an isolation module 163;

[0143] The charging module 161 is configured to input the blanking input signal to the blanking pull - up control node H according to the blanking input signal;

[0144] The storage module 162 is configured to store a blanking pull - up signal; wherein, one end of the storage module is connected to the blanking pull - up control node H;

[0145] The isolation module 163 is configured to input the blanking pull - up signal to the first pull - up node Q(N) during the blanking period of one frame.

[0146] For the specific working process and principle of the charging module, storage module, and isolation module in the blanking input sub - circuit, reference can be made to the prior art, and details are not described herein in the present application.

[0147] In a possible implementation manner, refer to Figure 7 , the shift - register unit further includes: a display reset sub - circuit 17, a blanking reset sub - circuit 18, a third pull - down sub - circuit 19, and a fourth pull - down sub - circuit 20;

[0148] The display reset sub - circuit 17 is configured to reset the first pull - up node Q(N) under the control of a display reset control signal;

[0149] The blanking reset sub - circuit 18 is used to reset the first pull - up node Q(N) under the control of a blanking reset control signal before the end of the blanking period of a frame;

[0150] The third pull - down sub - circuit 19 is used to pull down the potential of the pull - down node QB when the blanking pull - up signal is input to the first pull - up node Q(N);

[0151] The fourth pull - down sub - circuit 20 is used to pull down the potential of the pull - down node QB when the display pull - up signal is input to the first pull - up node Q(N).

[0152] The specific working processes and principles of the display reset sub - circuit, the blanking reset sub - circuit, the third pull - down sub - circuit, and the fourth pull - down sub - circuit can be referred to the prior art, and are not elaborated herein.

[0153] In a possible implementation, refer to Figure 8 , the charging module 161 includes a first transistor M1 and a second transistor M2; the storage module 162 includes a first capacitor C1; the isolation module 163 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5;

[0154] The control terminal of the first transistor M1 is respectively connected to the control signal terminal OE and the control terminal of the second transistor M2. The first terminal of the first transistor M1 is connected to the blanking input terminal, and the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2;

[0155] The second terminal of the second transistor M2 is respectively connected to the first terminal of the first capacitor C1, the blanking pull - up control node H, and the control terminal of the third transistor M3;

[0156] The first terminal of the third transistor M3 is connected to the first clock signal terminal CLKA, and the second terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4;

[0157] The control terminal of the fourth transistor M4 is respectively connected to the first clock signal terminal CLKA and the control terminal of the fifth transistor M5. The second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5;

[0158] The second terminal of the fifth transistor M5 is connected to the first pull - up node Q(N).

[0159] When the blanking pull-up control node H is maintained at a high potential under the control of the storage module, the third transistor M3 is turned on. When the first clock signal terminal CLKA outputs a high-potential signal, the fourth transistor M4 and the fifth transistor M5 are turned on, and the high-potential signal output from the first clock signal terminal CLKA is input as the blanking pull-up signal to the first pull-up node Q(N).

[0160] The specific working processes and principles of the charging module, the storage module, and the isolation module in the blanking input sub-circuit can be referred to the prior art, and will not be elaborated herein in the present application.

[0161] It should be noted that Figure 8 in [reference], the blanking input terminal of the Nth shift register unit is connected to the shift signal output terminal CR(N - 2) of the (N - 2)th shift register unit, the display input terminal of the Nth shift register unit is connected to the shift signal output terminal CR(N - 3) of the (N - 3)th shift register unit, and the display reset control signal terminal of the Nth shift register unit is connected to the shift signal output terminal CR(N + 2) of the (N + 2)th shift register unit as an example for illustration. It can be understood that Figure 8 in the Nth shift register unit illustrated in [reference], N ∈ M, and N is an integer greater than 3.

[0162] In a possible implementation manner, referring to Figure 8 , the display input sub-circuit 11 includes a seventh transistor M7 and an eighth transistor M8;

[0163] The control terminal of the seventh transistor M7 is respectively connected to the display input terminal CR(N - 3), the first terminal of the seventh transistor M7, and the control terminal of the eighth transistor M8. The second terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8;

[0164] The second terminal of the eighth transistor M8 is connected to the first pull-up node Q(N).

[0165] The specific working process of the display input sub-circuit will be described in detail later.

[0166] In a possible implementation manner, referring to Figure 8 , the blanking reset sub-circuit 18 includes a ninth transistor M9 and a tenth transistor M10;

[0167] The control terminal of the ninth transistor M9 is respectively connected to the blanking reset control signal terminal TRST and the control terminal of the tenth transistor M10. The first terminal of the ninth transistor M9 is connected to the first pull-up node Q(N). The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10;

[0168] The second terminal of the tenth transistor M10 is connected to the first constant low potential terminal VGL1.

[0169] Before the end of the blanking period of a frame, the blanking reset control signal terminal TRST can output a high potential signal. At this time, the ninth transistor and the tenth transistor are turned on, and the first pull-up node Q(N) is pulled down to a low potential.

[0170] For the specific working process and principle of the blanking reset sub-circuit, reference can be made to the prior art, and details are not described herein in this application.

[0171] In a possible implementation, refer to Figure 8 , the display reset sub-circuit 17 includes a twelfth transistor M12 and a thirteenth transistor M13;

[0172] The control terminal of the twelfth transistor M12 is respectively connected to the display reset control signal terminal CR(N + 2) and the control terminal of the thirteenth transistor M13. The first terminal of the twelfth transistor M12 is connected to the first pull-up node Q(N), and the second terminal of the twelfth transistor M12 is connected to the first terminal of the thirteenth transistor M13;

[0173] The second terminal of the thirteenth transistor M13 is connected to the first constant low potential terminal VGL1.

[0174] During the display period of a frame, when the display reset control signal terminal CR(N + 2) outputs a high potential signal, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, and the first pull-up node Q(N) is pulled down to a low potential.

[0175] For the specific working process and principle of the display reset sub-circuit, reference can be made to the prior art, and details are not described herein in this application.

[0176] In a possible implementation, refer to Figure 8 , the first pull-down sub-circuit 13 includes a fourteenth transistor M14 and a fifteenth transistor M15;

[0177] The control terminal of the fourteenth transistor M14 is respectively connected to the control terminal of the fifteenth transistor M15 and the pull-down node QB. The first terminal of the fourteenth transistor M14 is connected to the first pull-up node Q(N), and the second terminal of the fourteenth transistor M14 is connected to the first terminal of the fifteenth transistor M15;

[0178] The second terminal of the fifteenth transistor M15 is connected to the first constant low potential terminal VGL1.

[0179] When the pull - down node QB is at a high potential, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the first pull - up node Q(N) is controlled to be at a low potential.

[0180] The specific working process and principle of the first pull - down sub - circuit can be referred to the prior art, and will not be elaborated herein in this application.

[0181] In a possible implementation manner, refer to Figure 8 , the second pull - down sub - circuit 14 includes a twenty - fourth transistor M24 and a twenty - sixth transistor M26;

[0182] The control terminal of the twenty - fourth transistor M24 is connected to the pull - down node QB, the first terminal of the twenty - fourth transistor M24 is connected to the shift signal output terminal CR(N), and the second terminal of the twenty - fourth transistor M24 is connected to the first constant low - potential terminal VGL1;

[0183] The control terminal of the twenty - sixth transistor M26 is connected to the pull - down node QB, the first terminal of the twenty - sixth transistor M26 is connected to the pixel signal output terminal G(N), and the second terminal of the twenty - sixth transistor M26 is connected to the second constant low - potential terminal VGL2.

[0184] When the pull - down node QB is at a high potential, the twenty - fourth transistor M24 and the twenty - sixth transistor M26 are turned on, and the shift signal output terminal CR(N) and the pixel signal output terminal G(N) are controlled to be at a low potential.

[0185] The specific working process and principle of the second pull - down sub - circuit can be referred to the prior art, and will not be elaborated herein in this application.

[0186] In a possible implementation manner, refer to Figure 8 , the third pull - down sub - circuit 19 includes a twentieth transistor M20 and a twenty - first transistor M21;

[0187] The control terminal of the twentieth transistor M20 is connected to the first clock signal terminal CLKA, the first terminal of the twentieth transistor M20 is connected to the pull - down node QB, and the second terminal of the twentieth transistor M20 is connected to the first terminal of the twenty - first transistor M21;

[0188] The control terminal of the twenty - first transistor M21 is connected to the blanking pull - up control node H, and the second terminal of the twenty - first transistor M21 is connected to the first constant low - potential terminal VGL1.

[0189] When both the first clock signal terminal CLKA and the blanking pull - up control node H are at a high potential, the potential of the pull - down node QB is quickly pulled down through the first constant low - potential terminal VGL1.

[0190] The specific working process and principle of the third pull-down sub-circuit can be referred to the prior art, and will not be elaborated in this application.

[0191] In a possible implementation, referring to Figure 8 , the fourth pull-down sub-circuit 20 includes a twenty-second transistor M22;

[0192] The control terminal of the twenty-second transistor M22 is connected to the display input terminal CR(N - 3), the first terminal of the twenty-second transistor M22 is connected to the pull-down node QB, and the second terminal of the twenty-second transistor M22 is connected to the first constant low potential terminal VGL1.

[0193] When the display input terminal CR(N - 3) is at a high potential, the potential of the pull-down node QB is quickly pulled down through the first constant low potential terminal VGL1.

[0194] The specific working process and principle of the fourth pull-down sub-circuit can be referred to the prior art, and will not be elaborated in this application.

[0195] In a possible implementation, referring to Figure 8 , the output sub-circuit 15 includes a twenty-third transistor M23, a second capacitor C2, a twenty-fifth transistor M25, and a third capacitor C3;

[0196] The control terminal of the twenty-third transistor M23 is respectively connected to the first pull-up node Q(N) and the first terminal of the second capacitor C2. The first terminal of the twenty-third transistor M23 is connected to the second clock signal terminal CLKD1, and the second terminal of the twenty-third transistor M23 is respectively connected to the second terminal of the second capacitor C2 and the shift signal output terminal CR(N);

[0197] The control terminal of the twenty-fifth transistor M25 is respectively connected to the first pull-up node Q(N) and the first terminal of the third capacitor C3. The first terminal of the twenty-fifth transistor M25 is connected to the third clock signal terminal CLKE1, and the second terminal of the twenty-fifth transistor M25 is respectively connected to the second terminal of the third capacitor C3 and the pixel signal output terminal G(N).

[0198] The specific working process of the output sub-circuit during the display period will be described in detail later. The specific working process and principle of the output sub-circuit during the blanking period can be referred to the prior art, and will not be elaborated in this application.

[0199] In a possible implementation, referring to Figure 8 , the shift register unit further includes: a first anti-leakage electronic circuit 21;

[0200] The first anti-leakage electronic circuit 21 includes a thirty-third transistor M33; a control end of the thirty-third transistor M33 is connected to the blanking pull-up control node H, a first end of the thirty-third transistor M33 is respectively connected to a second end of the first transistor M1 and a first end of the second transistor M2, and a second end of the thirty-third transistor M33 is connected to a second constant voltage high potential end GVDD1;

[0201] The first anti-leakage electronic circuit 21 is configured to prevent the blanking pull-up control node H from leaking electricity to the blanking input end CR(N-2) under the control of the blanking pull-up control node H.

[0202] For the specific working process and principle of the first anti-leakage electronic circuit, reference can be made to the prior art, which will not be elaborated herein in this application.

[0203] In a possible implementation manner, referring to Figure 8 , the shift register unit further includes: a second anti-leakage electronic circuit 22;

[0204] The second anti-leakage electronic circuit 22 includes an eleventh transistor M11; a control end of the eleventh transistor M11 is connected to the first pull-up node Q(N), a first end of the eleventh transistor M11 is connected to a third constant voltage high potential end GVDD2, and a second end of the eleventh transistor M11 is respectively connected to a second end of the fourth transistor M4, a first end of the fifth transistor M5, a second end of the seventh transistor M7, a first end of the eighth transistor M8, a second end of the ninth transistor M9, a first end of the tenth transistor M10, a second end of the twelfth transistor M12, a first end of the thirteenth transistor M13, a second end of the fourteenth transistor M14, and a first end of the fifteenth transistor M15;

[0205] The second anti-leakage electronic circuit 22 is configured to prevent leakage in the isolation module 163, the display input module 11, the display reset sub-circuit 17, the blanking reset sub-circuit 18, and the first pull-down sub-circuit 13.

[0206] For the specific working process and principle of the second anti-leakage electronic circuit, reference can be made to the prior art, which will not be elaborated herein in this application.

[0207] In a possible implementation manner, the output sub-circuit 15 includes at least one pixel signal output end.

[0208] In one example, referring to Figure 9 , the output sub-circuit 15 may include 4 pixel signal output ends.

[0209] It should be noted thatFigures 4 - 9 In the illustrated shift register unit, the first inverter sub-circuit is taken as an example for illustration.

[0210] In a possible implementation manner, each transistor in the shift register unit is an N-type transistor.

[0211] It can be understood that for any transistor in the circuit of the present application, the transistor can be an N-type transistor or a P-type transistor, and can be specifically selected according to actual situations; the control end of the transistor is the gate, the first end of the transistor is the source or the drain, and the second end of the transistor is the drain or the source corresponding to the first end. It can be understood that the transistor can be a P-type transistor or an N-type transistor, and can be specifically selected according to actual situations, but the device connection manner of the circuit needs to be adjusted accordingly, and its replacement scheme is still within the protection scope of the present application.

[0212] It can be understood that the transistors used in the circuit of the present application can be MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors), or TFT transistors (Thin Film Transistors) or other types of transistors, and can be specifically selected according to actual situations, and its replacement scheme is still within the protection scope of the present application.

[0213] In a possible implementation manner, the blanking input end of the Nth-stage shift register unit is connected to the shift signal output end of the (N - 2)th-stage shift register unit;

[0214] The display input end of the Nth-stage shift register unit is connected to the shift signal output end of the (N - 3)th-stage shift register unit;

[0215] The display reset control signal end of the Nth-stage shift register unit is connected to the shift signal output end of the (N + 2)th-stage shift register unit;

[0216] Wherein, N ∈ M, and N is an integer greater than 3.

[0217] In an example, N can be 5. For the 5th-stage shift register unit, its display reset control signal end is connected to the shift signal output end of the 7th-stage shift register unit. Therefore, when the shift signal output end of the 7th-stage shift register unit outputs the first shift signal CR(N + 2), the first pull-up node Q(N) of the 5th-stage shift register unit is reset to a low potential.

[0218] The embodiment of the present application further provides a driving method for a gate driving circuit, which can be applied to the gate driving circuit in the above embodiment. The method includes:

[0219] During the display period of one frame, it includes a first pull-up stage and a first output stage;

[0220] During the first pull-up stage, a display pull-up signal is input to the first pull-up node through a display input sub-circuit;

[0221] During the first output stage, under the control of the first pull-up node, a first shift signal and a first pixel signal are output through an output sub-circuit;

[0222] During the blanking period of one frame, it includes a second pull-up stage and a second output stage;

[0223] During the second pull-up stage, a blanking pull-up signal is input to the first pull-up node through a blanking input sub-circuit;

[0224] During the second output stage, under the control of the first pull-up node, a second shift signal and a second pixel signal are output through an output sub-circuit.

[0225] Taking N = 5 as an example below, based on Figure 8 The specific working process of the 5th-stage shift register unit will be described:

[0226] First, when the control signal terminal OE and the blanking reset control signal terminal TRST are both at high potential, the blanking pull-up control node H and the first pull-up node Q(N) are reset. The process of resetting the first pull-up node Q(N) can refer to the above description. Before the end of the blanking period of one frame, a high potential is output through the control signal terminal OE to control the first transistor M1 and the second transistor M2 to conduct, and the initial reset control signal is received to reset the blanking pull-up control node H.

[0227] During the display period of one frame, 1. The display input terminal CR <n-3>When the high potential causes the seventh transistor M7 and the eighth transistor M8 to conduct, the first pull-up node Q<5> is written with a high potential and remains at the high potential. The low potentials of the second clock signal terminal CLKD1 and the third clock signal terminal CLKE1 cause both the first shift signal output from the shift signal output terminal CR<5> and the first pixel signal output from the pixel signal output terminal G<5> to be at low potentials.

[0228] 2. When both the second clock signal terminal CLKD1 and the third clock signal terminal CLKE1 are at high potentials, at this time, due to the existence of the second capacitor C2 and the third capacitor C3, the first pull-up node Q<5> remains at the high potential, and both the first shift signal output from the shift signal output terminal CR<5> and the first pixel signal output from the pixel signal output terminal G<5> are at high potentials.

[0229] 3. When the second clock signal terminal CLKD1 and the third clock signal terminal CLKE1 become low potentials, and at the same time CR<7> becomes high potential, which causes the twelfth transistor M12 and the thirteenth transistor M13 to conduct, making Q<5>, CR<5> and G<5> become low potentials.

[0230] Figure 10 is based on Figure 8 is a timing diagram of each signal of the 5th stage shift register unit. Among them, 1F is one frame, Display is the display period, and Blank is the blanking period.

[0231] Figure 11 is based on Figure 2b , the second terminal of the twenty-seventh transistor M27 is connected to the shift signal output terminal CR <n>Schematic diagram of a shift register unit Figure 12 Based on Figure 2b The second terminal of the twenty-seventh transistor M27 is connected to the pixel signal output terminal G <n> / Schematic diagram of the shift register unit of the first pull-up node Q(N), Figure 13 Based on Figure 3b , the second terminal of the thirty-second transistor M32 is connected to the pixel signal output terminal G <n> / First pull-up node Q(N) / Shift signal output terminal CR <n>Schematic diagram of a shift register unit.

[0232] An embodiment of the present application further provides a display device, and the display device includes the gate driving circuit described in any one of the above embodiments.

[0233] In one example, the display device may be an LTPO OLED (Low Temperature Polycrystalline Oxide, Organic Light-Emitting Diode) display product. The advantage of the LTPO OLED display product is that it can achieve low-frequency refresh due to the lower leakage current, greatly reducing the power consumption of the mobile phone.

[0234] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0235] Each embodiment in this specification is described in a related manner. The same or similar parts between each embodiment can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0236] The above is only the preferred embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.< / n> < / n> < / n> < / n>

Claims

1. A gate driving circuit, characterized in that, it includes M cascaded shift register units, where M is an integer greater than 1, and each shift register unit includes: a display input sub - circuit, a first inverting sub - circuit, a first pull - down sub - circuit, a second pull - down sub - circuit, and an output sub - circuit; The display input sub - circuit is configured to receive a display input signal through a display input terminal, and input a display pull - up signal to a first pull - up node during a display period of one frame according to the display input signal; The first inverting sub - circuit is configured to control the potential of a pull - down node according to the first pull - up node, so that the potential of the first pull - up node is opposite to the potential of the pull - down node; The first pull - down sub - circuit is configured to pull down the potential of the first pull - up node under the control of the pull - down node; The second pull - down sub - circuit is configured to pull down the potential of the output terminal of the output sub - circuit under the control of the pull - down node; The output sub - circuit is configured to output a first shift signal through its own shift signal output terminal and output a first pixel signal through its own pixel signal output terminal under the control of the first pull - up node; The first inverting sub - circuit includes an eighteenth transistor, a thirtieth transistor, a nineteenth transistor, a twenty - seventh transistor, and a twenty - eighth transistor; The control terminal of the eighteenth transistor is respectively connected to a first constant high - potential terminal, the first terminal of the eighteenth transistor, and the control terminal of the thirtieth transistor. The second terminal of the eighteenth transistor is connected to the first terminal of the thirtieth transistor. The second terminal of the thirtieth transistor is respectively connected to the control terminal of the nineteenth transistor and the first terminal of the twenty - seventh transistor. The first terminal of the nineteenth transistor is connected to the first constant high - potential terminal. The second terminal of the nineteenth transistor is respectively connected to the first terminal of the twenty - eighth transistor and the pull - down node. The control terminal of the twenty - eighth transistor is connected to the first pull - up node, and the second terminal of the twenty - eighth transistor is connected to a first constant low - potential terminal. The control terminal of the twenty - seventh transistor is connected to the first pull - up node, and the second terminal of the twenty - seventh transistor is connected to a target signal terminal; Wherein, when the first pull - up node is at a high potential, the target signal terminal outputs a high - potential signal to the second terminal of the twenty - seventh transistor, and the potential of the high - potential signal output by the target signal terminal is greater than the potential of the first constant high - potential terminal.

2. A gate driving circuit, characterized in that, it includes M cascaded shift register units, where M is an integer greater than 1, and each shift register unit includes: a display input sub - circuit, a second inverting sub - circuit, a first pull - down sub - circuit, a second pull - down sub - circuit, and an output sub - circuit; The display input sub - circuit is configured to receive a display input signal through a display input terminal, and input a display pull - up signal to a first pull - up node during a display period of one frame according to the display input signal; The second inverting sub - circuit is configured to control the potential of a pull - down node according to the first pull - up node, so that the potential of the first pull - up node is opposite to the potential of the pull - down node; The first pull-down sub-circuit is configured to pull down the potential of the first pull-up node under the control of the pull-down node; The second pull-down sub-circuit is configured to pull down the potential of the output end of the output sub-circuit under the control of the pull-down node; The output sub-circuit is configured to output a shift signal through its own shift signal output end and output a pixel signal through its own pixel signal output end under the control of the first pull-up node; The second inverter sub-circuit includes a thirty-first transistor and a thirty-second transistor; The control end of the thirty-first transistor is respectively connected to the first end of the thirty-first transistor and the first constant high potential end. The second end of the thirty-first transistor is respectively connected to the first end of the thirty-second transistor and the pull-down node. The control end of the thirty-second transistor is connected to the first pull-up node, and the second end of the thirty-second transistor is connected to the target signal end; Wherein, when the first pull-up node is at a high potential, the target signal end outputs a high potential signal to the second end of the thirty-second transistor, and the potential of the high potential signal output by the target signal end is greater than the potential of the first constant high potential end.

3. The gate driving circuit according to claim 1 or 2, characterized in that, The target signal end is a shift signal output end; or, the target signal end is a pixel signal output end; or, the target signal end is the first pull-up node.

4. The gate driving circuit according to claim 3, characterized in that, The shift register unit further includes: a blanking input sub-circuit; The blanking input sub-circuit is configured to receive a blanking input signal through a blanking input end and input a blanking pull-up signal to the first pull-up node during a blanking period of one frame according to the blanking input signal; The output sub-circuit is further configured to output a second shift signal through its own shift signal output end and output a second pixel signal through its own pixel signal output end under the control of the first pull-up node.

5. The gate driving circuit according to claim 4, characterized in that, The blanking input sub-circuit includes: A charging module, a storage module, and an isolation module; The charging module is configured to input the blanking input signal to a blanking pull-up control node according to the blanking input signal; The storage module is configured to store a blanking pull-up signal; wherein, one end of the storage module is connected to the blanking pull-up control node; The isolation module is configured to input the blanking pull-up signal to the first pull-up node during a blanking period of one frame.

6. The gate driving circuit according to claim 5, characterized in that, The shift register unit further includes: a display reset sub-circuit, a blanking reset sub-circuit, a third pull-down sub-circuit, and a fourth pull-down sub-circuit; The display reset sub-circuit is configured to reset the first pull-up node under the control of a display reset control signal; The blanking reset sub-circuit is configured to reset the first pull-up node under the control of a blanking reset control signal before the end of a blanking period of one frame; The third pull-down sub-circuit is configured to pull down the potential of the pull-down node when the blanking pull-up signal is input to the first pull-up node; The fourth pull-down sub-circuit is configured to pull down the potential of the pull-down node when the display pull-up signal is input to the first pull-up node.

7. The gate driving circuit according to claim 6, wherein, the charging module includes a first transistor and a second transistor; the storage module includes a first capacitor; the isolation module includes a third transistor, a fourth transistor, and a fifth transistor; the control terminal of the first transistor is respectively connected to the control signal terminal and the control terminal of the second transistor, the first terminal of the first transistor is connected to the blanking input terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor; the second terminal of the second transistor is respectively connected to the first terminal of the first capacitor, the blanking pull-up control node, and the control terminal of the third transistor; the first terminal of the third transistor is connected to the first clock signal terminal, and the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the control terminal of the fourth transistor is respectively connected to the first clock signal terminal and the control terminal of the fifth transistor, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor; the second terminal of the fifth transistor is connected to the first pull-up node.

8. The gate driving circuit according to claim 7, wherein, the display input sub-circuit includes a seventh transistor and an eighth transistor; the control terminal of the seventh transistor is respectively connected to the display input terminal, the first terminal of the seventh transistor, and the control terminal of the eighth transistor, and the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor; the second terminal of the eighth transistor is connected to the first pull-up node.

9. The gate driving circuit according to claim 8, wherein, the blanking reset sub-circuit includes a ninth transistor and a tenth transistor; the control terminal of the ninth transistor is respectively connected to the blanking reset control signal terminal and the control terminal of the tenth transistor, the first terminal of the ninth transistor is connected to the first pull-up node, and the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor; the second terminal of the tenth transistor is connected to the first constant low potential terminal.

10. The gate driving circuit according to claim 9, wherein, the display reset sub-circuit includes a twelfth transistor and a thirteenth transistor; the control terminal of the twelfth transistor is respectively connected to the display reset control signal terminal and the control terminal of the thirteenth transistor, the first terminal of the twelfth transistor is connected to the first pull-up node, and the second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor; the second terminal of the thirteenth transistor is connected to the first constant low potential terminal.

11. The gate driving circuit according to claim 10, wherein, the first pull-down sub-circuit includes a fourteenth transistor and a fifteenth transistor; The control terminal of the fourteenth transistor is respectively connected to the control terminal of the fifteenth transistor and the pull-down node. The first terminal of the fourteenth transistor is connected to the first pull-up node, and the second terminal of the fourteenth transistor is connected to the first terminal of the fifteenth transistor; The second terminal of the fifteenth transistor is connected to the first constant low potential terminal.

12. The gate driving circuit according to claim 11, wherein, the second pull-down sub-circuit includes a twenty-fourth transistor and a twenty-sixth transistor; The control terminal of the twenty-fourth transistor is connected to the pull-down node. The first terminal of the twenty-fourth transistor is connected to the shift signal output terminal, and the second terminal of the twenty-fourth transistor is connected to the first constant low potential terminal; The control terminal of the twenty-sixth transistor is connected to the pull-down node. The first terminal of the twenty-sixth transistor is connected to the pixel signal output terminal, and the second terminal of the twenty-sixth transistor is connected to the second constant low potential terminal.

13. The gate driving circuit according to claim 12, wherein, the third pull-down sub-circuit includes a twentieth transistor and a twenty-first transistor; The control terminal of the twentieth transistor is connected to the first clock signal terminal. The first terminal of the twentieth transistor is connected to the pull-down node, and the second terminal of the twentieth transistor is connected to the first terminal of the twenty-first transistor; The control terminal of the twenty-first transistor is connected to the blanking pull-up control node, and the second terminal of the twenty-first transistor is connected to the first constant low potential terminal.

14. The gate driving circuit according to claim 13, wherein, the fourth pull-down sub-circuit includes a twenty-second transistor; The control terminal of the twenty-second transistor is connected to the display input terminal. The first terminal of the twenty-second transistor is connected to the pull-down node, and the second terminal of the twenty-second transistor is connected to the first constant low potential terminal.

15. The gate driving circuit according to claim 14, wherein, the output sub-circuit includes a twenty-third transistor, a second capacitor, a twenty-fifth transistor, and a third capacitor; The control terminal of the twenty-third transistor is respectively connected to the first pull-up node and the first terminal of the second capacitor. The first terminal of the twenty-third transistor is connected to the second clock signal terminal, and the second terminal of the twenty-third transistor is respectively connected to the second terminal of the second capacitor and the shift signal output terminal; The control terminal of the twenty-fifth transistor is respectively connected to the first pull-up node and the first terminal of the third capacitor. The first terminal of the twenty-fifth transistor is connected to the third clock signal terminal, and the second terminal of the twenty-fifth transistor is respectively connected to the second terminal of the third capacitor and the pixel signal output terminal.

16. The gate driving circuit according to claim 15, wherein, the shift register unit further includes: a first anti-leakage electronic circuit; The first anti-leakage electronic circuit includes a thirty-third transistor; a control end of the thirty-third transistor is connected to the blanking pull-up control node, a first end of the thirty-third transistor is respectively connected to a second end of the first transistor and a first end of the second transistor, and a second end of the thirty-third transistor is connected to a second constant voltage high potential end; The first anti-leakage electronic circuit is configured to prevent the blanking pull-up control node from leaking electricity to the blanking input end under the control of the blanking pull-up control node.

17. The gate driving circuit according to claim 16, wherein, the shift register unit further includes: a second anti-leakage electronic circuit; The second anti-leakage electronic circuit includes an eleventh transistor; a control end of the eleventh transistor is connected to the first pull-up node, a first end of the eleventh transistor is connected to a third constant voltage high potential end, and a second end of the eleventh transistor is respectively connected to a second end of the fourth transistor, a first end of the fifth transistor, a second end of the seventh transistor, a first end of the eighth transistor, a second end of the ninth transistor, a first end of the tenth transistor, a second end of the twelfth transistor, a first end of the thirteenth transistor, a second end of the fourteenth transistor, and a first end of the fifteenth transistor; The second anti-leakage electronic circuit is configured to prevent the isolation module, the display input module, the display reset sub-circuit, the blanking reset sub-circuit, and the first pull-down sub-circuit from leaking electricity.

18. The gate driving circuit according to claim 17, wherein, the output sub-circuit includes at least one pixel signal output end.

19. The gate driving circuit according to claim 17, wherein, a blanking input end of the Nth stage shift register unit is connected to a shift signal output end of the (N - 2)th stage shift register unit; a display input end of the Nth stage shift register unit is connected to a shift signal output end of the (N - 3)th stage shift register unit; a display reset control signal end of the Nth stage shift register unit is connected to a shift signal output end of the (N + 2)th stage shift register unit; wherein, N ∈ M, and N is an integer greater than 3.

20. A driving method for a gate driving circuit, wherein, applied to the gate driving circuit according to any one of claims 4 - 19, the method includes: During a display period of one frame, including a first pull-up stage and a first output stage; During the first pull-up stage, input a display pull-up signal to the first pull-up node through the display input sub-circuit; During the first output stage, under the control of the first pull-up node, output a first shift signal and a first pixel signal through the output sub-circuit; During a blanking period of one frame, including a second pull-up stage and a second output stage; During the second pull-up stage, input a blanking pull-up signal to the first pull-up node through the blanking input sub-circuit; During the second output stage, under the control of the first pull-up node, output a second shift signal and a second pixel signal through the output sub-circuit.

21. A display device, wherein, The display device includes the gate driving circuit according to any one of claims 1-19 above.

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