Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, a sub-pixel comprises a main light-emitting device and at least one secondary light-emitting device, and a pixel circuit comprises a main driving module, a secondary driving module and a data writing module; the first ends of the main driving module and the secondary driving module are electrically connected with the output end of the data writing module, and the input end of the data writing module is electrically connected with a data line; the pixel circuit further comprises a main light-emitting control module and a secondary light-emitting control module. The main light-emitting control module is electrically connected between the main driving module and the main light-emitting device, and the secondary light-emitting control module is electrically connected between the secondary driving module and the secondary light-emitting device. In the technical scheme provided by the embodiment of the invention, each driving module does not need to generate larger light-emitting driving current; the requirement for the performance of the driving module is relatively low, it is avoided that too much heat generated by the pixel circuit influences light emitting of the light-emitting device, the requirement for the computing power of the driving IC is relatively low, and the pixel circuit which is small in occupied area and relatively simple in structure can be obtained.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, more and more functions are integrated into display devices. Currently, consumers pay more attention to privacy when using display devices. Therefore, display devices need to have an anti-peeping effect during display.

[0003] In the prior art, a solution to achieve the anti-peeping effect is to control the collimated light emitted by the display device using technologies such as black matrices and liquid crystal gratings. This solution increases the complexity of the manufacturing process of the display device, increases costs and power consumption, and has a greater impact on the color trajectory of the display device, resulting in a relatively serious color deviation problem. Summary of the Invention

[0004] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of this application provides a display panel, including:

[0006] Sub-pixels, where each sub-pixel includes a main light-emitting device and at least one secondary light-emitting device;

[0007] A pixel circuit, including a main driving module, a secondary driving module, and a data writing module; the first ends of the main driving module and the secondary driving module are both electrically connected to the output end of the data writing module, and the input end of the data writing module is electrically connected to a data line;

[0008] Wherein, the pixel circuit further includes a main light-emitting control module and a secondary light-emitting control module; the main light-emitting control module is electrically connected between the main driving module and the main light-emitting device, and the secondary light-emitting control module is electrically connected between the secondary driving module and the secondary light-emitting device.

[0009] In a second aspect, an embodiment of this application provides a display device, including the display panel provided in the first aspect.

[0010] In the technical solution provided by the embodiments of this application, each driving module does not need to generate a larger light-emitting driving current, the performance requirements for the driving module are relatively low, it avoids excessive heat generation in the pixel circuit affecting the light emission of the light-emitting device, the computing power requirements for the driving IC are relatively low, and it is beneficial to obtain a pixel circuit with a relatively small occupied area and a relatively simple structure. Description of the Drawings

[0011] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present application;

[0013] Figure 2 Schematic diagram of a pixel circuit and a sub-pixel provided by an embodiment of the present application;

[0014] Figure 3 For Figure 1 A cross-sectional schematic diagram along the A1 - A2 direction in

[0015] Figure 4 Schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 5 Schematic diagram of the light emission of a sub-pixel in a display panel provided by an embodiment of the present application;

[0017] Figure 6 For Figure 1 A cross-sectional schematic diagram along the A1 - A2 direction in

[0018] Figure 7 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0019] Figure 8 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0020] Figure 9 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0021] Figure 10 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0022] Figure 11 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0023] Figure 12 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application;

[0024] Figure 13A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0025] Figure 14 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0026] Figure 15 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0027] Figure 16 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0028] Figure 17 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0029] Figure 18 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0030] Figure 19 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0031] Figure 20 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0032] Figure 21 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0033] Figure 22 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0034] Figure 23 is Figure 22 A corresponding equivalent circuit diagram;

[0035] Figure 24 is Figure 23 A corresponding timing diagram;

[0036] Figure 25 is Figure 22 Another corresponding equivalent circuit diagram;

[0037] Figure 26 is Figure 25 A corresponding timing diagram;

[0038] Figure 27 A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application;

[0039] Figure 28 For Figure 27 Another equivalent circuit diagram corresponding thereto;

[0040] Figure 29 For Figure 28 A timing diagram corresponding thereto;

[0041] Figure 30 A schematic diagram of the connection between sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application;

[0042] Figure 31 For Figure 30 Another equivalent circuit diagram corresponding thereto;

[0043] Figure 32 For Figure 31 A timing diagram corresponding thereto;

[0044] Figure 33 For Figure 30 Another equivalent circuit diagram corresponding thereto;

[0045] Figure 34 A schematic diagram of sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application;

[0046] Figure 35 For Figure 34 Another equivalent circuit diagram corresponding thereto;

[0047] Figure 36 For Figure 35 A timing diagram corresponding thereto;

[0048] Figure 37 A schematic diagram of the connection between sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application;

[0049] Figure 38 For Figure 37 Another equivalent circuit diagram corresponding thereto;

[0050] Figure 39 For Figure 38 A timing diagram corresponding thereto;

[0051] Figure 40 A schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0052] For a better understanding of the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0053] It should be clear that the described embodiments are only some of the embodiments of the present application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0054] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0055] It should be understood that the term "and / or" used herein is only an association relationship describing associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0056] In the description of this specification, it should be understood that the words such as "substantially", "approximately", "about", "around", "roughly", "generally" described in the claims and embodiments of the present application refer to values that can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0057] It should be understood that although terms such as first and second may be used in the embodiments of the present application to describe transistors, etc., these should not be limited to these terms. These terms are only used to distinguish transistors, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first transistor may also be referred to as the second transistor, and similarly, the second transistor may also be referred to as the first transistor. Through careful and in-depth research, the applicant of this case provides a solution to the problems existing in the prior art.

[0058] Figure 1 A schematic diagram of a display panel provided for the embodiments of the present application.

[0059] As Figure 1 shown, the display panel 01 includes a plurality of sub-pixels 11, and the sub-pixels 11 are light-emitting units in the display panel 01. Among them, the sub-pixel 11 includes a main light-emitting device 111 and at least one secondary light-emitting device 112. Then, the sub-pixel 11 may include a plurality of light-emitting devices 110 that can each emit light, and the plurality of light-emitting devices 110 include the main light-emitting device 111 and the secondary light-emitting device 112. In the direction parallel to the plane where the display panel 01 is located, the area occupied by the main light-emitting device 111 in the sub-pixel 11 may be larger than the area occupied by the secondary light-emitting device 112 in the sub-pixel 11.

[0060] The case where the main light-emitting device 111 emits light and the secondary light-emitting device 112 emits light, and the case where the main light-emitting device 111 emits light and the secondary light-emitting device 112 does not emit light can be different light-emitting modes of the sub-pixel 11, which respectively correspond to different working modes of the display panel 01. By setting the main light-emitting device 111 and the secondary light-emitting device 112 in the sub-pixel 11, the display panel 01 can have different working modes. For example, the display panel 01 can have two working modes: a privacy mode and a sharing mode, or the display panel 01 can have two working modes: a low-brightness mode and a high-brightness mode, etc.

[0061] Among them, the light-emitting device can be an organic light-emitting diode (OLED), a mini light-emitting diode (Mini-LED), a micro light-emitting diode (Micro-LED), or other light-emitting devices. In addition, the main light-emitting device 111 and the secondary light-emitting device 112 can be light-emitting devices of the same type. For example, both the main light-emitting device 111 and the secondary light-emitting device 112 can be OLEDs.

[0062] As Figure 1 shown, the display panel 01 further includes a pixel circuit 12. The pixel circuit 12 can be electrically connected to the main light-emitting device 111 and the secondary light-emitting device 112. Among them, the same pixel circuit 12 can be electrically connected to both the main light-emitting device 111 and the secondary light-emitting device 112 in the sub-pixel 11, and is used to provide signals for the main light-emitting device 111 and the secondary light-emitting device 112. In order to enable the multiple light-emitting devices 10 in the sub-pixel 11 to emit light independently, the pixel circuit 12 can include multiple output terminals, and these multiple output terminals can be respectively electrically connected to the main light-emitting device 111 and the secondary light-emitting device 112 of the sub-pixel 11.

[0063] In the embodiment of the present application, the same pixel circuit 12 is electrically connected to the main light-emitting device 111 and the secondary light-emitting device 112, so the main light-emitting device 111 and at least some of the secondary light-emitting devices 112 can be electrically connected to the same pixel circuit 12. Compared with the solution where the main light-emitting device 111 and the secondary light-emitting device 112 are respectively electrically connected to different pixel circuits 12, the solution provided by the embodiment of the present application can reduce the number of pixel circuits 12 in the display panel 01, reduce the design difficulty of the display panel 01, and is beneficial to achieving high resolution.

[0064] It should be noted that, for the sake of clearly showing the connection relationship between the pixel circuit 12 and the main light-emitting device 111 and the secondary light-emitting device 112, Figure 1 the pixel circuit 12 in

[0065] Figure 2Schematic diagram of a pixel circuit and a sub-pixel provided by an embodiment of the present application.

[0066] As Figure 2 shown, the pixel circuit 12 includes a main driving module 121, a secondary driving module 121', and a data writing module 122. The first ends ED1 of the main driving module 121 and the secondary driving module 121' are both electrically connected to the output end OUT2 of the data writing module 122. As Figure 2 shown, the first ends ED1' of the main driving module 121 and the secondary driving module 121' are electrically connected, and the output end OUT2 of the data writing module 122 is electrically connected to the first end ED1 of the main driving module 121 and the first end ED1' of the secondary driving module 121'. In addition, the input end IN2 of the data writing module 122 is electrically connected to the data line DL. When the data writing module 122 is turned on, it can transmit the data voltage on the data line DL to the first end ED1 of the main driving module 121 and the first end ED1 of the secondary driving module 121'. Among them, the main driving module 121 can generate a driving current for controlling the main light-emitting device 111 to emit light according to the data voltage at its first end ED1, and the secondary driving module 121' can generate a driving current for controlling the secondary light-emitting device 112 to emit light according to the data voltage at its first end ED1'.

[0067] In the embodiment of the present application, the pixel circuit 12 further includes a main light-emitting control module 123 and a secondary light-emitting control module 123'. The main light-emitting control module 123 is electrically connected between the main driving module 121 and the main light-emitting device 111, and the secondary light-emitting control module 123' is electrically connected between the secondary driving module 121' and the secondary light-emitting device 112. For example, as Figure 2 shown, the main light-emitting control module 123 includes an input end IN3 and an output end OUT3. The input end IN3 of the main light-emitting control module 123 is electrically connected to the output end OUT1 of the main driving module 121, and the output end OUT3 of the main light-emitting control module 123 is electrically connected to the main light-emitting device 111. The secondary light-emitting control module 123' includes an input end IN3' and an output end OUT3'. The input end IN3' of the secondary light-emitting control module 123' is electrically connected to the output end OUT1' of the secondary driving module 121', and the output end OUT3' of the secondary light-emitting control module 123' is electrically connected to the secondary light-emitting device 112. Among them, the main light-emitting control module 123 is used to turn on when the main light-emitting device 111 needs to emit light, so as to electrically conduct the main light-emitting device 111 and the main driving module 121. The secondary control module is used to turn on when the secondary light-emitting device 112 needs to emit light, so as to conduct the secondary light-emitting device 112 and the secondary driving module 121'. The main light-emitting device 111 is electrically connected to the main driving module 121 through the main light-emitting control module 123, and the secondary light-emitting device 112 is electrically connected to the secondary driving module 121' through the secondary light-emitting control module 123'. Therefore, the light emission of the main light-emitting device 111 and the secondary light-emitting device 112 is flexibly controllable.

[0068] If the main light-emitting device 111 and the secondary light-emitting device 112 are connected to the same driving module during light emission, when both the main light-emitting device 111 and the secondary light-emitting device 112 emit light, the driving current generated by the driving module should be the sum of the driving current required by the main light-emitting device 111 and the driving current required by the secondary light-emitting device 112 to meet the light-emitting brightness requirement of the sub-pixel 11. And the technical solution provided by the embodiments of the present application can, when the main light-emitting device 111 emits light, electrically connect the main driving module 121 to the main light-emitting device 111 and provide a driving current for it; and can, when the secondary light-emitting device 112 emits light, electrically connect the secondary driving module 121' to the secondary light-emitting device 112 and provide a driving current for it. Therefore, the main driving module 121 only needs to generate the driving current required by the main light-emitting device 111 and the secondary driving module 121' only needs to generate the driving current required by the secondary light-emitting device 112. Compared with the main light-emitting device 111 and the secondary light-emitting device 112 being connected to the same driving module during light emission, in the technical solution provided by the embodiments of the present application, each driving module does not need to generate a larger light-emitting driving current, the performance requirements for the driving module are relatively low, and it is avoided that the pixel circuit 12 generates too much heat and affects the light emission of the light-emitting device.

[0069] If the main light-emitting device 111 and the secondary light-emitting device 112 are connected to the same driving module during light emission, the data voltage required by the driving module when the main light-emitting device 111 and the secondary light-emitting device 112 are both at the target light-emitting brightness is different from the data voltage required by the driving module when only the main light-emitting device 111 is at the target light-emitting brightness. At this time, the display panel 01 has relatively high computing power requirements for the driving IC. And in the technical solution provided by the embodiments of the present application, whether only the main light-emitting device 111 is at the target light-emitting brightness or the main light-emitting device 111 and the secondary light-emitting device 112 are both at the target light-emitting brightness, the first end ED1 of the main driving module 121 can receive the same data voltage in these two cases to generate the same driving current, and then the light-emitting brightness of the main light-emitting device 111 in the above two cases is the target light-emitting brightness. Therefore, the display panel 01 provided by the embodiments of the present application has relatively low computing power requirements for the driving IC.

[0070] In addition, in the technical solution provided by the embodiments of the present application, the data voltages received by the main driving module 121 and the secondary driving module 121' included in the pixel circuit 12 are both transmitted to their first ends ED1 by the same data writing module 122, which is beneficial to obtaining a pixel circuit 12 with a relatively small occupied area and a relatively simple structure.

[0071] Figure 3 For Figure 1 a schematic cross-sectional view along the A1 - A2 direction in

[0072] In an embodiment of the present application, asFigure 3 As shown, the main light-emitting device 111 includes a first electrode 1111 and a second electrode 1112, and the secondary light-emitting device 112 includes a first electrode 1121 and a second electrode 1122.

[0073] If the first electrode 1111 of the main light-emitting device 111 is electrically connected to the first electrode 1121 of the secondary light-emitting device 112, then the first electrodes 1111 and 1121 included in the main light-emitting device 111 and the secondary light-emitting device 112 respectively can be electrically connected to the same signal line or electrode, reducing the wiring difficulty. For example, the first electrodes 1111 of the main light-emitting device 111 and the first electrodes 1121 of the secondary light-emitting device 112 both receive a low-level power supply voltage, and as Figure 3 shown, the first electrode 1111 of the main light-emitting device 111 and the first electrode 1121 of the secondary light-emitting device 112 are both part of the cathode layer.

[0074] Combined with Figure 3 and Figure 1 and Figure 2 , the second electrode 1112 of the main light-emitting device 111 is electrically connected to the main light-emitting control module 123, and the second electrode 1122 of the secondary light-emitting device 112 is electrically connected to the secondary light-emitting control module 123'. The light-emitting control module can control whether the light-emitting device 110 it is electrically connected to can be electrically connected to the corresponding driving module. Therefore, even if the first electrode 1111 of the main light-emitting device 111 is electrically connected to the first electrode 1121 of the secondary light-emitting device 112, since the second electrode 1112 of the main light-emitting device 111 and the second electrode 1122 of the secondary light-emitting device 112 are electrically connected to different light-emitting control modules respectively, it makes it flexible and controllable whether the main light-emitting device 111 can emit light and whether the secondary light-emitting device 112 can emit light.

[0075] As Figure 3 shown, a light-emitting layer 1100 is included between the first electrode 1111 and the second electrode 1112 of the main light-emitting device 111, and a light-emitting layer 1100 is also included between the first electrode 1121 and the second electrode 1122 of the secondary light-emitting device 112. In addition, the main light-emitting device 111 and the secondary light-emitting device 112 in the same sub-pixel 11 emit light of the same color, then the light-emitting layer 1100 belonging to the main light-emitting device 111 and the light-emitting layer 1100 belonging to the secondary light-emitting device 112 in the same sub-pixel 11 can be prepared simultaneously. For example, when the light-emitting layer 1100 is prepared by an evaporation process, the light-emitting layer 1100 included in the main light-emitting device 111 and the light-emitting layer 1100 included in the secondary light-emitting device 112 in the same sub-pixel 11 can use the same mask plate, and the evaporation materials corresponding to the light-emitting layers 1100 of the main light-emitting device 111 and the secondary light-emitting device 112 in the same sub-pixel 11 can be evaporated and deposited into the sub-pixel 11 through the same opening in the mask plate. In addition, as Figure 3As shown, the light-emitting layers 1100 included in the main light-emitting device 111 and the sub-light-emitting device 112 in the same sub-pixel 11 may be an integrated structure.

[0076] The second electrode 1121 may be a reflective electrode. At this time, the first electrode 1111 of the main light-emitting device 111 may be located on the side of the second electrode 1112 facing the light-emitting surface of the display panel 01, and the first electrode 1121 of the sub-light-emitting device 112 may be located on the side of the second electrode 1122 facing the light-emitting surface of the display panel 01. Then, the second electrode 1112 of the main light-emitting device 111 may be located on the side of the first electrode 1111 facing the backlight surface of the display panel 01, and the second electrode 1122 of the sub-light-emitting device 112 may be located on the side of the first electrode 1121 facing the backlight surface of the display panel 01. Therefore, the light emitted by the main light-emitting device 111 toward the backlight surface of the display panel 01 can be reflected by the second electrode 1112 of the main light-emitting device 111 and then emitted toward the light-emitting surface of the display panel 01. The light emitted by the sub-light-emitting device 112 toward the backlight surface of the display panel 01 can be reflected by the second electrode 1122 of the sub-light-emitting device 112 and then emitted toward the light-emitting surface of the display panel 01, thereby increasing the light extraction rate of the display panel 01, improving the brightness of the display panel 01, or reducing the power consumption of the display panel 01.

[0077] In the embodiment of the present application, the sub-light-emitting device 112 in the sub-pixel 11 is located on the periphery of the main light-emitting device 111. The plane where the second electrode 1112 in the main light-emitting device 111 is located is parallel to the plane where the display panel 01 is located, and the angle α between the plane where the second electrode 1122 in the sub-light-emitting device 112 is located and the plane where the display panel 01 is located is greater than 0°. Since the plane where the second electrode 1112 in the main light-emitting device 111 is located is parallel to the plane where the display panel 01 is located, the light emitted by the main light-emitting device 111 is substantially parallel to the plane where the display panel 01 is located, that is, the main light-emitting device 111 mainly emits positive-view or small-view light. Since the angle α between the plane where the second electrode 1122 in the sub-light-emitting device 112 is located and the plane where the display panel 01 is located is greater than 0°, the plane where the second electrode 1122 in the sub-light-emitting device 112 is located is an inclined surface relative to the plane where the display panel 01 is located. Therefore, the light emitted by the sub-light-emitting device 112 is mainly large-angle light. For example, as Figure 3 shown, the sub-light-emitting device 112 on the left side of the main light-emitting device 111 can emit light whose propagation direction is toward the upper right, and the sub-light-emitting device 112 on the left side of the main light-emitting device 111 can emit light whose propagation direction is toward the upper right.

[0078] It should be noted that the plane where the second electrode 1112 in the main light-emitting device 111 is parallel to the plane where the display panel 01 is located does not mean that the second electrode 1112 of the main light-emitting device 111 must be a flat plane. The second electrode 1112 can be a plane with a rough surface within the process accuracy range; the second electrode 1112 can also be an arc surface with a certain curvature. The plane where the second electrode 1112 in the main light-emitting device 111 is parallel to the plane where the display panel 01 is located can mean that the plane where the main part of the second electrode 1112 in the main light-emitting device 111 is located or the section plane of the second electrode 1112 is parallel to the plane where the display panel 01 is located.

[0079] Correspondingly, the angle α between the plane where the second electrode 1122 in the secondary light-emitting device 112 is located and the plane where the display panel 01 is located is greater than 0°, which does not mean that the second electrode 1122 of the secondary light-emitting device 112 must be a flat plane. The second electrode 1122 can be a plane with a rough surface within the process accuracy range; the second electrode 1122 can also be an arc surface with a certain curvature. The angle α between the plane where the second electrode 1122 in the secondary light-emitting device 112 is located and the plane where the display panel 01 is located being greater than 0° can mean that the angle α between the plane where the main part of the second electrode 1122 in the secondary light-emitting device 112 is located or the section plane of the second electrode 1122 and the plane where the display panel 01 is located is greater than 0°.

[0080] As Figure 3 shown, the display panel 01 can include a pixel definition layer 101 and pixel definition slots are formed on the pixel definition layer 101. The second electrode 1112 of the main light-emitting device 111 and the second electrode 1122 of the secondary light-emitting device 112 are mainly located in the pixel definition slots, and the opening area of the pixel definition slots is basically the area of the sub-pixel 11. Among them, the side wall of the pixel definition slot can be an inclined side wall, and the second electrode 1122 of the secondary light-emitting device 112 is arranged on the side wall of the pixel definition slot so that the plane where it is located can be an inclined plane.

[0081] In an embodiment of the present application, as Figure 1 shown, the secondary light-emitting devices 112 in the sub-pixel 11 can be located on opposite sides of the main light-emitting device 111. For example, as Figure 1 shown, the sub-pixel 11 includes 2 secondary light-emitting devices 112, and the 2 secondary light-emitting devices 111 are respectively located on opposite sides of the main light-emitting device 111.

[0082] Figure 4 It is a schematic diagram of a display panel provided by an embodiment of the present application.

[0083] In an embodiment of the present application, as Figure 4As shown, the secondary light-emitting device 112 in the sub-pixel 11 can be located on either side of the primary light-emitting device 111. For example, as Figure 4 shown, the sub-pixel 11 includes 4 secondary light-emitting devices 112, and the 4 secondary light-emitting devices 111 are respectively located above, below, to the left, and to the right of the primary light-emitting device 111.

[0084] Figure 5 This is a schematic diagram of the light emission of a sub-pixel in a display panel provided by an embodiment of the present application.

[0085] In some embodiments of the present application, as Figure 5 shown, the operating modes of the display panel 01 include a privacy mode and a sharing mode. In the sharing mode, users can see the display content of the display panel 01 from multiple viewing angles; in the privacy mode, users need to be at a specific viewing angle to see the display content of the display panel 01.

[0086] Among them, in the privacy mode, the primary light-emitting device 111 emits light and the secondary light-emitting device 112 does not emit light; in the sharing mode, the primary light-emitting device 111 and at least some of the secondary light-emitting devices 112 emit light.

[0087] When the secondary light-emitting device 112 is located outside the primary light-emitting device 111 in the sub-pixel 11 and the angle α between the plane where the second electrode 1122 serving as the reflective electrode in the secondary light-emitting device 112 and the plane where the display panel 01 is located is greater than 0°, the secondary light-emitting device 112 can emit large-angle light L1 toward the light-emitting surface of the display panel 01. For example, as Figure 5 shown, the secondary light-emitting device 112 located on the left side of the primary light-emitting device 111 in can emit large-angle light L1 toward the upper right of the area where the sub-pixel 11 is located, and the secondary light-emitting device 112 located on the right side of the primary light-emitting device 111 can emit large-angle light L1 toward the upper left of the area where the sub-pixel 11 is located. And the primary light-emitting device 111 can emit small-angle light L2 toward the light-emitting surface of the display panel 01. Therefore, when the primary light-emitting device 111 and at least some of the secondary light-emitting devices 112 emit light, the primary light-emitting device 111 can mainly provide display light for users within a small viewing angle range, and the light-emitting secondary light-emitting devices 112 can mainly provide display light for users within a large viewing angle range. The display content of the display panel 01 can be viewed by users within a small viewing angle and some large viewing angles, which is the sharing mode. When the primary light-emitting device 111 emits light and none of the secondary light-emitting devices 112 emits light, the display content of the display panel 01 can only be viewed by users within a small viewing angle range, which is the privacy mode.

[0088] Correspondingly, in the privacy mode, in order to make the main light-emitting device 111 emit light and any one of the secondary light-emitting devices 112 not emit light, the main light-emitting control module 123 in the pixel circuit 12 is turned on to electrically connect the main driving module 121 and the main light-emitting device 111, so that the main light-emitting device 111 can emit light; and, the secondary light-emitting control module 123' in the pixel circuit 12 is turned off to disconnect the secondary light-emitting device 112 from the secondary driving module 121', so that the secondary light-emitting device 112 does not emit light. In the sharing mode, in order to make the main light-emitting device 111 and at least some of the secondary light-emitting devices 112 emit light, the main light-emitting control module 123 in the pixel circuit 12 is turned on to electrically connect the main driving module 121 and the main light-emitting device 111, so that the main light-emitting device 111 can emit light, and at least some of the secondary light-emitting control modules 123' in the pixel circuit 12 are turned on to electrically connect the secondary light-emitting devices 112 connected thereto and the secondary driving module 121', so that these secondary light-emitting devices 112 can emit light.

[0089] It should be noted that, in some sharing modes, the secondary light-emitting devices 112 in the sub-pixels 11 may not emit light. For example, as Figure 1 shown, both of the 2 secondary light-emitting devices 112 in the sub-pixel 11 do not emit light; for example, as Figure 4 shown, all 4 secondary light-emitting devices 112 in the sub-pixel 11 do not emit light. In some sharing modes, some of the secondary light-emitting devices 112 in the sub-pixels 11 may not emit light and some of the secondary light-emitting devices 111 may emit light. For example, as Figure 4 shown, the upper and lower 2 secondary light-emitting devices 112 in the sub-pixel 11 do not emit light and the left and right 2 secondary light-emitting devices 112 emit light, so as to achieve privacy for the upper and lower angles and sharing for the left and right angles.

[0090] Figure 6 is Figure 1 a schematic cross-sectional view along the A1-A2 direction in

[0091] In order to achieve a better privacy effect, the pixel defining slot can have a deeper depth to better collimate the light of the main light-emitting device 111, and thus achieve a better privacy effect. In an embodiment of the present application, as Figure 6 shown, the display panel 01 may further include a planarization layer 102, and the planarization layer 102 is located on the side of the pixel defining layer 101 away from the light-emitting surface of the display panel 01. Among them, the planarization layer 102 is provided with a groove on the side away from the light-emitting surface of the display panel 01 in the area where the sub-pixel 11 is located, and the pixel defining layer 101 is provided with a hollow portion in the area where the sub-pixel 11 is located. The groove and the hollow portion communicate to form a pixel defining slot, so that the pixel defining slot has a deeper depth.

[0092] Figure 7A schematic diagram of the connection between a sub-pixel and a pixel circuit provided by an embodiment of the present application.

[0093] In an embodiment of the present application, as Figure 7 shown, the sub-pixel 11 includes at least two sub-light-emitting devices 112. Among them, the at least two sub-light-emitting devices 112 are respectively electrically connected to the same sub-driving module 121' through different sub-light-emitting control modules 123', that is, multiple sub-light-emitting devices 112 belonging to the same sub-pixel 11 are electrically connected to the same sub-driving module 121' through different sub-light-emitting control modules 123'. For example, as Figure 7 shown, the sub-pixel 11 includes a main light-emitting device 111 and two sub-light-emitting devices 112. The main light-emitting device 111 is electrically connected to the main driving module 121 through the main light-emitting control module 123, and the two sub-light-emitting devices 112 are respectively connected to the same sub-driving module 121' through different sub-light-emitting control modules 123'.

[0094] In this embodiment, when different sub-light-emitting devices 112 in the same sub-pixel 11 emit light, the same sub-driving module 121' generates driving current. For example, the sub-pixel 11 includes two sub-light-emitting devices 112 as Figure 7 shown and the two sub-light-emitting devices 112 are electrically connected to the same sub-driving module through different sub-light-emitting control modules. When any one of the two sub-light-emitting devices 112 needs to emit light, the sub-light-emitting control module 123' connected to the any one of the sub-light-emitting devices 112 is turned on so that the any one of the sub-light-emitting devices 112 is electrically connected to the sub-driving module 121'; when both of the two sub-light-emitting devices 112 need to emit light, the sub-light-emitting control modules 123' respectively connected to the two sub-light-emitting devices 112 are both turned on so that the two sub-light-emitting devices 112 are both electrically connected to the sub-driving module 121'.

[0095] When the sub-pixel 11 includes multiple sub-light-emitting devices 112 and the multiple sub-light-emitting devices 112 are respectively electrically connected to the same sub-driving module 121' through different sub-light-emitting control modules 123', the pixel circuit 12 electrically connected to the sub-pixel 11 includes a smaller number of sub-driving modules 121'. Therefore, the structure of the pixel circuit 12 is simpler and the occupied area can be smaller.

[0096] In this embodiment, although a secondary driving module 121' needs to provide driving current required for light emission for a plurality of secondary light-emitting devices 112, the primary driving module that provides driving current for the primary light-emitting device 111 does not provide light-emitting driving current for other light-emitting devices. Since the secondary light-emitting devices 112 occupy a relatively small area in the sub-pixel 11 and the primary light-emitting device 111 occupies a relatively large area in the sub-pixel 11, therefore, a slight difference in the light-emitting brightness of the secondary light-emitting devices 112 has little impact on the overall brightness of the sub-pixel 11, and the light-emitting brightness of the primary light-emitting device 111 is the main factor affecting the overall brightness of the sub-pixel 11. Therefore, the technical solution of the embodiment of the present application can not only enable the sub-pixel 11 to have an ideal brightness, but also make the structure of the pixel circuit 12 simple and occupy a small area.

[0097] It should be noted that Figure 7 illustrates the case where two secondary light-emitting devices 112 are included in the sub-pixel 11. In an actual product, the sub-pixel 11 may include secondary light-emitting devices 112 with a quantity greater than or equal to 3, and different secondary light-emitting devices 112 included in the sub-pixel 11 can be electrically connected to the same secondary driving module 121' through different secondary light-emitting control modules 123'.

[0098] In an embodiment of the present application, as Figure 2 shown, the sub-pixel 11 includes at least two secondary light-emitting devices 112, wherein the at least two secondary light-emitting devices 112 are respectively electrically connected to different secondary driving modules 121' through different secondary light-emitting control modules 123', that is, a plurality of secondary light-emitting devices 112 belonging to the same sub-pixel 11 are respectively electrically connected to different secondary driving modules 121' through different secondary light-emitting control modules 123'. For example, as Figure 2 shown, the sub-pixel 11 includes a primary light-emitting device 111 and two secondary light-emitting devices 112. The primary light-emitting device 111 is electrically connected to the primary driving module 121 through the primary light-emitting control module 123. One of the two secondary light-emitting devices 112 is electrically connected to one secondary driving module 121' through one secondary light-emitting control module 123', and the other secondary light-emitting device 112 is electrically connected to another secondary driving module 121' through another secondary light-emitting control module 123'.

[0099] Figure 8 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0100] In an embodiment of the present application, as Figure 8As shown, the pixel circuit 12 further includes a main reset module 124 and a secondary reset module 124'. The output terminal OUT4 of the main reset module 124 is electrically connected to the main light-emitting device 111, and the output terminal OUT4' of the secondary reset module 124' is electrically connected to the secondary light-emitting device 112. In addition, the input terminal IN4 of the main reset module 124 is electrically connected to the reset signal line RL, and the input terminal IN4' of the secondary reset module 124' is electrically connected to the reset signal line RL.

[0101] Among them, the main reset module 124 is used to reset the main light-emitting device 111, and the secondary reset module 124' is used to reset the secondary light-emitting device 112. When it is necessary to reset the main light-emitting device 111, the main reset module 124 is turned on and used to transmit the reset signal on the reset signal line RL to one end of the main light-emitting device 111 that is electrically connected to the main reset module 124, so as to reset this end in the main light-emitting device 111. When it is necessary to reset the secondary light-emitting device 112, the secondary reset module 124' is turned on and used to transmit the reset signal on the reset signal line RL to one end of the secondary light-emitting device 112 that is electrically connected to the secondary reset module 124', so as to reset this end in the secondary light-emitting device 112. For example, as Figure 8 shown, the output terminal OUT4 of the main reset module 124 is electrically connected to the anode terminal of the main light-emitting device 111, and when the main reset module 124 is turned on, the anode terminal of the main light-emitting device 111 can be reset. The output terminal OUT4' of the secondary reset module 124' is electrically connected to the anode terminal of the secondary light-emitting device 112, and when the secondary reset module 124' is turned on, the anode terminal of the secondary light-emitting device 112 can be reset.

[0102] In this embodiment, whether it is the main light-emitting device 111 or the secondary light-emitting device 112, different light-emitting devices need to be electrically connected to different reset modules to avoid short circuits when different light-emitting devices are electrically connected to the same reset module.

[0103] In an embodiment of the present application, the sub-pixel 11 includes at least two secondary light-emitting devices 112, and the pixel circuit 12 includes at least two secondary reset modules 124'. Among them, the at least two secondary light-emitting devices 112 are respectively electrically connected to the output terminals OUT4' of different secondary reset modules 124'. For example, as Figure 8 shown, the sub-pixel 11 includes 2 secondary light-emitting devices 112, and the anode terminals of the 2 secondary light-emitting devices 112 are respectively electrically connected to the output terminals OUT4' of different secondary reset modules 124'.

[0104] In the embodiment of the present application, if the control terminals of at least two secondary reset modules 124' are electrically connected to the same control line, the at least two secondary reset modules 124' can be turned on simultaneously and reset the secondary light-emitting devices 112 to which they are respectively electrically connected.

[0105] Figure 9 Schematic diagram of the connection between sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application.

[0106] In an implementable manner, the control terminals of all sub-reset modules 124' in the pixel circuit 12 are electrically connected to the same control line. For example, as Figure 8 shown, the pixel circuit 12 includes 2 sub-reset modules 124', the output terminals OUT4' of the 2 sub-reset modules 124' are respectively electrically connected to different sub-light-emitting devices 112, and the control terminals CTR4' of the 2 sub-reset modules 124' are electrically connected to the same control line CL. For example, as Figure 9 shown, the pixel circuit 12 includes 4 sub-reset modules 124', the output terminals OUT4' of the 4 sub-reset modules 124' are respectively electrically connected to different sub-light-emitting devices 112, and the control terminals CTR4' of the 4 sub-reset modules 124' are electrically connected to the same control line CL.

[0107] By electrically connecting the control terminals of at least two sub-reset modules 124' to the same control line CL, the number of control lines CL for controlling the turn-on and turn-off of the sub-reset modules 124' can be reduced, and the wiring difficulty in the display panel 01 can be reduced.

[0108] Figure 10 Schematic diagram of the connection between sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application.

[0109] In an implementable manner, the control terminals CTR4' of some sub-reset modules 124' in the pixel circuit 12 are electrically connected to the same control line CL, and the control terminals CTR4' of some sub-reset modules 124' are electrically connected to different control lines CL. For example, as Figure 10 shown, the pixel circuit 12 includes 4 sub-reset modules 124', and the output terminals OUT4' of the 4 sub-reset modules 124' are respectively electrically connected to different sub-light-emitting devices 112. The control terminals CTR4' of 2 of the 4 sub-reset modules 124' are electrically connected to 1 control line CL1, and the control terminals CTR4' of the other 2 sub-reset modules 124' are electrically connected to another control line CL2.

[0110] Combined with Figure 4 and Figure 10, in some anti-peeping modes, the display panel 01 is used to achieve upper and lower anti-peeping. In this mode, the upper and lower two sub-light-emitting devices 112 in the sub-pixel 11 can remain unlit, that is, it is not necessary to reset these two sub-light-emitting devices 112 every time the display panel 01 displays multiple frames of images; in some anti-peeping modes, the display panel 01 is used to achieve left and right anti-peeping. In this mode, the left and right two sub-light-emitting devices 112 in the sub-pixel 11 can remain unlit, that is, it is not necessary to reset these two sub-light-emitting devices 112 every time the display panel 01 displays multiple frames of images. In this implementation, by electrically connecting the control terminals of some sub-reset modules 124' to different control lines CL, the reset frequency of some sub-light-emitting devices 112 when they are unlit can be reduced, thereby reducing power consumption.

[0111] In an embodiment of the present application, as Figure 8 and Figure 9 shown, the control terminal CTR4 of the main reset module 124 is electrically connected to the control terminal CTR4' of the sub-reset module 124' by the same control line CL. Therefore, the main light-emitting device 111 and the sub-light-emitting device 112 can be reset simultaneously. For example, as Figure 8 shown, the pixel circuit 12 includes a main reset module 124 and two sub-reset modules 124'. The control terminal CTR4 of the main reset module 124 and the control terminals CTR4' of the two sub-reset modules 124' are electrically connected and both are electrically connected to the same control line CL. For example, as Figure 9 shown, the pixel circuit 12 includes a main reset module 124 and four sub-reset modules 124'. The control terminal CTR4 of the main reset module 124 and the control terminals CTR4' of the four sub-reset modules 124' are electrically connected and both are electrically connected to the same control line CL. This embodiment can effectively reduce the number of control lines CL electrically connected to the main reset module 124 and the sub-reset module 124' in the pixel circuit 12.

[0112] Figure 11 Schematic diagram of the connection between the sub-pixel and the pixel circuit in a display panel provided by an embodiment of the present application.

[0113] In an embodiment of the present application, as Figure 11 shown, the control terminal CTR4 of the main reset module 124 is electrically connected to the control terminal CTR4' of the sub-reset module 124' by different control lines CL. Therefore, the reset of the main light-emitting device 111 and the reset of the sub-light-emitting device 112 can be controlled separately. For example, as Figure 11 shown, the pixel circuit 12 includes a main reset module 124 and two sub-reset modules 124'. The control terminal CTR4 of the main reset module 124 is electrically connected to the control line CL3 and the control terminals CTR4' of the two sub-reset modules 124' are electrically connected to the control line CL2.

[0114] In the technical solution provided by this embodiment, if a control line CL is not electrically connected to the control terminal CTR4 of the main reset module 124 and the control terminal CTR4' of the secondary reset module 124' at the same time, the load of the control line CL can be reduced, and the reset accuracy of the light-emitting device 110 can be improved.

[0115] In addition, in this embodiment, whether to use the secondary reset module 124' to reset the secondary light-emitting device 112 can be selected according to the working mode of the display panel 01, which is beneficial to reducing power consumption. For example, in the privacy mode, the main light-emitting device 111 in the sub-pixel 11 emits light and the secondary light-emitting device 112 remains unlit. At this time, it is not necessary to reset the secondary light-emitting device 112 when the display panel 01 displays multiple frames of images and it is necessary to reset the main light-emitting device 111. Therefore, the technical solution provided by the embodiment of the present application can achieve resetting the main light-emitting device 111 in the privacy mode and reducing the reset frequency of the secondary light-emitting device 112 or not resetting the secondary light-emitting device 112.

[0116] Figure 12 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application. Figure 13 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0117] In an embodiment of the present application, as Figure 12 and Figure 13 , the main reset module 124 includes a main reset transistor T41. The first pole of the main reset transistor T41 is electrically connected to the reset signal line RL, and the second pole of the main reset transistor T41 is electrically connected to the main light-emitting device 111. Among them, the first pole of the main reset transistor T41 can be the input terminal IN4 of the main reset module 124, the second pole of the main reset transistor T41 can be the output terminal OUT4 of the main reset module 124, and the gate of the main reset transistor T41 can be the control terminal CTR4 of the main reset module 124.

[0118] Please continue to refer to Figure 12 and Figure 13 , the secondary reset module 124' includes a secondary reset transistor T42. The first pole of the secondary reset transistor T42 is electrically connected to the reset signal line RL, and the second pole of the secondary reset transistor T42 is electrically connected to the secondary light-emitting device 112. Among them, the first pole of the secondary reset transistor T42 can be the input terminal IN4' of the secondary reset module 124', the second pole of the secondary reset transistor T42 can be the output terminal OUT4' of the secondary reset module 124', and the gate of the secondary reset transistor T42 can be the control terminal CTR4' of the secondary reset module 124'.

[0119] Among them, the first poles of the main reset transistor T41 and the secondary reset transistor T42 can be connected to the same reset signal line RL. For example, as Figure 12 and Figure 13 shown, the first poles of the main reset transistor T41 and the secondary reset transistor T42 are both electrically connected to the first reset signal line RL1. In addition, the first poles of the main reset transistor T41 and the secondary reset transistor T42 can also be connected to different reset signal lines RL.

[0120] As Figure 12 and Figure 13 shown, the gates of at least some of the secondary reset transistors T42 in the pixel circuit 12 are electrically connected to the same control line CL. In addition, as Figure 12 shown, the gate of the main reset transistor T41 in the pixel circuit 12 and the gate of the secondary reset transistor T42 can be electrically connected to the same control line CL, or, as Figure 14 shown, the gate of the main reset transistor T41 in the pixel circuit 12 and the gate of the secondary reset transistor T42 can be electrically connected to different control lines CL.

[0121] Figure 14 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0122] In an embodiment of the present application, as Figure 14 shown, the main driving module 121 includes a main driving transistor T01. The first pole of the main driving transistor T01 is electrically connected to the input terminal IN3 of the main light-emitting control module 123. The output terminal OUT3 of the main light-emitting control module 123 is electrically connected to the main light-emitting device 111. Then, when the main light-emitting control module 123 is turned on, the first pole of the main driving transistor T01 is electrically connected to the main light-emitting device 111 and can be used to generate the driving current required for the main light-emitting device 111 to emit light. The secondary driving module 121' includes a secondary driving transistor T02. The first pole of the secondary driving transistor T02 is electrically connected to the input terminal IN3' of the secondary light-emitting control module 123'. The output terminal OUT3' of the secondary light-emitting control module 123' is electrically connected to the secondary light-emitting device 112. Then, when the secondary light-emitting control module 123' is turned on, the first pole of the secondary driving transistor T02 is electrically connected to the secondary light-emitting device 112 and can be used to generate the driving current required for the secondary light-emitting device 112 to emit light. Among them, the first pole of the main driving transistor T01 can be the output terminal OUT1 of the main driving module 121, and the first pole of the secondary driving transistor T02 can be the output terminal OUT1' of the secondary driving module 121'.

[0123] The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected and are both electrically connected to the output terminal OUT2 of the data writing module 122. The data writing module 122 is used to write a data voltage to the gates of the main driving transistor T01 and the secondary driving transistor T02. The main driving transistor T01 can generate a corresponding driving current according to the voltage of its second pole and the voltage of its gate. The secondary driving transistor T02 can generate a corresponding driving current according to the voltage of its second pole and the voltage of its gate. Among them, the gate of the main driving transistor T01 can be the first end ED1 of the main driving module 121, that is, the control end of the active module 121; the gate of the secondary driving transistor T02 can be the control end ED1' of the secondary driving module 121', that is, the control end of the secondary active module 121'.

[0124] Figure 15 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application. Figure 16 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0125] In an embodiment of the present application, as Figure 15 and Figure 16 shown, the pixel circuit further includes a threshold grabbing module 125. The input terminal IN5 of the threshold grabbing module 125 is electrically connected to the first pole or the second pole of the main driving transistor T01, and the output terminal OUT5 of the threshold grabbing module 125 is electrically connected to the gate of the main driving transistor T01. For example, as Figure 15 shown, the input terminal IN5 of the threshold grabbing module 125 is electrically connected to the second pole of the main driving transistor T01 and the output terminal OUT5 of the threshold grabbing module 125 is electrically connected to the gate of the main driving transistor T01. For example, as Figure 16 shown, the input terminal IN5 of the threshold grabbing module 125 is electrically connected to the first pole of the driving transistor T01 and the output terminal OUT5 of the threshold grabbing module 125 is electrically connected to the gate of the main driving transistor T01.

[0126] When the input terminal IN5 of the threshold grabbing module 125 is electrically connected to the second pole of the main driving transistor T01 and the output terminal OUT5 of the threshold grabbing module 125 is electrically connected to the gate of the main driving transistor T01, when grabbing the threshold of the main driving transistor T01, the relevant voltage will be transmitted from the first pole of the driving transistor T01 through the turned-on driving transistor 125 to the second pole of the driving transistor T01, and then transmitted to the gate of the driving transistor T01 through the turned-on threshold grabbing module 125.

[0127] When the input terminal IN5 of the threshold grabbing module 125 is electrically connected to the first pole of the main driving transistor T01 and the output terminal OUT5 of the threshold grabbing module 125 is electrically connected to the gate of the main driving transistor T01, when grabbing the threshold of the main driving transistor T01, the relevant voltage will be transmitted from the second pole of the driving transistor T01 to the first pole of the driving transistor T01 through the turned-on driving transistor 125, and then further transmitted to the gate of the driving transistor T01 through the turned-on threshold grabbing module 125.

[0128] Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, the threshold grabbing module 125 also grabs the threshold voltage of the main driving transistor T01 to the gate of the sub-driving transistor T02. Among them, the transistor specifications of the sub-driving transistor T02 and the main driving transistor T01 are almost the same, so the threshold voltage of the sub-driving transistor T02 is basically the same as the threshold voltage of the main driving transistor T01. Therefore, when the threshold grabbing module 125 grabs the threshold voltage of the main driving transistor T01 to the gate of the main driving transistor T01, it also grabs the threshold voltage of the sub-driving transistor T01 to the gate of the sub-driving transistor T02 at the same time. In addition, since the light-emitting area ratio of the sub-light-emitting device 112 in the sub-pixel 11 is relatively small, and its slightly unsatisfactory brightness has little impact on the overall brightness of the sub-pixel 11, therefore, a threshold grabbing module 125 may not be provided for the sub-driving transistor T02 that provides a driving current for the sub-light-emitting device 112.

[0129] The threshold grabbing module 125 can grab the threshold voltages of the main driving transistor T01 and the sub-driving transistor T02 to the gate, so that the driving current generated by the main driving transistor T01 is not affected by threshold drift and the driving current generated by the sub-driving transistor T01 is not affected by threshold drift. In addition, sharing the threshold grabbing transistor 125 by the main driving transistor T01 and the sub-driving transistor T02 in the pixel circuit 12 can reduce the complexity of the structure of the pixel circuit 12 and the area it may occupy.

[0130] Figure 17 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0131] In a technical solution corresponding to this embodiment, as Figure 17 shown, the pixel circuit 12 further includes a main power supply voltage writing module 126 and a sub-power supply voltage writing module 126'.

[0132] The input terminal IN6 of the main power supply voltage writing module 126 is electrically connected to the first power supply voltage line VDD, and the output terminal OUT6 of the main power supply voltage writing module 126 is electrically connected to the second pole of the main driving transistor T01. The main power supply voltage writing module 126 is used to write the power supply voltage on the first power supply voltage line VDD to the second pole of the main driving transistor T01. When the main power supply voltage writing module 126 is turned on, the power supply voltage transmitted on the first power supply voltage line VDD can be transmitted to the second pole of the main driving transistor T01. The main driving transistor T01 can be turned on or off based on the voltage difference between its gate and the second pole. When the main driving transistor T01 is turned on and electrically conducts with the main light-emitting device 111, a corresponding driving current can be generated.

[0133] The input terminal IN6' of the secondary power supply voltage writing module 126' is electrically connected to the first power supply voltage line VDD, and the output terminal OUT6' of the secondary power supply voltage writing module 126' is electrically connected to the second pole of the secondary driving transistor T02. The secondary power supply voltage writing module 126' is used to write the power supply voltage on the first power supply voltage line VDD to the second pole of the secondary driving transistor T02. When the secondary power supply voltage writing module 126' is turned on, the power supply voltage transmitted on the first power supply voltage line VDD can be transmitted to the second pole of the secondary driving transistor T02. The secondary driving transistor T02 can be turned on or off based on the voltage difference between its gate and the second pole. When the main driving transistor T02 is turned on and electrically conducts with the secondary light-emitting device 112, a corresponding driving current can be generated.

[0134] In this technical solution, different power supply voltage writing modules are electrically connected between the second pole of the main driving transistor T01 and the first power supply voltage line VDD and between the second pole of the secondary driving transistor T02 and the first power supply voltage line VDD respectively. Then, whether the second pole of the active driving transistor T01 is supplied with the power supply voltage on the first power supply voltage line VDD and whether the second pole of the secondary driving transistor T02 is supplied with the power supply voltage on the first power supply voltage line VDD can be flexibly controlled. For example, in an anti-peeping mode, the main light-emitting device 111 needs to emit light and the secondary light-emitting devices 112 do not need to emit light. At this time, the main power supply voltage writing module 126 is turned on and the power supply voltage on the first power supply voltage line VDD is transmitted to the second pole of the main driving transistor T01. The second pole of the secondary driving transistor T02 does not need to receive the power supply voltage and the secondary power supply voltage writing module 126' does not need to be turned on.

[0135] Figure 18 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0136] In this technical solution, as Figure 18As shown, the main power supply voltage writing module 126 may include a main power supply voltage writing transistor T61, and the secondary power supply voltage writing module 126' may include a secondary power supply voltage writing transistor T62.

[0137] The first pole of the main power supply voltage writing transistor T61 is electrically connected to the first power supply voltage line VDD, and the second pole of the main power supply voltage writing transistor T61 is electrically connected to the second pole of the main driving transistor T01. The first pole of the main power supply voltage transistor T61 may be the input terminal IN6 of the main power supply voltage writing module 126, and the second pole of the main power supply voltage writing transistor T61 may be the output terminal OUT6 of the main power supply voltage writing module 126.

[0138] The first pole of the secondary power supply voltage writing transistor T62 is electrically connected to the first power supply voltage line VDD, and the second pole of the secondary power supply voltage writing transistor T62 is electrically connected to the second pole of the secondary driving transistor T02. The first pole of the secondary power supply voltage transistor T62 may be the input terminal IN6' of the secondary power supply voltage writing module 126', and the second pole of the main power supply voltage writing transistor T61 may be the output terminal OUT6' of the secondary power supply voltage writing module 126'.

[0139] In an implementable manner, as Figure 17 and Figure 18 shown, the secondary power supply voltage writing module 126' is electrically connected to the secondary driving module 121' in a one-to-one correspondence. For example, as Figure 17 and Figure 18 shown, the pixel circuit 12 includes 2 secondary driving transistors T02 and includes 2 secondary power supply voltage writing modules 126'. The output terminals OUT6' of the 2 secondary power supply voltage writing modules 126' are respectively electrically connected to the second poles of the 2 secondary driving transistors T02, and the input terminals IN6' are electrically connected to the first power supply voltage line VDD. In this implementation manner, whether the second poles of different secondary driving transistors T02 are powered by the power supply voltage on the first power supply voltage line VDD can be controlled more flexibly.

[0140] Figure 19 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application. Figure 20 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0141] In an implementable manner, as Figure 19 and Figure 20 shown, the pixel circuit includes a plurality of secondary driving modules 121'; the same secondary power supply voltage writing module 126' is electrically connected between at least two secondary driving modules 121' and the first power supply voltage line VDD. For example, as Figure 19As shown, the pixel circuit 12 includes 2 sub-driving transistors T02 and includes 1 sub-power voltage writing module 126'. The output terminal OUT6' of the 1 sub-power voltage writing module 126' is electrically connected to the second poles of the 2 sub-driving transistors T02, and the input terminal IN6' is electrically connected to the first power voltage line VDD. For example, as Figure 20 As shown, the pixel circuit 12 includes 4 sub-driving transistors T02 and includes 2 sub-power voltage writing modules 126'. The output terminal OUT6' of one of the 2 sub-power voltage writing modules 126' is electrically connected to the second poles of the 2 sub-driving transistors T02, and the output terminal OUT6' of the other is electrically connected to the second poles of the other 2 sub-driving transistors T02.

[0142] Figure 21 It is a schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0143] In a technical solution corresponding to this embodiment, as Figure 21 As shown, the pixel circuit 12 further includes a power voltage writing module 1260. The power voltage writing module 1260 is electrically connected between the first power voltage line VDD, the main driving module 121, and the sub-driving module 121'. As Figure 21 As shown, the input terminal IN60 of the power voltage writing module 1260 is electrically connected to the first power voltage line VDD, and the output terminal OUT60 of the power voltage writing module 1260 is electrically connected to the second pole of the main driving transistor T01 and the second poles of the sub-driving transistors T02. That is, in this technical solution, the main driving transistor T01 and the sub-driving transistors T02 are electrically connected to the first power voltage line VDD through the same power voltage writing module 1260. In this technical solution, the power voltage module 1260 is used to transmit the power voltage on the first power voltage line VDD to the second pole of the main driving transistor T01 and the second poles of the sub-driving transistors T02 simultaneously when it is turned on.

[0144] In this technical solution, the main driving transistor T01 and the sub-driving transistors T02 use the same power voltage writing module 1260 to receive the power voltage on the first power voltage line VDD, which can simplify the structure of the pixel circuit 12.

[0145] In this technical solution, as Figure 21As shown, the power supply voltage writing module 126 includes a power supply voltage writing transistor T6. The first pole of the power supply voltage writing transistor T6 is electrically connected to the first power supply voltage line VDD, and the second pole of the power supply voltage writing transistor T6 is electrically connected to the second pole of the main driving transistor T01 and the second pole of the sub-driving transistor T02. Among them, the first pole of the power supply voltage writing transistor T6 can be the input terminal IN60 of the power supply voltage writing module 126, and the second pole of the power supply voltage writing transistor T6 can be the output terminal OUT60 of the power supply voltage writing module 126.

[0146] Figure 22 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0147] In a technical solution corresponding to this embodiment, as Figure 22 shown, the data writing module 122 includes a data writing transistor T2. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the second pole of the main driving transistor T01. Among them, the first pole of the data writing transistor T2 can be the input terminal IN2 of the data writing module 122, and the second pole of the data writing transistor T2 can be the output terminal OUT2 of the data writing module 122.

[0148] In addition, please continue to refer to Figure 22 , the threshold grabbing module 125 includes a threshold grabbing transistor T5. The first pole of the threshold grabbing transistor T5 is electrically connected to the first pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. Among them, the first pole of the threshold grabbing transistor T5 can be the input terminal IN5 of the threshold grabbing module 125, and the second pole of the threshold grabbing transistor T5 can be the output terminal OUT5 of the threshold grabbing module 125.

[0149] In this technical solution, after the data writing transistor T2 is turned on, the data voltage on the data line DL is written into the second pole of the main driving transistor T01. The data voltage at the second pole of the main driving transistor T01 is then written into the gate of the main driving transistor T01 through the turned-on main driving transistor T01, and correspondingly, it is also written into the gate of the sub-driving transistor T02. Among them, when the data voltage is written into the gate of the main driving transistor T01, the data voltage also passes through the turned-on threshold grabbing transistor T5, and the data voltage written into the gate of the main driving transistor T01 and the gate of the sub-driving transistor T02 is related to the threshold voltage of the main driving transistor T01.

[0150] Figure 23 For Figure 22 a corresponding equivalent circuit diagram.

[0151] In one embodiment of the present application, the main light-emitting control module 123 includes a main light-emitting control transistor T31, and a first pole of the main light-emitting control transistor T31 is electrically connected to a first pole of the main driving transistor T01, and a second pole of the main light-emitting control transistor T31 is electrically connected to the main light-emitting device 111. Wherein, the first pole of the main light-emitting control transistor T31 can be an input terminal IN3 of the main light-emitting control module 123, and the second pole of the main light-emitting control transistor T31 can be an output terminal OUT3 of the main light-emitting control module 123. The secondary light-emitting control module 123' includes a secondary light-emitting control transistor T32, and a first pole of the secondary light-emitting control transistor T32 is electrically connected to a first pole of the secondary driving transistor T02, and a second pole of the secondary light-emitting control transistor T32 is electrically connected to the secondary light-emitting device 112. Wherein, the first pole of the secondary light-emitting control transistor T32 can be an input terminal IN3' of the secondary light-emitting control module 123', and the second pole of the secondary light-emitting control transistor T32 can be an output terminal OUT3' of the secondary light-emitting control module 123'.

[0152] Such as Figure 23As shown, the sub-pixel 11 includes a main light-emitting device 111 and a secondary light-emitting device 112. Correspondingly, the pixel circuit 11 includes a main driving transistor T01, a secondary driving transistor T02, a main light-emitting control transistor T31, and a secondary light-emitting control transistor T32. The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected. The first pole of the main driving transistor T01 is electrically connected to the first pole of the main light-emitting control transistor T31, and the first pole of the secondary driving transistor T02 is electrically connected to the first pole of the secondary light-emitting control transistor T32. The second pole of the main light-emitting control transistor T31 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary light-emitting control transistor T32 is electrically connected to the anodic terminal of the secondary light-emitting device 112. In addition, the pixel circuit 11 further includes a data writing transistor T2 and a threshold grabbing transistor T5. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the second pole of the main driving transistor T01. The first pole of the threshold grabbing transistor T5 is electrically connected to the first pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. The pixel circuit 11 further includes a main power supply voltage writing transistor T61, a secondary power supply voltage writing transistor T62, a main reset transistor T41, and a secondary reset transistor T41. The first poles of the main power supply voltage writing transistor T61 and the secondary power supply voltage writing transistor T62 are both electrically connected to the first power supply voltage line VDD. The second pole of the main power supply voltage writing transistor T61 is electrically connected to the second pole of the main driving transistor T01, and the second pole of the secondary power supply voltage writing transistor T62 is electrically connected to the second pole of the secondary driving transistor T02. The first poles of the main reset transistor T41 and the secondary reset transistor T41 are both electrically connected to the first reset signal line RL1. The second pole of the main reset transistor T41 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary reset transistor T42 is electrically connected to the anodic terminal of the secondary light-emitting device 112. The pixel circuit 11 may further include a reset transistor T7 and a capacitor Cst. The first pole of the reset transistor T7 is electrically connected to the second reset signal line RL2, and the second pole of the reset transistor T7 is electrically connected to the gate of the main driving transistor T01. One plate of the capacitor Cst is electrically connected to the first power supply voltage line VDD, and the other plate is electrically connected to the gate of the main driving transistor T01. In addition, the cathodic terminals of the main light-emitting device 111 and the secondary light-emitting device 112 may be electrically connected to the second power supply voltage line VEE.

[0153] In an implementation manner of this embodiment, as Figure 23As shown, the gate of the data writing transistor T2 is electrically connected to the scan line S2, the gate of the threshold grabbing transistor T5 is electrically connected to the scan line S5, the gates of the main reset transistor T41 and the sub-reset transistor T41 are electrically connected to the scan line S4, the gate of the reset transistor T7 is electrically connected to the scan line S7, the gates of the main power voltage writing transistor T61 and the sub-power voltage writing transistor T62 are electrically connected to the scan line S6, the gate of the main light emitting control transistor T31 is electrically connected to the scan line S31, and the gate of the sub-light emitting control transistor T32 is electrically connected to the scan line S32.

[0154] Figure 24 is Figure 23 a corresponding timing diagram.

[0155] As Figure 24 shown, a working cycle R0 of the pixel circuit includes a reset stage R1, a data writing stage R2, and a light emitting stage R3. The working modes of the display panel include a shared mode and an anti-peeping mode.

[0156] Combined with Figure 23 and Figure 24 , in the reset stage R1, the scan lines S4 and S7 can transmit an enable signal to control the main reset transistor T41 and the sub-reset transistor T42 to turn on respectively to reset the anodic ends of the main light emitting device 111 and the sub-light emitting device 112, and the reset transistor T7 turns on to reset the gate of the main driving transistor T01. Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, the gate of the sub-driving transistor T02 is thus reset. It should be noted that the reset transistor T7 and the main reset transistor T41 and the sub-reset transistor T42 may not be turned on simultaneously.

[0157] Combined with Figure 23 and Figure 24 , in the data writing stage R2, the scan lines S2 and S5 transmit an enable signal, the data writing transistor T2 and the threshold grabbing transistor T5 turn on, and the data voltage on the data line DL is written into the gate of the main driving transistor T01 through the turned-on data writing transistor T2, the main driving transistor T01, and the threshold grabbing transistor T5. Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, the data voltage is thus written into the gate of the sub-driving transistor T02.

[0158] Combined with Figure 23 and Figure 24, during the light-emitting stage R3 in the anti-peeking mode, the scan lines S6 and S31 transmit an enable signal to turn on the main power voltage writing transistor T61 and the main light-emitting control transistor T31, so that the main driving transistor T01 generates a driving current and controls the main light-emitting device 111 to emit light; the scan line S32 transmits a non-enable signal to turn off the secondary light-emitting control transistor T32, so that the secondary light-emitting device 112 does not emit light. During the light-emitting stage R3 in the shared mode, the scan lines S6, S31 and S32 transmit an enable signal to turn on the main power voltage writing transistor T61, the secondary power voltage writing transistor T62, the main light-emitting control transistor T31 and the secondary light-emitting control transistor T32, so that the main driving transistor T01 generates a driving current and supplies it to the main light-emitting device 111 and the secondary driving transistor T02 generates a driving current and supplies it to the secondary light-emitting device 112.

[0159] Among them, the scan line S4 and the scan line S7 can be multiplexed, and the scan line S2 and the scan line S5 can also be multiplexed. Also, the scan S6 and the scan line S31 can also be multiplexed.

[0160] It should be noted that the gates of the main light-emitting control transistor T31 and the secondary light-emitting control transistor T32 are electrically connected to different scan lines; however, according to the specific forms of the anti-peeking mode and the shared mode of the display panel 01, the gates of multiple secondary light-emitting control transistors T32 in the pixel circuit 11 can be electrically connected to the same scan line so that all the secondary light-emitting devices 112 in the sub-pixel 11 do not emit light simultaneously; or, the gates of some secondary light-emitting control transistors T32 in the pixel circuit 11 and the gates of another part of the secondary light-emitting control transistors T32 can be electrically connected to different scan lines, so that some of the secondary light-emitting devices 111 in the sub-pixel 11 can emit light and some of the secondary light-emitting devices 111 can not emit light simultaneously.

[0161] In addition, the gates of the main power voltage writing transistor T61 and the secondary power voltage writing transistor T62 in the pixel circuit 12 can also be electrically connected to different scan lines. Further, the gates of some secondary power voltage writing transistors T62 in the pixel circuit 12 and the gates of another part of the secondary power voltage writing transistors T62 can also be electrically connected to different scan lines.

[0162] In addition, the gates of the main reset transistor T41 and the secondary reset transistor T42 in the pixel circuit 12 can also be electrically connected to different scan lines. Further, the gates of some secondary reset transistors T42 in the pixel circuit 12 and the gates of another part of the secondary reset transistors T42 can also be electrically connected to different scan lines.

[0163] Figure 25 For Figure 22 a corresponding equivalent circuit diagram, Figure 26 For Figure 25A corresponding timing diagram.

[0164] The equivalent circuit diagram of sub-pixel 11 and pixel circuit 12 can be as Figure 25 shown, and the difference from Figure 23 is that in pixel circuit 12, the gate of main power voltage writing transistor T61 is electrically connected to scan line S61, the gate of secondary power voltage writing transistor T62 is electrically connected to scan line S62, the gate of main reset transistor T41 is electrically connected to scan line S41, and the gate of secondary reset transistor T42 is electrically connected to scan line S42.

[0165] Combined with Figure 25 and Figure 26 , in the reset stage R1 in the anti-peeping mode, scan lines S41 and S7 can transmit an enabling signal to control the main reset transistor T41 to turn on to reset the anode terminal of the main light-emitting device 111, and the reset transistor T7 turns on to reset the gate of the main driving transistor T01; in at least part of the reset stage R1 in the anti-peeping mode, scan line S42 transmits a non-enabling signal, the secondary reset transistor T42 is turned off and there is no need to reset the anode terminal of the secondary light-emitting device 112.

[0166] Combined with Figure 25 and Figure 26 , in the reset stage R1 in the sharing mode, scan lines S41, S42 and S7 can transmit an enabling signal to control both the main reset transistor T41 and the secondary reset transistor T42 to turn on to respectively reset the anode terminal of the main light-emitting device 111 and the anode terminal of the secondary light-emitting device 112, and the reset transistor T7 turns on to reset the gate of the main driving transistor T01.

[0167] Combined with Figure 25 and Figure 26 , in the light-emitting stage R3 in the anti-peeping mode, scan lines S61 and S31 transmit an enabling signal to turn on the main power voltage writing transistor T61 and the main light-emitting control transistor T31, so that the main driving transistor T01 generates a driving current and supplies it to the main light-emitting device 111; and scan lines S62 and S32 transmit a non-enabling signal to turn off the secondary power voltage writing transistor T62 and the secondary light-emitting control transistor T62, so that the secondary light-emitting device 112 does not emit light.

[0168] Combined with Figure 25 and Figure 26, in the light-emitting stage R3 in the sharing mode, the scan lines S61, S62, S31, and S32 transmit enable signals to turn on the main power voltage writing transistor T61, the sub-power voltage writing transistor T62, the main light-emitting control transistor T31, and the sub-light-emitting control transistor T32, so that the main driving transistor T01 generates a driving current and supplies it to the main light-emitting device 111, and the sub-driving transistor T02 generates a driving current and supplies it to the sub-light-emitting device 112.

[0169] Among them, the scan line S41 and the scan line S7 can be multiplexed, and the scan line S2 and the scan line S5 can also be multiplexed. Also, the scan S61 and the scan line S31 can be multiplexed, and the scan S62 and the scan line S32 can be multiplexed.

[0170] It should be noted that some transistors in the pixel circuit 11 can be N-channel transistors and some transistors can be P-channel transistors. For example, Figure 23 and Figure 25 the threshold capture transistor T5 in can be an N-channel transistor and other transistors can be P-channel transistors; or, Figure 23 and Figure 25 the threshold capture transistor T5 and the reset transistor T8 in can be N-channel transistors and other transistors can be P-channel transistors.

[0171] In addition, the pixel circuit 11 may further include a bias transistor, and the bias transistor can be electrically connected to the first pole and / or the second pole of the main driving transistor T01, and is used to transmit a bias voltage to the first pole and / or the second pole of the main driving transistor T01 to reduce the threshold drift of the main driving transistor T01.

[0172] Figure 27 It is a schematic connection diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0173] In a technical solution corresponding to this embodiment, as Figure 27 shown, the data writing module 122 includes a data writing transistor T2. The first pole of the data writing transistor T2 is electrically connected to the data line, and the second pole of the data writing transistor T2 is electrically connected to the first pole of the main driving transistor T01. Among them, the first pole of the data writing transistor T2 can be the input end of the data writing module 122, and the second pole of the data writing transistor T2 can be the output end of the data writing module 122.

[0174] In addition, please continue to refer to Figure 27, the threshold voltage sampling module 125 includes a threshold voltage sampling transistor T5. The first pole of the threshold voltage sampling transistor T5 is electrically connected to the second pole of the main driving transistor, and the second pole of the threshold voltage sampling transistor T5 is electrically connected to the gate of the main driving transistor. Wherein, the first pole of the threshold voltage sampling transistor T5 can be the input terminal IN5 of the threshold voltage sampling module 125, and the second pole of the threshold voltage sampling transistor T5 can be the output terminal OUT5 of the threshold voltage sampling module 125.

[0175] In this technical solution, after the data writing transistor T2 is turned on, the data voltage on the data line DL is written into the first pole of the main driving transistor T01. The data voltage at the first pole of the main driving transistor T01 is then written into the gate of the main driving transistor T01 through the turned-on main driving transistor T01. Correspondingly, it is also written into the gate of the secondary driving transistor T02. Wherein, when the data voltage is written into the gate of the main driving transistor T01, the data voltage also passes through the turned-on threshold voltage sampling transistor T5. The data voltage written into the gate of the main driving transistor T01 and the gate of the secondary driving transistor T02 is related to the threshold voltage of the main driving transistor T01.

[0176] Figure 28 For Figure 27 A corresponding alternative equivalent circuit diagram.

[0177] Such as Figure 28As shown, the sub-pixel 11 includes a main light-emitting device 111 and a secondary light-emitting device 112. Correspondingly, the pixel circuit 11 includes a main driving transistor T01, a secondary driving transistor T02, a main light-emitting control transistor T31, and a secondary light-emitting control transistor T32. The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected, and the first pole of the main driving transistor T01 is electrically connected to the first pole of the main light-emitting control transistor T31, and the first pole of the secondary driving transistor T02 is electrically connected to the first pole of the secondary light-emitting control transistor T32. The second pole of the main light-emitting control transistor T31 is electrically connected to the anode terminal of the main light-emitting device 111, and the second pole of the secondary light-emitting control transistor T32 is electrically connected to the anode terminal of the secondary light-emitting device 112. In addition, the pixel circuit 11 further includes a data writing transistor T2 and a threshold grabbing transistor T5. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the first pole of the main driving transistor T01. The first pole of the threshold grabbing transistor T5 is electrically connected to the second pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. The pixel circuit 11 further includes a main power supply voltage writing transistor T61, a secondary power supply voltage writing transistor T62, a main reset transistor T41, and a secondary reset transistor T41. The first poles of the main power supply voltage writing transistor T61 and the secondary power supply voltage writing transistor T62 are both electrically connected to the first power supply voltage line VDD, and the second pole of the main power supply voltage writing transistor T61 is electrically connected to the second pole of the main driving transistor T01, and the second pole of the secondary power supply voltage writing transistor T62 is electrically connected to the second pole of the secondary driving transistor T02. The first poles of the main reset transistor T41 and the secondary reset transistor T41 are both electrically connected to the first reset signal line RL1. The second pole of the main reset transistor T41 is electrically connected to the anode terminal of the main light-emitting device 111, and the second pole of the secondary reset transistor T42 is electrically connected to the anode terminal of the secondary light-emitting device 112. The pixel circuit 11 may further include a capacitor Cst. One plate of the capacitor Cst is electrically connected to the second pole of the main reset transistor T41, and the other plate is electrically connected to the gate of the main driving transistor T01. In addition, the cathode terminals of the main light-emitting device 111 and the secondary light-emitting device 112 may be electrically connected to the second power supply voltage line VEE.

[0178] In one implementation of this embodiment, as Figure 23As shown, the gate of data writing transistor T2 is electrically connected to scan line S2, the gate of threshold grabbing transistor T5 is electrically connected to scan line S5, the gates of main reset transistor T41 and sub-reset transistor T41 are electrically connected to scan line S4, the gates of main power voltage writing transistor T61 and sub-power voltage writing transistor T62 are electrically connected to scan line S6, the gate of main light emitting control transistor T31 is electrically connected to scan line S31, and the gate of sub-light emitting control transistor T32 is electrically connected to scan line S32. It should be noted that the scan line electrically connected to the gate of the transistor can be a control line electrically connected to the corresponding module.

[0179] Figure 29 is Figure 28 a corresponding timing diagram.

[0180] As Figure 29 shown, a working cycle R0 of the pixel circuit includes a reset stage R1, a data writing stage R2, a threshold grabbing stage R20, and a light emitting stage R3. The working modes of display panel 01 include a sharing mode and an anti-peeping mode.

[0181] Combined with Figure 28 and Figure 29 , in the reset stage R1, scan lines S4, S5, and S6 can transmit an enable signal to control the main reset transistor T41 and the sub-reset transistor T42 to turn on and respectively reset the anodic terminals of the main light emitting device 111 and the sub-light emitting device 111; the main power voltage writing transistor T61 and the threshold grabbing transistor T5 turn on to reset the gate of the main driving transistor T01. Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, the gate of the sub-driving transistor T02 is also reset.

[0182] Combined with Figure 28 and Figure 29 , in the data writing stage R2, scan line S2 transmits an enable signal, data writing transistor T2 turns on, and the data voltage on data line DL is written into the first pole of main driving transistor T01 through the turned-on data writing transistor T2 and main driving transistor T01.

[0183] Combined with Figure 28 and Figure 29, during the threshold grabbing stage R20, the scan lines S4 and S5 transmit the enable signal, the threshold grabbing transistor T5 is turned on, and the data voltage on the first pole of the main driving transistor T01 starts to be written into the gate of the main driving transistor T01. When the main driving transistor T01 is turned off, the gate potential of the main driving transistor T01 is related to the data voltage and its threshold voltage. Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, the data voltage and the threshold voltage are thus written into the gate of the sub-driving transistor T02.

[0184] Combined with Figure 28 and Figure 29 , during the light-emitting stage R3 in the anti-peeping mode, the scan lines S6 and S31 transmit the enable signal to turn on the main power voltage writing transistor T61 and the main light-emitting control transistor T31, so that the main driving transistor T01 generates a driving current and controls the main light-emitting device 111 to emit light; the scan line S32 transmits a non-enable signal to turn off the sub-light-emitting control transistor T32, so that the sub-light-emitting device 112 does not emit light. During the light-emitting stage R3 in the shared mode, the scan lines S6, S31 and S32 transmit the enable signal to turn on the main power voltage writing transistor T61, the sub-power voltage writing transistor T62, the main light-emitting control transistor T31 and the sub-light-emitting control transistor T32, so that the main driving transistor T01 generates a driving current and supplies it to the main light-emitting device 111 and the sub-driving transistor T02 generates a driving current and supplies it to the sub-light-emitting device 112.

[0185] Among them, the scan lines S4 and S5 are multiplexed.

[0186] It should be noted that the gates of the main light-emitting control transistor T31 and the sub-light-emitting control transistor T32 are electrically connected to different scan lines; however, according to the specific forms of the anti-peeping mode and the shared mode of the display panel 01, the gates of multiple sub-light-emitting control transistors T32 in the pixel circuit 11 can be electrically connected to the same scan line so that all the sub-light-emitting devices 112 in the sub-pixel 11 do not emit light at the same time; or, the gates of some sub-light-emitting control transistors T32 in the pixel circuit 11 and the gates of another part of the sub-light-emitting control transistors T32 can be electrically connected to different scan lines, so that some of the sub-light-emitting devices 112 in the sub-pixel 11 emit light and some of the sub-light-emitting devices 112 can not emit light.

[0187] In addition, the gates of the main power supply voltage writing transistor T61 and the sub-power supply voltage writing transistor T62 in the pixel circuit 12 may also be electrically connected to different scan lines. Further, the gates of some of the sub-power supply voltage writing transistors T62 and the gates of another part of the sub-power supply voltage writing transistors T62 in the pixel circuit 12 may also be electrically connected to different scan lines. In addition, the gates of the main reset transistor T41 and the sub-reset transistor T42 in the pixel circuit 12 may also be electrically connected to different scan lines. Further, the gates of some of the sub-reset transistors T42 and the gates of another part of the sub-reset transistors T42 in the pixel circuit 12 may also be electrically connected to different scan lines. This has been described in the previous technical solution and will not be elaborated here.

[0188] Figure 30 Schematic diagram of the connection between a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0189] In an embodiment of the present application, the data writing module 122 includes a data writing transistor T2 and a first capacitor C1; a first pole of the data writing transistor T2 is electrically connected to the data line DL and a second pole of the data writing transistor T2 is electrically connected to a first electrode plate of the first capacitor C1, and a second electrode plate of the first capacitor C1 is electrically connected to the gate of the main driving transistor T01. Among them, the first pole of the data writing transistor T2 may be the input terminal IN2 of the data writing module 122 and the second pole of the data writing transistor T2 may be the output terminal OUT2 of the data writing module 122.

[0190] In this technical solution, after the data writing transistor T2 is turned on, the data voltage on the data line DL is written into the first electrode plate of the first capacitor C1, and then the gate potential of the main driving transistor T01 is coupled by using the first capacitor C1, so that the gate potential of the main driving transistor T01 is related to the data voltage, which is equivalent to writing the data voltage into the gate of the main driving transistor T01.

[0191] Figure 31 For Figure 30 Corresponding equivalent circuit diagram.

[0192] In an embodiment of the present application, as Figure 31As shown, the sub-pixel 11 includes a main light-emitting device 111 and a secondary light-emitting device 112. Correspondingly, the pixel circuit 11 includes a main driving transistor T01, a secondary driving transistor T02, a main light-emitting control transistor T31, and a secondary light-emitting control transistor T32. The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected, and the first pole of the main driving transistor T01 is electrically connected to the first pole of the main light-emitting control transistor T31, and the first pole of the secondary driving transistor T02 is electrically connected to the first pole of the secondary light-emitting control transistor T32. The second pole of the main light-emitting control transistor T31 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary light-emitting control transistor T32 is electrically connected to the anodic terminal of the secondary light-emitting device 112. In addition, the pixel circuit 11 further includes a data writing transistor T2, a threshold grabbing transistor T5, and a first capacitor C1. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the first electrode plate of the first capacitor C1. The second electrode plate of the first capacitor C1 is electrically connected to the gate of the main driving transistor T01. The first pole of the threshold grabbing transistor T5 is electrically connected to the first pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. The pixel circuit 11 further includes a main reset transistor T41 and a secondary reset transistor T41. The first poles of the main reset transistor T41 and the secondary reset transistor T41 are both electrically connected to the first reset signal line RL1. The second pole of the main reset transistor T41 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary reset transistor T42 is electrically connected to the anodic terminal of the secondary light-emitting device 112. The pixel circuit 11 may further include a reset transistor T7. The first pole of the reset transistor T7 is electrically connected to the first reset signal line RL1, and the second pole of the reset transistor T7 is electrically connected to the first electrode plate of the first capacitor C1. In addition, the cathodic terminals of the main light-emitting device 111 and the secondary light-emitting device 112 may be electrically connected to the second power supply voltage line VEE.

[0193] In one implementation of this embodiment, as Figure 23 shown, the gate of the data writing transistor T2 is electrically connected to the scan line S2, the gate of the threshold grabbing transistor T5 is electrically connected to the scan line S5, the gates of the main reset transistor T41 and the secondary reset transistor T41 are electrically connected to the scan line S4, the gate of the reset transistor T7 is electrically connected to the scan line S7, the gate of the main light-emitting control transistor T31 is electrically connected to the scan line S31, and the gate of the secondary light-emitting control transistor T32 is electrically connected to the scan line S32.

[0194] Figure 32 is Figure 31 a corresponding timing diagram.

[0195] As Figure 32As shown, one working cycle R0 of the pixel circuit includes a reset stage R1, a data writing stage R2, and a light emitting stage R3. The working modes of the display panel include a shared mode and a privacy mode.

[0196] Combined with Figure 31 and Figure 32 , in the reset stage R1, the scan lines S31, S4, S5, and S7 can transmit an enable signal. The main light emitting control transistor T01, the main reset transistor T41, and the threshold grabbing transistor T5 are turned on and the anodic end of the main light emitting device 111, the gate of the main driving transistor T01, and the first pole are reset. Since the gate of the sub-driving transistor T02 is electrically connected to the gate of the main driving transistor T01, therefore, the gate of the sub-driving transistor T02 is also reset. The sub-reset transistor T42 is turned on and the anodic end of the sub-light emitting device 112 is reset. The reset transistor T7 is turned on to reset the first plate of the first capacitor C1. It should be noted that the reset transistor T7 may not be connected to the same scan line as the main reset transistor T41 and the sub-reset transistor T42 and they may not be turned on simultaneously.

[0197] Combined with Figure 31 and Figure 32 , in the data writing stage R2, the scan lines S2, S31, S4, and S5 transmit an enable signal. The data writing transistor T2 is turned on, and the data voltage on the data line DL is written into the first plate of the first capacitor C1 through the turned-on data writing transistor T2; the main light emitting control transistor T01, the main reset transistor T41, and the threshold grabbing transistor T5 are turned on so that the power supply voltage on the power supply voltage line VDD starts to be written into the gate of the main driving transistor T01 and the final potential of the main driving transistor T01 in this stage is related to its threshold voltage.

[0198] Combined with Figure 31 and Figure 32, in the emission stage R3, the scan line S31 and the scan line S7 are turned on, the main emission control transistor T31 and the data writing transistor T2 are turned on, the potential of the first electrode plate of the first capacitor C1 drops and pulls down the gate potential of the main driving transistor T01 through coupling, and makes the gate potential of the main driving transistor T01 related to the data voltage. Among them, in the emission stage R3 in the anti-peeping mode, the scan line S31 and the scan line S7 transmit the enable signal and the scan line S32 does not transmit the enable signal. At this time, the main driving transistor T01 generates an emission driving current and controls the main light-emitting device 111 to emit light, and the secondary emission control transistor T32 is turned off so that the secondary light-emitting device 112 does not emit light. In the emission stage R3 in the sharing mode, the scan line S31, the scan line S32 and the scan line S7 transmit the enable signal. At this time, the main driving transistor T01 generates an emission driving current and controls the main light-emitting device 111 to emit light, and the secondary driving transistor T02 generates an emission driving current and controls the secondary light-emitting device 112 to emit light.

[0199] Among them, the scan line S4 and the scan line S5 can be multiplexed.

[0200] It should be noted that the gate electrodes of the main emission control transistor T31 and the secondary emission control transistor T32 are electrically connected to different scan lines; however, according to the specific forms of the anti-peeping mode and the sharing mode of the display panel 01, the gate electrodes of multiple secondary emission control transistors T32 in the pixel circuit 11 can be electrically connected to the same scan line so that all the secondary light-emitting devices 112 in the sub-pixel 11 do not emit light at the same time; or, the gate electrodes of some of the secondary emission control transistors T32 in the pixel circuit 11 and the gate electrodes of another part of the secondary emission control transistors T32 can be electrically connected to different scan lines, so that some of the secondary light-emitting devices 111 in the sub-pixel 11 can emit light and some of the secondary light-emitting devices 111 can not emit light at the same time.

[0201] In addition, the gate electrodes of the main reset transistor T41 and the secondary reset transistor T42 in the pixel circuit 12 can also be electrically connected to different scan lines. Further, the gate electrodes of some of the secondary reset transistors T42 in the pixel circuit 12 and the gate electrodes of another part of the secondary reset transistors T42 can also be electrically connected to different scan lines. This point has been described in the above solution and will not be elaborated here.

[0202] Figure 33 For Figure 30 a corresponding equivalent circuit diagram.

[0203] Relative to Figure 31 , Figure 33The pixel circuit 11 shown may further include a voltage stabilizing capacitor C0 and a reset transistor T8. One plate of the voltage stabilizing capacitor C0 is electrically connected to the power supply voltage line VDD, and the other plate is electrically connected to the first plate of the first capacitor C1. The first pole of the reset transistor T8 is electrically connected to the second power supply voltage line RL2, and the second pole of the reset transistor T8 is electrically connected to the second plate of the first capacitor C1.

[0204] Figure 34 It is a schematic diagram of a sub-pixel and a pixel circuit in a display panel provided by an embodiment of the present application.

[0205] In an embodiment of the present application, as Figure 34 shown, the data writing module 122 includes a data writing transistor T2 and a first capacitor C1. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1 is electrically connected to the second pole of the main driving transistor T01. Among them, the first pole of the data writing transistor T2 can be the input end IN2 of the data writing module 122, and the second pole of the data writing transistor T2 can be the output end OUT2 of the data writing module 122.

[0206] In this technical solution, after the data writing transistor T2 is turned on, the data voltage on the data line DL is written into the first plate of the first capacitor C1. Subsequently, the first capacitor C1 is used to couple the gate potential of the main driving transistor T01, so that the gate potential of the main driving transistor T01 is related to the data voltage, which is equivalent to writing the data voltage into the gate of the main driving transistor T01.

[0207] In a technical solution corresponding to this embodiment, as Figure 34 shown, the threshold grabbing module 125 includes a threshold grabbing transistor T5. The first pole of the threshold grabbing transistor T5 is electrically connected to the second pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. Among them, the first pole of the threshold grabbing transistor T5 can be the input end IN5 of the threshold grabbing module 125, and the second pole of the threshold grabbing transistor T5 can be the output end OUT5 of the threshold grabbing module 125.

[0208] In this technical solution, after the threshold grabbing transistor T5 is turned on, the relevant signal is written from the first pole of the main driving transistor T01 through the turned-on main driving transistor T01 and the threshold grabbing transistor T5 into the gate of the main driving transistor T01, so that the potential of the threshold grabbing transistor T5 is related to the threshold voltage of the main driving transistor T01.

[0209] Figure 35 For Figure 34 a corresponding equivalent circuit diagram.

[0210] In one embodiment of the present application, as Figure 35 shown, the sub-pixel 11 includes a main light-emitting device 111 and a secondary light-emitting device 112. Correspondingly, the pixel circuit 11 includes a main driving transistor T01, a secondary driving transistor T02, a main light-emitting control transistor T31, and a secondary light-emitting control transistor T32. The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected, and the first pole of the main driving transistor T01 is electrically connected to the first pole of the main light-emitting control transistor T31, and the first pole of the secondary driving transistor T02 is electrically connected to the first pole of the secondary light-emitting control transistor T32. The second pole of the main light-emitting control transistor T31 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary light-emitting control transistor T32 is electrically connected to the anodic terminal of the secondary light-emitting device 112. In addition, the pixel circuit 11 further includes a data writing transistor T2, a threshold grabbing transistor T5, and a first capacitor C1. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the first electrode plate of the first capacitor C1. The second electrode plate of the first capacitor C1 is electrically connected to the second pole of the main driving transistor T01. The first pole of the threshold grabbing transistor T5 is electrically connected to the second pole of the main driving transistor T01, and the second pole of the threshold grabbing transistor T5 is electrically connected to the gate of the main driving transistor T01. The pixel circuit 11 further includes a main reset transistor T41 and a secondary reset transistor T41. The first poles of the main reset transistor T41 and the secondary reset transistor T41 are both electrically connected to the first reset signal line RL1. The second pole of the main reset transistor T41 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary reset transistor T42 is electrically connected to the anodic terminal of the secondary light-emitting device 112. The pixel circuit 11 may further include a reset transistor T7 and a second capacitor C2. The first pole of the reset transistor T7 is electrically connected to the second reset signal line RL2, the second pole of the reset transistor T7 is electrically connected to the first electrode plate of the first capacitor C1, the first electrode plate of the second capacitor C2 is electrically connected to the gate of the main driving transistor T01, and the first electrode plate of the second capacitor C2 is electrically connected to the second pole of the main light-emitting control transistor T31. The pixel circuit 11 further includes a main power supply voltage writing transistor T6. The first extreme of the main power supply voltage writing transistor T6 is electrically connected to the power supply voltage line VDD, and the second pole is electrically connected to the second pole of the main driving transistor T01. In addition, the cathodic terminals of the main light-emitting device 111 and the secondary light-emitting device 112 may be electrically connected to the second power supply voltage line VEE.

[0211] Among them, the first poles of the main reset transistor T41, the secondary reset transistor T41, and the main reset transistor T41 may also be electrically connected and are all electrically connected to the first reset signal line RL1.

[0212] In one implementation manner of this embodiment, as Figure 23As shown, the gate of the data writing transistor T2 is electrically connected to the scan line S2, the gate of the threshold grabbing transistor T5 is electrically connected to the scan line S5, the gates of the main reset transistor T41 and the secondary reset transistor T41 are electrically connected to the scan line S4, the gate of the reset transistor T7 is electrically connected to the scan line S7, the gate of the main light-emitting control transistor T31 is electrically connected to the scan line S31, and the gate of the secondary light-emitting control transistor T32 is electrically connected to the scan line S32.

[0213] Figure 36 is Figure 35 a corresponding timing diagram.

[0214] As Figure 36 shown, a working cycle R0 of the pixel circuit includes a reset stage R1, a threshold grabbing stage T20, a data writing stage R2, and a light-emitting stage R3. The working modes of the display panel include a shared mode and an anti-peeping mode.

[0215] Combined with Figure 35 and Figure 36 , in the reset stage R1, the scan lines S31, S4, S5, S6, and S7 can transmit an enable signal. The main power supply voltage writes the transistor T6 and the main driving transistor T01 so that the power supply voltage is written to the gate of the main driving transistor T01. The main reset transistor T41 and the main light-emitting control transistor T31 are turned on, and the first reset signal on the first reset signal line RL1 is written to the first pole of the main light-emitting control transistor T31. The reset transistor T7 is turned on and the first plate of the first capacitor C1 is reset.

[0216] Combined with Figure 35 and Figure 36 , in the threshold grabbing stage R20, the scan lines S31, S4, S5, and S7 can transmit an enable signal. The threshold grabbing transistor T5, the main driving transistor T01, the main light-emitting control transistor T31, and the main reset transistor T41 are turned on. The main driving transistor T01 discharges the charge to the first reset signal line RL1, and when the main driving transistor T01 is turned off, the gate voltage of the main driving transistor T01 is related to its threshold voltage.

[0217] Combined with Figure 35 and Figure 36 , in the data writing stage R2, the scan lines S2, S4, and S5 transmit an enable signal. The data writing transistor T2 is turned on, and the data voltage on the data line DL is written to the first plate of the first capacitor C1 through the turned-on data writing transistor T2, and the potential of the second plate of the first capacitor C1 is coupled and written to the gate of the main driving transistor T01 through the turned-on threshold grabbing transistor T5.

[0218] Combined with Figure 35 andFigure 36 During the light-emitting stage R3, the scan lines S31 and S6 transmit an enable signal, turning on the main light-emitting control transistor T31 and the power supply voltage writing transistor T6. The main driving transistor T01 generates a driving current and controls the main light-emitting device 111 to emit light. Among them, during the light-emitting stage R3 in the anti-peeping mode, the scan lines S31 and S6 transmit an enable signal and the scan line S32 does not transmit an enable signal. At this time, the main driving transistor T01 generates a light-emitting driving current and controls the main light-emitting device 111 to emit light, and the secondary light-emitting control transistor T32 is turned off so that the secondary light-emitting device 112 does not emit light. During the light-emitting stage R3 in the sharing mode, the scan lines S31, S32, and S6 transmit an enable signal. At this time, the main driving transistor T01 generates a light-emitting driving current and controls the main light-emitting device 111 to emit light, and the secondary driving transistor T02 generates a light-emitting driving current and controls the secondary light-emitting device 112 to emit light.

[0219] Among them, the scan lines S4 and S5 can be multiplexed.

[0220] It should be noted that the gates of the main light-emitting control transistor T31 and the secondary light-emitting control transistor T32 are electrically connected to different scan lines; however, according to the specific forms of the anti-peeping mode and the sharing mode of the display panel 01, the gates of multiple secondary light-emitting control transistors T32 in the pixel circuit 11 can be electrically connected to the same scan line so that all the secondary light-emitting devices 112 in the sub-pixel 11 do not emit light simultaneously; or, the gates of some of the secondary light-emitting control transistors T32 in the pixel circuit 11 and the gates of another part of the secondary light-emitting control transistors T32 can be electrically connected to different scan lines, so that some of the secondary light-emitting devices 111 in the sub-pixel 11 can emit light and some of the secondary light-emitting devices 111 can not emit light simultaneously.

[0221] In addition, the gates of the main reset transistor T41 and the secondary reset transistor T42 in the pixel circuit 12 can also be electrically connected to different scan lines. Further, the gates of some of the secondary reset transistors T42 in the pixel circuit 12 and the gates of another part of the secondary reset transistors T42 can also be electrically connected to different scan lines. This point has been described in the above solution and will not be elaborated here.

[0222] Figure 37 It is a schematic diagram of the connection between sub-pixels and pixel circuits in a display panel provided by an embodiment of the present application.

[0223] In an embodiment of the present application, as Figure 37As shown, the pixel circuit 11 further includes a threshold grabbing transistor T5 and a second capacitor C2. A first pole of the threshold grabbing transistor T5 is electrically connected to a power supply voltage line VDD, and a first plate of the second capacitor C2 is electrically connected to a gate of the main driving transistor T01. Among a second pole of the threshold grabbing transistor T5 and a second plate of the second capacitor C2, one is electrically connected to a first pole of the main driving transistor T01 and the other is electrically connected to a second pole of the main driving transistor T02.

[0224] In a technical solution corresponding to this embodiment, as Figure 36 shown, the data writing module 122 includes a data writing transistor T2. A first pole of the data writing transistor T2 is electrically connected to a data line, and a second pole of the data writing transistor T2 is electrically connected to a gate of the main driving transistor T01.

[0225] Figure 38 is Figure 37 a corresponding equivalent circuit diagram.

[0226] In an embodiment of the present application, as Figure 38As shown, the sub-pixel 11 includes a main light-emitting device 111 and a secondary light-emitting device 112. Correspondingly, the pixel circuit 11 includes a main driving transistor T01, a secondary driving transistor T02, a main light-emitting control transistor T31, and a secondary light-emitting control transistor T32. The gates of the main driving transistor T01 and the secondary driving transistor T02 are electrically connected, and the first pole of the main driving transistor T01 is electrically connected to the first pole of the main light-emitting control transistor T31, and the first pole of the secondary driving transistor T02 is electrically connected to the first pole of the secondary light-emitting control transistor T32. The second pole of the main light-emitting control transistor T31 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary light-emitting control transistor T32 is electrically connected to the anodic terminal of the secondary light-emitting device 112. In addition, the pixel circuit 11 further includes a data writing transistor T2, a threshold grabbing transistor T5, and a second capacitor C2. The first pole of the data writing transistor T2 is electrically connected to the data line DL, and the second pole of the data writing transistor T2 is electrically connected to the gate of the main driving transistor T01. The first pole of the threshold grabbing transistor T5 is electrically connected to the power supply voltage line VDD, and the second pole of the threshold grabbing transistor T5 is electrically connected to the second pole of the main driving transistor T01. The first plate of the second capacitor C2 is electrically connected to the gate of the main driving transistor T01, and the second plate of the second capacitor C2 is electrically connected to the first pole of the main driving transistor T01. The pixel circuit 11 further includes a main reset transistor T41 and a secondary reset transistor T41. The first poles of the main reset transistor T41 and the secondary reset transistor T41 are both electrically connected to the first reset signal line RL1. The second pole of the main reset transistor T41 is electrically connected to the anodic terminal of the main light-emitting device 111, and the second pole of the secondary reset transistor T42 is electrically connected to the anodic terminal of the secondary light-emitting device 112. The pixel circuit 11 may further include a reset transistor T7 and a third capacitor C3. The first pole of the reset transistor T7 is electrically connected to the second reset signal line RL2, and the second pole of the reset transistor T7 is electrically connected to the gate of the main driving transistor T01. One plate of the third capacitor C3 is electrically connected to the first pole of the main driving transistor T01, and the other plate is electrically connected to the second pole of the main light-emitting control transistor T31. In addition, the cathodic terminals of the main light-emitting device 111 and the secondary light-emitting device 112 may be electrically connected to the second power supply voltage line VEE.

[0227] In one implementation of this embodiment, as Figure 38 shown, the gate of the data writing transistor T2 is electrically connected to the scan line S2, the gate of the threshold grabbing transistor T5 is electrically connected to the scan line S5, the gates of the main reset transistor T41 and the secondary reset transistor T41 are electrically connected to the scan line S4, the gate of the reset transistor T7 is electrically connected to the scan line S7, the gate of the main light-emitting control transistor T31 is electrically connected to the scan line S31, and the gate of the secondary light-emitting control transistor T32 is electrically connected to the scan line S32.

[0228] Figure 39 For Figure 38 a corresponding timing diagram.

[0229] As Figure 39 shown, a working cycle R0 of the pixel circuit includes a reset stage R1, a threshold grabbing stage T20, a data writing stage R2, and a light emitting stage R3. The working modes of the display panel include a sharing mode and an anti-peeping mode.

[0230] Combined with Figure 38 and Figure 39 , in the reset stage R1, the scan line S31, the scan line S4, and the scan line S7 can transmit an enable signal. The turned-on main reset transistor T41 and the main light emission control transistor T31 reset the first and second poles of the main light emission control transistor T31. The turned-on secondary reset transistor T41 resets the anodic end of the secondary light emitting device 112. The turned-on reset transistor T7 resets the gate of the main driving transistor T01. Among them, the potential of the first pole of the reset main driving transistor T01 is less than the potential of the gate of the main driving transistor T01, and the main driving transistor T01 is turned on.

[0231] Combined with Figure 38 and Figure 39 , in the threshold grabbing stage R20, the scan line S4, the scan line S5, and the scan line S7 can transmit an enable signal. The threshold grabbing transistor T5 is turned on and writes the power supply voltage on the power supply voltage line VDD into the second plate of the second capacitor C2 through the turned-on main driving transistor T01. The voltage when the main driving transistor T01 is turned off is related to its threshold voltage.

[0232] Combined with Figure 38 and Figure 39 , in the data writing stage R2, the scan line S2, the scan line S4, and the scan line S31 transmit an enable signal. The data writing transistor T2 is turned on, and the data voltage on the data line DL is written into the first plate of the second capacitor C2 through the turned-on data writing transistor T2, and the potential after coupling of the second plate of the second capacitor C2 is related to the data voltage.

[0233] Combined with Figure 38 and Figure 39, during the light-emitting stage R3, the scan lines S31 and S5 transmit the enable signal, the main light-emitting control transistor T31 and the threshold-grabbing transistor T5 are turned on, and the main driving transistor T01 generates a driving current and controls the main light-emitting device 111 to emit light. Among them, during the light-emitting stage R3 in the anti-peeking mode, the scan lines S31 and S5 transmit the enable signal and the scan line S32 does not transmit the enable signal. At this time, the main driving transistor T01 generates a light-emitting driving current and controls the main light-emitting device 111 to emit light, and the secondary light-emitting control transistor T32 is turned off so that the secondary light-emitting device 112 does not emit light. During the light-emitting stage R3 in the sharing mode, the scan lines S31, S32, and S5 transmit the enable signal. At this time, the main driving transistor T01 generates a light-emitting driving current and controls the main light-emitting device 111 to emit light, and the secondary driving transistor T02 generates a light-emitting driving current and controls the secondary light-emitting device 112 to emit light.

[0234] Among them, the scan line S4 and the scan line S5 can be multiplexed.

[0235] It should be noted that the gates of the main light-emitting control transistor T31 and the secondary light-emitting control transistor T32 are electrically connected to different scan lines; however, according to the specific forms of the anti-peeking mode and the sharing mode of the display panel 01, the gates of multiple secondary light-emitting control transistors T32 in the pixel circuit 11 can be electrically connected to the same scan line so that all the secondary light-emitting devices 112 in the sub-pixel 11 do not emit light simultaneously; or, the gates of some of the secondary light-emitting control transistors T32 in the pixel circuit 11 and the gates of another part of the secondary light-emitting control transistors T32 can be electrically connected to different scan lines, so that some of the secondary light-emitting devices 111 in the sub-pixel 11 can emit light and some of the secondary light-emitting devices 111 can not emit light simultaneously.

[0236] In addition, the gates of the main reset transistor T41 and the secondary reset transistor T42 in the pixel circuit 12 can also be electrically connected to different scan lines. Further, the gates of some of the secondary reset transistors T42 in the pixel circuit 12 and the gates of another part of the secondary reset transistors T42 can also be electrically connected to different scan lines. This point has been described in the above solution and will not be elaborated here.

[0237] Figure 40 It is a schematic diagram of a display device provided by an embodiment of the present application.

[0238] Based on the same inventive concept, an embodiment of the present invention also provides a display device, as Figure 39 shown, the display device includes the above-mentioned display panel 01. Of course, Figure 40 the display device shown is only for schematic illustration, and the display device can be any electronic device with a display function such as a mobile phone, a tablet computer, a notebook computer, an e-book, or a television.

[0239] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: a sub-pixel, the sub-pixel comprising a main light emitting device and at least one sub-light emitting device; A pixel circuit, the pixel circuit comprising a main driving module, a sub-driving module and a data writing module; the first ends of the main driving module and the sub-driving module are electrically connected to the output end of the data writing module, and the input end of the data writing module is electrically connected to the data line; Wherein, the pixel circuit also includes a main light-emitting control module and a secondary light-emitting control module; the main light-emitting control module is electrically connected between the main driving module and the main light-emitting device, and the secondary light-emitting control module is electrically connected between the secondary driving module and the secondary light-emitting device.

2. The display panel according to claim 1, characterized in that: The sub-pixel includes at least two sub-light emitting devices, and the at least two sub-light emitting devices are electrically connected to the same sub-driving module through different sub-light emitting control modules.

3. The display panel according to claim 1, characterized in that: The sub-pixel includes at least two sub-light emitting devices, and the at least two sub-light emitting devices are electrically connected to different sub-driving modules through different sub-light emitting control modules.

4. The display panel according to claim 1, characterized in that: The pixel circuit also includes a main reset module and a secondary reset module; The output end of the master reset module is electrically connected to the master light emitting device and the input end of the master reset module is electrically connected to the reset signal line; the output end of the secondary reset module is electrically connected to the secondary light emitting device and the input end of the secondary reset module is electrically connected to the reset signal line.

5. The display panel according to claim 4, characterized in that: The sub-pixel includes at least two sub-light emitting devices, and the pixel circuit includes at least two sub-reset modules; The at least two secondary light emitting devices are electrically connected to output terminals of different secondary reset modules respectively, and control terminals of the at least two secondary reset modules are electrically connected to the same control line.

6. The display panel according to claim 4, characterized in that: The control end of the main reset module and the control end of the secondary reset module are electrically connected to the same control line.

7. The display panel according to claim 4, characterized in that: The main reset module includes a main reset transistor, and the secondary reset module includes a secondary reset transistor; The first electrodes of the main reset transistor and the secondary reset transistor are both electrically connected to the first reset signal line, the second electrode of the main reset transistor is electrically connected to the main light emitting device, and the second electrode of the secondary reset transistor is electrically connected to the secondary light emitting device.

8. The display panel according to claim 1, characterized in that: The main driving module includes a main driving transistor, and the secondary driving module includes a secondary driving transistor; the first electrode of the main driving transistor is electrically connected to the input end of the main light-emitting control module, and the output end of the main light-emitting control module is electrically connected to the main light-emitting device; the first electrode of the secondary driving transistor is electrically connected to the input end of the secondary light-emitting control module, and the output end of the secondary light-emitting control module is electrically connected to the secondary light-emitting device The gate of the main driving transistor and the gate of the sub-driving transistor are electrically connected and are both electrically connected to the output end of the data writing module.

9. The display panel according to claim 8, characterized in that: The pixel circuit further comprises a threshold capture module, an input end of the threshold capture module is electrically connected to the first electrode or the second electrode of the driving transistor, and an output end of the threshold capture module is electrically connected to the gate of the driving transistor.

10. The display panel according to claim 9, characterized in that: The data writing module comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected to the data line and a second electrode of the data writing transistor is electrically connected to the second electrode of the main driving transistor; The threshold capture module includes a threshold capture transistor, a first electrode of the threshold capture transistor is electrically connected to a first electrode of the main driving transistor, and a second electrode of the threshold capture transistor is electrically connected to a gate of the main driving transistor.

11. The display panel according to claim 9, characterized in that: The data writing module comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected to the data line and a second electrode of the data writing transistor is electrically connected to the first electrode of the main driving transistor; The threshold capture module includes a threshold capture transistor, a first electrode of the threshold capture transistor is electrically connected to a second electrode of the main driving transistor, and a second electrode of the threshold capture transistor is electrically connected to a gate of the main driving transistor.

12. The display panel according to claim 9, characterized in that: The pixel circuit further includes a main power supply voltage writing module and a secondary power supply voltage writing module; The input end of the main power supply voltage writing module is electrically connected to the first power supply voltage line and the output end of the main power supply voltage writing module is electrically connected to the second pole of the main driving transistor, and the input end of the secondary power supply voltage writing module is electrically connected to the first power supply voltage line and the output end of the secondary power supply voltage writing module is electrically connected to the second pole of the secondary driving transistor.

13. The display panel according to claim 12, characterized in that: The pixel circuit includes a plurality of sub-driving modules; The same sub-power voltage writing module is electrically connected between at least two of the sub-driving modules and the first power voltage line.

14. The display panel according to claim 12, characterized in that: The secondary power supply voltage writing module is electrically connected to the secondary driving module in a one-to-one correspondence.

15. The display panel according to claim 12, characterized in that: The main power supply voltage writing module includes a main power supply voltage writing transistor, a first pole of the main power supply voltage writing transistor is electrically connected to the first power supply voltage line and a second pole of the main power supply voltage writing transistor is electrically connected to the second pole of the main driving transistor, a first pole of the secondary power supply voltage writing transistor is electrically connected to the first power supply voltage line and a second pole of the secondary power supply voltage writing transistor is electrically connected to the second pole of the secondary driving transistor.

16. The display panel according to claim 9, characterized in that: The pixel circuit also includes a power supply voltage writing module; The power voltage writing module is electrically connected between the first power voltage line and the main driving module and the sub-driving module.

17. The display panel according to claim 16, characterized in that: The power supply voltage writing module includes a power supply voltage writing transistor; A first electrode of the power supply voltage write transistor is electrically connected to the first power supply voltage line, and a second electrode of the power supply voltage write transistor is electrically connected to a second electrode of the main drive transistor and a second electrode of the sub drive transistor.

18. The display panel according to claim 9, characterized in that: The data writing module includes a data writing transistor and a first capacitor; the first electrode of the data writing transistor is electrically connected to the data line and the second electrode of the data writing transistor is electrically connected to the first plate of the first capacitor, and the second plate of the first capacitor is electrically connected to the gate of the main driving transistor.

19. The display panel according to claim 9, characterized in that: The data writing module includes a data writing transistor and a first capacitor; the first electrode of the data writing transistor is electrically connected to the data line and the second electrode of the data writing transistor is electrically connected to the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor is electrically connected to the second electrode of the main driving transistor.

20. The display panel according to claim 19, characterized in that: The threshold capture module includes a threshold capture transistor, a first electrode of the threshold capture transistor is electrically connected to a second electrode of the main driving transistor, and a second electrode of the threshold capture transistor is electrically connected to a gate of the main driving transistor.

21. The display panel according to claim 8, characterized in that: The pixel circuit also includes a threshold grabbing transistor and a second capacitor, the first electrode of the threshold grabbing transistor is electrically connected to the power supply voltage line, and the first plate of the second capacitor is electrically connected to the gate of the main driving transistor; the second electrode of the threshold grabbing transistor and the second plate of the second capacitor, one is electrically connected to the first electrode of the main driving transistor and the other is electrically connected to the second electrode of the main driving transistor.

22. The display panel according to claim 21, characterized in that: The data writing module includes a data writing transistor, a first electrode of the data writing transistor is electrically connected to the data line and a second electrode of the data writing transistor is electrically connected to the gate of the main driving transistor.

23. The display panel according to claim 1, characterized in that: The main light emitting device and the sub-light emitting device both include a first electrode and a second electrode, the first electrode of the main light emitting device is electrically connected to the first electrode of the sub-light emitting device, the second electrode of the main light emitting device is electrically connected to the main light emitting control module, and the second electrode of the sub-light emitting device is electrically connected to the sub-light emitting control module; The first electrode of the main light emitting device is located on the side of the second electrode facing the light emitting surface of the display panel, the first electrode of the secondary light emitting device is located on the side of the second electrode facing the light emitting surface of the display panel, and the second electrode is a reflective electrode; Among them, the secondary light-emitting device in the sub-pixel is located at the periphery of the main light-emitting device, the plane where the second electrode in the main light-emitting device is located is parallel to the plane where the display panel is located, and the angle between the plane where the second electrode in the secondary light-emitting device is located and the plane where the display panel is located is greater than 0°.

24. The display panel according to claim 23, characterized in that: The working modes of the display panel include an anti-peeping mode and a sharing mode; In the anti-peeping mode, the main light emitting device emits light and the secondary light emitting device does not emit light; In the sharing mode, the main light emitting device and at least part of the secondary light emitting devices emit light.

25. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-24.

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