Data interface device and related data transmission method

Abstract

The invention provides a data interface device and a related data transmission method.The data interface device can comprise a sending module and a receiving module, the sending module is located in a first clock domain, the first clock domain corresponds to a first clock period, the receiving module is located in a second clock domain, and the second clock domain corresponds to a second clock period. The sending module is electrically connected with the receiving module; the sending module can be used for determining N data sending moments in a first time period based on a ratio of T1 to T2 when the length T1 of the first clock period is smaller than the length T2 of the second clock period, the first time period comprises M first clock periods, N and M are positive integers, and the ratio of N and M is smaller than or equal to the ratio of T1 to T2; and sequentially sending data to the receiving module at the N data sending moments. Homologous cross-clock domain data transmission is performed based on the data interface device, the delay of data transmission can be reduced, the chip area is saved, and the hardware cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of digital integrated circuit design, and particularly relates to a data interface device and a related data transmission method. Background Art

[0002] In a digital circuit system, different modules may use different clock signals such as frequency and phase. At this time, these modules can be said to be in different clock domains, and the data transmission between these modules can be called cross-clock domain (CDC) data transmission. When these clock signals are all derived clocks from the same clock source, such data transmission is also called data transmission in the same-source cross-clock domain.

[0003] In the prior art, data transmission in the same-source cross-clock domain can be achieved between different modules through a data interface device. This data interface device usually includes components such as a first-in-first-out (FIFO) memory and a single-bit data transmission structure. Specifically, the read and write pointers of the FIFO memory can be transmitted between different modules through this single-bit transmission structure, and then the state of the FIFO memory can be judged according to the read and write pointers. When the FIFO memory is in a non-empty or non-full state, different modules can respectively read data from the FIFO memory or write data into the FIFO memory, so as to achieve data transmission. For the above data transmission process, on the one hand, when using this single-bit transmission structure to transmit the read and write pointers, since this single-bit transmission structure usually includes multiple stages of flip-flops, a large delay will be generated for the transmission of each bit of data, thus increasing the overall delay of data transmission; on the other hand, since the FIFO memory needs to be read and written multiple times, the frequent read and write processes will increase the power consumption of the digital circuit system. In addition, due to different modules using clock signals with different frequencies, the data read and write rates of the FIFO memory do not match. In order to avoid data loss, the depth of the FIFO memory needs to be adjusted according to the frequencies of these clock signals and their frequency ratios, so that the FIFO memory needs to occupy a large chip area, increasing additional costs.

[0004] Therefore, when data transmission in the same-source cross-clock domain is carried out between different modules of a digital circuit system, how to reduce the delay of data transmission, save chip area and reduce hardware costs is an urgent problem to be solved. Summary of the Invention

[0005] To solve the above technical problems, an embodiment of the present application provides a data interface device and a related data transmission method, which are used to reduce data transmission latency, save chip area, and reduce hardware costs when performing data transmission across clock domains with the same source between different modules of a digital circuit system.

[0006] In a first aspect, an embodiment of the present application provides a data interface device, which may include a sending module and a receiving module. Among them, the sending module is in a first clock domain, the first clock domain corresponds to a first clock period, the receiving module is in a second clock domain, the second clock domain corresponds to a second clock period, and the sending module is electrically connected to the receiving module;

[0007] The sending module is configured to: when the length T1 of the first clock period is less than the length T2 of the second clock period, determine N data sending times within a first time period based on the ratio of T1 to T2, where the first time period includes M first clock periods, both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2; sequentially send data to the receiving module at the N data sending times.

[0008] An embodiment of the present application provides a data interface device. In terms of the overall structure, the data interface device may include two main parts: a sending module and a receiving module, and the sending module is electrically connected to the receiving module. The data interface device can be used to support data transmission between different modules in a digital circuit system, such as a transmitting end TX and a receiving end RX. Among them, the transmitting end TX and the sending module are both driven by a clock signal tx_clk (i.e., in the first clock domain); the receiving end RX and the receiving module are both driven by a clock signal rx_clk (i.e., in the second clock domain); the length of one clock cycle of the clock signal tx_clk (i.e., the first clock cycle) is T1, and the length of one clock cycle of the clock signal rx_clk (i.e., the second clock cycle) is T2. In the embodiment of the present application, when T1 is less than T2, within a first time period with a duration of M cycles of the clock signal tx_clk (i.e., M first clock cycles), the transmitting end TX sends data N times to the receiving module through the sending module respectively in N of these cycles (i.e., N first clock cycles where the N data sending moments are located). Thus, when a preset condition is met, such as the ratio of N to M is equal to the ratio of T1 to T2, the receiving end RX can sample the N times of data through the receiving module within N cycles of the clock signal rx_clk (i.e., N second clock cycles with a duration equal to the first time period); or when a preset condition is met, such as the ratio of N to M is less than the ratio of T1 to T2, the receiving end RX can sample the N times of data through the receiving module within several cycles of the clock signal rx_clk (with a duration equal to the first time period and greater than N second clock cycles). In summary, when T1 is less than T2 and the above preset conditions are met, the transmitting end TX can send data N times to the receiving module through the sending module within the first time period, and within several second clock cycles (at least N second clock cycles) with a duration equal to the first time period, the receiving end RX can perform at least N data samplings through the receiving module (because each second clock cycle can sample once). Therefore, for the N times of data sent by the transmitting end TX through the sending module, the receiving end RX can achieve non - missing data sampling and reception through the receiving module, thereby realizing the matching of the data sampling rate and the data sending rate based on this data interface device without introducing other data storage units for buffering (for example, the first - in - first - out FIFO memory in the prior art). This can not only avoid the occurrence of data loss, achieve cross - clock - domain data transmission with low latency, but also help save the chip area occupied by the data interface device and reduce the hardware cost.

[0009] In a possible implementation manner, the sending module is specifically configured to: write data to a register at the N data sending moments in sequence, where the register is electrically connected to the receiving module; the receiving module is configured to: read the data in the register. The embodiment of the present application provides a specific solution for the sending module to send data to the receiving module. Through direct writing and reading of the register, data transmission between the sending module and the receiving module is realized. The transmission process is simple and direct, which is beneficial to saving chip area, reducing hardware cost, and reducing system power consumption.

[0010] In a possible implementation manner, the sending module is specifically configured to: write data to different registers at any two adjacent data sending moments, where the different registers are connected in parallel and are electrically connected to the receiving module. The embodiment of the present application provides a specific solution for the sending module to send data to the receiving module. The sending module can stagger the time and send data to the receiving module through different registers in a rotating manner. Thus, there is sufficient time for the receiving module to read the data written to any one register by the sending module, and it will not be overwritten because the sending module writes data again immediately, or the receiving module sampling fails because the sending module writes data again immediately, avoiding errors such as data omission during data transmission.

[0011] In a possible implementation manner, the sending module is specifically configured to: sequentially send multiple groups of first test signals to the receiving module based on the ratio of T1 to T2, where the first test signal includes a level signal whose signal flips occur at (N - L) first moments in sequence, and L is an integer greater than 0 and less than N; the receiving module is specifically configured to: sequentially receive the multiple groups of first test signals and determine whether the (N - L) first moments in the first test signal satisfy a first condition, where the first condition includes that the (N - L) first moments are sequentially before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock cycles; the sending module is specifically configured to: receive a feedback signal and determine the N data sending moments based on the feedback signal, where the feedback signal is the response of the receiving module to the multiple groups of first test signals.

[0012] The embodiment of the present application provides a specific solution for the sending module to determine N data sending moments in M first clock cycles. When the ratio of N to M is equal to the ratio of T1 to T2, since the lengths of M first clock cycles and N second clock cycles are equal, the receiving module can receive N data sent by the sending module in N consecutive second clock cycles. Thus, the sending module can send multiple groups of first test signals to the receiving module based on the ratio of T1 to T2, and each group of first test signals can simulate the sending module sending data to the receiving module at (N - L) data sending moments through a level signal that undergoes (N - L) signal flips. After that, the receiving module can simulate whether there will be an error in receiving data when the sending module sends data at (N - L) data sending moments by receiving the first test signal (i.e., determine whether the (N - L) first moments meet the first condition), and then the sending module can determine which group or groups of first test signals simulate (N - L) data sending moments that will not cause errors in receiving data through the feedback signal sent by the receiving module, and further determine the N data sending moments, ensuring the security of data transmission.

[0013] In a possible implementation manner, the receiving module is specifically configured to: sequentially send multiple groups of feedback signals to the sending module, where each group of feedback signals corresponds to a group of the first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal meet the first condition; the sending module is specifically configured to: sequentially receive the multiple groups of feedback signals and determine the N data sending moments based on the multiple groups of feedback signals. The embodiment of the present application provides a corresponding relationship between the feedback signal and the first test signal. Each group of feedback signals corresponds to a group of first test signals, and the feedback signal is used to reflect whether the corresponding first test signal meets the first condition. Thus, the sending module can determine whether the (N - L) data sending moments simulated by a corresponding group of first test signals are safe through a group of feedback signals transmitted by the receiving module.

[0014] In a possible implementation, the sending module is specifically configured to: during the first time period, write data to the register for the first time at the first L data sending times among the N data sending times. An embodiment of the present application provides a specific solution for the value of L. Since the sending module can send data to the receiving module through one or more registers, during the M first clock cycles (i.e., the first time period), when the sending module writes data to any one of the registers for the first time, there is a risk that the receiving module cannot sample the data in time. Therefore, among the N data sending times, except for the first L data sending times when the sending module writes data to the register for the first time, the first test signal is required to be simulated to confirm whether it will cause an error when receiving data.

[0015] In a possible implementation, the sending module includes: an index generator, configured to generate multiple groups of indexes based on the ratio of T1 and T2, and any one group of the indexes includes N index values, where the N index values are all integers, and each index value corresponds to one of the first clock cycles within the first time period; a test signal generator, configured to sequentially send multiple groups of first test signals to the receiving module based on the multiple groups of indexes, where each group of the first test signals corresponds to one group of the indexes. An embodiment of the present application provides a specific composition and function of the sending module. The sending module can generate several groups of indexes through the index generator. The N index values included in each group of indexes correspond to one of the first clock cycles in the first time period (for example, the index value 0 corresponds to the first clock cycle in the first time period) to correspond to the N data sending times. Then, the sending module can generate and send a corresponding group of first test signals through the test signal generator according to the N index values in each group of indexes (for example, generate a level signal with (N - L) signal flips according to (N - L) of the index values), so as to realize the simulation of the first test signal for the N data sending times when the sending module sends data.

[0016] In a possible implementation manner, the sending module is specifically configured to: determine a target test signal from the multiple groups of first test signals based on the multiple groups of feedback signals, where the (N - L) first moments in the target test signal satisfy the first condition; determine N first clock cycles within the first time period based on a group of indexes corresponding to the target test signal, where the N data sending moments are respectively located in the N first clock cycles. An embodiment of the present application provides a specific solution for the sending module to determine N data sending moments based on feedback signals. The sending module can determine which group or groups of first test signals among the multiple groups of first test signals simulate (N - L) data sending moments that will not cause errors when receiving data (i.e., the (N - L) first moments satisfy the first condition), then select a group of first test signals as the target test signal, and then determine N first clock cycles within the first time period from the N index values in a group of indexes corresponding to the target test signal, and further determine the N data sending moments respectively located in the N first clock cycles.

[0017] In a possible implementation manner, the index generator is specifically configured to: when the ratio of T1 to T2 is equal to the ratio of N to M, generate a group of indexes as the initial indexes; the index values in the initial indexes include all integers greater than (I×J - 1) and less than or equal to (I×J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N; generate the other groups of indexes in the multiple groups of indexes based on the initial indexes. An embodiment of the present application provides a specific solution for the index generator to generate multiple groups of indexes based on the ratio of T1 to T2. The index generator can first generate one group of indexes (i.e., the initial indexes) among the multiple groups of indexes, and then obtain the remaining other groups of indexes from this group of indexes. In the embodiment of the present application, when the ratio of T1 to T2 is equal to the ratio of N to M, since each index value corresponds to a first clock cycle, at this time, determining the N index values in a group of indexes is equivalent to determining N first clock cycles among consecutive M first clock cycles (i.e., the first time period). Therefore, determining the index values in the initial indexes as all integers greater than (I×J - 1) and less than or equal to (I×J) is equivalent to dividing the first time period into N parts, so that the N first clock cycles are respectively located in these N parts, thereby making the distribution of the N first clock cycles in the first time period more uniform, which is equivalent to making the distribution of the N data sending moments in the first time period more uniform, thereby increasing the minimum interval time for the sending module to write data to the same register, reducing the probability of errors in the data received by the receiving module, and further increasing the probability that the (N - L) first moments in the first test signal corresponding to the initial indexes satisfy the first condition.

[0018] In a possible implementation manner, the index generator is specifically configured to: generate one or more groups of the indexes based on the initial index as one or more groups of derivative indexes; wherein, the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index value in the derivative index is equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, and Q is an integer greater than 0 and less than M. The embodiment of the present application provides a specific solution for the index generator to generate other groups of indexes based on the initial index. Other groups of indexes can be obtained by subtracting the same integer from some or all of the index values in the initial index (that is, the index value in the derivative index is equal to (P - Q), and at this time (P - Q) is greater than or equal to 0 and less than M), or by subtracting the same integer from some or all of the index values in the initial index and then adding M (that is, the index value in the derivative index is equal to (P - Q + M), and at this time (P - Q + M) is greater than or equal to 0 and less than M). Based on the above, compared with the initial index, the relative differences between the N index values in other groups of indexes remain unchanged, so that the distribution of the N first clock cycles corresponding to the N index values is as uniform as before.

[0019] In a possible implementation manner, the N data sending moments are all at the rising edge of the first clock cycle; the test signal generator is specifically configured to: respectively send a group of corresponding first test signals to the receiving module based on each group of the indexes, the first test signal includes a start test signal, and the start test signal includes a level signal whose signal flips at the falling edge of the Xth first clock cycle in the second time period; wherein, the second time period includes M first clock cycles; X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in the index corresponding to the first test signal. The embodiment of the present application provides a specific solution for the test signal generator to generate and send the first test signal. The test signal generator generates and sends a group of corresponding first test signals based on a group of indexes each time, and each group of first test signals includes a level signal (that is, the start test signal), and this level signal flips at the falling edge of the clock cycle corresponding to the first index value, which is used to simulate the first data sending moment when the sending module first sends data to the receiving module within the first time period. And because the flip of this level signal occurs at the falling edge, compared with the first data sending moment at the rising edge, it lags behind half of the first clock cycle. Therefore, the receiving module can determine based on the flip of this level signal that the data sent by the sending module at the first data sending moment has been written into the register and remains stable, and thus starts to sample this register.

[0020] In a possible implementation, the sending module is specifically configured to: alternately write data to Y registers at the N data sending moments in sequence, where Y is an integer greater than 1 and less than N; the level signal that undergoes signal transitions at (N - L) first moments includes Y sub-test signals; where the index value in the index corresponding to the first test signal is denoted as B K , and the index value B K is the Kth index value after sorting the index values in the index from smallest to largest, K = 1, 2, 3,..., N; the Zth sub-test signal among the Y sub-test signals is denoted as A Z , Z = 1, 2, 3,..., Y; the Y sub-test signals include: A 1 , A 2 , A 3 ,... A Y ; when the value of K is equal to (R × Y + Z), the Zth sub-test signal A Z undergoes a transition at the falling edge of the Bth K first clock cycle in the second time period; R is a positive integer.

[0021] The embodiments of the present application provide a specific composition of the first test signal. When the sending module alternately writes data to Y registers at N data sending moments (for example, if Y = 2, the sending module writes data to the first register at the 1st, 3rd, 5th,... data sending moments, and writes data to the second register at the 2nd, 4th, 6th,... data sending moments), since the N index values in a group of indexes correspond to N first clock cycles (the N data sending moments are respectively at the rising edges of these N first clock cycles), and in the first test signal corresponding to this group of indexes, the level signal that undergoes (N - L) signal transitions is used to simulate the sending module alternately writing data to Y registers, so this level signal can be divided into Y sub-signals (i.e., Y sub-test signals), and each sub-signal is used to simulate the sending module writing data to one of the registers and needs to undergo a transition at the corresponding first clock cycle (for example, if Y = 2, the 1st sub-test signal undergoes a transition at the falling edge before the first clock cycle corresponding to the (2 × R + 1)th index value, that is, half a first clock cycle earlier before the 3rd, 5th, 7th,... data sending moments), so that the change in the order of the time when the receiving module samples any sub-signal and the time when this sub-signal undergoes a transition affects the sampling result of the receiving module for this sub-signal.

[0022] In a possible implementation, the receiving module is specifically configured to: within the second time period, after detecting a signal level inversion of the start test signal, alternately sample the Y sub-test signals at the (N - L) second moments in sequence to obtain test signal sampling values, and determine whether the test signal sampling values are equal to a preset reference value; when the test signal sampling values are equal to the reference value, determine that the (N - L) first moments satisfy the first condition. The embodiment of the present application provides a specific solution for determining whether the (N - L) first moments in the first test signal satisfy the first condition. By sampling the Y sub-signals in the first test signal through the receiving module, if the sampling time of the receiving module is after the signal inversion time of any one sub-signal, the sampling result of the receiving module (i.e., the test signal sampling value) will not be equal to the preset reference value, indicating that when the sending module simulated by the first test signal sends data at the N data sending moments, there is a risk of incorrect data reception by the receiving module, that is, the (N - L) first moments in the first test signal do not satisfy the first condition.

[0023] In a possible implementation, the receiving module is further configured to: when the length T1 of the first clock cycle is greater than or equal to the length T2 of the second clock cycle, receive a second test signal sent by the sending module within a third time period, the third time period including F second clock cycles, the second test signal including a level signal with signal inversions occurring at E third moments in sequence; determine E data reception moments within a fourth time period based on the second test signal, where the fourth time period includes F second clock cycles, both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2; receive the data sent by the sending module at the E data reception moments in sequence. The embodiment of the present application provides a specific solution for data transmission when T1 is greater than or equal to T2. When T1 is greater than or equal to T2, within a time period equal to several cycles of the clock signal rx_clk (such as F second clock cycles) (i.e., within the fourth time period), the receiving end RX only receives the data sent by the sending module at some of these cycles (such as E data reception moments). Thus, when the preset condition is met (i.e., the ratio of F to E is greater than or equal to the ratio of T1 to T2), the number of times the receiving end RX samples the data within this time period through this receiving module can cover the number of times the sending module sends data to this receiving module, avoiding data loss. Additionally, by using the level signal with E signal inversions sent by the sending module (i.e., the second test signal), the receiving module can determine at which moments (i.e., the E data reception moments) sampling the data can obtain new data, avoiding data duplication.

[0024] In a possible implementation, the receiving module is specifically configured to: sequentially read the data in the register at the E data receiving moments, where the register is electrically connected to the receiving module; the sending module is further configured to: write data to the register. The embodiment of the present application provides a specific solution for the receiving module to receive the data sent by the sending module. Through direct writing and reading of the register, the data transmission between the sending module and the receiving module is realized, and the transmission process is simple and direct, which is beneficial to reducing the hardware cost and system power consumption.

[0025] In a possible implementation, the receiving module is specifically configured to: read the data in different registers at any two adjacent data receiving moments, where the different registers are connected in parallel and electrically connected to the receiving module. The embodiment of the present application provides a specific solution for the receiving module to receive the data sent by the sending module. The sending module can stagger the time and send data to the receiving module through different registers in a rotation manner. Thus, the data written by the sending module to any one register has sufficient time to be read by the receiving module, and will not be overwritten because the sending module immediately writes data again, or the receiving module sampling fails because the sending module immediately writes data again, avoiding errors such as data omission in the data transmission process.

[0026] In a possible implementation, the receiving module is specifically configured to: when, at the Gth second clock cycle in the third time period, it is detected that the signal level of the second test signal flips, determine that the data receiving moment is at the Gth second clock cycle in the fourth time period, or determine that the data receiving moment is at the (G + 1)th second clock cycle in the fourth time period; G is an integer greater than or equal to 1 and less than F. The embodiment of the present application provides a specific solution for the receiving module to determine the E data receiving moments based on the second test signal. Since within the third time period, the level signals that flip E times in the second test signal (i.e., the level signals that flip at E third moments) are used to simulate the E times of data received by the receiving module from the sending module within the fourth time period, when the receiving module detects that the level signal flips at a certain second clock cycle in the third time period (i.e., the Gth second clock cycle in the third time period), it means that the receiving module can receive non-repeated data at the second clock cycle corresponding to this second clock cycle in the fourth time period (i.e., the Gth or (G + 1)th second clock cycle in the fourth time period).

[0027] Second aspect, an embodiment of the present application provides a data transmission method, which is applied to a data interface device. The data interface device includes a sending module and a receiving module. Among them, the sending module is in a first clock domain, the first clock domain corresponds to a first clock period, the receiving module is in a second clock domain, the second clock domain corresponds to a second clock period, and the sending module is electrically connected to the receiving module;

[0028] The data transmission method may include: when the length T1 of the first clock period is less than the length T2 of the second clock period, determining, by the sending module, N data sending times within a first time period based on the ratio of T1 to T2, where the first time period includes M first clock periods, both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2; sending data to the receiving module by the sending module at the N data sending times in sequence.

[0029] An embodiment of the present application provides a data transmission method. This data transmission method can be implemented based on a data interface device. In terms of the overall structure, the data interface device can include two major parts: a sending module and a receiving module. The sending module is electrically connected to the receiving module. This data transmission method can be used to implement data transmission between different modules in a digital circuit system, such as a transmitting end TX and a receiving end RX, based on this data interface device. Among them, both the transmitting end TX and the sending module are driven by a clock signal tx_clk (i.e., in the first clock domain); both the receiving end RX and the receiving module are driven by a clock signal rx_clk (i.e., in the second clock domain); the length of one clock cycle of the clock signal tx_clk (i.e., the first clock cycle) is T1, and the length of one clock cycle of the clock signal rx_clk (i.e., the second clock cycle) is T2. In the embodiment of the present application, when T1 is less than T2, within a first time period with a duration of M cycles of the clock signal tx_clk (i.e., M first clock cycles), the transmitting end TX sends data N times to the receiving module through the sending module respectively in N of these cycles (i.e., N first clock cycles where the N data sending moments are located). Thus, when a preset condition is met, such as the ratio of N to M is equal to the ratio of T1 to T2, the receiving end RX can sample the N times of data through the receiving module within N cycles of the clock signal rx_clk (i.e., N second clock cycles with a duration equal to the first time period); or when a preset condition is met, such as the ratio of N to M is less than the ratio of T1 to T2, the receiving end RX can sample the N times of data through the receiving module within several cycles of the clock signal rx_clk (with a duration equal to the first time period and greater than N second clock cycles). In summary, when T1 is less than T2 and the above preset conditions are met, the transmitting end TX can send data N times to the receiving module through the sending module within the first time period, and within several second clock cycles (at least N second clock cycles) with a duration equal to the first time period, the receiving end RX can perform at least N data samplings through the receiving module (because each second clock cycle can sample once). Therefore, for the N times of data sent by the transmitting end TX through the sending module, the receiving end RX can achieve non - missing data sampling and reception through the receiving module, thereby realizing the matching of the data sampling rate and the data sending rate based on this data interface device without introducing other data storage units for buffering (for example, the first - in - first - out FIFO memory in the prior art). This can not only avoid data loss and achieve cross - clock - domain data transmission with low latency, but also help save the chip area occupied by the data interface device and reduce the hardware cost.

[0030] In a possible implementation, the process of the sending module sequentially sending data to the receiving module at the N data sending moments includes: the sending module sequentially writing data into a register at the N data sending moments, and the receiving module reading the data in the register, where the register is electrically connected to the receiving module.

[0031] In a possible implementation, the process of the sending module sequentially writing data into a register at the N data sending moments includes: the sending module writing data into different registers at any two adjacent data sending moments, where the different registers are connected in parallel and are electrically connected to the receiving module.

[0032] In a possible implementation, the process of the sending module determining the N data sending moments within a first time period based on the ratio of T1 to T2 includes: the sending module sequentially sending multiple groups of first test signals to the receiving module based on the ratio of T1 to T2, where the first test signals include level signals that sequentially flip at (N - L) first moments, and L is an integer greater than 0 and less than N; the receiving module sequentially receiving the multiple groups of first test signals and determining whether the (N - L) first moments in the first test signals meet a first condition, where the first condition includes that the (N - L) first moments are sequentially before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock cycles; the sending module receiving a feedback signal and determining the N data sending moments based on the feedback signal, where the feedback signal is the response of the receiving module to the multiple groups of first test signals.

[0033] In a possible implementation, the process of the sending module receiving a feedback signal and determining the N data sending moments based on the feedback signal includes: the receiving module sequentially sending multiple groups of feedback signals to the sending module, where each group of feedback signals corresponds to a group of the first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal meet the first condition; the sending module sequentially receiving the multiple groups of feedback signals and determining the N data sending moments based on the multiple groups of feedback signals.

[0034] In a possible implementation, the process of the sending module sequentially writing data into a register at the N data sending moments includes: within the first time period, the sending module initially writes data into the register at the first L data sending moments among the N data sending moments.

[0035] In a possible implementation, the sending module sequentially sends multiple first test signals to the receiving module based on the ratio of T1 to T2, including: generating, by the sending module, multiple groups of indexes based on the ratio of T1 to T2, and any one group of the indexes includes N index values, where the N index values are all integers, and each index value corresponds to one of the first clock cycles within the first time period; sequentially sending, by the sending module, multiple groups of first test signals to the receiving module based on the multiple groups of indexes, where each group of the first test signals corresponds to one group of the indexes.

[0036] In a possible implementation, determining the N data sending moments based on the multiple groups of feedback signals includes: determining, by the sending module, a target test signal from the multiple groups of first test signals based on the multiple groups of feedback signals, where the (N - L) first moments in the target test signal satisfy the first condition; determining, by the sending module, N first clock cycles within the first time period based on a group of the indexes corresponding to the target test signal, where the N data sending moments are respectively located in the N first clock cycles.

[0037] In a possible implementation, generating, by the sending module, multiple groups of indexes based on the ratio of T1 to T2 includes: when the ratio of T1 to T2 is equal to the ratio of N to M, generating, by the sending module, a group of the indexes as an initial index; the index values in the initial index include all integers greater than (I × J - 1) and less than or equal to (I × J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N; generating, by the sending module, the other groups of indexes in the multiple groups of indexes based on the initial index.

[0038] In a possible implementation, generating, by the sending module, the other groups of indexes in the multiple groups of indexes based on the initial index includes: generating, by the sending module, one or more groups of the indexes as one or more groups of derivative indexes; where the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index values in the derivative indexes are equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, and Q is an integer greater than 0 and less than M.

[0039] In a possible implementation, the N data transmission times are all at the rising edge of the first clock cycle; the step of sequentially transmitting multiple groups of first test signals from the sending module to the receiving module based on the multiple groups of indexes includes: respectively transmitting a corresponding group of the first test signals from the sending module to the receiving module based on each group of the indexes, where the first test signal includes a start test signal, and the start test signal includes a level signal whose signal flips at the falling edge of the X-th first clock cycle in the second time period; where the second time period includes M first clock cycles; X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in the indexes corresponding to the first test signal.

[0040] In a possible implementation, the step of writing data to the register by the sending module at the N data transmission times in sequence includes: the sending module alternately writes data to Y registers at the N data transmission times in sequence, where Y is an integer greater than 1 and less than N; the level signals that sequentially flip at (N - L) first times include Y sub-test signals; where the index values in the indexes corresponding to the first test signal are denoted as B K , and the index value B K is the K-th index value after sorting the index values in the indexes from small to large, K = 1, 2, 3,..., N; the Z-th sub-test signal in the Y sub-test signals is denoted as A Z , Z = 1, 2, 3,..., Y; the Y sub-test signals include: A 1 , A 2 , A 3 ,... A Y ; when the value of K is equal to (R × Y + Z), the Z-th sub-test signal A Z flips at the falling edge of the B-th K first clock cycle in the second time period; R is a positive integer.

[0041] In a possible implementation, the step of determining whether the (N - L) first times in the first test signal meet the first condition includes: within the second time period, after detecting that the signal level of the start test signal flips through the receiving module, the receiving module alternately samples the Y sub-test signals at the (N - L) second times in sequence to obtain test signal sampling values, and determines whether the test signal sampling values are equal to a preset reference value; when the test signal sampling values are equal to the reference value, the receiving module determines that the (N - L) first times meet the first condition.

[0042] In a possible implementation, the method further includes: when the length T1 of the first clock cycle is greater than or equal to the length T2 of the second clock cycle, the receiving module receives a second test signal sent by the sending module within a third time period, the third time period includes F second clock cycles, the second test signal includes a level signal whose signal level flips successively at E third moments; the receiving module determines E data reception moments within a fourth time period based on the second test signal, where the fourth time period includes F second clock cycles, both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2; the receiving module receives data sent by the sending module successively at the E data reception moments.

[0043] In a possible implementation, the receiving module receiving data sent by the sending module successively at the E data reception moments includes: the sending module writes data to a register, and the receiving module reads the data in the register successively at the E data reception moments, where the register is electrically connected to the receiving module.

[0044] In a possible implementation, the receiving module reading the data in the register successively at the E data reception moments includes: the receiving module reads the data in different registers at any two adjacent data reception moments, where the different registers are connected in parallel and are electrically connected to the receiving module.

[0045] In a possible implementation, the determining E data reception moments within a fourth time period based on the second test signal includes: when the receiving module detects that the signal level of the second test signal flips at the G-th second clock cycle within the third time period, the receiving module determines that the data reception moment is within the G-th second clock cycle of the fourth time period, or determines that the data reception moment is within the (G + 1)-th second clock cycle of the fourth time period; G is an integer greater than or equal to 1 and less than F.

[0046] In a third aspect, an embodiment of the present application provides a computer program product, which includes computer program code. When the computer program product runs on a computer, it causes the computer to execute the data transmission method in any possible implementation of the second aspect above.

[0047] Fourthly, an embodiment of the present application provides a computer-readable storage medium, including computer instructions, which when running on a computing device, cause the computing device to execute the data transmission method provided in any possible implementation manner of the second aspect above.

[0048] Fifthly, the present application provides a digital circuit, which includes the data interface device provided in any possible implementation manner of the first aspect above. This digital circuit can be composed of the data interface device, or can include the data interface device and other discrete devices. It can be understood that the data transmission method provided in the second aspect and the digital circuit provided in the fifth aspect can both be implemented based on the data interface device provided in the first aspect of the present application. The beneficial effects that can be achieved can refer to the beneficial effects in the corresponding device, which will not be elaborated here. The computer program product provided in the third aspect and the computer-readable storage medium provided in the fourth aspect are both used to execute the data transmission method provided in any possible implementation manner of the second aspect of the present application. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method and device, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1A is a schematic structural diagram of an existing data interface device provided by an embodiment of the present application;

[0051] Figure 1B is a schematic diagram of the working principle of an existing data interface device provided by an embodiment of the present application;

[0052] Figure 1C is a schematic diagram of the working principle of another existing data interface device provided by an embodiment of the present application;

[0053] Figure 2 is a schematic diagram of an application scenario of a data interface device provided by an embodiment of the present application;

[0054] Figure 3 is a schematic diagram of the system architecture of a data interface device provided by an embodiment of the present application;

[0055] Figure 4A is a schematic structural diagram of a data interface device provided by an embodiment of the present application;

[0056] Figure 4BIt is a schematic structural diagram of another data interface device provided by an embodiment of the present application;

[0057] Figure 4C It is a schematic structural diagram of yet another data interface device provided by an embodiment of the present application;

[0058] Figure 5 It is a schematic flowchart of a data transmission method provided by an embodiment of the present application;

[0059] Figure 6A It is a schematic flowchart of another data transmission method provided by an embodiment of the present application;

[0060] Figure 6B It is a schematic diagram of the working principle of a data transmission method provided by an embodiment of the present application;

[0061] Figure 6C It is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application;

[0062] Figure 6D It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0063] Figure 6E It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0064] Figure 6F It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0065] Figure 7A It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0066] Figure 7B It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0067] Figure 7C It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0068] Figure 7D It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application;

[0069] Figure 7E It is a schematic diagram of the working principle of yet another data transmission method provided by an embodiment of the present application. Detailed implementation manners

[0070] Next, the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application.

[0071] The terms "first", "second", "third", "fourth", etc. in the description, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0072] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0073] The terms "component", "module", "system", etc. used in this specification are used to denote computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, an application running on a computing device and the computing device can both be components. One or more components can reside in a process and / or execution thread, and a component can be located on one computer and / or distributed between two or more computers. In addition, these components can execute from various computer-readable media on which various data structures are stored. A component can communicate, for example, through local and / or remote processes according to a signal having one or more data packets (such as data from two components interacting with another component among a local system, a distributed system, and / or a network, such as data interacting with other systems through signals on the Internet).

[0074] First, analyze and propose the specific technical problems to be solved by this application. When different modules in a digital circuit system use different clock signals such as frequency and phase, and these clock signals are all derived clocks from the same clock source, how to achieve data transmission between these different modules, that is, how to achieve data transmission across clock domains with the same source. In the prior art, there is mainly the following Solution 1:

[0075] Solution 1: Implement data transmission across clock domains with the same source through a data interface device based on a first-in, first-out (FIFO) memory. Please refer to Figure 1A , Figure 1AIt is a schematic structural diagram of an existing data interface device provided by an embodiment of the present application. For data transmission across the same-source clock domains, it can be implemented based on the Figure 1A data interface device shown in

[0076] Specifically, the write data control module 101 can transfer the write pointer wptr to the read data control module 105 through the N-stage synchronizer 104, and at the same time receive the read pointer rptr transmitted from the read data control module 105 through the N-stage synchronizer 103. Then, the write data control module 101 and the read data control module 105 respectively compare the magnitudes of the write pointer wptr and the read pointer rptr to determine whether the state of the first-in first-out FIFO memory 102 is "full" or "empty". When the first-in first-out FIFO memory 102 is in the "not full" state, the write enable signal wen output by the write data control module 101 is valid, so that the write data signal wdata writes data into the first-in first-out FIFO memory 102, and the write address waddr is incremented by 1; correspondingly, when the first-in first-out FIFO memory 102 is in the "not empty" state, the read data control module 105 causes the read data signal rdata to read data from the first-in first-out FIFO memory 102, and the read address raddr is incremented by 1.

[0077] Among them, Figure 1A the N-stage synchronizer 103 and the N-stage synchronizer 104 shown in Figure 1B can be cascaded by N-stage flip-flops (Flip Flop), please refer to Figure 1B It is a schematic diagram of the working principle of an existing data interface device provided by an embodiment of the present application. As Figure 1B shown, when performing data transmission across the same-source clock domains, since the sending end TX and the receiving end RX are in different clock domains (i.e., driven by clock signals Tx_clk and Rx_clk respectively, and the clock frequencies F1≠F2), by using a two-stage synchronizer composed of two cascaded flip-flops for clock beating, the frequency of data signal changes across the clock can be reduced, the probability of metastability occurrence and propagation can be reduced, and the stability of data transmission can be improved.

[0078] This solution has the following multiple disadvantages:

[0079] Disadvantage 1: During the data transmission process, it is necessary to perform multiple read and write operations on the first-in first-out FIFO memory. The frequent read and write processes will increase the power consumption of the digital circuit system. As Figure 1AAs shown, under the control of the write data control module 101 and the read data control module 105, each write and read of data needs to pass through the first-in-first-out (FIFO) memory 102 for transfer. Generally speaking, the first-in-first-out (FIFO) memory 102 can adopt a dual-port random access memory (Dual RAM). When the data volume is large, a large number of frequent read and write operations on the first-in-first-out (FIFO) memory 102 are not conducive to reducing the system power consumption.

[0080] Disadvantage 2: During the data transmission process, since different modules use clock signals with different frequencies, in order to avoid data loss, the depth of the first-in-first-out (FIFO) memory needs to be adapted to the frequencies of these clock signals, resulting in the first-in-first-out (FIFO) memory occupying a relatively large chip area. For example, as Figure 1A shown, when the frequency of the clock signal wclk is higher than the frequency of the clock signal rclk, the frequency of writing the write data signal wdata into the first-in-first-out (FIFO) memory 102 is higher than the frequency of reading the read data signal rdata from the first-in-first-out (FIFO) memory 102. In order to avoid data overflow and ensure the data transmission rate, the first-in-first-out (FIFO) memory 102 needs a relatively large depth, so that the storage capacity of the first-in-first-out (FIFO) memory 102 is sufficient to cover the difference in the amount of data before writing and reading data.

[0081] Disadvantage 3: During the data transmission process, it is necessary to transmit the read and write pointers of the first-in-first-out memory at the same time. Currently, it is usually necessary to convert the read and write pointers into the Gray Code form first, and then transmit them through a single-bit transmission structure (for example, Figure 1A the N-stage synchronizer 103 and the N-stage synchronizer 104 shown in Figure 1C , Figure 1C which is a schematic diagram of the working principle of another existing data interface device provided by an embodiment of the present application. As Figure 1C shown, taking the time when the write data control module 101 receives the write signal write as the starting time (i.e., t = 0), then each bit of the write pointer wptr sent by the write data control module to the N-stage synchronizer needs to consume one clock cycle of the clock signal wclk (i.e., t = 1). Since the N-stage synchronizer 104 usually includes N flip-flops, each bit of the write pointer wptr needs to consume N clock cycles of the clock signal wclk after passing through the N-stage synchronizer 104 (i.e., t = 1 + N). Therefore, each time the data is read from the first-in-first-out (FIFO) memory through the read data signal rdata (i.e., t = 1 + N), there is a relatively large delay compared to the starting time (i.e., t = 0), thus increasing the overall delay of data transmission.

[0082] Considering the disadvantages of the existing technologies, the technical problems to be actually solved by this application include: when performing data transmission across clock domains with the same source between different modules in a digital circuit system, how to reduce the data transmission delay, save chip area, and reduce hardware costs.

[0083] To facilitate the understanding of the embodiments of this application, the following are exemplary scenarios where the data interface device in this application is applied, which may include:

[0084] Scenario 1, when different modules in a digital circuit system use different clock signals (usually, the frequencies and phases of these clock signals are different), and these clock signals are all derived clocks of the same clock source, that is, these different modules belong to a system with the same source, the data transmission between these different modules (that is, data transmission across clock domains with the same source, or asynchronous data transmission with the same source) can be implemented based on the data interface device in this application. Please refer to Figure 2 , Figure 2 FIG. is a schematic diagram of an application scenario of a data interface device provided by an embodiment of this application. As Figure 2 shown, Chip0, Chip1, and Chip2 may be different bare chips (Dies). A clock source (Clock Source) can act on multiple clock managers (Clock Managers) in different bare chips, and a clock manager can provide clock signals as a drive for multiple modules. At this time, the data transmission between these modules all belongs to data transmission across clock domains with the same source. For example, as Figure 2 shown, the clock manager Clock Manager 0 under the action of the clock source Clock Source 0 provides clock signals Clk0 and Clk1 for the modules module0 and module1 respectively. When the frequencies of the clock signals Clk0 and Clk1 are different, the data transmission between the modules module0 and module1 belongs to data transmission across clock domains with the same source; the clock managers Clock Manager 1 and Clock Manager 2 under the action of the clock source Clock Source 0 provide clock signals Clk2 and Clk3 for the modules module2 and module3 respectively. At this time, the data transmission between the modules module2 and module3, and the data transmission between the modules module2 and module0 or module1 all belong to data transmission across clock domains with the same source. In addition, as Figure 2 shown, since the modules module4 and module5, and the modules module4 and module7 do not belong to a system with the same source, the data transmission between the modules module4 and module5, and the data transmission between the modules module4 and module7 do not belong to data transmission across clock domains with the same source.

[0085] It can be understood that the above application scenarios are only an exemplary implementation manner in the embodiments of the present application, and the application scenarios in the embodiments of the present application include but are not limited to the above application scenarios.

[0086] Based on the above-mentioned technical problems and the corresponding application scenarios in the present application, and in order to facilitate the understanding of the embodiments of the present application, the data interface device provided by the embodiments of the present application will be described below.

[0087] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the system architecture of a data interface device provided by an embodiment of the present application. As Figure 3 shown, the data interface device may include a sending module 302 and a receiving module 303. Among them, both the sending module 302 and the sending end 301 use the clock signal tx_clk, that is, they are both in the first clock domain; both the receiving module 303 and the receiving end 304 use the clock signal rx_clk, that is, they are both in the second clock domain; the clock signal tx_clk and the clock signal rx_clk are different derived clocks of the same clock source. When data is transmitted, after the sending end 301 sends the data signal tx_data to the sending module 302, the sending module 302 then sends the data to the receiving module 303, and then the receiving module 303 sends the data signal rx_data to the receiving end 304.

[0088] Exemplarily, before the sending module 302 sends the data signal to the receiving module 303, the sending module 302 may first send a test signal to the receiving module 303.

[0089] Exemplarily, the sending module 302 may send the data signal to the receiving module 303 through a register circuit. Please refer to Figure 4A , Figure 4A which is a schematic diagram of the structure of a data interface device provided by an embodiment of the present application. As Figure 4A shown, the register circuit 401 belongs to the sending module 302 shown in Figure 3 , that is, the register circuit 401 belongs to the first clock domain; the sampling circuit 402 belongs to Figure 3The receiving module 303 shown in [figure reference] where the sampling circuit 402 belongs to the second clock domain. Optionally, the register circuit 401 may include two registers connected in parallel (hereinafter referred to as odd-even registers), and the sampling circuit 402 may include a multiplexer and a register connected in series. Specifically, under the action of the enable signal en1 and the enable signal en2 sent by the control circuit 403, the data signal tx_data writes data into one of the registers in the odd-even register each time. After that, the register that has received the data passes the data signal to the sampling circuit 402. The multiplexer in the sampling circuit 402 is connected to the register that has received the data under the action of the selection signal sel sent by the control circuit 403, and writes the data signal received from the register into the next-level register, thereby obtaining the data signal rx_data.

[0090] It can be understood that Figure 3 the system architecture in [figure reference] is only an exemplary implementation manner in the embodiments of the present application. The data interface device in the embodiments of the present application includes but is not limited to the above system architecture. Figure 4A the structure of the data interface device in [figure reference] is only an exemplary implementation manner in the embodiments of the present application. The data interface device in the embodiments of the present application includes but is not limited to the above structure.

[0091] Based on Figure 3 the system architecture provided in [figure reference], the embodiments of the present application provide a data interface device applied to this system architecture. Please refer to Figure 4B , Figure 4B which is a schematic structural diagram of another data interface device provided by the embodiments of the present application. As Figure 4B shown, the data interface device may include a sending module 302 and a receiving module 303. Among them, the sending module 302 and the sending end 301 both use the clock signal tx_clk, that is, they are both in the first clock domain; the receiving module 303 and the receiving end 304 both use the clock signal rx_clk, that is, they are both in the second clock domain; the clock signal tx_clk and the clock signal rx_clk are different derived clocks of the same clock source, and one clock cycle of the clock signal tx_clk and the clock signal rx_clk are the first clock cycle and the second clock cycle respectively.

[0092] Exemplarily, as Figure 4B shown, the process of data transmission between the sending end 301 and the receiving end 304 through the data interface device may include 4 parts as follows:

[0093] (1) Before data transmission, the sending end 301 can apply to the sending module 302 for sending new data through the signal request (for example, setting the signal request to a high level). After that, the sending module 302 can prompt the sending end 301 through the signal acknowledge that it can start sending data;

[0094] (2) During data transmission, the sending end 301 can send the data signal tx_data to the sending module 302 (that is, the signal tx_data[`DW - 1:0] in Figure 4B . Here, [`DW - 1:0] can be used to indicate that the data bit width of this signal is 1, which will not be elaborated below); After that, the sending module 302 can send data to the receiving module 303 through the data signal tx_data_odd and the data signal tx_data_even;

[0095] (3) During data transmission, the receiving module 303 can send the safely sampled data to the receiving end 304 through the data signal sel_data. At the same time, the receiving module 303 can prompt the receiving end 304 through the signal data_valid which sampling data is valid at which moments (for example, when the signal data_valid is at a high level, the sampling value of the data signal sel_data by the receiving end 304 is valid). In addition, the receiving module 303 can prompt the receiving end 304 to perform Clock Gating through the signal clock_valid. Generally speaking, since the time for the receiving end 304 to perform Clock Gating needs to be earlier than the data sampling time, therefore, the signal clock_valid needs to be sent before the signal data_valid (for example, before the signal data_valid is set to a high level, the signal clock_valid is set to a low level half a second clock cycle in advance);

[0096] (4) When the current data transmission process ends, the digital circuit system can reset the sending end 301 and the sending module 302 through the reset signal rst_n_tx, and reset the receiving end 304 and the receiving module 303 through the reset signal rst_n_rx.

[0097] The sending module 302 can be used to determine N data sending moments within the first time period based on the ratio of T1 and T2 when the length T1 of the first clock cycle is less than the length T2 of the second clock cycle, and sequentially send data to the receiving module 303 at these N data sending moments; where the first time period includes M first clock cycles, and both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2.

[0098] Optionally, the sending module 302 can be used to write data to a register at N data sending moments in sequence. The register is electrically connected to the receiving module 303; the receiving module 303 can be used to read the data in the register. For example, as Figure 4B shown, the sending module 302 can send data to the receiving module 303 through the data signal tx_data_odd and the data signal tx_data_even. Among them, the data signal tx_data_odd and the data signal tx_data_even can be based on, such as Figure 4A shown in the register circuit 401 and the sampling circuit 402 to achieve signal transmission.

[0099] Optionally, the sending module 302 can be used to write data to different registers at any two adjacent data sending moments. Among them, the different registers are connected in parallel and are electrically connected to the receiving module 303. For example, as Figure 4A shown, under the action of the enable signal en1 and the enable signal en2 sent by the control circuit 403, the sending module 302 can alternately write data to the parity register through the data signal tx_data. In addition, as Figure 4B shown, the sending module 302 can alternately write data to two registers (that is, the parity register as Figure 4A shown) through the data signal tx_data_odd and the data signal tx_data_even (that is, the data signal tx_data as Figure 4A shown). At the same time, the sending module 302 can also use the signal enable[1:0] to prompt the receiving module 303 whether the data in the two registers is valid, and can use the signal enable_clock[1:0] to prompt the receiving module 303 to perform clock gating, so as to send the data to the receiving module 303.

[0100] Optionally, the sending module 302 can be used to sequentially send multiple groups of first test signals to the receiving module 303 based on the ratio of T1 to T2. The first test signal includes a level signal that sequentially flips at (N - L) first moments. L is an integer greater than 0 and less than N; the receiving module 303 can be used to sequentially receive the multiple groups of first test signals and determine whether the (N - L) first moments in the first test signal meet the first condition. Among them, the first condition includes that the (N - L) first moments are sequentially before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock cycles; the sending module 302 can be used to receive a feedback signal and determine N data sending moments based on the feedback signal. Among them, the feedback signal is the response of the receiving module 303 to the multiple groups of first test signals. For example, as Figure 4BAs shown, both the sending module 302 and the receiving module 303 have input signals M[3:0] and input signals N[3:0] with a data bit width equal to 3. Among them, the magnitude of the value transmitted by the input signal M[3:0] is denoted as M 0 , and the magnitude of the value transmitted by the input signal N[3:0] is denoted as N 0 . Then the ratio of N 0 to M 0 can be equal to the ratio of T1 to T2. After that, the sending module 302 can, based on the values of N 0 and M 0 (i.e., the ratio of T1 to T2), send a set of first test signals to the receiving module 303 in multiple times, each time through the signal test_tx, the signal pattern_test_odd, and the signal pattern_test_even. After receiving one set of the first test signals, the receiving module 303 can determine whether the (N - L) first moments in this set of the first test signals meet the first condition, and send a feedback signal to the sending module 302 through the signal pattern_error. It can be understood that the signals test_tx, pattern_test_odd, and pattern_test_even (i.e., a set of first test signals) shown in Figure 4B can be level signals, and the signal pattern_error (i.e., the feedback signal) shown in Figure 4B can also be a level signal.

[0101] Optionally, the receiving module 303 can be used to send multiple sets of feedback signals to the sending module 302 in sequence. Among them, each set of feedback signals corresponds to a set of first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding set of first test signals meet the first condition. The sending module 302 can be used to receive the multiple sets of feedback signals in sequence and determine N data sending moments based on the multiple sets of feedback signals. For example, as shown in Figure 4B , each time the receiving module 303 receives a set of first test signals through the signal test_tx, the signal pattern_test_odd, and the signal pattern_test_even, it sends a corresponding set of feedback signals to the sending module 302 through the signal pattern_error. The feedback signal can be used to indicate whether the (N - L) first moments in this set of first test signals meet the first condition. For example, if the signal pattern_error is at a high level, it means that the (N - L) first moments in this set of first test signals do not meet the first condition.

[0102] Optionally, the sending module 302 can be used to initially write data to the register at the first L data sending moments among the N data sending moments within the first time period. For example, as Figure 4A shown, within a first time period, if the sending module 302 alternately writes data to the parity register at the N data sending moments through the data signal tx_data, the sending module 302 can initially write data to the odd register at the first data sending moment and initially write data to the even register at the second data sending moment, that is, L = 2; where the odd register and the even register are different registers in the parity register.

[0103] Exemplarily, please refer to Figure 4C , Figure 4C which is a schematic structural diagram of another data interface device provided by an embodiment of the present application. As Figure 4C shown, the sending module 302 can include a register circuit 3021, an index generator 3022, and a test signal generator 3023; the receiving module 303 can include a data selector 3031 and a referee 3032. Among them,

[0104] The register circuit 3021 can include one or more registers connected in parallel. The register circuit 3021 can be used to receive the written data through the one or more registers connected in parallel and send the data to the receiving module 303. For example, the register circuit 3021 can include two registers connected in parallel (i.e., the parity register) as shown in the register circuit 401 in Figure 4A . At this time, as Figure 4C shown, the register circuit 3021 can receive the data written by the data signal tx_data through the parity register and then send the data to the receiving module 303 through the data signals tx_data_odd and tx_data_even;

[0105] The index generator 3022 can be used to generate multiple groups of indexes based on the ratio of T1 and T2, and any group of indexes includes N index values, where the N index values are all integers and each index value corresponds to a first clock cycle within the first time period;

[0106] The test signal generator 3023 can be used to sequentially send multiple groups of first test signals to the receiving module 303 based on the multiple groups of indexes, where each group of first test signals corresponds to a group of indexes;

[0107] The data selector 3031 can be used to select one register from the one or more registers connected in parallel in the register circuit 3021, and the data in this register can be used for data sampling;

[0108] The arbiter 3032 can be used to sequentially receive multiple groups of first test signals sent by the test signal generator 3023, determine whether the (N - L) first moments in the first test signal meet the first condition, and sequentially send multiple groups of feedback signals to the index generator 3022; wherein, each group of feedback signals corresponds to a group of first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal meet the first condition.

[0109] Optionally, the sending module 302 can be used to determine a target test signal from multiple groups of first test signals based on multiple groups of feedback signals, where the (N - L) first moments in the target test signal meet the first condition; based on a group of indexes corresponding to the target test signal, determine N first clock cycles within the first time period, where the N data sending moments are respectively located in the N first clock cycles.

[0110] Optionally, the index generator 3022 can be used to generate a group of indexes as the initial index when the ratio of T1 to T2 is equal to the ratio of N to M; based on the initial index, generate the other groups of indexes in the multiple groups of indexes; wherein, the index values in the initial index include all integers greater than (I×J - 1) and less than or equal to (I×J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N.

[0111] Optionally, the index generator 3022 can be used to generate one or more groups of indexes based on the initial index as one or more groups of derivative indexes; wherein, the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index values in the derivative indexes are equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, and Q is an integer greater than 0 and less than M.

[0112] Optionally, when the N data sending moments are all at the rising edge of the first clock cycle, the test signal generator 3023 can be used to respectively send a group of corresponding first test signals to the receiving module 303 based on each group of indexes, the first test signal includes a starting test signal, and the starting test signal includes a level signal whose signal flips at the falling edge of the Xth first clock cycle in the second time period; wherein, the second time period includes M first clock cycles; X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in a group of indexes corresponding to the first test signal. For example, Figure 4CAs shown, each time the test signal generator 3023 receives the indication information to start sending the first test signal through the signal test (for example, the test signal generator 3023 detects that the signal test flips from low level to high level), the test signal generator 3023 can send the starting test signal in each group of the first test signals to the referee 3032 through the signal test_tx. Among them, if the smallest index value in the indexes corresponding to this group of the first test signals is 1, the signal test_tx can flip from low level to high level in the second first clock cycle of this second time period.

[0113] Optionally, the sending module 302 can be used to alternately write data to Y registers at N data sending times in sequence, where Y is an integer greater than 1 and less than N; at this time, the level signals that flip in (N - L) first times in each group of the first test signals include Y sub-test signals; where the index value in a group of indexes corresponding to this first test signal is denoted as B K , and the index value B K is the Kth index value after sorting the index values in this group of indexes from small to large, K = 1, 2, 3,..., N; the Zth sub-test signal in this Y sub-test signals is denoted as A Z , Z = 1, 2, 3,..., Y; this Y sub-test signals include: A 1 , A 2 , A 3 ,... A Y ; when the value of K is equal to (R × Y + Z), the Zth sub-test signal A Z flips at the falling edge of the B K th first clock cycle in the second time period (when all N data sending times are at the rising edge of the first clock cycle); R is a positive integer. For example, as Figure 4C shown, when all N data sending times are at the rising edge of the first clock cycle, if the sending module 302 alternately writes data to the parity register in the register circuit 3021 at N data sending times in sequence (that is, Y = 2), then each group of the first test signals includes two sub-test signals, which are the signal pattern_test_odd (that is, the 1st sub-test signal, at this time Z = 1) and the signal pattern_test_even (that is, the 2nd sub-test signal, at this time Z = 2) shown in Figure 4C ; thus, when the value of K is equal to (2R + 1) (that is, when K is an odd number greater than 1), the signal pattern_test_odd flips at the falling edge of the B K th first clock cycle in the second time period, and when the value of K is equal to (2R + 2) (that is, when K is an even number greater than 2), the signal pattern_test_even flips at the falling edge of the BK There is a flip at the falling edge of a first clock cycle.

[0114] Optionally, the receiving module 303 can be used to alternately sample the Y sub-test signals in the first test signal at (N - L) second moments in sequence after detecting a flip in the signal level of the start test signal in the first test signal within a second time period, obtain a test signal sampling value, and determine whether the test signal sampling value is equal to a preset reference value; when the test signal sampling value is equal to the reference value, it is determined that the (N - L) first moments in the first test signal meet the first condition.

[0115] Optionally, when the length T1 of the first clock cycle is greater than or equal to the length T2 of the second clock cycle, the receiving module 303 can also be used to receive a second test signal sent by the sending module 302 within a third time period; determine E data reception moments within a fourth time period based on the second test signal; receive the data sent by the sending module 302 at the E data reception moments in sequence; wherein, the third time period includes F second clock cycles, the second test signal includes a level signal that flips at E third moments in sequence, the fourth time period includes F of the second clock cycles, both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2. For example, as Figure 4C shown, when the test signal generator 3023 receives an indication message to start sending the second test signal through the signal test each time, the test signal generator 3023 can send the second test signal to the arbiter 3032 through the signals pattern_test_odd and pattern_test_even, where the signals pattern_test_odd and pattern_test_even can be level signals.

[0116] Optionally, the receiving module 303 can be used to read the data in the register at the E data reception moments in sequence, and the register is electrically connected to the receiving module 303; the sending module 302 can be used to write data to the register.

[0117] Optionally, the receiving module 303 can be used to read the data in different registers at any two adjacent data reception moments, where the different registers are connected in parallel and are electrically connected to the receiving module 303.

[0118] Optionally, the receiving module 303 may be configured to determine that the data reception time is located in the G-th second clock cycle of the fourth time period, or determine that the data reception time is located in the (G + 1)-th second clock cycle of the fourth time period when the signal level of the second test signal is detected to flip in the G-th second clock cycle of the third time period; G is an integer greater than or equal to 1 and less than F.

[0119] Exemplarily, as Figure 4C shown, when T1 is less than T2, the process of data transmission through the sending module 302 and the receiving module 303 in the data interface device may include three parts as follows:

[0120] (1) Before data transmission, the index generator 3022 may receive indication information of preparing to send new data through the signal request. After that, the index generator 3022 and the arbiter 3032 may obtain the ratio of the first clock cycle T1 and the second clock cycle T2 through the input signals M[3:0] and the input signals N[3:0], and compare the magnitudes of T1 and T2;

[0121] (2) When T1 is less than T2, before data transmission, the index generator 3022 may generate multiple groups of indexes based on the ratio of T1 and T2, and sequentially send the multiple groups of indexes to the test signal generator 3023 through the signal pattern[1:0]; the test signal generator 3023 may generate a group of corresponding first test signals based on each group of indexes, and may be divided into multiple times. Each time after receiving the indication information of starting to send the first test signal through the signal test, a group of first test signals is sent to the receiving module 303 through the signal test_tx, the signal pattern_test_odd, and the signal pattern_test_even; the arbiter 3032 may determine whether the (N - L) first moments in the received first test signals meet the first condition, and may send a feedback signal corresponding to the first test signal to the index generator 3022 through the signal pattern_error; the index generator 3022 may determine the target test signal from the multiple groups of first test signals based on the feedback signal, and determine N data transmission times based on the N index values corresponding to the target test signal;

[0122] (3) When T1 is less than T2, during data transmission, the index generator 3022 can, based on the determined N data transmission times, control the data signal tx_data to alternately write data into the odd register and the even register in the register circuit 3021 through the enable signal enable_odd and the enable signal enable_even; afterwards, the register circuit 3021 can alternately send data to the data selector 3031 through the data signal tx_data_odd and the data signal tx_data_even; meanwhile, the arbiter 3032 can determine whether the data in the odd register and the even register in the register circuit 3021 is valid through the signals enable[1:0] and enable_clock[1:0], and control the data selector 3031 to select one of the data signals tx_data_odd and tx_data_even as the signal sel_data for data sampling through the control signal sel;

[0123] It can be understood that when T1 is greater than or equal to T2, data transmission can be performed through the sending module 302 and the receiving module 303 in the data interface device, which can refer to the above process and will not be elaborated here.

[0124] It can be understood that Figure 4B and Figure 4C the structure of the data interface device in

[0125] is only an exemplary implementation manner in the embodiments of the present application, and the structure of the data interface device in the embodiments of the present application includes but is not limited to the above structure. Figure 4B and Figure 4C Based on the structure of the data interface device provided in

[0126] Please refer to Figure 5 , Figure 5 which is a schematic flowchart of a data transmission method provided by an embodiment of the present application. This method can be applied to the data interface device described in the above Figure 3 and this data interface device can be used to support and execute Figure 5 the method flow steps S501 - S507 shown in Figure 4B and Figure 4C will be described below in conjunction with the appended

[0127] Step S501: Obtain the ratio of the length T1 of the first clock cycle to the length T2 of the second clock cycle.

[0128] Specifically, both the sending module and the receiving module in the data interface device can obtain the ratio of the length T1 of the first clock cycle to the length T2 of the second clock cycle. For example, as Figure 3 shown, one clock cycle of the clock signal tx_clk is the first clock cycle, and one clock cycle of the clock signal rx_clk is the second clock cycle.

[0129] Exemplarily, the data interface device can obtain the ratio of the length T1 of the first clock cycle to the length T2 of the second clock cycle by obtaining two values (the ratio of the two values is equal to the ratio of T1 and T2). For example, as Figure 4B shown, the sending module 302 and the receiving module 303 in the data interface device are respectively driven by the clock signal tx_clk and the clock signal rx_clk, and both have inputs M[3:0] and inputs N[3:0] with a data bit width equal to 3. Among them, the magnitude of the value transmitted by the input M[3:0] is denoted as M, and the magnitude of the value transmitted by the input N[3:0] is denoted as N. Then, the ratio of N to M is equal to the ratio of T1 to T2.

[0130] Optionally, the ratio of the length T1 of the first clock cycle to the length T2 of the second clock cycle can be obtained by obtaining the magnitudes of the clock frequencies of the clock signal tx_clk and the clock signal rx_clk, or by obtaining the ratio of the clock frequencies of the clock signal tx_clk and the clock signal rx_clk. For example, denoting the clock frequency of the clock signal tx_clk as f 0X and denoting the clock frequency of the clock signal rx_clk as f RX , then the ratio of f RX to f TX is equal to the ratio of T1 to T2.

[0131] Step S502: Determine whether the length T1 of the first clock cycle is less than the length T2 of the second clock cycle.

[0132] Specifically, it can be determined whether the length T1 of the first clock cycle is less than the length T2 of the second clock cycle by using the ratio of T1 and T2 obtained in the above step S501. For example, as Figure 4B shown, after the sending module 302 and the receiving module 303 in the data interface device obtain the values M and N through the inputs M[3:0] and inputs N[3:0] respectively, since the ratio of N to M is equal to the ratio of T1 to T2, the sending module 302 and the receiving module 303 can determine whether T1 is less than T2 by comparing the magnitudes of the values M and N.

[0133] Step S503: When the length T1 of the first clock cycle is less than the length T2 of the second clock cycle, the sending module determines N data sending moments within the first time period based on the ratio of T1 to T2.

[0134] Specifically, the first time period may include M first clock cycles, where both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2. For example, as Figure 4B shown, the sending module 302 and the receiving module 303 in the data interface device can obtain the values of M and N through input M[3:0] and input N[3:0] respectively.

[0135] Exemplarily, for how the sending module determines N data sending moments within the first time period based on the ratio of T1 to T2, please refer to Figure 6A Figure 6A which is a schematic flowchart of another data transmission method provided by an embodiment of the present application. This method can be applied to the data interface device described above Figure 3 and this data interface device can be used to support and execute the method flow steps S601 - S605 shown in Figure 6A . The following will be described from both sides of the sending module and the receiving module in combination with the attached Figure 3 drawings.

[0136] Step S601: When the length T1 of the first clock cycle is less than the length T2 of the second clock cycle, the sending module generates multiple groups of indexes based on the ratio of T1 to T2.

[0137] Specifically, any group of indexes generated by the sending module includes N index values, all of which are integers, and each index value corresponds to a first clock cycle within the first time period.

[0138] Optionally, when the size of the index value is V, the index value corresponds to the (V + 1)-th first clock cycle within the first time period, where V is an integer greater than or equal to 0 and less than M. Please refer to Figure 6B Figure 6B which is a schematic diagram of the working principle of a data transmission method provided by an embodiment of the present application. As Figure 6B shown, when the first time period includes 8 consecutive clock cycles of the clock signal tx_clk (i.e., M = 8), for a group of indexes including 3 index values (i.e., N = 3), if the 3 index values are 0, 5, and 7 respectively, then the 3 index values correspond to the 1st, 6th, and 8th first clock cycles (i.e., the clock cycles of the clock signal tx_clk) within the first time period respectively.

[0139] Optionally, when the ratio of T1 to T2 is equal to the ratio of N to M, a set of indexes can be generated by the sending module as the initial indexes. After that, based on the initial indexes, the sending module can generate the other groups of indexes in the multiple groups of indexes. Among them, the index values in the initial indexes include all integers greater than (I×J - 1) and less than or equal to (I×J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N. For example, please refer to Figure 6C , Figure 6C which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 6C shown, when the ratio of T1 to T2 is equal to 7 divided by 16, the positive integers M and N can be 16 and 7 respectively. At this time, the index value V in the initial indexes satisfies the following inequality:

[0140]

[0141] where I is an integer greater than or equal to 0 and less than 7. Therefore, the index value V in the initial indexes can be 0, 2, 4, 6, 9, 11, 13 respectively, and each index value corresponds to a first clock cycle.

[0142] Optionally, when the ratio of T1 to T2 is equal to the ratio of N to M, after generating the initial indexes by the sending module, the sending module can generate one or more groups of indexes based on the initial indexes as one or more groups of derivative indexes. Among them, the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index value in the derivative indexes is equal to (P - Q) or equal to (P - Q + M), where P is the index value in the initial indexes and Q is an integer greater than 0 and less than M. For example, please refer to Figure 6D , Figure 6D which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 6D shown, when the ratio of T1 to T2 is equal to 7 divided by 16, the positive integers M and N can be 16 and 7 respectively, so that a set of initial indexes as shown in ① in Figure 6D can be obtained. The initial indexes include 7 index values: 0, 2, 4, 6, 9, 11, 13. Based on the initial indexes, multiple groups of derivative indexes can be obtained. One group of derivative indexes is shown in ② in Figure 6D . This group of derivative indexes includes 7 index values: 1, 3, 5, 8, 10, 12, 15. Among them, the index values 1, 3, 5, 8, 10, 12 in this group of derivative indexes are respectively equal to the corresponding index values in the initial indexes minus 1 (i.e., P minus Q), and the index value 15 in this group of derivative indexes is equal to the corresponding index value in the initial indexes minus 1 and then plus 16 (i.e., P minus Q and then plus M).

[0143] Optionally, when the ratio of T1 to T2 is equal to the ratio of N to M, after generating the initial index through the sending module, each index value in the initial index can be subtracted by Q through the sending module to obtain N first intermediate values; then, M is added to each of the N first intermediate values to obtain N second intermediate values; thereafter, a set of derivative indexes is generated based on the N first intermediate values and the N second intermediate values, where the index values in the set of derivative indexes include the values greater than or equal to 0 in the N first intermediate values and the values less than M in the N second intermediate values. For example, as Figure 6D shown, after generating a set of initial indexes as shown in Figure 6D ① through the sending module, each index value in the initial index can be subtracted by 1 (i.e., subtracted by Q) to obtain 7 first intermediate values: -1, 1, 3, 5, 8, 10, 12; then, 16 (i.e., added by M) is added to each of the 7 first intermediate values to obtain 7 second intermediate values: 15, 17, 19, 21, 24, 26, 28; thus, a set of derivative indexes as shown in Figure 6D ② can be obtained from the values greater than or equal to 0 in the 7 first intermediate values and the values less than 16 in the 7 second intermediate values.

[0144] Optionally, when the ratio of T1 to T2 is equal to the ratio of N to M, after generating the initial index through the sending module, the sending module can generate one or more sets of indexes based on the initial index as one or more sets of derivative indexes, where the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index values in the derivative indexes are equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, Q is an integer greater than 0 and less than M, and Q is an integer multiple of the positive integer H. Regarding the value of the positive integer H, it can be divided into the following two cases:

[0145] (1) When M = N + 1, and the sending module sends data to the receiving module alternately through Y registers (i.e., the sending module alternately writes data to Y registers at the N data sending times) where Y is an integer greater than 1 and less than N, D is equal to the total number of derivative indexes, max{} is the operation of taking the maximum value, is the operator for rounding down.

[0146] For example, please refer to Figure 6E , Figure 6E which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 6E shown, when M and N are equal to 16 and 15 respectively, and the sending module sends data to the receiving module alternately through two registers (i.e., Y = 2), the sending module can generate as shown in Figure 6EA set of initial indexes shown in ①, where the index values in the initial indexes include all integers greater than (I×J - 1) and less than or equal to (I×J). Here, I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N. Therefore, this initial index includes 15 index values greater than or equal to 0 and less than or equal to 14, corresponding respectively to the 15 clock cycles of tx_clk as shown in Figure 6E ①. After that, the sending module can generate 3 other sets of derivative indexes (i.e., D = 3) based on this initial index. At this time, H can be calculated to be 4 according to the formula in (1). Therefore, these 3 sets of derivative indexes are as follows:

[0147] Derivative index 1: As shown in Figure 6E ②, the index values in this set of derivative indexes are equal to the corresponding index values in the initial index minus 4 (i.e., P minus Q, where Q is equal to H), or equal to the corresponding index values in the initial index minus 4 and then plus 16 (i.e., P minus Q plus M, where Q is equal to H).

[0148] Derivative index 2: As shown in Figure 6E ③, the index values in this set of derivative indexes are equal to the corresponding index values in the initial index minus 8 (i.e., P minus Q, where Q is equal to 2H), or equal to the corresponding index values in the initial index minus 8 and then plus 16 (i.e., P minus Q plus M, where Q is equal to 2H).

[0149] Derivative index 3: As shown in Figure 6E ④, the index values in this set of derivative indexes are equal to the corresponding index values in the initial index minus 12 (i.e., P minus Q, where Q is equal to 3H), or equal to the corresponding index values in the initial index minus 12 and then plus 16 (i.e., P minus Q plus M, where Q is equal to 3H).

[0150] (2) When M≠N + 1, where, D is equal to the total number of derivative indexes, max{} is the operation of taking the maximum value, is the operator for floor division, and % is the operator for taking the remainder.

[0151] For example, please refer to Figure 6F , Figure 6F which is a schematic diagram of the working principle of another data transmission method provided by the embodiments of the present application. As shown in Figure 6F when M and N are equal to 16 and 13 respectively, a set of initial indexes as shown in Figure 6F ① can be generated by the sending module. The index values in this initial index include all integers greater than (I×J - 1) and less than or equal to (I×J). Here, I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N. Therefore, this initial index includes 13 index values, corresponding respectively to the 13 clock cycles of tx_clk as shown in Figure 6FThe 13 clock cycles of tx_clk shown in ①. After that, the sending module can generate 3 other sets of derivative indexes (i.e., D = 3) based on this initial index. At this time, H can be calculated to be 1 according to the formula in (2). Therefore, these 3 sets of derivative indexes are as follows:

[0152] Derivative index 1: As Figure 6F shown in ②, the index value in this set of derivative indexes is equal to the corresponding index value in the initial index minus 1 (i.e., P minus Q, and Q is equal to H), or equal to the corresponding index value in the initial index minus 1 and then plus 16 (i.e., P minus Q plus M, and Q is equal to H).

[0153] Derivative index 2: As Figure 6F shown in ③, the index value in this set of derivative indexes is equal to the corresponding index value in the initial index minus 2 (i.e., P minus Q, and Q is equal to 2H), or equal to the corresponding index value in the initial index minus 2 and then plus 16 (i.e., P minus Q plus M, and Q is equal to 2H).

[0154] Derivative index 3: As Figure 6F shown in ④, the index value in this set of derivative indexes is equal to the corresponding index value in the initial index minus 3 (i.e., P minus Q, and Q is equal to 3H), or equal to the corresponding index value in the initial index minus 3 and then plus 16 (i.e., P minus Q plus M, and Q is equal to 3H).

[0155] Step S602: The sending module sequentially sends multiple sets of first test signals to the receiving module based on the multiple sets of indexes.

[0156] Specifically, each set of first test signals includes a level signal that sequentially flips at (N - L) first moments, where L is an integer greater than 0 and less than N.

[0157] Optionally, the sending module can send a set of corresponding first test signals to the receiving module based on a set of indexes in each second time period. This second time period includes M first clock cycles. For example, please refer to Figure 7A , Figure 7A which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 7A shown, the sending module can sequentially send 4 sets of first test signals to the receiving module based on 4 sets of indexes. Among them, the sending module sends a set of first test signals to the receiving module every M first clock cycles (i.e., every second time period), and each set of first test signals corresponds to a set of indexes.

[0158] Optionally, after sending a set of first test signals to the receiving module based on the initial index through the sending module, a set of first test signals may be sent to the receiving module based on each set of derived indexes in ascending order of Q; wherein, the index values in the derived indexes are all integers greater than or equal to 0 and less than M, and the index values in the derived indexes are equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, Q is an integer greater than 0 and less than M, and Q is an integer multiple of the positive integer H.

[0159] Optionally, when the N data sending moments are all at the rising edge of the first clock cycle, a set of corresponding first test signals may be sent to the receiving module based on a set of indexes by the sending module in each second time period, the second time period includes M first clock cycles, the first test signal includes a starting test signal, and the starting test signal includes a level signal whose signal flips at the falling edge of the X-th first clock cycle in the second time period; wherein, X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in the set of indexes corresponding to the first test signal.

[0160] For example, please refer to Figure 7B , Figure 7B is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. When the N data sending moments are all at the rising edge of the first clock cycle (such as Figure 7B the rising edge of the clock signal tx_clk shown in), a set of corresponding first test signals may be sent to the receiving module based on a set of indexes by the sending module within a second time period including 16 first clock cycles (i.e., M = 16), wherein, there are 7 index values (i.e., N = 7) in the set of indexes, which are: 0, 2, 4, 6, 9, 11, 13; the first test signal includes a starting test signal as shown by the test_tx signal in Figure 7B , and since the smallest index value in the set of indexes corresponding to the first test signal is equal to 0, the starting test signal is a level signal whose signal flips at the falling edge of the first first clock cycle (i.e., X = 1) in the second time period. Optionally, when the N data sending moments are all at the rising edge of the first clock cycle, data may be alternately written into Y registers by the sending module at the N data sending moments in sequence, Y is an integer greater than 1 and less than N, at this time, the level signals whose signals flip at (N - L) first moments in the first test signal may include Y sub-test signals; wherein, the index values in a set of indexes corresponding to the first test signal are denoted as B K , and the index value B K is the K-th index value after sorting the index values in the set of indexes from small to large, K = 1, 2, 3,... N; the Z-th sub-test signal in the Y sub-test signals is denoted as AZ , Z = 1, 2, 3, …… Y; The Y-channel sub-test signals include: A 1 , A 2 , A 3 , …… A Y ; When the magnitude of K is equal to (R × Y + Z), the Z-th channel sub-test signal A Z flips at the falling edge of the B K -th first clock cycle in the second time period; R is a positive integer.

[0161] For example, as Figure 7B shown, when data is alternately written to two registers (i.e., Y = 2, hereinafter referred to as the odd register and the even register respectively) at 7 data transmission times (i.e., N = 7) in sequence through the transmission module, at this time, the level signal of the first test signal that flips at the (N - L) first times in sequence may include two-channel sub-test signals, as follows:

[0162] (1) The 1st channel sub-test signal A 1 (i.e., Figure 7B the test_odd signal in, at this time Z = 1). As Figure 7B shown by the test_odd signal in, since a set of indexes corresponding to the first test signal includes 7 index values, which are: 0, 2, 4, 6, 9, 11, 13; therefore, each index value in this set of indexes can be denoted as: B 1 = 0, B 2 = 2, B 3 = 4, B 4 = 6, B 5 = 9, B 6 = 11, B 7 = 13; Thus, the 1st channel sub-test signal A 1 can have 3 signal level flips in the second time period, as follows:

[0163] For the first time, when R = 1, at this time (R × Y + Z) i.e., (2 × R + 1) is equal to 3, as Figure 7B shown by the test_odd signal in, the 1st channel sub-test signal A 1 flips at the falling edge of the 4th (i.e., the B 3 -th) first clock cycle in the second time period;

[0164] For the second time, when R = 2, at this time (R × Y + Z) i.e., (2 × R + 1) is equal to 5, as Figure 7B shown by the test_odd signal in, the 1st channel sub-test signal A 1 flips at the falling edge of the 9th (i.e., the B 5 -th) first clock cycle in the second time period;

[0165] Thirdly, when R = 3, at this time (R×Y + Z), that is, (2×R + 1), is equal to 7, as shown by the test_odd signal in Figure 7B the first sub-test signal A flips at the falling edge of the 13th (i.e., the Bth 1 one) first clock cycle in the second time period. 7

[0166] (2) The second sub-test signal A 2 (that is, Figure 7B the test_even signal in, at this time Z = 2). As shown by the test_even signal in Figure 7B Based on the above, the second sub-test signal A 2 can have 2 signal level flips within this second time period, as follows:

[0167] First, when R = 1, at this time (R×Y + Z), that is, (2×R + 2), is equal to 4, as shown by the test_even signal in Figure 7B the second sub-test signal A flips at the falling edge of the 6th (i.e., the Bth 2 one) first clock cycle in the second time period; 4

[0168] Second, when R = 2, at this time (R×Y + Z), that is, (2×R + 2), is equal to 6, as shown by the test_even signal in Figure 7B the second sub-test signal A flips at the falling edge of the 11th (i.e., the Bth 2 one) first clock cycle in the second time period. 6

[0169] Based on the above, as shown by the test_odd signal and the test_even signal in Figure 7B the first sub-test signal A 1 and the second sub-test signal A 2 in the first test signal are level signals that flip signals in sequence at 5 first moments (i.e., (N - L) is equal to 5, where L = Y = 2).

[0170] In a possible implementation manner, these N data sending moments can also all be at the falling edge of the first clock cycle. At this time, step S602 can be executed with reference to the above exemplary embodiments and will not be elaborated here.

[0171] Step S603: Receive the multiple groups of first test signals in sequence through the receiving module, and determine whether the (N - L) first moments in the first test signal meet the first condition.

[0172] ​​​Specifically, the first condition includes that (N - L) first moments in the first test signal are successively before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock cycles.

[0173] Optionally, within the second time period, after detecting a signal level flip of the start test signal through the receiving module, the receiving module may alternately sample the Y sub-test signals in the first test signal at the (N - L) second moments in sequence to obtain test signal sampling values, and determine whether the test signal sampling values are equal to a preset reference value; when the test signal sampling values are equal to the reference value, the receiving module may determine that the (N - L) first moments satisfy the first condition.

[0174] For example, please refer to Figure 7C , Figure 7C which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 7C shown, within the second time period including 16 first clock cycles (i.e., M = 16), the transmitting module may send a group of first test signals to the receiving module based on a group of indexes including 13 index values (i.e., N = 13), and the first test signal may include three signals as follows:

[0175] (1) A start test signal, as shown by the test_tx signal in Figure 7C ;

[0176] (2) The first sub-test signal, as shown by the test_odd signal in Figure 7C ;

[0177] (3) The second sub-test signal, as shown by the test_even signal in Figure 7C .

[0178] As Figure 7C shown, after detecting a signal level flip of the start test signal through the receiving module, the receiving module may alternately sample the first sub-test signal and the second sub-test signal at 11 second moments (at this time (N - L) is equal to 11 and L = 2) in sequence, where the sampling edges (i.e., the second moments) of the receiving module may be respectively at 11 consecutive rising edges of the clock signal rx_clk (successively marked with serial numbers ), and when the receiving module performs this alternate sampling, it may start sampling from the first sub-test signal.

[0179] After that, 11 test signal sampling values may be obtained through the alternate sampling of the receiving module. Refer to Figure 7CAt the rising edge of the clock signal rx_clk, the positional relationship between the test_odd signal and the test_even signal yields 11 test signal sampling values. Arranged in chronological order, these 11 test signal sampling values are: 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0 (i.e., the binary sequence 110111011010). Then, the receiving module can compare these 11 test signal sampling values with a preset reference value. When the comparison result is inconsistent, the error_tmp signal is set to high level; when the comparison result is consistent, the error_tmp signal is set to low level. If all 11 test signal sampling values are equal to the corresponding reference values, it can be determined that these 11 first moments (i.e., the rising edges of the test_odd signal and the test_even signal) meet the first condition, and the pattern_error signal will remain low level. Otherwise, when the error_tmp signal is set to high level, the pattern_error signal will flip and remain high level.

[0180] Among them, the preset reference value can be, for example, Figure 7C the signal level value shown by the reference signal in Figure 7C . At this time, arranged in chronological order, the preset reference value includes 11 values, which are: 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1 (i.e., the binary sequence 00110011001); the preset reference value corresponds one by one to the test signal sampling values in chronological order. It should be noted that, as

[0181] Based on the above, as Figure 7C shown in

[0182] In a possible implementation, when the sending module alternately writes data to Y registers at the N data sending moments in sequence, after arranging (N - L) values in the preset reference value in chronological order, they can respectively correspond to the first (N - L) values in a cycle sequence; wherein, each cycle of the cycle sequence includes consecutive Y 0s and consecutive Y 1s, and L is equal to Y. For example, when the sending module alternately writes data to the parity register at the 13 data sending moments in sequence (i.e., when N = 13, Y = L = 2), the 11 values in the preset reference value, after being arranged in chronological order, are respectively: 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1; at this time, these 11 values respectively correspond to the first 11 values of the cycle sequence 001100110011... with a cycle of 0011.

[0183] Step S604: The receiving module sequentially sends multiple groups of feedback signals to the sending module.

[0184] Specifically, each group of feedback signals corresponds to a group of first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal meet the first condition. For example, the feedback signal can be the pattern_error signal as shown in Figure 7C wherein, the pattern_error signal is a level signal; since after the receiving module samples the first sub-test signal (i.e., the test_odd signal) in the first test signal and obtains a test signal sampling value of 1, which is not equal to the preset reference value 0 (i.e., the low level of the reference signal), the 11 first moments in the first test signal do not meet the first condition. At this time, the pattern_error signal is set from the initial low level to a high level (used to indicate that the 11 first moments in the first test signal do not meet the first condition), and remains at the high level unchanged during the second time period.

[0185] Optionally, the receiving module can send a group of corresponding feedback signals to the sending module based on a group of first test signals in each second time period, and the second time period includes M first clock cycles. For example, as shown in Figure 7A the receiving module can sequentially send 3 groups of feedback signals to the sending module based on 3 groups of first test signals, wherein the receiving module sends a group of feedback signals to the sending module every N second clock cycles (with a length equal to M first clock cycles, i.e., a second time period).

[0186] Optionally, in each second time period, the receiving module may send a corresponding set of feedback signals to the sending module based on the first test signals sent by the sending module in the previous second time period. The second time period includes M first clock cycles. For example, as Figure 7A shown, the receiving module may send feedback signal 1, feedback signal 2, and feedback signal 3 (3 sets of feedback signals) to the sending module based on test signal 1, test signal 2, and test signal 3 (3 sets of first test signals) respectively.

[0187] Step S605: The sending module sequentially receives the multiple sets of feedback signals and determines the N data sending moments based on the multiple sets of feedback signals.

[0188] Specifically, the sending module may determine a set of indexes based on the multiple sets of feedback signals and determine N first clock cycles within the first time period based on the set of indexes. The N data sending moments are respectively located in the N first clock cycles.

[0189] Optionally, the sending module may determine a target test signal from the multiple sets of first test signals based on the multiple sets of feedback signals. (N - L) first moments in the target test signal meet the first condition. Then, the sending module determines N first clock cycles within the first time period based on a set of indexes corresponding to the target test signal. The N data sending moments are respectively located in the N first clock cycles. For example, as Figure 7AAs shown, after the feedback signal 1, feedback signal 2, and feedback signal 3 (3 groups of feedback signals) are sequentially received by the sending module, if only the feedback signal 2 among the 3 groups of feedback signals indicates that (N - L) first moments in the corresponding test signal 2 (a group of first test signals) meet the first condition, then the test signal 2 can be determined as the target test signal. Subsequently, if a group of indexes corresponding to the test signal 2 includes the index values: 0, 2, 8 (3 index values when N = 3), and the 3 index values respectively correspond to the 1st, 3rd, and 9th first clock cycles in the first time period, then the sending module can determine that the 3 data sending moments are respectively located at the 1st, 3rd, and 9th first clock cycles in the first time period. Optionally, when C groups of feedback signals are sequentially received by the sending module, the sending module can determine whether each group of feedback signals in the C groups of feedback signals meets the second condition, where the second condition is that the group of feedback signals indicates that (N - L) first moments in the corresponding first test signal meet the first condition, and C is an integer greater than 1; when the 1st group of feedback signals in the C groups of feedback signals meets the second condition, the sending module can determine that the first test signal corresponding to the 1st group of feedback signals is the target test signal; when the Dth group of feedback signals in the C groups of feedback signals meets the second condition, and the previous (D - 1) groups of feedback signals in the C groups of feedback signals do not meet the second condition, the sending module can determine that the first test signal corresponding to the Dth group of feedback signals is the target test signal, and D is an integer greater than 1 and less than or equal to C. For example, as Figure 7A shown, when the feedback signal 1, feedback signal 2, and feedback signal 3 (3 groups of feedback signals) are sequentially received by the sending module, if the feedback signal 1 indicates that (N - L) first moments in the corresponding first test signal (i.e., test signal 1) meet the first condition, then the sending module can determine that the test signal 1 is the target test signal; if the feedback signal 3 indicates that (N - L) first moments in the corresponding first test signal (i.e., test signal 3) meet the first condition, and the feedback signal 1 and feedback signal 2 respectively indicate that (N - L) first moments in the corresponding first test signals (i.e., test signal 1 and test signal 2) do not meet the first condition, then the sending module can determine that the test signal 3 is the target test signal.

[0190] Optionally, when (C + 1) groups of first test signals are sequentially sent by the sending module and C groups of feedback signals are sequentially received by the sending module, it can be determined by the sending module whether each group of feedback signals in the C groups of feedback signals meets the second condition, where the second condition is that the group of feedback signals indicates that (N - L) first moments in the corresponding first test signal meet the first condition, and C is an integer greater than 1; when none of the C groups of feedback signals meet the second condition, it can be determined by the sending module that (N - L) first moments in the (C + 1)th group of first test signals in the (C + 1) groups of first test signals meet the first condition, and the (C + 1)th group of first test signals is determined to be the target test signal. For example, as Figure 7A shown, when test signal 1, test signal 2, test signal 3, and test signal 4 (4 groups of first test signals) are sequentially sent by the sending module and feedback signal 1, feedback signal 2, and feedback signal 3 (3 groups of feedback signals) are sequentially received by the sending module, if none of the 3 groups of feedback signals meet the second condition, it can be determined by the sending module that (N - L) first moments in the 4th group of first test signals (i.e., test signal 4) meet the first condition, and it can be determined by the sending module that test signal 4 is the target test signal.

[0191] Step S504: The sending module sequentially sends data to the receiving module at the N data sending moments.

[0192] Specifically, the N data sending moments are respectively located in N of the M consecutive first clock cycles, and the N data sending moments are all at the rising edge of the first clock cycle or all at the falling edge of the first clock cycle.

[0193] Optionally, the sending module can sequentially write data to the register at the N data sending moments, and the receiving module reads the data in the register, where the register is electrically connected to the receiving module.

[0194] Optionally, the sending module can sequentially write data to the register at the N data sending moments, where, at any two adjacent data sending moments, the sending module writes data to different registers, and the different registers are connected in parallel and are electrically connected to the receiving module.

[0195] Optionally, the sending module can sequentially write data to the register at the N data sending moments, where, in each first time period, the sending module initially writes data to the register at the first L of the N data sending moments. For example, when the sending module sequentially writes data to Y registers at the N data sending moments, L and Y are equal in size.

[0196] Step S505: When the length T1 of the first clock cycle is greater than or equal to the length T2 of the second clock cycle, the receiving module receives the second test signal sent by the sending module within a third time period.

[0197] Specifically, the third time period may include F second clock cycles, and the second test signal may include a level signal whose signal level flips at E third moments in sequence. For example, please refer to Figure 7D , Figure 7D which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 7D shown, when T1 is greater than or equal to T2, within the third time period, the receiving module can receive the second test signal sent by the sending module within E first clock cycles. The second test signal may include signals test_odd and test_even whose signal levels flip at the falling edges of E consecutive clock signals tx_clk (i.e., E third moments).

[0198] Step S506: The receiving module determines E data reception moments within a fourth time period based on the second test signal.

[0199] Specifically, the fourth time period may include F second clock cycles. Both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2.

[0200] Optionally, when the receiving module detects that the signal level of the second test signal flips in the Gth second clock cycle within the third time period, the receiving module can determine that the data reception moment is located in the Gth second clock cycle within the fourth time period, or determine that the data reception moment is located in the (G + 1)th second clock cycle within the fourth time period; G is an integer greater than or equal to 1 and less than F. For example, please refer to Figure 7E , Figure 7E which is a schematic diagram of the working principle of another data transmission method provided by an embodiment of the present application. As Figure 7E shown, if the receiving module receives the test signal 2 (i.e., the second test signal) sent by the sending module within the first F second clock cycles (i.e., the third time period) and detects that the test signal 2 flips in the Gth second clock cycle within the third time period, it can be determined that the data reception moment in the subsequent F second clock cycles (i.e., the fourth time period, at this time the sending module can simultaneously send the next set of second test signals, i.e., test signal 3) is located in the Gth or (G + 1)th second clock cycle within the fourth time period.

[0201] It should be noted that each third time period can correspond to a fourth time period. At the same time, any fourth time period can also be used as a new third time period, thus corresponding to a new fourth time period. For example, as Figure 7E shown, the third time period during which the receiving module receives the test signal 2 sent by the sending module corresponds to the fourth time period during which the receiving module receives data 2. At the same time, this fourth time period can be used as a new third time period for the receiving module to receive the test signal 3, thus corresponding to a new fourth time period for the receiving module to receive data 3.

[0202] Step S507: The receiving module sequentially receives the data sent by the sending module at the E data receiving moments.

[0203] Specifically, the E data receiving moments are respectively located in E of the F consecutive second clock cycles, and the E data receiving moments are all at the rising edge of the second clock cycle or all at the falling edge of the second clock cycle. For example, as Figure 7E shown, when the ratio of F to E is equal to the ratio of T1 to T2, the sending module can sequentially send E times of data (such as sending data 1) in E first clock cycles (the duration is equal to F second clock cycles), so that within the F second clock cycles (i.e., the fourth time period), the receiving module can sequentially receive the E times of data (such as receiving data 1) at the E data receiving moments.

[0204] Optionally, the sending module can write data to the register, and the receiving module sequentially reads the data in the register at the E data receiving moments, where the register is electrically connected to the receiving module.

[0205] Optionally, at any two adjacent data receiving moments, the sending module can write data to different registers, and the receiving module reads the data in the different registers, where the different registers are connected in parallel and are electrically connected to the receiving module.

[0206] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0207] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps may be able to adopt other sequences or be performed simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0208] In several embodiments provided in this application, it should be understood that the disclosed device or apparatus can be implemented in other ways. For example, the device embodiments or apparatus embodiments described above are merely illustrative. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices, apparatuses or units can be in electrical or other forms.

[0209] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0210] In addition, each functional unit in the embodiments of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0211] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server or a network device, etc., specifically, the processor in the computer device) to execute all or part of the steps of the above methods in the various embodiments of this application. Among them, the aforementioned storage medium can include: USB flash drives, mobile hard disks, magnetic disks, optical discs, read-only memory (ROM) or random access memory (RAM), etc., various media that can store program codes.

[0212] As described above, the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data interface device, characterized in that, the data interface device includes a sending module and a receiving module, wherein, the sending module is in a first clock domain, the first clock domain corresponds to a first clock period, the receiving module is in a second clock domain, the second clock domain corresponds to a second clock period, and the sending module is electrically connected to the receiving module; the sending module is used for: when the length T1 of the first clock period is less than the length T2 of the second clock period, determining N data sending moments within a first time period based on the ratio of T1 to T2, wherein, the first time period includes M first clock periods, both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2; sequentially sending data to the receiving module at the N data sending moments.

2. The device according to claim 1, characterized in that, the sending module is specifically used for: sequentially writing data into a register at the N data sending moments, the register is electrically connected to the receiving module; the receiving module is used for: reading the data in the register.

3. The device according to claim 2, characterized in that, the sending module is specifically used for: writing data into different registers at any two adjacent data sending moments, wherein, the different registers are connected in parallel and are electrically connected to the receiving module.

4. The device according to claim 2 or 3, characterized in that, the sending module is specifically used for: sequentially sending multiple groups of first test signals to the receiving module based on the ratio of T1 to T2, the first test signal includes a level signal that sequentially flips at (N - L) first moments, L is an integer greater than 0 and less than N; the receiving module is specifically used for: sequentially receiving the multiple groups of first test signals and determining whether the (N - L) first moments in the first test signal satisfy a first condition, wherein, the first condition includes that the (N - L) first moments are sequentially before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock periods; the sending module is specifically used for: receiving a feedback signal and determining the N data sending moments based on the feedback signal, wherein, the feedback signal is the response of the receiving module to the multiple groups of first test signals.

5. The method according to claim 4, characterized in that, the receiving module is specifically used for: sequentially sending multiple groups of feedback signals to the sending module, wherein, each group of feedback signals corresponds to a group of the first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal satisfy the first condition; the sending module is specifically used for: sequentially receiving the multiple groups of feedback signals and determining the N data sending moments based on the multiple groups of feedback signals.

6. The device according to claim 5, characterized in that, the sending module includes: An index generator, configured to generate multiple groups of indexes based on the ratio of T1 and T2, and any one group of the indexes includes N index values, where the N index values are all integers, and each index value corresponds to one of the first clock cycles within the first time period; A test signal generator, configured to sequentially send multiple groups of first test signals to the receiving module based on the multiple groups of indexes, where each group of the first test signals corresponds to one group of the indexes.

7. The apparatus according to claim 6, wherein, the sending module is specifically configured to: Based on the multiple groups of feedback signals, determine a target test signal from the multiple groups of first test signals, and the (N - L) first moments in the target test signal satisfy the first condition; Based on a group of the indexes corresponding to the target test signal, determine N first clock cycles within the first time period, where the N data sending moments are respectively located in the N first clock cycles.

8. The apparatus according to claim 6 or 7, wherein, the index generator is specifically configured to: When the ratio of T1 and T2 is equal to the ratio of N and M, generate a group of the indexes as an initial index; the index values in the initial index include all integers greater than (I × J - 1) and less than or equal to (I × J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N; Based on the initial index, generate the other groups of indexes in the multiple groups of indexes.

9. The apparatus according to claim 8, wherein, the index generator is specifically configured to: Generate one or more groups of the indexes based on the initial index as one or more groups of derivative indexes; where the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index values in the derivative indexes are equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, and Q is an integer greater than 0 and less than M.

10. The apparatus according to any one of claims 6 - 9, wherein, the N data sending moments are all at the rising edge of the first clock cycle; the test signal generator is specifically configured to: Send a corresponding group of the first test signals to the receiving module respectively based on each group of the indexes, and the first test signal includes a starting test signal, and the starting test signal includes a level signal whose signal flips at the falling edge of the Xth first clock cycle in the second time period; wherein, the second time period includes M first clock cycles; X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in the indexes corresponding to the first test signal.

11. The apparatus according to claim 10, wherein, the sending module is specifically configured to: Sequentially write data to Y registers at the N data sending moments, where Y is an integer greater than 1 and less than N; The level signals that sequentially flip signals at (N - L) first moments include Y sub-test signals; where the index value in the index corresponding to the first test signal is denoted as B K , and the index value B K is the Kth index value after sorting the index values in the index from smallest to largest, K = 1, 2, 3,..., N; the Zth sub-test signal in the Y sub-test signals is denoted as A Z , Z = 1, 2, 3,..., Y; the Y sub-test signals include: A 1 , A 2 , A 3 ,... A Y ; when the value of K is equal to (R × Y + Z), the Zth sub-test signal A Z flips at the falling edge of the B K th first clock cycle in the second time period; R is a positive integer.

12. The apparatus according to claim 11, wherein, the receiving module is specifically configured to: During the second time period, after detecting a signal level inversion of the starting test signal, the Y-channel sub-test signals are alternately sampled at the (N - L) second moments in sequence to obtain test signal sampling values, and it is determined whether the test signal sampling values are equal to a preset reference value; When the test signal sampling value is equal to the reference value, it is determined that the (N - L) first moments satisfy the first condition.

13. The apparatus according to any one of claims 1 - 12, wherein, the receiving module is further configured to: when the length T1 of the first clock period is greater than or equal to the length T2 of the second clock period, receive a second test signal sent by the sending module in a third time period, the third time period includes F second clock periods, and the second test signal includes a level signal whose signal level is inverted at E third moments in sequence; determine E data reception moments in a fourth time period based on the second test signal, where the fourth time period includes F second clock periods, both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2; receive the data sent by the sending module at the E data reception moments in sequence.

14. The apparatus according to claim 13, wherein, the receiving module is specifically configured to: when, in the G-th second clock period in the third time period, it is detected that the signal level of the second test signal is inverted, determine that the data reception moment is located in the G-th second clock period in the fourth time period, or determine that the data reception moment is located in the (G + 1)-th second clock period in the fourth time period; G is an integer greater than or equal to 1 and less than F.

15. A data transmission method, wherein, applied to a data interface device, the data interface device includes a sending module and a receiving module, wherein the sending module is in a first clock domain, the first clock domain corresponds to a first clock period, the receiving module is in a second clock domain, the second clock domain corresponds to a second clock period, and the sending module is electrically connected to the receiving module; the method includes: when the length T1 of the first clock period is less than the length T2 of the second clock period, determine, by the sending module, N data transmission moments in a first time period based on the ratio of T1 to T2, where the first time period includes M first clock periods, both N and M are positive integers, and the ratio of N to M is less than or equal to the ratio of T1 to T2; send data to the receiving module at the N data transmission moments in sequence by the sending module.

16. The method according to claim 15, wherein, the step of sending data to the receiving module at the N data transmission moments in sequence by the sending module includes: write data to a register at the N data transmission moments in sequence by the sending module, and read the data in the register by the receiving module, where the register is electrically connected to the receiving module.

17. The method according to claim 16, wherein, the step of writing data into the register by the sending module at the N data sending moments in sequence includes: writing data into different registers by the sending module at any two adjacent data sending moments, wherein the different registers are connected in parallel and electrically connected to the receiving module.

18. The method according to claim 16 or 17, wherein, the step of determining the N data sending moments within the first time period by the sending module based on the ratio of T1 and T2 includes: sending multiple groups of first test signals to the receiving module in sequence by the sending module based on the ratio of T1 and T2, the first test signals including level signals with signal flips occurring at (N - L) first moments in sequence, L being an integer greater than 0 and less than N; receiving the multiple groups of first test signals in sequence by the receiving module and determining whether the (N - L) first moments in the first test signals meet a first condition, wherein the first condition includes that the (N - L) first moments are respectively before (N - L) second moments, and the (N - L) second moments are respectively located in consecutive (N - L) second clock cycles; receiving a feedback signal by the sending module and determining the N data sending moments based on the feedback signal, wherein the feedback signal is the response of the receiving module to the multiple groups of first test signals.

19. The method according to claim 18, wherein, the step of receiving a feedback signal by the sending module and determining the N data sending moments based on the feedback signal includes: sending multiple groups of feedback signals to the sending module in sequence by the receiving module, wherein each group of feedback signals corresponds to a group of the first test signals, and the feedback signal is used to indicate whether the (N - L) first moments in the corresponding first test signal meet the first condition; receiving the multiple groups of feedback signals in sequence by the sending module and determining the N data sending moments based on the multiple groups of feedback signals.

20. The method according to claim 19, wherein, the step of sending multiple types of first test signals to the receiving module in sequence by the sending module based on the ratio of T1 and T2 includes: generating multiple groups of indexes by the sending module based on the ratio of T1 and T2, and any group of indexes includes N index values, wherein the N index values are all integers, and each index value corresponds to a first clock cycle within the first time period; sending multiple groups of first test signals to the receiving module in sequence by the sending module based on the multiple groups of indexes, wherein each group of first test signals corresponds to a group of indexes.

21. The method according to claim 20, wherein, the step of determining the N data sending moments based on the multiple groups of feedback signals includes: The sending module determines a target test signal from the multiple groups of first test signals based on the multiple groups of feedback signals, and the (N - L) first moments in the target test signal satisfy the first condition; The sending module determines N first clock cycles within the first time period based on a group of the indexes corresponding to the target test signal, where the N data sending moments are respectively located in the N first clock cycles.

22. The method according to claim 20 or 21, wherein, the generating, by the sending module, multiple groups of indexes based on the ratio of T1 to T2 includes: when the ratio of T1 to T2 is equal to the ratio of N to M, the sending module generates a group of the indexes as an initial index; the index values in the initial index include all integers greater than (I×J - 1) and less than or equal to (I×J), where I is an integer greater than or equal to 0 and less than N, and J is equal to M divided by N; the sending module generates the other groups of indexes in the multiple groups of indexes based on the initial index.

23. The method according to claim 22, wherein, the generating, by the sending module, the other groups of indexes in the multiple groups of indexes based on the initial index includes: the sending module generates one or more groups of the indexes as one or more groups of derivative indexes based on the initial index; wherein, the index values in the derivative indexes are all integers greater than or equal to 0 and less than M, and the index value in the derivative index is equal to (P - Q) or equal to (P - Q + M), P is the index value in the initial index, and Q is an integer greater than 0 and less than M.

24. The method according to any one of claims 20 - 23, wherein, the N data sending moments are all at the rising edge of the first clock cycle; the sending module sequentially sends multiple groups of first test signals to the receiving module based on the multiple groups of indexes, including: the sending module respectively sends a group of corresponding first test signals to the receiving module based on each group of the indexes, the first test signal includes a starting test signal, and the starting test signal includes a level signal whose signal flips at the falling edge of the Xth first clock cycle in the second time period; wherein, the second time period includes M first clock cycles; X is an integer greater than or equal to 1 and less than M, and (X - 1) is equal to the smallest index value in the index corresponding to the first test signal.

25. The method according to claim 24, wherein, the writing, by the sending module, data into registers at the N data sending moments in sequence includes: the sending module alternately writes data into Y registers at the N data sending moments in sequence, Y is an integer greater than 1 and less than N; The level signals that sequentially flip signals at (N - L) first moments include Y sub-test signals; wherein, the index value in the index corresponding to the first test signal is denoted as B K , and the index value B K is the Kth index value after sorting the index values in the index from small to large, K = 1, 2, 3,..., N; the Zth sub-test signal in the Y sub-test signals is denoted as A Z , Z = 1, 2, 3,..., Y; the Y sub-test signals include: A 1 , A 2 , A 3 ,... A Y ; when the value of K is equal to (R × Y + Z), the Zth sub-test signal A Z flips at the falling edge of the B K th first clock cycle in the second time period; R is a positive integer.

26. The method according to claim 25, wherein, the determining whether the (N - L) first moments in the first test signal satisfy the first condition includes: During the second time period, after detecting a signal level inversion of the start test signal through the receiving module, the receiving module alternately samples the Y-channel sub-test signals at the (N - L) second moments in sequence to obtain test signal sampling values, and determines whether the test signal sampling values are equal to a preset reference value; When the test signal sampling values are equal to the reference value, the receiving module determines that the (N - L) first moments satisfy the first condition.

27. The method according to any one of claims 15 - 26, wherein, the method further includes: When the length T1 of the first clock period is greater than or equal to the length T2 of the second clock period, the receiving module receives a second test signal sent by the sending module during a third time period, the third time period includes F second clock periods, and the second test signal includes a level signal whose signal level is inverted at E third moments in sequence; The receiving module determines E data reception moments within a fourth time period based on the second test signal, wherein the fourth time period includes F second clock periods, both E and F are positive integers, and the ratio of F to E is greater than or equal to the ratio of T1 to T2; The receiving module receives the data sent by the sending module at the E data reception moments in sequence.

28. The method according to claim 27, wherein, the determining of the E data reception moments within the fourth time period based on the second test signal includes: When the receiving module detects a signal level inversion of the second test signal during the G-th second clock period in the third time period, the receiving module determines that the data reception moment is located in the G-th second clock period within the fourth time period, or determines that the data reception moment is located in the (G + 1)-th second clock period within the fourth time period; G is an integer greater than or equal to 1 and less than F.

29. A computer program product, comprising a computer program, wherein, when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 15 - 28 are implemented.

30. A computer-readable storage medium, wherein, the computer-readable storage medium is used to store a computer program, and when the computer program is executed, the method according to any one of claims 15 - 28 is executed.

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