Method and device for rapidly judging VT change trend, computer equipment and storage medium

Abstract

The invention relates to the technical field of NAND FLASH, and discloses a method and device for quickly judging a VT change trend, computer equipment and a storage medium. The method comprises the following steps of: reading data of a plurality of pages in a word line, and longitudinally obtaining a pattern data length; counting the number corresponding to the length of the pattern data, and recording the number as RN; comparing the RN with a set value to obtain a comparison result; and according to the comparison result, judging the variation trend of the VT so as to obtain a corresponding conclusion. By implementing the method provided by the invention, the data of the plurality of pages in the word line is read, and the length of the pattern data is longitudinally analyzed, so that the change characteristics of the data distribution of the storage unit in the NAND FLASH can be quickly captured, the speed of judging the VT change trend is obviously improved, and the time cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of NAND FLASH, and more particularly to a method, device, computer device and storage medium for quickly determining the VT change trend. Background Art

[0002] As a widely used non-volatile storage medium, NAND FLASH plays a crucial role in the field of data storage. However, during its complex working process, the performance and data stability of NAND FLASH are vulnerable to various external factors. Among them, temperature and data retention time are two of the most significant factors. The combined effect of these factors will cause the threshold voltage (VT) of the internal storage units of NAND FLASH to drift, thereby posing a challenge to the accurate reading of data.

[0003] The threshold voltage VT is a key parameter for determining whether the data stored in the NAND FLASH storage unit is "0" or "1". Under normal circumstances, by detecting the value of VT, the data state represented by the storage unit can be accurately distinguished. However, when VT drifts due to external factors, the original determination logic based on the VT value may fail, resulting in the inability to accurately identify the state of the storage unit when reading data, thereby causing the problem of read data failure.

[0004] Read data failure not only means the direct loss of data, but also triggers the error correction process of the storage system. The error correction process usually relies on technical means such as error correction code (ECC), and attempts to recover the damaged data through algorithms. Although these technologies have improved the data recovery ability to a certain extent, they also bring additional time overhead. The introduction of the error correction process increases the overall data reading time, has a negative impact on the reading performance of the storage system, and may lead to a decline in service quality (QOS), such as the deterioration of service indicators such as the inability to accurately complete data reading within the specified time.

[0005] To address the above problems, the manufacturers of NAND FLASH have put forward a key requirement: the data "0" and "1" stored in NAND FLASH should be relatively evenly distributed. This balanced data distribution state is crucial for maintaining the performance stability of the storage unit. It helps to reduce problems such as abnormal electrical characteristics caused by uneven data distribution, thereby improving the reliability and durability of the storage unit.

[0006] In response to the challenges brought by data distribution and VT drift in NAND FLASH, the industry usually adopts the following two methods to deal with them:

[0007] Direct background scanning method without VT change trend determination: This method does not pre-determine the change trend of VT, but directly determines the optimal read voltage through background scanning. Although this method simplifies the operation process to a certain extent, its efficiency and accuracy may be limited due to the lack of targeted adjustment.

[0008] Method of adding additional read operations: To more precisely adjust the read voltage, another approach is to add additional read operations during the reading process. These additional read operations are used to more carefully monitor the change of VT, so as to more accurately adjust the read voltage to adapt to the current data state. However, although this method improves the accuracy of data reading, it also increases the operation complexity and time cost.

[0009] In summary, NAND FLASH faces many challenges during data storage and reading, especially in data distribution and threshold voltage drift. To overcome these challenges, the industry continuously explores and optimizes relevant technical means to improve the performance and stability of the storage system. Summary of the Invention

[0010] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, device, equipment and medium for quickly determining the change trend of VT.

[0011] To solve the above technical problems, the present invention adopts the following technical solutions:

[0012] In the first aspect, a method for quickly determining the change trend of VT is provided, including:

[0013] Read the data of multiple pages in the word line to obtain the pattern data length longitudinally;

[0014] Count the number corresponding to the pattern data length, denoted as RN;

[0015] Compare RN with a set value to obtain a comparison result;

[0016] According to the comparison result, determine the change trend of VT to obtain a corresponding conclusion.

[0017] In the second aspect, a device for quickly determining the change trend of VT is provided, including:

[0018] A reading and obtaining unit for reading the data of multiple pages in the word line to obtain the pattern data length longitudinally;

[0019] A statistical unit for counting the number corresponding to the pattern data length, denoted as RN;

[0020] A comparison unit for comparing RN with a set value to obtain a comparison result;

[0021] A determination unit, configured to determine the change trend of VT according to the comparison result, so as to obtain a corresponding conclusion.

[0022] In a third aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for quickly determining the change trend of VT are implemented.

[0023] In a fourth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the method for quickly determining the change trend of VT are implemented.

[0024] The method for quickly determining the change trend of VT can quickly capture the change characteristics of the data distribution in the NAND FLASH internal storage unit by reading the data of multiple pages in the word line and longitudinally analyzing the pattern data length. This analysis method based on data pattern significantly improves the speed of determining the change trend of VT compared with the traditional direct measurement or scanning method, and reduces the time cost. In addition, by using the phenomenon of relatively uniform distribution of NAND FLASH data, by counting the number (RN) corresponding to the pattern data length and comparing it with a set value, the change trend of VT can be determined more accurately. This method not only considers the state of a single storage unit, but also grasps the change law of data distribution as a whole, thereby improving the accuracy of determination. An accurate determination of the change trend of VT helps the storage system to timely adjust the read voltage to adapt to the change of the storage unit state, which can not only reduce the probability of read data failure, but also avoid unnecessary error correction processes, thereby optimizing the overall performance of the storage system and improving the data read speed and stability.

[0025] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a flowchart of the method for quickly determining the change trend of VT provided by the embodiment of the present invention;

[0028] Figure 2 It is a schematic diagram of the application scenario of the TLC Gray code provided by the embodiment of the present invention;

[0029] Figure 3 Schematic diagram of the application scenario of page data provided by the embodiments of the present invention;

[0030] Figure 4 Schematic block diagram of the device for quickly determining the VT change trend provided by the embodiments of the present invention;

[0031] Figure 5 Schematic diagram of the structure of the computer device in the embodiments of the present invention. Specific embodiments

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0033] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0034] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0035] It should be further understood that the term "and / or" used in this specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0036] Please refer to Figures 1 to 3 In the specific embodiments shown, the present invention discloses a method for quickly determining the VT change trend, including the following steps:

[0037] S110, read the data of multiple pages within the word line to obtain the pattern data length longitudinally;

[0038] Refer to Figure 2 and Figure 3 As shown, there are differences in the VT division of MLC / TLC / QLC / PLC of different NAND manufacturers, Figure 2Taking the TLC gray code of 2-3-2 as an example to illustrate the implementation method of the present invention, but the present invention is not limited to TLC. The low page is distinguished by A and E; the middle page uses B, D, F; the high page uses C and G.

[0039] In the field of NAND flash memory, there are multiple different manufacturers. When different manufacturers produce flash memories with multi-level storage cell structures, there are differences in the threshold voltage (VT) division for multi-level cells (MLC, TLC, QLC, PLC, etc.). This means that different manufacturers, relying on their respective technologies and design concepts, will have different VT ranges for storing different data states in storage cells.

[0040] Here, the case where the gray code of TLC (Triple-Level Cell, that is, three-level storage cell) is 2-3-2 is taken as an example to elaborate on the implementation method involved in the present invention. The gray code is a special coding method and is widely used in fields such as digital circuits. Its characteristic is that only one binary digit changes between adjacent coding values. Using the gray code in NAND flash memory helps reduce errors caused by factors such as voltage fluctuations during data reading and writing. Each storage cell of TLC can store 3 bits of binary data, and the 2-3-2 representation is a division or configuration related to the gray code of different bits. And it is particularly emphasized that the method proposed in the present invention is not limited to the TLC storage structure, which means that the related principles, implementation ideas, etc. of the invention can also be applied to other multi-level storage cell structures, such as MLC (Multi-Level Cell, two-level storage cell, each storage cell can store 2 bits of binary data), QLC (Quad-Level Cell, four-level storage cell, each storage cell can store 4 bits of binary data), PLC (Penta-Level Cell, five-level storage cell, each storage cell can store 5 bits of binary data), etc.

[0041] Then it further explains the method of distinguishing data under the TLC storage structure for different "pages" (which can be simply understood as a logical unit for flash memory to store data, similar to a page of a book, a small partition for storing data, and different pages can store different data blocks). Specifically, low pages (referring to pages that are relatively low in the storage hierarchy or a certain logical order) are distinguished by "A" and "E", that is, using these two identifiers or some characteristics related to them to define different data situations in low pages; middle pages (pages in the middle level) use "B", "D", and "F" to distinguish the data therein; high pages (pages in a relatively high position) use "C" and "G" to perform corresponding data distinction operations. This distinction method may be closely related to the threshold voltage of the storage unit, data encoding, and subsequent data processing logic, etc. Through such a distinction, it helps to more accurately achieve the goals of data processing, determination, and corresponding function implementation involved in the present invention.

[0042] Among them, the definitions of professional terms are as follows:

[0043] NAND FLASH: A non-volatile flash memory storage technology. Based on the flash memory storage principle, with floating-gate transistors as the basic storage units, it represents data "0" or "1" by controlling the threshold voltage of the transistors, and has characteristics such as high storage density and low cost. It is widely used in storage devices such as solid-state drives (SSDs), USB flash drives, and memory cards.

[0044] Data retention: Data retention refers to the ability of a storage medium to correctly retain the stored data after a certain period of time. For NAND FLASH, over time and due to various environmental factors, the stored data may be lost or incorrect. Measuring how long it can reliably store data is an embodiment of the data retention characteristic.

[0045] QOS (Quality of Service): Quality of Service refers to the performance of a system or service in meeting user requirements, covering multiple dimensions of indicators such as response time, data accuracy, and availability. In the storage field, the speed, accuracy of reading data, and whether it can be read within the specified time all belong to the category of storage service quality.

[0046] Word line: A word line is a type of connection in an integrated circuit memory structure (such as a NAND flash memory array). It extends horizontally (in the typical structural schematic angle), connecting multiple memory cells. When performing operations such as data reading and writing, by applying corresponding electrical signals to the word line, the corresponding row of memory cells can be selected for operation, playing a role similar to address selection and control.

[0047] Pattern: In this context, a pattern refers to a specific arrangement form of data, that is, a form in which the data stored in the memory cells in NAND flash is organized in a certain order. Different arrangement forms may reflect different states or characteristics of the memory cells. For example, different patterns may be associated with different situations of threshold voltages.

[0048] MLC (Multi-Level Cell): A multi-level cell is a type of memory cell in flash memory technology. Each memory cell can store 2 bits of binary data. Compared with traditional single-level memory cells (which can only store 1 bit of binary data, representing either "0" or "1"), it can represent more data states in a single memory cell by more finely dividing the threshold voltage range, thereby increasing the storage density. However, it also increases the complexity of read / write control and the dependence on error correction and other technologies to a certain extent.

[0049] TLC (Triple-Level Cell): A triple-level cell can store 3 bits of binary data per memory cell. Similarly, by making multi-level divisions of the threshold voltage, it achieves a higher storage density than MLC. However, it faces more challenges in terms of read / write performance and data retention ability compared to single-level memory cells. Therefore, more complex control circuits and error correction mechanisms are required to ensure its normal operation.

[0050] QLC (Quad-Level Cell): A quad-level cell can store 4 bits of binary data per memory cell, further enhancing the storage density. It is a commonly used type of memory cell in large-capacity storage application scenarios. However, as the number of stored bits increases, its requirements for storage environment, read / write speed, error correction ability, etc. become more stringent.

[0051] PLC (Penta-Level Cell): A penta-level cell is a relatively new type of memory cell with a higher storage density. Each memory cell can store 5 bits of binary data. However, due to more storage layers, technical challenges such as data accuracy and read / write stability are more prominent. Currently, it is in a stage of continuous development and improvement.

[0052] VT (Threshold Voltage): In semiconductor devices (such as memory cell transistors in NAND FLASH), the threshold voltage is the critical voltage value that causes the device to start conducting or turning off. For NAND FLASH memory cells, when the applied control voltage is higher than the threshold voltage, the transistor exhibits a conductive state corresponding to storing a data value (such as "1"), and when it is lower than the threshold voltage, it exhibits another conductive state corresponding to another data value (such as "0"). It is a key electrical parameter for determining the data state of memory cells. In the memory cells of NAND flash, by setting different threshold voltage ranges, the memory cells can exhibit different conductive states, thereby corresponding to different binary data. For example, in TLC, different VT ranges can respectively correspond to different 3-bit binary data combinations such as 000, 001, 010, etc.

[0053] gray code: Also known as cyclic binary code or reflected binary code, it is a special digital coding method. Its characteristic is that only one binary digit changes between two adjacent codes. The advantage of applying gray code in NAND flash is that when the threshold voltage changes slightly due to various factors (such as temperature, process technology fluctuations, etc.), compared with ordinary binary coding, using gray code can reduce the probability of data error conversion and improve the reliability of data reading and writing.

[0054] page: A logical partition unit in flash memory storage, similar to the pages in a book, is a relatively independent small area for storing data. Multiple pages together constitute the entire storage capacity of the flash memory. Different pages can store different data blocks, and there are corresponding logics and processes for read and write operations, address management, and data organization.

[0055] In Figure 3 data is arranged horizontally, and vertically is the pattern. Taking this Figure 3 as an example, the count of the pattern "111" is 4. However, Figure 3 this is only an example, and the actual data volume can be larger.

[0056] Combining Figure 2 and Figure 3 , Figure 2 it is TLC NAND. One cell stores 3 bits of information, which is divided into 8 parts. Among them, the 3-bit information belongs to the low, medium, and high 3 pages respectively. The partitioning method for each medium is different. Figure 2 The example is the mainstream 2-3-3 partitioning. For each of these 8 parts, it is fixed for each page and combined into a fixed pattern value. Vertically, it can be considered as the pattern value. Figure 2It is arranged in low, medium, and high order. If the page order changes, the pattern value will change accordingly. However, no matter how it changes, there are always these 8 states, that is, 3-bit information. Figure 3 Used for explanation. Three pieces of data are read out (TLC has 3 pieces), and the vertical direction represents the pattern value.

[0057] In a storage system (such as NAND FLASH), storage cells represent different binary data combinations through different threshold voltage (VT) ranges. These different binary data combinations (such as "000", "001", etc.) are different patterns, which represent different data states. Multiple pages together constitute the storage capacity of the entire flash memory. Different pages can store different data blocks, and there are corresponding logics and processes in terms of read / write operations, address management, and data organization. A page is further divided into low, medium, and high parts, and different parts have different differentiation identifiers and corresponding data processing characteristics. For example, as mentioned above, the low page is differentiated by A and E; the middle page is differentiated by B, D, and F; the high page uses C and G to distinguish data conditions.

[0058] Among them, the relationship between the pattern and the page is analyzed as follows:

[0059] Association at the data organization level: In a storage system, each bit of data ultimately needs to be stored in the logical unit of a page, and different patterns represent different combinations of bit states (e.g., the 8 patterns corresponding to 3-bit binary data in a TLC storage unit). The low, middle, and high divisions of a page provide a way to classify and organize data at a larger logical unit level. The pattern corresponding to each bit will be regularly assigned to different low, middle, and high regions of the page according to the data state it represents and the VT region of the corresponding storage unit. For example, perhaps the data states represented by certain specific patterns are more suitable for storage in the low page region due to factors such as their electrical characteristics, read / write frequency requirements, or relevance to other data, while the patterns corresponding to others are arranged in the middle or high page regions to achieve a more reasonable and orderly organization of data within the page, facilitating subsequent read / write and management operations. From the perspective of data distribution uniformity, it is expected that different patterns can be relatively evenly distributed throughout the storage area according to the data uniformity principle. However, when it comes to the low, middle, and high divisions of a page, this uniformity will be correspondingly reflected within each part. For example, different patterns within the low page region will also be distributed as evenly as possible according to a certain ratio and rules to ensure the stability and read / write efficiency of the data in this region. The same applies to the middle and high page regions, and there may be a certain connection and complementary relationship in the distribution of data patterns between different regions, jointly maintaining the rationality of data distribution throughout the page and even the entire storage system.

[0060] Association at the read-write operation level: During a read operation, first, relevant information such as the address is used to locate the corresponding page, and then the specific area where the target data is located is searched according to the low, middle, and high divisions of the page. Pages in different areas may involve different read orders, voltage control strategies, etc. when being read. Moreover, for each bit's corresponding pattern, due to the different page areas it is in, the difficulty of reading it, and the read rules it follows will also vary. For example, data in the low page area may be read first or in a relatively simple and direct way, and the reading of the corresponding pattern will also be carried out according to this setting; the reading of data in the high page area may have a more complex process, and the reading of the pattern in this area will also be coordinated with the corresponding complex operations. This makes the arrangement of the pattern and the low, middle, and high divisions of the page interact and be associated with each other during the read operation. In terms of the write operation, when new data (i.e., a new pattern) is to be written, the system will determine which specific page area to write the bit data corresponding to the new pattern based on factors such as the low, middle, and high divisions of the page, the current data storage status and data distribution in each area, etc. For example, if there is enough free space in the low page area and the pattern of the data to be written currently has a strong correlation with the existing data in this area, then it may be preferentially written into the low page area. In this way, the division of the page affects the writing position of the pattern, and thus affects the arrangement of the pattern in the entire storage system.

[0061] Association at the functional cooperation and overall performance guarantee level: The low, middle, and high divisions of the page and the arrangement of each bit's corresponding pattern work together to guarantee the overall performance of the storage system. The division of the page helps to optimize the address management of the storage system and improve the read-write speed (such as by partitioning and storing data of different importance and different read-write frequencies), while the reasonable arrangement of the pattern ensures the stability, accuracy of data storage, and the realization of functions such as error correction based on principles such as the electrical characteristics of the data and data uniformity. The two cooperate with each other, enabling the storage system to operate efficiently and stably. For example, while meeting the requirements of quickly reading and writing common data (specific pattern data stored in appropriate areas such as the low page), it can also properly handle relatively complex and infrequently used data (corresponding pattern data stored in other page areas), maintaining the performance balance of the entire storage system.

[0062] Generally speaking, the arrangement of the pattern corresponding to each bit is closely related to the low, middle, and high divisions of the page in terms of data organization, read and write operations, and overall performance guarantee. They cooperate with each other to jointly serve the efficient and stable operation of the storage system.

[0063] Specifically, first, select one or more target word lines from the NAND FLASH storage array for read operations. The selection of the target word line can be based on the actual needs or preset strategies of the storage system. Sequentially read multiple pages within the selected word line. Each page contains a certain number of memory cells, and the data in these memory cells is stored in units of bits. During the read process, the data status (such as "0" or "1") of each memory cell can be recorded. Vertically analyze the data of the multiple pages read, that is, observe the change law of the data status along the direction of the word line. By comparing the data status between adjacent memory cells or adjacent pages, data patterns can be identified. The data pattern may be manifested as continuous identical data status (such as continuous "0" or "1"), or as a specific combination of data status. For each identified data pattern, calculate its length. The length of the data pattern refers to the number of memory cells with continuous identical data status in the pattern. By statistically analyzing the data patterns of different lengths, the characteristics of data distribution can be further analyzed.

[0064] By implementing the above-mentioned operation of reading the data of multiple pages within the word line to longitudinally obtain the pattern data length, the following technical effects are brought:

[0065] Improve the accuracy of data pattern recognition: By vertically analyzing the data of multiple pages, the change law of the data status can be more comprehensively captured, so as to more accurately identify the data pattern, which helps the subsequent determination of the VT change trend.

[0066] Enhance the sensitivity to the VT change trend: The length of the data pattern is closely related to the threshold voltage (VT) status of the memory cell; when the VT changes, the length of the data pattern will also change accordingly; therefore, by calculating and analyzing the length of the data pattern, the change trend of the VT can be captured more sensitively.

[0067] Optimize the read strategy of the storage system: Based on the analysis of the data pattern length, the storage system can dynamically adjust the read voltage and read strategy to adapt to the change of the memory cell status, which helps to improve the accuracy and stability of data reading and reduce the probability of read data failure.

[0068] Improve the overall performance of the storage system: By quickly and accurately determining the VT change trend and taking corresponding adjustment measures, the storage system can manage storage resources more effectively, improve data read / write speed and storage density, which helps to improve the overall performance of the storage system and user experience.

[0069] S120, count the number corresponding to the pattern data length, denoted as RN;

[0070] Specifically, the data length is denoted as max_count_bit, and RN is max_count_bit / the number of VT regions.

[0071] Among them, when reading the same data of multiple pages of the target word line, still taking Figure 2 as an example, for TLC NAND, one word line has 3 pages. Suppose one word line has 18 * 1028 * 8 cells, and one cell stores 3 bits of information, then the size of each page is 18 * 1028 * 8 * 3 bits. The data length here refers to the data at the same position belonging to three pages. For example, the starting address of the low page read is at an offset of 4KB, the data length is 4KB, and for the other 2 pages, there must be the same offset and the same data length. The offset must be the same, and the data length must also be consistent. That is to say, the data length here is the data of the same position and equal length belonging to 3 pages of the target word line.

[0072] The data length can vary according to actual needs, and the data length is denoted as max_count_bit. According to the data uniformity principle, the theoretical number of each pattern: base = max_count_bit divided by the number of VT regions. The number of VT regions is 2 for SLC, 4 for MLC, 8 for TLC, and 16 for QLC. Refer to Figure 2 and Figure 3, the present invention takes TLC as an example. That is to say, vertically, it is obtained that VT1 corresponds to pattern1 "111"; VT2 corresponds to pattern2 "011"; VT3 corresponds to pattern3 "001"; VT4 corresponds to pattern4 "000"; VT5 corresponds to pattern5 "010"; VT6 corresponds to pattern6 "110"; VT7 corresponds to pattern7 "100"; VT8 corresponds to pattern8 "101". Then, count the quantities of pattern1, pattern2, pattern3, pattern4, pattern5, pattern6, pattern7, and pattern8 respectively, and record them as R1, R2, R3, R4, R5, R6, R7, and R8 respectively.

[0073] That is to say, according to the actual requirements or preset strategies of the storage system, determine the data length to be analyzed. Taking TLC NAND FLASH as an example, assume that a word line contains 18 * 1028 * 8 memory cells, and each memory cell stores 3 bit information. Then the size of each page is 18 * 1028 * 8 * 3 bit. In this case, a suitable data length can be selected for analysis, such as 4KB. It should be noted that the data length should span multiple pages, and the positions of these pages in the word line should be the same, that is, the offsets must be consistent. For example, if the starting address of the low page is selected at an offset of 4KB, and the data length is 4KB, then the other two pages (the middle page and the high page) must also start from the same offset, and the data length must also be 4KB.

[0074] According to the type of NAND FLASH (such as TLC), determine the number of VT (threshold voltage) regions. For TLC NAND FLASH, there are usually 8 VT regions, and each region corresponds to a specific data pattern. Refer to Figure 2 and Figure 3 , a specific data pattern can be assigned to each VT region. For example, VT1 corresponds to pattern1 "111", VT2 corresponds to pattern2 "011", and so on until VT8 corresponds to pattern8 "101".

[0075] After determining the data length and pattern, start reading the data of multiple pages within the target word line and analyze these data vertically to identify each pattern. For each identified pattern, count the number of times it appears, and record these counts as R1, R2, R3, ..., RN respectively, where N is the number of VT regions (for TLC NAND FLASH, N = 8). It should be noted that RN here is actually the normalized value obtained by dividing the ratio of the number of each pattern to the total data length (max_count_bit) by the number of VT regions. However, for convenience, the number of each pattern can be directly counted and normalized as needed in subsequent analysis. According to the data uniformity principle, the theoretical number of each pattern can be calculated. This theoretical number is obtained by dividing the total data length (max_count_bit) by the number of VT regions. However, in practical applications, due to the influence of various factors (such as data writing mode, storage cell aging, etc.), the actually counted number of patterns may differ from the theoretical number.

[0076] S130, compare RN with the set value to obtain the comparison result;

[0077] Specifically, the set value is base, base = max_count_bit, and the comparison result includes equal to, less than, or greater than. Among them, the comparison rule is to compare the RN value of each pattern with max_count_bit to determine whether RN is equal to, less than, or greater than max_count_bit. It should be noted that since RN is the normalized quantity, directly comparing it with max_count_bit may not be very appropriate. In practical applications, a threshold based on max_count_bit may need to be introduced for comparison. For example, a threshold can be set as a certain percentage (such as 1%, 10%, etc.) of max_count_bit, and then RN is compared with this threshold. According to the comparison rule, perform the comparison operation on the RN value of each pattern. If RN is equal to the set value (or threshold), record it as "equal to"; if RN is less than the set value (or threshold), record it as "less than"; if RN is greater than the set value (or threshold), record it as "greater than". Finally, analyze the performance status of the storage cell according to the comparison result. If the RN value of a certain pattern is much lower than the threshold, it may mean that there is an abnormality in the VT region corresponding to this pattern or the performance of the storage cell has decreased. At this time, corresponding measures can be taken for further analysis and processing.

[0078] S140, according to the comparison result, determine the change trend of VT to obtain the corresponding conclusion.

[0079] Specifically, the corresponding conclusions include that the optimal voltage is at the current position, the optimal voltage is to the left of the current position, or the optimal voltage is to the right of the current position.

[0080] Among them, the determination process of VT1 is as follows:

[0081] Case 1: If the corresponding R1 of pattern1 is equal to base, it indicates that "A" is appropriate, and the optimal voltage corresponding to "A" is at the current position;

[0082] Case 2: If the corresponding R1 of pattern1 is less than base, it indicates that VT1 has shifted to the right, and the optimal voltage corresponding to "A" is to the right of the current position; the difference DIFF1 = base – R1;

[0083] Case 3: If the corresponding R1 of pattern1 is greater than base, it indicates that VT2 has shifted to the left, and the optimal voltage corresponding to "A" is to the left of the current position.

[0084] The determination process of VT2 depends on the determination situation of VT1:

[0085] Case 4: VT1 satisfies Case 1 (VT1 has not moved). If the corresponding R2 of pattern2 is equal to base, the optimal voltage corresponding to "B" is at the current position, and VT2 has not changed;

[0086] Case 5: VT1 satisfies Case 1 (VT1 has not moved). If the corresponding R2 of pattern2 is less than base, it indicates that VT2 has shifted to the right, and the optimal voltage corresponding to "B" is to the right of the current position;

[0087] Case 6: VT1 satisfies Case 1 (VT1 has not moved). If the corresponding R2 of pattern2 is greater than base, it indicates that VT2 has shifted to the left, and the optimal voltage corresponding to "B" is to the left of the current position;

[0088] Case 7: VT1 satisfies Case 2 (VT1 has shifted to the right). If the corresponding R2 of pattern2 is equal to base, it indicates that VT2 has shifted to the right, and the optimal voltage corresponding to "B" is to the right of the current position;

[0089] Case 8: VT1 satisfies Case 2 (VT1 has shifted to the right). If the corresponding R2 of pattern2 is less than base, it indicates that VT2 has shifted to the left, and the optimal voltage corresponding to "B" is to the left of the current position;

[0090] Case 9: VT1 satisfies Case 2 (VT1 shifts right). If the corresponding R2 of pattern2 is greater than base, calculate R2 minus base minus DIFF1. If it is greater than 0, it means VT2 shifts left, and the optimal voltage corresponding to "B" is on the left side of the current position; if it is less than 0, it means VT2 shifts right, and the optimal voltage corresponding to "B" is on the right side of the current position; if it is greater than 0, it means VT2 shifts left, and the optimal voltage corresponding to "B" is on the left side of the current position; if it is equal to 0, it means the optimal voltage corresponding to "B" is at the current position.

[0091] Case 10: VT1 satisfies Case 3 (VT2 shifts left). If the corresponding R2 of pattern2 is equal to base, it means VT2 shifts left, and the optimal voltage corresponding to "B" is on the left side of the current position.

[0092] Case 11: VT1 satisfies Case 3 (VT2 shifts left). If the corresponding R2 of pattern2 is less than base, it is the same as in Case 3, normal situation.

[0093] Case 12: VT1 satisfies Case 3 (VT2 shifts left). If the corresponding R2 of pattern2 is greater than base, it means VT2 shifts left and the shifting amplitude is larger, and the optimal voltage corresponding to "B" is on the left side of the current position.

[0094] The determination of VT3 depends on the determination situation of VT2:

[0095] Divide the determination situation of VT2 into three cases: unchanged, shifted left, shifted right. Similar to the determination process of VT2, the situation of VT3 can be determined.

[0096] The determination of VT4 depends on the determination situation of VT3. Similar to the determination process of VT2, the situation of VT4 can be determined.

[0097] The determination of VT5 depends on the determination situation of VT4. Similar to the determination process of VT2, the situation of VT5 can be determined.

[0098] The determination of VT6 depends on the determination situation of VT5. Similar to the determination process of VT2, the situation of VT6 can be determined.

[0099] The determination of VT7 depends on the determination situation of VT6. Similar to the determination process of VT2, the situation of VT7 can be determined.

[0100] The determination of VT8 depends on the determination situation of VT7. Similar to the determination process of VT2, the situation of VT8 can be determined.

[0101] Among them, VT8 is on the far right, and only VT7 and itself have an impact. The previous VT2, VT3, VT4, VT5, VT6, and VT7 are affected by both the left and right sides and themselves.

[0102] In addition, during the process of determining R3, R4... R8, R_N–base–D I FF_(N-1) is adopted; R_N is the data volume of the pattern to be determined for the Nth one. D I FF_(N-1) is the difference brought about by the right shift of the previous VT, that is, base–R_(N-1); D I FF is only used starting from the determination of R2, that is, N>1; substituting D I FF, R_N–base–(base–R_(N-1)), which expands to the general formula: R_N+R_(N-1)–2base.

[0103] The present invention can quickly capture the change characteristics of the data distribution in the internal storage unit of NAND FLASH by reading the data of multiple pages in the word line and longitudinally analyzing the pattern data length. This analysis method based on data pattern significantly improves the speed of determining the VT change trend compared with the traditional direct measurement or scanning method, and reduces the time cost. In addition, by utilizing the phenomenon of relatively uniform distribution of NAND FLASH data, by statistically counting the number (RN) corresponding to the pattern data length and comparing it with the set value, the change trend of VT can be determined more accurately. This method not only considers the state of a single storage unit, but also grasps the change law of the data distribution as a whole, thereby improving the accuracy of determination. An accurate determination of the VT change trend helps the storage system to timely adjust the read voltage to adapt to the change of the storage unit state, which can not only reduce the probability of read data failure, but also avoid unnecessary error correction processes, thereby optimizing the overall performance of the storage system and improving the data read speed and stability. In addition, since the present invention can quickly and accurately determine the VT change trend and take corresponding adjustment measures, it can ensure that the storage system accurately completes relevant service indicators such as data reading within the specified time, which is of great significance for improving user satisfaction and service quality. In addition, by determining the VT change trend in advance and taking preventive measures, the present invention helps to reduce the maintenance cost of the storage system caused by data loss or read errors, which can not only save human resources and time costs, but also reduce the potential economic losses caused by data damage.

[0104] Figure 4 It is a schematic block diagram of a device 300 for quickly determining the VT change trend provided by an embodiment of the present invention. As Figure 4As shown, corresponding to the above method for quickly determining the VT change trend, the present invention also provides a device 300 for quickly determining the VT change trend. The device 300 for quickly determining the VT change trend includes units for executing the above method for quickly determining the VT change trend, and the device can be configured in a server. Specifically, please refer to Figure 4 , the device 300 for quickly determining the VT change trend includes a reading and obtaining unit 301, a statistical unit 302, a comparison unit 303, and a determination unit 304;

[0105] The reading and obtaining unit 301 is used to read data of multiple pages within a word line to obtain the pattern data length longitudinally;

[0106] The statistical unit 302 is used to count the number corresponding to the pattern data length, denoted as RN;

[0107] The comparison unit 303 is used to compare RN with a set value to obtain a comparison result;

[0108] The determination unit 304 is used to determine the change trend of VT according to the comparison result to obtain a corresponding conclusion.

[0109] In one embodiment, the data length is denoted as max_count_bit, and RN is max_count_bit / the number of VT regions.

[0110] In one embodiment, the comparison result includes equal to, less than, or greater than.

[0111] In one embodiment, the corresponding conclusion includes that the optimal voltage is at the current position, the optimal voltage is to the left of the current position, or the optimal voltage is to the right of the current position.

[0112] It should be noted that those skilled in the art can clearly understand the specific implementation processes of the above device 300 for quickly determining the VT change trend and each unit, and can refer to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and brevity of description, they will not be elaborated here.

[0113] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 5As shown. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it realizes the functions or steps on the server side of a method for quickly determining the VT change trend.

[0114] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0115] Read the data of multiple pages in the word line to obtain the pattern data length longitudinally; count the number corresponding to the pattern data length, denoted as RN; compare RN with a set value to obtain a comparison result; according to the comparison result, determine the change trend of VT to obtain a corresponding conclusion.

[0116] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the following steps are implemented:

[0117] Read the data of multiple pages in the word line to obtain the pattern data length longitudinally; count the number corresponding to the pattern data length, denoted as RN; compare RN with a set value to obtain a comparison result; according to the comparison result, determine the change trend of VT to obtain a corresponding conclusion.

[0118] It should be noted that for the functions or steps that the above computer-readable storage medium or computer device can achieve, reference can be made to the relevant descriptions on the server side and the client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0119] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0121] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for quickly determining the VT change trend, characterized in that: include: Read the data of multiple pages in a word line to obtain the pattern data length vertically; Count the number of pattern data lengths, recorded as RN; Compare RN with the set value to obtain a comparison result; According to the comparison results, the change trend of VT is determined to obtain the corresponding conclusion.

2. The method for quickly determining VT change trend according to claim 1, characterized in that: The data length is recorded as max_count_bit, and the RN is max_count_bit / number of VT areas.

3. The method for quickly determining VT change trend according to claim 1, characterized in that: The comparison result includes equal to, less than or greater than.

4. The method for quickly determining VT change trend according to claim 1, characterized in that: The corresponding conclusions include that the optimal voltage is at the current position, the optimal voltage is at the left of the current position, or the optimal voltage is at the right of the current position.

5. A device for quickly determining the trend of VT changes, characterized in that: include: A read unit is used to read data of multiple pages in a word line to obtain the pattern data length vertically; A statistical unit is used to count the number corresponding to the length of pattern data, denoted as RN; A comparison unit, used for comparing RN with a set value to obtain a comparison result; The determination unit is used to determine the change trend of VT according to the comparison result to obtain a corresponding conclusion.

6. The device for quickly determining VT change trend according to claim 5, characterized in that: The data length is recorded as max_count_bit, and the RN is max_count_bit / number of VT areas.

7. The device for quickly determining VT change trend according to claim 5, characterized in that: The comparison result includes equal to, less than or greater than.

8. The device for quickly determining VT change trend according to claim 5, characterized in that: The corresponding conclusions include that the optimal voltage is at the current position, the optimal voltage is at the left of the current position, or the optimal voltage is at the right of the current position.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for quickly determining the VT change trend as described in any one of claims 1 to 4 are implemented.

10. A storage medium, wherein the computer-readable storage medium stores a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for quickly determining the VT change trend as described in any one of claims 1 to 4 are implemented.

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