Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; wherein the memory cell array comprises a plurality of word lines; the operation method comprises the following steps: at a first moment, applying a pre-charging voltage to a selected word line in a plurality of word lines; at a second moment before the first moment, voltage applied to a non-selected word line adjacent to the selected word line is changed from first voltage to second voltage; wherein the first voltage is greater than the second voltage; and applying a voltage pulse to the selected word line at a third moment before the first moment.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory, an operation method thereof, and a memory system. Background Art

[0002] As the density of memories continues to increase, the storage cells exhibit the characteristic of physical volume reduction, and the word lines in the memory are physically closer, and the coupling capacitance between adjacent word lines increases. Thus, during the operation of the memory, interference may occur between adjacent word lines, thereby affecting the reliability of the memory.

[0003] Currently, how to improve the reliability of memories has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, an operation method thereof, and a memory system.

[0005] In a first aspect, embodiments of the present disclosure provide an operation method of a memory. The memory includes: a storage cell array and a peripheral circuit coupled to the storage cell array. Among them, the storage cell array includes multiple word lines. The operation method includes:

[0006] At a first moment, a pre-charge voltage is applied to a selected word line among the multiple word lines.

[0007] At a second moment before the first moment, the voltage applied to a non-selected word line adjacent to the selected word line changes from a first voltage to a second voltage; wherein the first voltage is greater than the second voltage.

[0008] At a third moment before the first moment, a voltage pulse is applied to the selected word line.

[0009] In some embodiments, the third moment is not earlier than the second moment.

[0010] In some embodiments, the applying a voltage pulse to the selected word line at the third moment before the first moment includes:

[0011] At the third moment before the first moment, a third voltage is started to be applied to the selected word line; wherein the third voltage is greater than the absolute value of the difference between the first voltage and the second voltage.

[0012] In some embodiments, the applying a voltage pulse to the selected word line at the third moment before the first moment further includes:

[0013] At a fourth moment after the third moment and before the first moment, the application of the third voltage to the selected word line ends.

[0014] In some embodiments, the time duration between the second moment and the first moment is a first time duration; the time duration between the third moment and the fourth moment is a second time duration; wherein, the ratio between the second time duration and the first time duration is greater than 0.5.

[0015] In some embodiments, the operation method further includes:

[0016] At a fifth moment after the second moment, the voltage on the adjacent non-selected word line reaches the second voltage; wherein, the time duration between the second moment and the fifth moment is a third time duration; the third time duration is less than or equal to the first time duration.

[0017] In some embodiments, the operation method further includes:

[0018] At a sixth moment after the first moment, the selected word line is floated.

[0019] At a seventh moment after the first moment and before the sixth moment, the voltage applied to the adjacent non-selected word line changes from the second voltage to the fourth voltage; wherein, the second voltage is less than the fourth voltage.

[0020] In some embodiments, the operation method further includes:

[0021] At an eighth moment after the seventh moment, the voltage on the adjacent non-selected word line reaches the fourth voltage; wherein, the time duration between the seventh moment and the eighth moment is a fourth time duration, the time duration between the seventh moment and the sixth moment is a fifth time duration; the fourth time duration is less than or equal to the fifth time duration.

[0022] In some embodiments, the first voltage is the same as the fourth voltage.

[0023] In some embodiments, the operation method further includes:

[0024] At a ninth moment after the sixth moment, the selected word line starts to discharge.

[0025] In some embodiments, when the selected word line is the nth word line, the adjacent non-selected word lines include the (n - 1)th word line and the (n + 1)th word line; wherein, n is a natural number.

[0026] In some embodiments, the adjacent non-selected word lines further include the word lines that are spaced m word lines from the selected word line; wherein, m is a natural number, m is greater than or equal to 1 and m is less than or equal to 4.

[0027] Second aspect, embodiments of the present disclosure provide a memory, the memory comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes a plurality of word lines;

[0028] The peripheral circuit is configured to:

[0029] At a first moment, apply a precharge voltage to a selected word line among the plurality of word lines;

[0030] At a second moment before the first moment, change a voltage applied to a non-selected word line adjacent to the selected word line from a first voltage to a second voltage; wherein, the first voltage is greater than the second voltage;

[0031] At a third moment before the first moment, apply a voltage pulse to the selected word line.

[0032] In some embodiments, the peripheral circuit includes a word line driver circuit, a first voltage control circuit, and a second voltage control circuit;

[0033] The word line driver circuit is configured to: receive a main word line selection signal and a word line selection signal, connect the adjacent non-selected word line to the second voltage control circuit at the second moment, and connect the adjacent non-selected word line to the first voltage control circuit at the seventh moment;

[0034] Wherein, the main word line selection signal is used to select one main word line among a plurality of main word lines of the peripheral circuit, and each main word line corresponds to a plurality of word lines; the word line selection signal is used to select one word line among the plurality of word lines corresponding to the main word line.

[0035] In some embodiments, the second voltage control circuit is configured to: apply a second voltage to the adjacent non-selected word line at the second moment;

[0036] The word line driver circuit is configured to: start applying a third voltage to the selected word line at a third moment not earlier than the second moment; wherein, the third voltage is greater than the absolute value of the difference between the first voltage and the second voltage.

[0037] In some embodiments, the word line driver circuit is configured to:

[0038] End applying the third voltage to the selected word line at a fourth moment after the third moment and before the first moment.

[0039] In some embodiments, the word line driver circuit is configured to: float the selected word line at a sixth moment after the first moment;

[0040] The first voltage control circuit is configured to apply a fourth voltage to the adjacent unselected word line at a seventh time after the first time and before the sixth time; wherein, the second voltage is less than the fourth voltage.

[0041] In some embodiments, the duration between the second time and the first time is a first duration; the duration between the third time and the fourth time is a second duration; wherein, the ratio between the second duration and the first duration is greater than 0.5.

[0042] In some embodiments, the memory includes: a dynamic random access memory.

[0043] In a third aspect, an embodiment of the present disclosure provides a memory system, the memory system includes:

[0044] The memory as described in the above technical solution; and

[0045] A controller coupled to the memory and configured to control the memory.

[0046] An embodiment of the present disclosure provides a memory, an operation method thereof, and a memory system. The memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes a plurality of word lines; the operation method includes: applying a precharge voltage to a selected word line among the plurality of word lines at a first time; changing the voltage applied to an unselected word line adjacent to the selected word line from a first voltage to a second voltage at a second time before the first time; wherein, the first voltage is greater than the second voltage; applying a voltage pulse to the selected word line at a third time before the first time. In the embodiment of the present disclosure, by reducing the voltage applied to the adjacent unselected word line before precharging the selected word line, the rising amplitude of the voltage on the adjacent unselected word line is controlled; and by applying a voltage pulse to the selected word line before precharging the selected word line, the falling amplitude of the voltage on the selected word line is controlled, thereby reducing the duration of precharging the selected word line, and further improving the memory performance. Description of the Drawings

[0047] Figure 1 A waveform diagram of a memory read operation provided for some embodiments;

[0048] Figure 2 A timing diagram of accessing a selected word line provided for an embodiment of the present disclosure;

[0049] Figure 3 A waveform diagram of accessing a selected word line provided for an embodiment of the present disclosure;

[0050] Figure 4Schematic flowchart of the operation method of the memory provided by the embodiments of the present disclosure;

[0051] Figure 5 Timing diagram of accessing a selected word line provided by another embodiment of the present disclosure;

[0052] Figure 6 Waveform diagram of accessing a selected word line provided by another embodiment of the present disclosure;

[0053] Figure 7 Comparison diagram of the precharge time of accessing a selected word line in two embodiments of the present disclosure;

[0054] Figure 8 Schematic structural diagram of the memory provided by the embodiments of the present disclosure;

[0055] Figure 9 Partial schematic structural diagram of the peripheral circuit provided by the embodiments of the present disclosure;

[0056] Figure 10 Schematic structural diagram of the memory system provided by the embodiments of the present disclosure;

[0057] Figure 11 Schematic structural diagram of the electronic device provided by the embodiments of the present disclosure. Detailed implementation manners

[0058] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0059] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other instances, some well-known technical features are not described to avoid confusion with the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0060] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0061] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure. And when discussing a second element, component, region, layer, or portion, it does not imply that a first element, component, region, layer, or portion necessarily exists in the present disclosure.

[0062] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0063] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0064] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other implementation manners.

[0065] Reference Figure 1 , Figure 1 is a waveform diagram of a memory read operation provided for some embodiments. As Figure 1 shown, the horizontal axis represents time, and the vertical axis represents voltage. The read operation of a memory, such as a Dynamic Random Access Memory (DRAM), includes: a precharge operation (Precharge), an access operation (Access), a sense operation (Sense), and a restore operation (Restore). Among them, the precharge operation is stage Q0, the access operation is stage Q1, the sense operation is stage Q2, and the restore operation is stage Q3. Each memory cell in a DRAM includes a transistor and a storage capacitor. The gate of the transistor is connected to a word line (Word Line, WL), the drain of the transistor is connected to a bit line (Bit Line, BL), and the source of the transistor is connected to the storage capacitor. The voltage on the word line is used to control the on or off of the transistor, and the data stored in the storage capacitor is read using the bit line or data is written into the storage capacitor using the bit line for storage. The storage capacitor in the memory cell can store "0" or "1". Figure 1 Taking the process of reading "1" from the storage capacitor as an example for illustration.

[0066] In stage Q0, the precharge operation is performed to precharge the bit line to the reference voltage Vref, that is, Vcc / 2. Figure 1 Schematically shows the reference voltage Vref = Vcc / 2.

[0067] In stage Q1, the access operation is performed to carry out charge sharing. The transistor in the memory cell is turned on, and the bit line can access the storage capacitor in the memory cell. The positive charge in the storage capacitor in the memory cell will flow to the bit line, thereby pulling up the voltage of the bit line. Thus, charge sharing occurs between the charge in the bit line and the charge in the storage capacitor.

[0068] In stage Q2, a sense amplifier (SA) detects and amplifies the voltage difference between the bit line and the reference bit line connected to the sense amplifier. Among them, the sense amplifier includes a P-type control terminal (Sense-Amplifier P-Fet Control, SAP) and an N-type control terminal (Sense-Amplifier N-Fet Control, SAN). The voltage on SAP is set to the voltage of logic 1, that is, the high voltage Vcc, and the voltage on the bit line is pulled up to the high voltage Vcc by SAP; the voltage on SAN is set to the voltage of logic 0, that is, the low voltage Vss, and the voltage on the reference bit line is pulled down to the low voltage Vss by SAN.

[0069] In stage Q3, the voltage on the bit line is the high voltage Vcc. At this time, the bit line can charge the storage capacitor. After a certain period of time, the charge in the storage capacitor can be restored to the state before the read operation. In stage Q3, a read operation is performed. By controlling the column select signal (Column Selective Line, CSL), the column select transistor is turned on, and the data in the storage capacitor can be output to the input / output line (IO) by the sense amplifier.

[0070] In addition, Figure 1 schematically shows the delay time (Time of RAS to CAS Delay, t RCD ) of the memory row address (Row Address Strobe, RAS) transmitted to the column address (Column Address Strobe, CAS), that is, the sum of the durations of stage Q1 and stage Q2. Figure 1 It also schematically shows the time of row address strobe (Time of Row Address Strobe, t RAS ). The precharge duration (Time of Row Precharge, t RP ) refers to the duration of precharging the bit line to the reference voltage.

[0071] Refer to Figure 2 , Figure 2 which is a timing diagram of accessing a selected word line provided by an embodiment of the present disclosure. As Figure 2 shown, in the bank select signal lbk_plsb_en, the main word line select signal mwl_n <k>, word line selection signal wld <n>and a precharge control signal xpp <n>Under the trigger of, at the first time node T1, for the selected word line wl <n>Perform a pre-charge operation. Due to the existence of the word line resistance, the near end wl_near of the selected word line <n>and the distal end wl_far of the selected word line <n>Starting from the first time node T1, the time required to charge to the pre-charge voltage Vpp is different. Figure 2 The solid line in [reference] schematically shows the distal end wl_far of the selected word line <n>, the dashed line indicates the proximal end wl_near of the selected word line <n>, the proximal end wl_near of the selected word line <n>The duration required for the voltage on [object] to reach the pre-charge voltage Vpp is shorter.

[0072] Taking the far end wl_far<n+1> of an adjacent unselected word line as an example for illustration, when the selected word line wl <n>During the pre-charge operation, due to the word line coupling effect, the voltage on the far end wl_far<n+1> of the adjacent unselected word lines also rises. That is to say, during the process of accessing the selected word line of the memory, the voltage on the selected word line ramps up to a certain voltage value in a short time, which will cause the voltage on the nearby unselected word lines to be coupled and rise.

[0073] At the second time node T2 after the first time node T1, the selected word line wl <n>Start discharging. When the selected word line wl <n>During the discharging process, due to the word line coupling effect, the voltage on the far end wl_far<n+1> of the adjacent unselected word line also drops.

[0074] Thus, during the process of accessing the selected word line of the memory, due to the word line coupling effect, it may interfere with the adjacent unselected word lines, causing current to flow into or out of the adjacent memory cells, thereby affecting the reliability of the memory.

[0075] Still referring to Figure 1 As shown, at the third time node T3 before the first time node T1, for the selected word line wl <n>Before the pre-charging operation, the voltage applied by the local word line vwln<n+1 or n-1> to the far end wl_far<n+1> of the adjacent unselected word line changes from the fifth voltage V5 to the sixth voltage V6, and the fifth voltage V5 is greater than the sixth voltage V6. Thus, when selecting the word line wl <n>Before performing the pre-charge operation, the voltage applied to the far end wl_far<n+1> of the adjacent unselected word line is lowered in advance, so as to reduce the influence of the word line coupling effect on the voltage of the far end wl_far<n+1> of the adjacent unselected word line, and reduce the amplitude of the voltage rise on the far end wl_far<n+1> of the adjacent unselected word line.

[0076] Still referring to Figure 1 As shown, at the fourth time node T4 after the first time node T1 and before the second time node T2, the selected word line wl <n>Before discharging, the voltage applied by the local word line vwln<n+1 or n-1> to the far end wl_far<n+1> of the adjacent unselected word line changes from the sixth voltage V6 to the seventh voltage V7, and the sixth voltage V6 is less than the seventh voltage V7. Thus, for the selected word line wl <n>Before discharging, the voltage applied to the distal end wl_far<n+1> of the adjacent unselected word line is increased in advance to reduce the influence of the word line coupling effect on the voltage of the distal end wl_far<n+1> of the adjacent unselected word line, and reduce the amplitude of the voltage drop on the distal end wl_far<n+1> of the adjacent unselected word line.

[0077] In summary, by reducing the voltage applied to the adjacent unselected word line before pre-charging the selected word line, the amplitude of the voltage rise on the adjacent unselected word line is controlled. By increasing the voltage applied to the adjacent unselected word line before discharging the selected word line, the amplitude of the voltage drop on the adjacent unselected word line is controlled. In this way, during the charge-discharge process of the selected word line, the amplitude of the voltage change on the adjacent unselected word line can be effectively reduced, and the stored information of the adjacent memory cells can be prevented from being changed.

[0078] However, referring to Figure 2 As shown, by reducing the voltage applied to the adjacent unselected word line before pre-charging the selected word line, due to the word line coupling effect, the voltage on the selected word line will also drop, resulting in a longer duration required for the voltage on the selected word line to be charged to the pre-charge voltage Vpp during the subsequent pre-charging operation of the selected word line.

[0079] Referring to Figure 3 , Figure 3 is a waveform diagram of accessing a selected word line provided by an embodiment of the present disclosure. As Figure 3 shown, the abscissa is time and the ordinate is voltage. As Figure 3 shown in the dashed circle in, before the pre-charging operation of the selected word line, by reducing the voltage applied to the adjacent unselected word line, due to the word line coupling effect, the voltage on the selected word line will also drop. In other words, the starting voltage of the pre-charging operation of the selected word line will drop, resulting in an increase in the duration of the pre-charging operation of the selected word line.

[0080] In view of this, embodiments of the present disclosure provide a memory, an operation method thereof, and a memory system.

[0081] Referring to Figure 4 , Figure 4 is a schematic flow chart of an operation method of a memory provided by an embodiment of the present disclosure. As Figure 4 shown, embodiments of the present disclosure provide an operation method of a memory, the memory including: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes a plurality of word lines; the above operation method includes:

[0082] Step S401: Apply a pre-charge voltage to the selected word line among the plurality of word lines at a first moment;

[0083] Step S402: At a second moment before the first moment, the voltage applied to the unselected word line adjacent to the selected word line changes from a first voltage to a second voltage; wherein, the first voltage is greater than the second voltage.

[0084] Step S403: At a third moment before the first moment, a voltage pulse is applied to the selected word line.

[0085] In the embodiments of the present disclosure, by reducing the voltage applied to the adjacent unselected word line before pre-charging the selected word line, the rising amplitude of the voltage on the adjacent unselected word line is controlled; and a voltage pulse is applied to the selected word line before pre-charging the selected word line, the falling amplitude of the voltage on the selected word line is controlled, thereby reducing the pre-charging duration of the selected word line, and further improving the memory performance.

[0086] Reference Figure 5 , Figure 5 is a timing diagram for accessing a selected word line provided by another embodiment of the present disclosure. As Figure 5 shown, in step S401, the bank select signal lbk_plsb_en and the main word line select signal mwl_n <k>, word line selection signal wld <n>and a precharge control signal xpp <n>Under the trigger of, at the first moment t1, the selected word line wl <n>Perform a precharge operation. Due to the existence of the word line resistance, the proximal end wl_near of the selected word line <n>and the distal end wl_far of the selected word line <n>Starting from the first moment t1, the time required to charge to the pre-charge voltage Vpp is different. Figure 5 The solid line in it schematically shows the far end wl_far of the selected word line <n>, the dotted line indicates the proximal end wl_near of the selected word line <n>, the proximal end wl_near of the selected word line <n>The duration for the voltage on [it] to reach the pre-charge voltage is shorter.

[0087] It should be noted that the bank select signal lbk_plsb_en and the main word line select signal mwl_n <k>and word line selection signal wld <n>The enable states are all low voltages such as Vss, and the non - enable states are all high voltages such as Vpp or Vdd. The pre - charge control signal xpp <n>The enable state is a high voltage such as Vpp or Vdd, and the non - enable state is a low voltage such as Vss.

[0088] It can be understood that for the selected word line, the memory bank selection signal lbk_plsb_en, the main word line selection signal mwl_n <k>and a word line selection signal wld <n>All are in the enabled state, i.e., a low voltage such as Vss.

[0089] Here, the bank select signal lbk_plsb_en is used to select one bank among multiple banks; the main word line select signal mwl_n <k>For selecting one of multiple main word lines of a peripheral circuit, each main word line corresponding to multiple word lines; word line selection signal wld <n>Used to select one word line among multiple word lines corresponding to the main word line.

[0090] Here, at the first moment t1, for the selected word line wl <n>Perform a pre-charge operation, that is, apply a pre-charge voltage Vpp to the selected word line. For the selected word line, starting from the first moment t1, the proximal end wl_near of the selected word line <n>and the distal end wl_far of the selected word line <n>The voltage on [it] will all rise. After a certain duration, the proximal end wl_near of the selected word line <n>and the distal end wl_far of the selected word line <n>The voltage values on may all reach the voltage value of the pre-charge voltage.

[0091] Still referring to Figure 5 As shown, taking the far end wl_far<n+1> of the adjacent unselected word line as an example, in step S402, at the second moment t2 before the first moment t1, the voltage applied by the local word line vwln<n+1 or n-1> to the far end wl_far<n+1> of the adjacent unselected word line changes from the first voltage V1 to the second voltage V2; among them, the first voltage V1 is greater than the second voltage V2. Thus, on the selected word line wl <n>Before precharging starts at the first moment t1, the voltage applied to the far end wl_far<n+1> of the adjacent unselected word line is reduced in advance, so as to reduce the influence of the word line coupling effect on the voltage of the far end wl_far<n+1> of the adjacent unselected word line and reduce the rising amplitude of the voltage of the far end wl_far<n+1> of the adjacent unselected word line.

[0092] It can be understood that for the adjacent unselected word lines, the bank select signal lbk_plsb_en and the main word line select signal mwl_n <k>and word line selection signal wld <n>All are in the disabled state, i.e., a high voltage such as Vpp.

[0093] Continue to refer to Figure 5 As shown, in step S403, among the bank select signal lbk_plsb_en and the main word line select signal mwl_n <k>, word line selection signal wld <n>and a pre-charge control signal xpp <n>Upon triggering, the memory will, at the third moment t3 before the first moment t1, select the word line wl <n>A voltage pulse is applied thereto. Thus, when the selected word line wl <n>Before precharging starts from the first moment t1, the selected word line wl is precharged in advance <n>Apply a voltage pulse to control the selected word line wl <n>The magnitude of the voltage drop caused by the word line coupling effect, thus avoiding the selected word line wl <n>The starting voltage on the [object] is relatively low, resulting in an increase in the pre-charging duration.

[0094] It should be noted that applying a voltage pulse to the selected word line aims to compensate for the voltage drop of the selected word line due to the word line coupling effect. For example, the voltage applied to the adjacent non-selected word line changes from the first voltage V1 to the second voltage V2, and the voltage drop value on the non-selected word line is the difference between the first voltage V1 and the second voltage V2; during the above process, due to the word line coupling effect, the voltage drop value on the selected word line is less than or equal to the difference between the first voltage V1 and the second voltage V2. Applying a voltage pulse to the selected word line aims to further reduce or even basically eliminate the effect of the voltage on the selected word line being coupled and dropped. In this way, it is possible to avoid the situation where the voltage on the selected word line is relatively low at the first moment t1 (i.e., the moment when the pre-charging operation starts), resulting in an increase in the pre-charging duration.

[0095] In some embodiments, the third moment t3 is not earlier than the second moment t2.

[0096] Here, the third moment t3 can be the same as the second moment t2, or the third moment t3 can be later than the second moment t2. Exemplarily, Figure 5 Schematically shows that the third moment t3 is the same as the second moment t2.

[0097] In some embodiments, referring to Figure 5 As shown, step S403 includes: at the third moment t3 before the first moment t1, applying a voltage to the selected word line wl <n>Apply a third voltage V3 starting from the upper end; wherein, the third voltage V3 is greater than the absolute value of the difference between the first voltage V1 and the second voltage V2.

[0098] Here, at the second moment t2, reduce the voltage applied to the far end wl_far<n+1> of the adjacent non-selected word line, that is, reduce it from the first voltage V1 to the second voltage V2. Due to the word line coupling effect, the selected word line wl <n>The voltage on [it] also starts to decrease from the second moment t2; at the third moment t3, for the selected word line wl <n>Apply a third voltage V3 starting from the top to reduce the influence of the far end wl_far<n+1> of the adjacent unselected word line on the selected word line wl <n>coupling effect, thereby reducing the selected word line wl caused by the word line coupling effect <n>The magnitude of the voltage drop thereon, thereby reducing the impact on the selected word line wl <n>The duration for pre-charging.

[0099] In some embodiments, referring to Figure 5 as shown, at the third moment t3, the selected word line wl <n>Start applying the third voltage V3; Step S403 further includes: at the fourth moment t4, for the selected word line wl <n>End applying the third voltage V3; wherein, for the selected word line wl <n>Before performing the precharge operation, the selected word line wl <n>The duration of the applied voltage pulse is (t4 - t3).

[0100] Here, the fourth time t4 is later than the second time t2 and the fourth time t4 is earlier than the first time t1. That is to say, for the selected word line wl <n>The process of applying a voltage pulse is earlier than that for the selected word line wl <n>The process of performing a pre-charge operation. Specifically, the magnitude and duration of the voltage pulse applied to the selected word line can be flexibly selected according to the coupling effect of adjacent unselected word lines on the selected word line.

[0101] In some embodiments, referring to Figure 5 As shown, the duration between the second time t2 and the first time t1 is the first duration Δt1, i.e., (t1 - t2); the duration between the third time t3 and the fourth time t4 is the second duration Δt2, i.e., (t4 - t3); wherein, the ratio between the second duration Δt2 and the first duration Δt1 is greater than 0.5.

[0102] Here, the first duration Δt1 refers to when pre-charging the selected word line wl <n>The duration of applying the second voltage V2 to the far end wl_far<n+1> of the adjacent non-selected word line before performing the pre-charge operation. In other words, the first duration refers to when applying a voltage to the selected word line wl <n>The duration of pulling down the voltage on the far end wl_far<n+1> of the adjacent unselected word line before performing the precharge operation; or, the far end wl_far<n+1> of the adjacent unselected word line to the selected word line wl <n>Generate a word line coupling effect to select the word line wl <n>The duration for which the voltage on [it] is pulled down. The second duration Δt2 refers to the selected word line wl <n>The duration of the applied voltage pulse.

[0103] It should be noted that if the ratio between the second duration and the first duration is too small, the influence on the voltage of the selected word line may be limited, and it is difficult to control the amplitude of the voltage drop of the selected word line caused by the word line coupling effect.

[0104] In some embodiments, at the second moment t2, the selected word line wl <n>The voltage on and the selected word line wl at the first moment t1 <n>The voltages on are basically the same.

[0105] Here, basically the same means that the selected word line wl at the second moment t2 <n>The voltage on and the selected word line wl at the first moment t1 <n>The difference between the voltages on is less than a preset value. In a specific embodiment, the selected word line wl at the second moment t2 <n>The voltage on and the selected word line wl at the first moment t1 <n>The difference in voltage on is 0.

[0106] Thus, by applying a voltage pulse to the selected word line before performing the pre-charging operation on the selected word line, the coupling effect of the voltage drop on the unselected word line on the voltage of the selected word line can be effectively reduced or even basically eliminated, thereby improving the starting voltage of the pre-charging operation on the selected word line, and further improving the duration of the pre-charging of the selected word line.

[0107] In some embodiments, referring to Figure 5 As shown, at the fifth moment t5, the voltage on the adjacent unselected word line (for example, the far end wl_far<n+1> of the adjacent unselected word line) reaches the second voltage V2; wherein, the duration between the second moment t2 and the fifth moment t5 is the third duration Δt3, that is, (t5 - t2); the third duration Δt3 is less than or equal to the first duration Δt1.

[0108] Thus, by setting the third duration to ensure that the voltage on the adjacent unselected word line has reached the second voltage before pre-charging the selected word line, the control effect on the voltage change on the adjacent unselected word line during the pre-charging of the selected word line can be further improved.

[0109] Referring to Figure 6 , Figure 6 is a waveform diagram of accessing a selected word line provided by another embodiment of the present disclosure. As Figure 6 shown, the abscissa is time and the ordinate is voltage. As Figure 6 shown by the solid circular frame in, a voltage pulse is applied to the selected word line before performing the pre-charging operation on the selected word line. As Figure 6 shown by the dashed circular frame in, a voltage pulse is applied to the selected word line so that the voltage on the selected word line remains basically unchanged before performing the pre-charging operation; or, the amplitude of the voltage drop on the selected word line is reduced before performing the pre-charging operation.

[0110] Referring to Figure 7 , Figure 7 is a comparison diagram of the pre-charging time of accessing a selected word line in two embodiments of the present disclosure. As Figure 7 shown, the abscissa is time and the ordinate is voltage. Figure 7 It shows that before the pre-charge operation is performed on the selected word line, no voltage pulse is applied to the selected word line. At this time, the starting voltage of the pre-charge operation on the selected word line is relatively low, and the pre-charge duration is longer; and before the pre-charge operation is performed on the selected word line, a voltage pulse is applied to the selected word line. At this time, the starting voltage of the pre-charge operation on the selected word line is relatively high, and the pre-charge duration is shorter. That is to say, applying a voltage pulse to the selected word line before the pre-charge operation on the selected word line can control the amplitude of the voltage drop on the selected word line, thereby reducing the pre-charge duration of the selected word line, and further improving the memory performance.

[0111] In some embodiments, the above operation method further includes:

[0112] At the sixth moment t6 after the first moment t1, the selected word line starts to be floated;

[0113] At the seventh moment t7 after the first moment t1 and before the sixth moment t6, the voltage applied to the adjacent non-selected word line changes from the second voltage V2 to the fourth voltage V4; wherein, the second voltage V2 is less than the fourth voltage V4.

[0114] Reference Figure 5 As shown, at the sixth moment t6 after the first moment t1, the pre-charge control signal xpp <n>Switch from the enabled state to the disabled state and stop the selected word line wl <n>Perform a pre-charge operation on the selected word line wl <n>Start floating.

[0115] In some embodiments, referring to Figure 5 As shown, at the sixth moment t6, the selected word line wl <n>Start the floating operation. At the ninth moment t9 after a certain buffer time after the sixth moment t6, the word line wl is selected <n>Start discharging.

[0116] Taking the far end wl_far<n+1 or n-1> of the adjacent non-selected word line as an example, at the seventh moment t7 after the first moment t1 and before the sixth moment t6, the voltage applied to the far end wl_far<n+1 or n-1> of the adjacent non-selected word line by the local word line vwln<n+1 or n-1> changes from the second voltage V2 to the fourth voltage V4; wherein, the second voltage V2 is less than the fourth voltage V4. Thus, for the selected word line wl <n>Before floating starting from the sixth moment t6, the voltage applied to the far end wl_far<n+1 or n-1> of the adjacent unselected word line is raised in advance to reduce the influence of the word line coupling effect on the voltage of the far end wl_far<n+1 or n-1> of the adjacent unselected word line, and reduce the amplitude of the voltage drop on the far end wl_far<n+1 or n-1> of the adjacent unselected word line.

[0117] In summary, before pre-charging the selected word line, the voltage applied to the adjacent unselected word line is reduced in advance to control the amplitude of the voltage rise on the adjacent unselected word line. Before discharging the selected word line, the voltage applied to the adjacent unselected word line is raised in advance to control the amplitude of the voltage drop on the adjacent unselected word line. In this way, during the charging-discharging process of the selected word line, the amplitude of the voltage change on the adjacent unselected word line can be effectively reduced.

[0118] In some embodiments, referring to Figure 5 As shown, at the eighth moment t8, the voltage on the adjacent unselected word line (for example, the far end wl_far<n+1> of the adjacent unselected word line) reaches the fourth voltage V4; wherein, the duration between the seventh moment t7 and the eighth moment t8 is the fourth duration Δt4, that is, (t8 - t7), and the duration between the seventh moment t7 and the sixth moment t6 is the fifth duration Δt5, that is, (t6 - t7); the fourth duration Δt4 is less than or equal to the fifth duration Δt5.

[0119] In this way, by setting the fourth duration, it is ensured that the voltage on the adjacent unselected word line has reached the fourth voltage before starting to discharge the selected word line, so as to further improve the control effect on the voltage change of the adjacent unselected word line during the discharging process of the selected word line.

[0120] In some embodiments, the first voltage V1 is the same as the fourth voltage V4.

[0121] In some embodiments, the first voltage V1, the second voltage V2, and the fourth voltage V4 are all negative voltages.

[0122] In a specific embodiment, the first voltage V1 and the fourth voltage V4 can both be the negative voltage vwln, for example, -0.5V; the second voltage V2 can be the negative voltage vwln2, for example, -1V.

[0123] In some embodiments, when the selected word line is the nth word line, the adjacent unselected word lines include the (n - 1)th word line and the (n + 1)th word line; wherein, n is a natural number.

[0124] Exemplarily, when the selected word line is the 8th word line, the adjacent unselected word lines include the 7th and 9th word lines.

[0125] In some embodiments, the adjacent unselected word lines further include word lines spaced m word lines from the selected word line; where m is a natural number, m is greater than or equal to 1 and m is less than or equal to 4.

[0126] Exemplarily, when the selected word line is the 8th word line, the adjacent unselected word lines further include word lines spaced 1 word line from the selected word line, that is, the 6th word line and the 10th word line; the adjacent unselected word lines further include word lines spaced 2 word lines from the selected word line, that is, the 5th word line and the 11th word line; the adjacent unselected word lines further include word lines spaced 3 word lines from the selected word line, that is, the 4th word line and the 12th word line; the adjacent unselected word lines further include word lines spaced 4 word lines from the selected word line, that is, the 3rd word line and the 13th word line.

[0127] It should be noted that the adjacent unselected word lines may include multiple word lines. The closer the distance between the adjacent unselected word lines and the selected word line, the greater the coupling effect of the adjacent unselected word lines on the selected word line. In fact, the magnitude and duration of the voltage pulse applied to the selected word line before the precharging operation of the selected word line can be specifically selected according to the magnitude of the coupling effect of the adjacent unselected word lines on the selected word line.

[0128] Reference Figure 8 , Figure 8 is a schematic structural diagram of the memory provided by the embodiments of the present disclosure. As Figure 8 shown, an embodiment of the present disclosure provides a memory, and the memory 100 includes: a storage cell array 102 and a peripheral circuit 104 coupled to the storage cell array 102; where the storage cell array 102 includes multiple word lines;

[0129] The above-mentioned peripheral circuit 104 is configured to:

[0130] At a first moment, apply a precharging voltage to the selected word line among the multiple word lines;

[0131] At a second moment before the first moment, change the voltage applied to the unselected word line adjacent to the selected word line from a first voltage to a second voltage; where the first voltage is greater than the second voltage;

[0132] At a third moment before the first moment, apply a voltage pulse to the selected word line.

[0133] In an embodiment of the present disclosure, the peripheral circuit may be configured to control the amplitude of the voltage rise on an adjacent unselected word line by reducing the voltage applied to the adjacent unselected word line before precharging the selected word line; and the peripheral circuit may be configured to apply a voltage pulse to the selected word line before precharging the selected word line to control the amplitude of the voltage drop on the selected word line, thereby reducing the duration of precharging the selected word line, and further improving the memory performance.

[0134] In some embodiments, the peripheral circuit 104 includes a word line driving circuit 106, a first voltage control circuit 108, and a second voltage control circuit 110;

[0135] The word line driving circuit 106 is configured to: receive the main word line selection signal mwl_n <k>Word line select signal wld <n>, at the second moment, connecting the adjacent unselected word lines to the second voltage control circuit 110, and at the seventh moment, connecting the adjacent unselected word lines to the first voltage control circuit 108;

[0136] Among them, the main word line selection signal mwl_n <k>For selecting one of multiple main word lines of a peripheral circuit, each main word line corresponding to multiple word lines; word line selection signal wld <n>For selecting one word line out of multiple word lines corresponding to the main word line.

[0137] Combined Figure 5 and Figure 9 As shown, taking the case where the first voltage V1 is the same as the fourth voltage V4 as an example for illustration. At the second moment t2, the adjacent unselected word line is connected to the second voltage control circuit 110. The second voltage control circuit 110 responds to the second control signal wlup_vwln, and the second voltage control circuit 110 transmits the second voltage V2, that is, the negative voltage vwln2, to the adjacent unselected word line; at the seventh moment t7, the adjacent unselected word line is connected to the first voltage control circuit 108, and the first voltage control circuit 108 responds to the first control signal wlup_enb and transmits the fourth voltage V4 (or, the first voltage V1), that is, the negative voltage vwln, to the adjacent unselected word line.

[0138] In some embodiments, the second voltage control circuit 110 is configured to: at the second moment, apply the second voltage to the adjacent unselected word line;

[0139] The word line driving circuit 106 is configured to: at a third moment not earlier than the second moment, start applying a third voltage to the selected word line; wherein, the third voltage is greater than the absolute value of the difference between the first voltage and the second voltage.

[0140] In some embodiments, the word line driving circuit 106 is configured to:

[0141] At a fourth moment after the third moment and before the first moment, stop applying the third voltage to the selected word line.

[0142] In some embodiments, the word line driving circuit 106 is configured to: at a sixth moment after the first moment, float the selected word line;

[0143] The first voltage control circuit 108 is configured to: at a seventh moment after the first moment and before the sixth moment, apply the fourth voltage to the adjacent unselected word line; wherein, the second voltage is less than the fourth voltage.

[0144] In some embodiments, the duration between the second moment and the first moment is the first duration;

[0145] The duration between the third moment and the fourth moment is the second duration; wherein, the ratio between the second duration and the first duration is greater than 0.5.

[0146] Refer to Figure 9 , Figure 9 is a partial structural schematic diagram of the peripheral circuit provided by the embodiments of the present disclosure. As Figure 9 As shown, the peripheral circuit includes a word line driving circuit 106, a first voltage control circuit 108, and a second voltage control circuit 110.

[0147] The word line driving circuit 106 includes a third P-type transistor MP3, a sixth N-type transistor MN6, and a seventh N-type transistor MN7.

[0148] The third P-type transistor MP3 and the sixth N-type transistor MN6 are connected in series. The control terminals of the third P-type transistor MP3 and the sixth N-type transistor MN6 are connected and used to receive the main word line selection signal mwl_n <k>。The source terminal of the third P-type transistor MP3 is used to receive the precharge control signal xpp <n>。The drain terminal of the third P-type transistor MP3 and the drain terminal of the seventh N-type transistor MN7 are connected and commonly connected to the word line wl. The source terminal of the sixth N-type transistor MN6 is connected to the second node N2.

[0149] The control terminal of the seventh N-type transistor MN7 is used to receive the word line selection signal wld <n>, the drain terminal of the seventh N-type transistor MN7 is connected to the word line wl, and the source terminal of the seventh N-type transistor MN7 is connected to the second node N2.

[0150] Combined with Figure 5 and Figure 9 As shown, the precharge control signal xpp <n>The enable state is a high voltage such as Vpp or Vdd. At this time, the main word line selection signal mwl_n <k>and word line selection signal wld <n>are all low voltages, such as Vss. At the third moment t3, the precharge control signal xpp <n>When in the enabled state, a voltage pulse is applied to the selected word line; at the first moment t1, the precharge control signal xpp <n>When in the enabled state, a pre-charge operation can be performed on the selected word line.

[0151] It should be noted that for the selected word line, at this time the main word line selection signal mwl_n <k>and word line selection signal wld <n>All are in the enabled state, i.e., a low voltage such as Vss. That is to say, at this time, the third P-type transistor MP3 in the word line driving circuit 106 is in the conducting state, and the sixth N-type transistor MN6 and the seventh N-type transistor MN7 are both in the non-conducting state. A voltage pulse can be applied to the selected word line at the third moment t3, and a pre-charge voltage can be applied to the selected word line at the first moment t1.

[0152] The first voltage control circuit 108 may include a first P-type transistor MP1, a first N-type transistor MN1, and a second N-type transistor MN2.

[0153] The first P-type transistor MP1 and the first N-type transistor MN1 are connected in series. Specifically, the control terminals of the first P-type transistor MP1 and the first N-type transistor MN1 are connected and used to receive the enable control signal wlup_en. The source terminal of the first P-type transistor MP1 is used to receive a high voltage, such as Vpp. The drain terminals of the first P-type transistor MP1 and the first N-type transistor MN1 are connected and commonly connected to the first node N1. The drain terminals of the first P-type transistor MP1 and the first N-type transistor MN1 are used to output the first control signal wlup_enb. The source terminal of the first N-type transistor MN1 is used to receive a low voltage.

[0154] The control terminal of the second N-type transistor MN2 is used to receive the first control signal wlup_enb. The drain terminal of the second N-type transistor MN2 is connected to the second node N2. The source terminal of the second N-type transistor MN2 is used to receive a low voltage, such as the negative voltage vwln.

[0155] Combined Figure 5 and Figure 9 As shown, the enabled state of the first control signal wlup_enb is a high voltage, such as Vpp, and the non-enabled state of the first control signal wlup_enb is a low voltage, such as the negative voltage vwln. When the first control signal wlup_enb is in the enabled state, for example, at the seventh moment t7, the first voltage control circuit 108 is connected to the adjacent non-selected word line. In response to the first control signal wlup_enb, the first voltage control circuit 108 transmits the fourth voltage V4 (or, the first voltage V1), i.e., the negative voltage vwln, to the adjacent non-selected word line.

[0156] It should be noted that for the adjacent non-selected word lines, at this time, the main word line selection signal mwl_n <k>and word line selection signal wld <n>Both are in the non-enabled state, i.e., a high voltage such as Vpp. That is to say, at this time, the seventh N-type transistor MN7 is in the conducting state. At the seventh moment t7, the first voltage control circuit 108 can transmit the fourth voltage V4 to the adjacent unselected word line.

[0157] The second voltage control circuit 110 may include a second P-type transistor MP2, a third N-type transistor MN3, a fourth N-type transistor MN4, and a fifth N-type transistor MN5.

[0158] The second P-type transistor MP2 and the third N-type transistor MN3 are connected in series. Specifically, the control terminals of the second P-type transistor MP2 and the third N-type transistor MN3 are connected and commonly connected to the first node N1. The control terminals of the second P-type transistor MP2 and the third N-type transistor MN3 are used to receive the first control signal wlup_enb. The source terminal of the second P-type transistor MP2 is used to receive a high voltage, such as Vpp. The drain terminal of the second P-type transistor MP2 and the drain terminal of the third N-type transistor MN3 are connected and commonly connected to the third node N3. The drain terminal of the second P-type transistor MP2 and the drain terminal of the third N-type transistor MN3 are used to output the second control signal wlup_vwln. The source terminal of the third N-type transistor MN3 is used to receive a low voltage.

[0159] The control terminal of the fourth N-type transistor MN4 is used to receive the second control signal wlup_vwln. The drain terminal of the fourth N-type transistor MN4 is connected to the second node N2. The source terminal of the fourth N-type transistor MN4 and the drain terminal of the fifth N-type transistor MN5 are connected. The control terminal of the fifth N-type transistor MN5 is used to receive the word line selection signal wld <n>, the source terminal of the fifth N-type transistor MN5 is used to receive a low voltage, such as a negative voltage vwln2.

[0160] Combined Figure 5 with Figure 9 as shown, the enable state of the second control signal wlup_vwln is a high voltage, such as Vpp, and the non-enable state of the second control signal wlup_vwln is a low voltage, such as a negative voltage vwln. When the second control signal wlup_vwln is in the enable state, such as the second time t2, the second voltage control circuit is connected to the adjacent unselected word line, and the second voltage control circuit responds to the second control signal wlup_vwln and transmits the second voltage V2, that is, the negative voltage vwln2, to the adjacent unselected word line.

[0161] It should be noted that for the adjacent unselected word lines, at this time the main word line selection signal mwl_n <k>and word line selection signal wld <n>All are in the non-enabled state, i.e., a high voltage such as Vpp. That is to say, at this time, the fifth N-type transistor MN5 and the seventh N-type transistor MN7 are in the conducting state. At the seventh moment t2, the second voltage control circuit 110 can transmit the second voltage V2 to the adjacent unselected word line.

[0162] In addition, Figure 9 Only an optional implementation manner of the peripheral circuit is shown. In the embodiments of the present disclosure, there are no special limitations on the types and connection manners of the transistors in the word line driving circuit, the first voltage control circuit, and the second voltage control circuit, and they can be flexibly selected according to actual situations.

[0163] In some embodiments, the memory 100 includes: a dynamic random access memory.

[0164] In some embodiments, the memory of the dynamic random access memory conforms to the DDR2 memory specification.

[0165] In some embodiments, the memory of the dynamic random access memory conforms to the DDR3 memory specification.

[0166] In some embodiments, the memory of the dynamic random access memory conforms to the DDR4 memory specification.

[0167] In some embodiments, the memory of the dynamic random access memory conforms to the DDR5 memory specification.

[0168] In some embodiments, the memory of the dynamic random access memory conforms to the LPDDR4 memory specification.

[0169] In some embodiments, the memory of the dynamic random access memory conforms to the LPDDR5 memory specification.

[0170] Refer to Figure 10 , Figure 10 which is a schematic structural diagram of the memory system provided by the embodiments of the present disclosure. As Figure 10 shown, the embodiments of the present disclosure provide a memory system 200, and the memory system 200 includes:

[0171] The memory 100 as in the above technical solution; and

[0172] A controller 202 coupled to the memory 100 and configured to control the memory 100.

[0173] In some embodiments, the controller 202 can send to and receive from the memory 100 command / address signals C / A, clock signals CLK, control signals CTRL, data DQ, and / or data strobe signals DQS. The controller 202 can be configured to control the operations of the memory 100, such as read operations and write operations.

[0174] In some embodiments, the controller 202 may provide an interface to the memory 100 to manage the data stored in the memory 100. The controller 202 may also communicate with external devices (e.g., a host) according to a specific communication protocol. For example, the controller 202 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0175] In some embodiments, the controller 202 may be implemented as an independent chip or may be integrated with the memory 100. The controller 202 and one or more memories 100 may be integrated into various types of storage devices. That is, the memory system 200 may be implemented and encapsulated into different types of terminal electronic products.

[0176] In some embodiments, the memory may serve as a buffer in a memory system.

[0177] In some specific examples, a memory (e.g., DRAM) may be used as an auxiliary in a solid-state drive, which can bring improvements in aspects such as reading and writing to the solid-state drive. Currently, most high-end solid-state drive products choose to embed DRAM to improve product performance and random read / write speed. Exemplarily, when writing a file, especially a small file, the small file is processed by the DRAM and then stored in a flash memory, making the solid-state drive more efficient and faster.

[0178] Reference Figure 11 , Figure 11 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. As Figure 11 shown, an embodiment of the present disclosure provides an electronic device 300, and the electronic device 300 includes: a memory system 200 as described in the above technical solution; and a host 302 coupled to the memory system 200.

[0179] In some embodiments, the electronic device 300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0180] As Figure 11 shown, the electronic device 300 can include a host 302 and a memory system 200, and the memory system 200 has one or more memories 100 and a controller 202. The host 302 can be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)). The host 302 can be configured to send data to the memory 100 or receive data from the memory 100.

[0181] In some embodiments, the controller 202 is coupled to the memory 100 and the host 302, and is configured to control the memory 100. The controller 202 can manage the data stored in the memory 100 and communicate with the host 302.

[0182] Embodiments of the present disclosure provide a memory, an operation method thereof, and a memory system. The memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes a plurality of word lines; the operation method includes: at a first moment, applying a precharge voltage to a selected word line among the plurality of word lines; at a second moment before the first moment, changing a voltage applied to a non-selected word line adjacent to the selected word line from a first voltage to a second voltage; wherein, the first voltage is greater than the second voltage; at a third moment before the first moment, applying a voltage pulse to the selected word line. In the embodiments of the present disclosure, by reducing the voltage applied to an adjacent non-selected word line before precharging the selected word line, the rising amplitude of the voltage on the adjacent non-selected word line is controlled; and by applying a voltage pulse to the selected word line before precharging the selected word line, the falling amplitude of the voltage on the selected word line is controlled, so as to reduce the precharging duration of the selected word line, and further improve the memory performance.

[0183] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0184] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.< / n> < / k> < / n> < / n> < / k> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / k> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k>

Claims

1. A method for operating a memory, characterized in that, the memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes a plurality of word lines; the operating method includes: At a first moment, apply a precharge voltage to a selected word line among the plurality of word lines; At a second moment before the first moment, change the voltage applied to a non-selected word line adjacent to the selected word line from a first voltage to a second voltage; wherein, the first voltage is greater than the second voltage; At a third moment before the first moment, apply a voltage pulse to the selected word line.

2. The method for operating a memory according to claim 1, characterized in that, the third moment is not earlier than the second moment.

3. The method for operating a memory according to claim 1, characterized in that, applying a voltage pulse to the selected word line at the third moment before the first moment includes: At the third moment before the first moment, start applying a third voltage to the selected word line; wherein, the third voltage is greater than the absolute value of the difference between the first voltage and the second voltage.

4. The method for operating a memory according to claim 3, characterized in that, applying a voltage pulse to the selected word line at the third moment before the first moment further includes: At a fourth moment after the third moment and before the first moment, end applying the third voltage to the selected word line.

5. The method for operating a memory according to claim 4, characterized in that, the duration between the second moment and the first moment is a first duration; the duration between the third moment and the fourth moment is a second duration; wherein, the ratio of the second duration to the first duration is greater than 0.

5.

6. The method for operating a memory according to claim 5, characterized in that, the operating method further includes: At a fifth moment after the second moment, the voltage on the adjacent non-selected word line reaches the second voltage; wherein, the duration between the second moment and the fifth moment is a third duration; the third duration is less than or equal to the first duration.

7. The method for operating a memory according to claim 1, characterized in that, the operating method further includes: At a sixth moment after the first moment, float the selected word line; At a seventh moment after the first moment and before the sixth moment, change the voltage applied to the adjacent non-selected word line from the second voltage to a fourth voltage; wherein, the second voltage is less than the fourth voltage.

8. The method for operating a memory according to claim 7, characterized in that, the operating method further includes: At an eighth moment after the seventh moment, the voltage on the adjacent non-selected word line reaches the fourth voltage; wherein, the duration between the seventh moment and the eighth moment is a fourth duration, and the duration between the seventh moment and the sixth moment is a fifth duration; the fourth duration is less than or equal to the fifth duration.

9. The operating method of the memory according to claim 7, characterized in that, the first voltage is the same as the fourth voltage.

10. The operating method of the memory according to claim 7, characterized in that, the operating method further includes: at the ninth moment after the sixth moment, the selected word line starts to discharge.

11. The operating method of the memory according to claim 1, characterized in that, when the selected word line is the nth word line, the adjacent non-selected word lines include the (n - 1)th word line and the (n + 1)th word line; where n is a natural number.

12. The operating method of the memory according to claim 11, characterized in that, the adjacent non-selected word lines further include the word lines spaced m word lines from the selected word line; where m is a natural number, m is greater than or equal to 1 and m is less than or equal to 4.

13. A memory, characterized in that, the memory includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes multiple word lines; the peripheral circuit is configured to: at a first moment, apply a pre-charge voltage to a selected word line among the multiple word lines; at a second moment before the first moment, change the voltage applied to the non-selected word lines adjacent to the selected word line from a first voltage to a second voltage; wherein, the first voltage is greater than the second voltage; at a third moment before the first moment, apply a voltage pulse to the selected word line.

14. The memory according to claim 13, characterized in that, the peripheral circuit includes a word line driving circuit, a first voltage control circuit, and a second voltage control circuit; the word line driving circuit is configured to: receive a main word line selection signal and a word line selection signal, connect the adjacent non-selected word lines to the second voltage control circuit at the second moment, and connect the adjacent non-selected word lines to the first voltage control circuit at the seventh moment; wherein, the main word line selection signal is used to select one main word line among the multiple main word lines of the peripheral circuit, and each main word line corresponds to multiple word lines; the word line selection signal is used to select one word line among the multiple word lines corresponding to the main word line.

15. The memory according to claim 14, characterized in that, the second voltage control circuit is configured to: apply the second voltage to the adjacent non-selected word lines at the second moment; the word line driving circuit is configured to: start applying a third voltage to the selected word line at a third moment not earlier than the second moment; wherein, the third voltage is greater than the absolute value of the difference between the first voltage and the second voltage.

16. The memory according to claim 15, characterized in that, the word line driving circuit is configured to: end applying the third voltage to the selected word line at a fourth moment after the third moment and before the first moment.

17. The memory according to claim 16, characterized in that, the word line driving circuit is configured to: float the selected word line at the sixth moment after the first moment. The first voltage control circuit is configured to apply a fourth voltage to the adjacent unselected word lines at a seventh moment after the first moment and before the sixth moment; wherein, the second voltage is less than the fourth voltage.

18. The memory according to claim 16, wherein, a duration between the second moment and the first moment is a first duration; a duration between the third moment and the fourth moment is a second duration; wherein, a ratio between the second duration and the first duration is greater than 0.

5.

19. The memory according to claim 13, wherein, the memory includes: a dynamic random access memory.

20. A memory system, wherein, the memory system includes: a memory according to any one of claims 13 to 19; and a controller coupled to the memory and configured to control the memory.

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