Electronic component

Abstract

The invention provides an electronic component. The electronic component includes a ceramic element body and a sintered metal layer disposed on the ceramic element body. The sintered metal layer has: a first region including a plurality of first crystal grains formed of a first metal; a second region in contact with the first region and including a plurality of second crystal grains formed of a second metal different from the first metal; and a third region in contact with the second region and including glass. An existing ratio of the first region to the second region is greater than 1 in terms of an area ratio of the first region to the second region.

Description

Technical Field

[0001] The present invention relates to an electronic component. Background Art

[0002] Known electronic components include a plurality of ceramic green bodies and a sintered metal layer disposed on the ceramic green bodies (for example, refer to Japanese Patent Application Laid-Open No. 2008-60612). The external electrode contains Ag. Summary of the Invention

[0003] In an electronic component, its characteristics may deteriorate due to the infiltration of moisture.

[0004] An electronic component sometimes includes a plating layer outside the sintered metal layer. The plating layer is formed, for example, by a wet plating method. When the plating solution used in the wet plating method reaches the ceramic green body, the characteristics of the electronic component may deteriorate. Not only the plating solution, but also moisture present in the external environment of the electronic component may infiltrate into the electronic component.

[0005] An object of one aspect of the present invention is to provide an electronic component that suppresses deterioration of characteristics.

[0006] The electronic component according to one aspect of the present invention includes a ceramic green body and a sintered metal layer disposed on the ceramic green body. The sintered metal layer has: a first region including a plurality of first grains formed of a first metal; a second region adjacent to the first region and including a plurality of second grains formed of a second metal different from the first metal; and a third region adjacent to the second region and including glass. The proportion of the presence of the first region to the second region is greater than 1 in terms of the area ratio of the first region to the second region.

[0007] In the above aspect, the proportion of the presence of the first region to the second region is greater than 1 in terms of the area ratio of the first region to the second region. The plurality of second grains included in the second region are likely to be in contact with the plurality of first grains included in the first region having an area ratio greater than that of the second region. The plurality of second grains reduce the contact between the plurality of first grains. The glass included in the third region can be in contact with the second region and exists between the plurality of first grains with reduced contact with each other. The denseness of the sintered metal layer is improved. Therefore, the above aspect suppresses deterioration of the characteristics of the electronic component.

[0008] In the above aspect, in the cross-section of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1.

[0009] In a structure where the area ratio of the first region to the second region is greater than 1 in the cross-section of the sintered metal layer, in the above cross-section, multiple second grains are further likely to contact multiple first grains, further reducing the contact between multiple first grains. The glass contained in the third region can further contact the second region and exists between multiple first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure reliably suppresses the characteristic deterioration of the electronic component.

[0010] In the above-described mode, in the cross-section of the sintered metal layer, multiple first grains may have a larger particle size than multiple second grains.

[0011] In a structure where multiple first grains have a larger particle size than multiple second grains in the cross-section of the sintered metal layer, in the above cross-section, multiple second grains are likely to be located between multiple first grains, further reducing the contact between multiple first grains. The glass contained in the third region can further contact the second region and exists between multiple first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses the characteristic deterioration of the electronic component.

[0012] In the above-described mode, in the surface of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1.

[0013] In a structure where the area ratio of the first region to the second region is greater than 1 in the surface of the sintered metal layer, in the above surface, multiple second grains are more likely to contact multiple first grains, further reducing the contact between multiple first grains. The glass contained in the third region can further contact the second region and exists between multiple first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure reliably suppresses the characteristic deterioration of the electronic component.

[0014] In the above-described mode, in the surface of the sintered metal layer, multiple first grains may have a larger particle size than multiple second grains.

[0015] In a structure where multiple first grains have a larger particle size than multiple second grains in the surface of the sintered metal layer, in the above surface, multiple second grains are likely to be located between multiple first grains, further reducing the contact between multiple first grains. The glass contained in the third region can further contact the second region and exists between multiple first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses the characteristic deterioration of the electronic component.

[0016] In one of the above-described ways, pores may also be formed in the sintered metal layer such that a second region is exposed.

[0017] A structure in which pores are formed in the sintered metal layer such that a second region is exposed relieves the stress acting on the sintered metal layer and suppresses the generation of cracks in the ceramic green body. Therefore, this structure, for example, more reliably suppresses deterioration of the characteristics of the electronic component.

[0018] In one of the above-described ways, the grain boundary between the first grains and the second grains may include a region where there is no alloy of the first metal and the second metal.

[0019] In a region where there is no alloy of the first metal and the second metal, the first metal and the second metal exist independently of each other. In a structure including a region where there is no alloy of the first metal and the second metal, a plurality of second grains are likely to be located between a plurality of first grains, and further reduce the contact between the plurality of first grains. The glass contained in the third region can further contact the second region and exists between the plurality of first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses deterioration of the characteristics of the electronic component.

[0020] In one of the above-described ways, the second metal may also have a melting point higher than that of the first metal.

[0021] In a structure in which the second metal has a melting point higher than that of the first metal, the second metal is more likely to remain in a solid state than the first metal. A plurality of second grains further reduce the contact between the plurality of first grains. The glass contained in the third region can further contact the second region and exists between the plurality of first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses deterioration of the characteristics of the electronic component.

[0022] In one of the above-described ways, the second metal may also have a greater ionization tendency than the first metal.

[0023] In a structure in which the second metal has a greater ionization tendency than the first metal, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. A plurality of second grains further reduce the contact between the plurality of first grains. The glass contained in the third region can further contact the second region and exists between the plurality of first grains with reduced contact with each other. The densification of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses deterioration of the characteristics of the electronic component.

[0024] In one of the above-described ways, the ceramic green body includes a semiconductor ceramic material.

[0025] The present invention will be more fully understood from the following detailed description and the accompanying drawings, and the following description and drawings should not be regarded as limiting the present invention.

[0026] From the following detailed description, the further scope of application of the present invention will become clear. However, it should be understood that when presenting examples of the present invention, the detailed description and specific examples are given only by way of illustration, because it will be apparent to those skilled in the art that various changes can be made within the spirit and scope of the present invention. Description of the Drawings

[0027] Figure 1 is a perspective view of an electronic component according to an embodiment.

[0028] Figure 2 is a view showing a cross-sectional structure of the electronic component according to the present embodiment.

[0029] Figure 3 is a view showing a cross-sectional structure of the electronic component according to the present embodiment.

[0030] Figure 4 is a view showing a cross-sectional structure of a sintered metal layer.

[0031] Figure 5 is a view showing a cross-sectional structure of a sintered metal layer.

[0032] Figure 6 is a view showing a surface structure of a sintered metal layer.

[0033] Figure 7 is a view showing a surface structure of a sintered metal layer. Detailed Embodiments

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same structures or structures having the same functions, and repeated descriptions are omitted.

[0035] Refer to Figures 1 to 7 , and describe the structure of the chip varistor T1 according to the present embodiment. Figure 1 is a perspective view of the chip varistor according to the present embodiment. Figure 2 and Figure 3 are views showing a cross-sectional structure of the chip varistor according to the present embodiment. Figure 4 and Figure 5 are views showing a cross-sectional structure of a sintered metal layer. Figure 6 and Figure 7It is a diagram showing the structure of the surface of the sintered metal layer. In the present embodiment, the electronic component is, for example, a chip varistor T1. Hereinafter, the structure of the chip varistor T1 according to the present embodiment will be described.

[0036] As Figure 1 ~As Figure 3 shown, the chip varistor T1 includes a ceramic body 3, internal electrodes 5, and external electrodes 7. The ceramic body 3 is, for example, in the shape of a rectangular parallelepiped. In this specification, the shape of a rectangular parallelepiped includes the shape of a rectangular parallelepiped with chamfered corners and edges or the shape of a rectangular parallelepiped with rounded corners and edges. The internal electrodes 5 are disposed within the ceramic body 3. The external electrodes 7 are disposed on the ceramic body 3. In Figure 1 it, the illustration of the internal electrodes 5 is omitted.

[0037] The ceramic body 3 has a pair of side surfaces 3a facing each other, a pair of side surfaces 3c facing each other, and a pair of side surfaces 3e facing each other. Each of the side surfaces 3a, 3c, 3e is rectangular. In this specification, a rectangle includes, for example, a shape with chamfered corners or a shape with rounded corners.

[0038] A pair of side surfaces 3a face each other in the first direction D1. A pair of side surfaces 3c face each other in the second direction D2. The side surfaces 3e face each other in the third direction D3. The first direction D1 intersects the second direction D2 and intersects the third direction D3. The second direction D2 intersects the third direction D3, for example. For example, the first direction D1, the second direction D2, and the third direction D3 are orthogonal to each other. The side surface 3a is orthogonal to the first direction D1. The side surface 3c is orthogonal to the second direction D2. The side surface 3e is orthogonal to the third direction D3.

[0039] The side surface 3e extends in the first direction D1 so as to connect a pair of side surfaces 3a. The side surface 3e extends in the second direction D2 so as to connect a pair of side surfaces 3c. The side surface 3a extends in the third direction D3 so as to connect a pair of side surfaces 3e. The side surface 3c extends in the third direction D3 so as to connect a pair of side surfaces 3e.

[0040] The chip varistor T1 is, for example, soldered and mounted on an electronic device. The electronic device includes, for example, a circuit board or other electronic components. In the chip varistor T1, one of the four side surfaces 3a, 3c faces the electronic device. One of the four side surfaces 3a, 3c is disposed so as to form a mounting surface. One of the four side surfaces 3a, 3c is the mounting surface.

[0041] The ceramic body 3 includes a laminated structure in which a plurality of ceramic layers are laminated. In the present embodiment, the lamination direction of the plurality of ceramic layers coincides with the first direction D1. Each ceramic layer includes a sintered body exhibiting a varistor characteristic. The ceramic body 3 contains, for example, a semiconductor ceramic material. In the actual ceramic body 3, the respective ceramic layers are integrated to the extent that the boundaries between the respective ceramic layers cannot be recognized. The ceramic body 3 includes a varistor body.

[0042] The ceramic body 3 is mainly composed of ZnO (zinc oxide). The ceramic body 3 contains, for example, as sub-components, metallic elements including Co, rare earth metal elements (for example, Pr), Group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkaline earth metal elements (Mg, Ca, Sr, Ba). The ceramic body 3 may also contain oxides of the above metallic elements as sub-components. In the present embodiment, the ceramic body 3 contains Co, Pr, Cr, Ca, K, and Al as sub-components.

[0043] When the total content of all the materials constituting the ceramic body 3 is 100% by weight, the content of ZnO is, for example, 99.8 to 69.0% by weight. The content of the rare earth metal element (Pr) in the ceramic body 3 is, for example, about 0.01 to 10 atomic %. The rare earth metal element can exhibit a varistor characteristic.

[0044] The chip varistor T1 includes a covering layer 9. The covering layer 9 is disposed on the outer surfaces of the ceramic body 3, that is, a pair of side surfaces 3a, a pair of side surfaces 3c, and a pair of side surfaces 3e. The covering layer 9 covers the outer surfaces of the ceramic body 3. In the present embodiment, substantially the entire outer surface of the ceramic body 3 is covered. The covering layer 9 is, for example, directly disposed on the outer surface of the ceramic body 3. The covering layer 9 contains a glass material. The thickness of the covering layer 9 is, for example, 0.01 to 10 μm. In the present embodiment, the thickness of the covering layer 9 is 0.1 μm. The glass material includes, for example, SiO 2 -Al 2 O 3 -LiO 2 type crystallized glass. The glass material may also contain amorphous glass. The chip varistor T1 may also not include the covering layer 9.

[0045] The chip varistor T1 has, for example, a 0402 size in JIS notation. The 0402 size in JIS notation corresponds to the 01005 size in EIA notation. In this case, the length of the ceramic body 3 in the first direction D1 is, for example, about 0.2 mm. The length of the ceramic body 3 in the second direction D2 is about 0.2 mm. The length of the ceramic body 3 in the third direction D3 is about 0.4 mm.

[0046] As Figure 2 and Figure 3As shown, the chip varistor T1 includes a plurality of internal electrodes 5. In the present embodiment, the chip varistor T1 includes a pair of internal electrodes 5. The internal electrodes 5 face each other in the first direction D1. The pair of internal electrodes 5 are disposed within the ceramic green body 3. The internal electrodes 5 face the corresponding side surfaces 3a, respectively. The internal electrodes 5 are respectively connected to the corresponding external electrodes 7. The internal electrodes 5 are electrically and physically connected to the corresponding external electrodes 7.

[0047] When observed from the first direction D1, the pair of internal electrodes 5 have an overlapping region with each other. The pair of internal electrodes 5 are separated from each other in the first direction D1. The internal electrodes 5 respectively have a pair of surfaces facing each other in the first direction D1. One of the pair of surfaces of the internal electrode 5 faces the corresponding side surface 3a. The other of the pair of surfaces of the internal electrode 5 faces the other internal electrode 5.

[0048] The pair of internal electrodes 5 respectively have ends exposed from the corresponding side surfaces 3e. The ends of the pair of internal electrodes 5 each protrude from the corresponding side surface 3e and penetrate the covering layer 9. The ends of the pair of internal electrodes 5 each include a portion exposed from the covering layer 9. Except for the above-mentioned ends exposed from the covering layer 9, the pair of internal electrodes 5 are located within the ceramic green body 3.

[0049] When observed from the first direction D1, the pair of internal electrodes 5 are respectively rectangular, for example. In each of the pair of internal electrodes 5, the length in the third direction D3 is greater than the length in the second direction D2, for example. The sizes of the pair of internal electrodes 5 are substantially the same as each other. The thickness of the internal electrode 5 in the first direction D1 is, for example, 0.5 to 4.0 μm. The length of the internal electrode 5 in the second direction D2 is, for example, 100 μm. The length of the internal electrode 5 in the third direction D3 is, for example, 300 μm.

[0050] The pair of internal electrodes 5 each contain a noble metal or a noble metal alloy. The noble metal includes, for example, Ag, Pd, Au, or Pt. The noble metal alloy includes, for example, an Ag-Pd alloy. The internal electrode 5 may also contain a base metal or a base metal alloy. The base metal includes, for example, Cu or Ni. The internal electrode 5 is an internal conductor disposed within the ceramic green body 3 and contains a conductive material commonly used as an internal electrode of a multilayer electronic component. The conductive material includes, for example, a base metal. The conductive material includes, for example, Ni or Cu. The internal electrode 5 is formed as a sintered body of a conductive paste containing the above-mentioned types of conductive materials.

[0051] As Figures 1 to 3As shown, the chip varistor T1 includes a plurality of external electrodes 7. The chip varistor T1 includes, for example, a pair of external electrodes 7. The pair of external electrodes 7 are disposed on the ceramic green body 3. The pair of external electrodes 7 are disposed on the outer surface of the ceramic green body 3. The pair of external electrodes 7 are disposed, for example, at both ends in the third direction D3 of the ceramic green body 3. The pair of external electrodes 7 face each other in the third direction D3 with the ceramic green body 3 interposed therebetween. The pair of external electrodes 7 are separated from each other in the third direction D3.

[0052] The pair of external electrodes 7 are disposed, for example, on the covering layer 9. The pair of external electrodes 7 are physically and electrically connected to the corresponding internal electrodes 5 at the portions of the pair of internal electrodes 5 that are exposed from the covering layer 9, respectively. The covering layer 9 includes a portion covered by the pair of external electrodes 7 and a portion not covered by the pair of external electrodes 7.

[0053] The pair of external electrodes 7 are respectively disposed on the corresponding sides of the pair of side surfaces 3e. The pair of external electrodes 7 are disposed, for example, on the side surfaces 3e and on a part of each of the four side surfaces 3a, 3c. The above-mentioned part of each of the side surfaces 3a, 3c is a part of the area of each of the side surfaces 3a, 3c that is close to the side surface 3e. In the present embodiment, the pair of external electrodes 7 respectively cover the entire corresponding side surface 3e. The pair of external electrodes 7 cover the corners formed by the side surface 3e and the four side surfaces 3a, 3c and the ridge lines connecting the corners to each other.

[0054] The external electrode 7 includes a sintered metal layer 7a. The sintered metal layer 7a is formed by applying a conductive paste on the outer surface of the ceramic green body 3 and then performing sintering. The conductive paste includes metal powder, glass component, organic binder, and organic solvent. The sintered metal layer 7a is formed by sintering the metal components (metal powder) contained in the conductive paste. The sintered metal layer 7a includes a layer formed by sintering the metal powder contained in the conductive paste. The metal powder contained in the conductive paste includes metal powder of noble metal and metal powder of base metal. The noble metal includes Ag. The noble metal may also include Au, Pt, or Pd. The base metal may also include Cu or Ni. In the present embodiment, the sintered metal layer 7a includes Ag and Cu.

[0055] The external electrode 7 includes at least one plating layer on the sintered metal layer 7a. In the present embodiment, the external electrode 7 includes, for example, two plating layers 7b and 7c on the sintered metal layer 7a. The sintered metal layer 7a is a base layer for forming the plating layers 7b and 7c. The plating layer 7b is located between the sintered metal layer 7a and the plating layer 7c. The plating layer 7b includes, for example, a Ni plating layer. The plating layer 7b may also include a Sn plating layer, a Cu plating layer, or an Au plating layer instead of the Ni plating layer. The plating layer 7c includes a solder plating layer. The solder plating layer includes a Sn plating layer, a Sn-Ag alloy plating layer, a Sn-Bi alloy plating layer, or a Sn-Cu alloy plating layer. These plating layers are formed by a plating method. The plating method includes, for example, an electroplating method. The external electrode 7 may also include three plating layers on the sintered metal layer 7a. The thickness of the external electrode 7 is, for example, 10 to 30 μm.

[0056] Figure 4 is a view showing the structure of the cross section of the sintered metal layer 7a. Figure 5 is a view obtained by magnifying a part of the structure of the cross section of the sintered metal layer 7a. Figure 4 and Figure 5 is a view showing the structure of the cross section of the sintered metal layer 7a when cut by a plane parallel to the side surface 3c.

[0057] The sintered metal layer 7a has a region R1, a region R2 adjacent to the region R1, and a region R3 adjacent to the region R2. The region R1 includes a plurality of crystal grains CG1. The plurality of crystal grains CG1 are each formed of a first metal. The region R2 includes a plurality of crystal grains CG2. The plurality of crystal grains CG2 are each formed of a second metal. The second metal is different from the first metal. In the present embodiment, the first metal includes Ag, and the second metal includes Cu. The crystal grain CG1 includes Ag particles, and the crystal grain CG2 includes Cu particles. The region R3 includes glass G1. The glass G1 contains, for example, SiO 2 or B 2 O 3 .

[0058] For example, when the region R1 includes a first region, the region R2 includes a second region, and the region R3 includes a third region. For example, when the crystal grain CG1 includes a first crystal grain, the crystal grain CG2 includes a second crystal grain.

[0059] In the cross-section of the sintered metal layer 7a, the individual ones of the plurality of crystal grains CG1 are arranged in contact with each other. The plurality of crystal grains CG1 each have regions sintered to each other. The plurality of crystal grains CG2 include particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 include, for example, particles arranged in contact with each other and located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 contain particles located at positions along the grain boundaries formed along the plurality of crystal grains CG1. The plurality of crystal grains CG2 may also include a plurality of particles arranged along the grain boundaries formed along the plurality of crystal grains CG1. The plurality of crystal grains CG2 may also include particles individually located between the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0060] The cross-section of the sintered metal layer 7a includes the grain boundaries formed by the plurality of crystal grains CG1 and the grain boundaries formed by the plurality of crystal grains CG2. The grain boundaries between the crystal grains CG1 and the crystal grains CG2 include regions where there is no alloy of the first metal and the second metal. In the regions where there is no such alloy, at the portions where the crystal grains CG1 and the crystal grains CG2 are in direct contact with each other, the first metal and the second metal do not alloy with each other.

[0061] The second metal has a greater ionization tendency than the first metal. Therefore, Cu of the second metal reacts more easily with oxygen than Ag of the first metal. In the sintered metal layer 7a, Cu is more likely to exist as an oxide than Ag. In the present embodiment, the oxide of Cu includes, for example, CuО.

[0062] In the cross-section of the sintered metal layer 7a, the area of region R1 is larger than the area of region R2. That is, in the cross-section, the area ratio of region R1 to region R2 is greater than 1. The area of region R1 is the total area of the plurality of crystal grains CG1 exposed in the cross-section of the sintered metal layer 7a. The area of region R2 is the total area of the plurality of crystal grains CG2 exposed in the cross-section of the sintered metal layer 7a. In the sintered metal layer 7a, the proportion of the existence of region R1 and region R2 is greater than 1 in terms of the area ratio of region R1 to region R2.

[0063] The area ratio of regions R1 and R2 is obtained, for example, as follows.

[0064] At the position including regions R1 and R2, a cross-section photograph of the ceramic green body 3 is taken. The cross-section photograph is, for example, a photograph obtained by photographing the cross-section when the sintered metal layer 7a is cut by a plane orthogonal to the thickness direction of the sintered metal layer 7a. The cross-section is, for example, parallel to the side surface 3c. The cross-section photograph may also be, for example, a photograph obtained by photographing the cross-section of the sintered metal layer 7a when it is cut by a plane parallel to the side surface 3a or the side surface 3e. The cross-section photograph is, for example, an SEM (scanning electron microscope) photograph. The SEM photograph includes, for example, a composite image photograph.

[0065] In the calculation of the areas of regions R1 and R2, software is used to perform image processing on the acquired cross-sectional photographs. Based on the results of this image processing, the boundaries of each crystal grain CG1 and each crystal grain CG2 are distinguished, and the areas of the crystal grains CG1 and CG2 are calculated respectively. The area of region R1 is calculated as the product of the number of crystal grains CG1 contained in region R1 in the acquired cross-sectional photograph and the area of crystal grain CG1. The area of region R2 is calculated as the product of the number of crystal grains CG2 contained in region R2 in the acquired cross-sectional photograph and the area of crystal grain CG2.

[0066] The area ratio of region R1 to region R2 is obtained as the ratio of the area of region R1 calculated as described above to the area of region R2 calculated as described above.

[0067] Regarding the particle sizes of the crystal grains CG1 and CG2, for example, the areas of the crystal grains CG1 and CG2 calculated as described above are calculated as the particle sizes converted into the equivalent circle diameter. In the present embodiment, the particle sizes of all the crystal grains CG1 contained in region R1 can be calculated, and the particle sizes of all the crystal grains CG2 contained in region R2 can also be calculated. The particle sizes of any number of crystal grains CG1 among the crystal grains CG1 contained in region R1 can be calculated, and the particle sizes of any number of crystal grains CG2 among the crystal grains CG2 contained in region R2 can also be calculated. Any number is, for example, 50.

[0068] In the cross-section of the sintered metal layer 7a, the particle sizes of the plurality of crystal grains CG1 are larger than those of the plurality of crystal grains CG2. The particle size of crystal grain CG1 is, for example, 0.4 to 3.6 μm. The particle size of crystal grain CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the particle size of crystal grain CG1 is greater than the minimum value of the particle size of crystal grain CG2. The maximum value of the particle size of crystal grain CG1 is greater than the maximum value of the particle size of crystal grain CG2.

[0069] The sintered metal layer 7a contains glass G1. Glass G1 is contained in region R3. Region R3 is formed between the plurality of crystal grains CG1 when the plurality of crystal grains CG1 are sintered. For example, the glass component contained in the conductive paste for forming the sintered metal layer 7a softens when the sintered metal layer 7a is formed and flows into at least a part of the space between the plurality of crystal grains CG1. The glass component, for example, flows into at least a part of the space between the plurality of crystal grains CG1. The above glass component, for example, fills a part of the space between the plurality of crystal grains CG1. The glass solidified between the plurality of crystal grains CG1 constitutes region R3. There is a second metal around the glass G1 contained in region R3.

[0070] Void V1 is formed in the sintered metal layer 7a. Void V1 is formed when the sintered metal layer 7a is formed. Void V1 exists between the plurality of crystal grains CG1. Region R2 is exposed at void V1. The second metal is exposed at void V1. Void V1 is located between the plurality of crystal grains CG1 and is not filled with glass G1.

[0071] Figure 6 It is a view showing the structure of the surface of the sintered metal layer 7a. Figure 7 It is a view obtained by magnifying a part of the structure of the surface of the sintered metal layer 7a. Figure 6 and Figure 7 illustrate the surface 7s of the sintered metal layer 7a when viewed in the thickness direction of the sintered metal layer 7a. The thickness direction of the sintered metal layer 7a includes, for example, the third direction D3. In the present embodiment, the surface 7s of the sintered metal layer 7a has the same structure as Figure 4 the cross section of the sintered metal layer 7a illustrated.

[0072] In the surface 7s of the sintered metal layer 7a, the respective ones of the plurality of crystal grains CG1 are arranged in contact with each other. The plurality of crystal grains CG1 each have a region sintered to each other. The plurality of crystal grains CG2 include particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 include, for example, particles located between the plurality of crystal grains CG1 in a state of being arranged in contact with each other. The plurality of crystal grains CG2 include particles located at positions along the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0073] The surface 7s of the sintered metal layer 7a includes grain boundaries formed by the plurality of crystal grains CG1 and grain boundaries formed by the plurality of crystal grains CG2. The grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where there is no alloy of the first metal and the second metal. In the region where there is no such alloy, at the portion where the crystal grain CG1 and the crystal grain CG2 are in direct contact with each other, the first metal and the second metal are not alloyed with each other.

[0074] In the surface 7s, the area of the region R1 is larger than the area of the region R2. That is, in the surface, the area ratio of the region R1 to the region R2 is greater than 1. The area of the region R1 is the total area of the plurality of crystal grains CG1 exposed on the surface 7s. The area of the region R2 is the total area of the plurality of crystal grains CG2 exposed on the surface 7s. In the surface 7s, the existence ratio of the region R1 and the region R2 is greater than 1 in terms of the area ratio of the region R1 to the region R2.

[0075] In the surface 7s of the sintered metal layer 7a, the area ratio of the regions R1 and R2 is obtained, for example, in the same procedure as in the case of the cross section of the sintered metal layer 7a described above.

[0076] That is, a surface photograph of the ceramic green body 3 is taken at a position including the region R1 and the region R2. The surface photograph is, for example, a photograph taken of the surface 7s when viewed in the thickness direction of the sintered metal layer 7a. The surface 7s is, for example, parallel to the side surface 3e. The surface photograph may also be a photograph taken of the surface 7s parallel to either one of the side surfaces 3a and 3c. The surface photograph is, for example, an FE-SEM (field emission scanning electron microscope) photograph (for example, a secondary electron image photograph). Hereinafter, the area ratios of the regions R1 and R2 are obtained in the same manner as in the case of the cross section of the sintered metal layer 7a described above.

[0077] Regarding the particle diameters of the crystal grains CG1 and CG2, for example, the areas of the crystal grains CG1 and CG2 calculated as described above are calculated as the particle diameters converted into the equivalent circle diameter. In the surface 7s of the sintered metal layer 7a, a plurality of crystal grains CG1 have a larger particle diameter than a plurality of crystal grains CG2. The particle diameter of the crystal grain CG1 is, for example, 0.4 to 3.6 μm. The particle diameter of the crystal grain CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the particle diameter of the crystal grain CG1 is greater than the minimum value of the particle diameter of the crystal grain CG2. The maximum value of the particle diameter of the crystal grain CG1 is greater than the maximum value of the particle diameter of the crystal grain CG2.

[0078] The surface 7s of the sintered metal layer 7a contains the glass G1. The region R3 is formed between a plurality of crystal grains CG1 when the plurality of crystal grains CG1 forming the surface 7s of the sintered metal layer 7a are sintered. For example, the glass component contained in the conductive paste for forming the sintered metal layer 7a softens when the sintered metal layer 7a is formed and flows into a part between the plurality of crystal grains CG1 located on the surface 7s. The above glass component fills, for example, a part between the plurality of crystal grains CG1 located on the surface 7s.

[0079] Vacancies V1 are formed on the surface 7s of the sintered metal layer 7a. The vacancies V1 are formed when the surface 7s of the sintered metal layer 7a is formed. The vacancies V1 exist between a plurality of crystal grains CG1. The region R2 is exposed at the vacancies V1. The second metal is exposed at the vacancies V1.

[0080] The manufacturing method of the chip varistor T1 will be described.

[0081] In the present embodiment, first, a ceramic green body 3 in which an internal electrode 5 is disposed inside is prepared. The process of preparing the ceramic green body 3 is a known technique in the technical field, and thus more detailed description is omitted.

[0082] After preparing the ceramic green body 3 internally provided with the internal electrode 5, the external electrode 7 is formed. In the formation of the external electrode 7, a conductive paste is applied to the side surface 3e of the ceramic green body 3. In the present embodiment, the conductive paste for the external electrode 7 contains Ag particles, Cu particles, a glass component, and an organic binder. In the conductive paste, the content rate of the Ag particles is, for example, 65 to 80% by weight. The content rate of the Cu particles is, for example, 1 to 4% by weight. The content rate of the glass component is, for example, 3 to 7% by weight. The glass component contains, for example, SiO 2 or B 2 O 3 . In the conductive paste, the particle size of the Ag particles is, for example, 0.04 to 9.0 μm. The particle size of the Cu particles is, for example, 0.15 to 0.7 μm.

[0083] Next, in the firing furnace, the conductive paste is fired to form the sintered metal layer 7a. Through the firing process, the conductive paste is fired to form the sintered metal layer 7a. The firing process of the conductive paste includes, for example, a first temperature-raising process, a first heat-preserving process, a second temperature-raising process, a second heat-preserving process, and a temperature-lowering process. In the first heat-preserving process after the first temperature-raising process, the organic binder is removed. After the first heat-preserving process, in the second temperature-raising process, the glass is melted. After the glass starts to melt, the sintering of Ag starts. The temperature at which the sintering of Ag starts is higher than the case where the conductive paste does not contain Cu. At the temperature at which the sintering of Ag starts, Cu is not easily melted and remains in a solid state. Cu has a melting point higher than that of Ag. Cu reduces the contact between the first metals and delays the start of the sintering of Ag. For example, in the second temperature-raising process, Cu forms an oxide.

[0084] Among the sintered Ag, a plurality of voids V1 are formed. Cu inhibits the contact between the plurality of Ag, and at the plurality of voids V1, Cu is easily exposed. In the present embodiment, during the second temperature-raising process, the softened glass flows into the spaces between the plurality of Ag.

[0085] After passing through the second heat-preserving process and the temperature-lowering process, the sintered metal layer 7a is formed. The glass G1 that has flowed into the spaces between the plurality of Ag solidifies. In the present embodiment, then, for example, by a wet plating method, plating layers 7b and 7c are formed on the sintered metal layer 7a. The wet plating method includes an electroplating method.

[0086] Through the above process, the chip varistor T1 is manufactured. In the present embodiment, the ceramic green body 3 may also be subjected to an annealing treatment. The ceramic green body 3 may not be subjected to an annealing treatment.

[0087] In the chip varistor T1, in the sintered metal layer 7a, the content rate of the Ag particles is, for example, 88 to 94% by weight. The content rate of the copper oxide particles is, for example, 2 to 4% by weight. The content rate of the glass is, for example, 4 to 8% by weight. The copper oxide includes, for example, CuО.

[0088] As described above, in the chip varistor T1, the presence ratio of region R1 to region R2 is greater than 1 in terms of the area ratio of region R1 to region R2. A plurality of crystal grains CG2 included in region R2 are likely to be in contact with a plurality of crystal grains CG1 included in region R1 whose area ratio is greater than that of region R2. The plurality of crystal grains CG2 reduce the contact between the plurality of crystal grains CG1. The glass G1 included in region R3 can be in contact with region R2 and exists between the plurality of crystal grains CG1 whose contact with each other has been reduced. The denseness of the sintered metal layer 7a is increased. Therefore, the deterioration of the characteristics of the chip varistor T1 is suppressed. The characteristics of the chip varistor T1 include, for example, electrical characteristics.

[0089] In a chip varistor, a sintered metal layer without a second metal tends to have a structure in which glass oozes out to the surface of the sintered metal layer. In the sintered metal layer 7a containing a second metal, the glass G1 is not likely to ooze out from the surface 7s of the sintered metal layer 7a. The floating of the glass to the surface 7s of the sintered metal layer 7a is reduced. In the chip varistor T1, the glass G1 existing between the plurality of crystal grains CG1 increases the denseness of the sintered metal layer 7a.

[0090] In the chip varistor T1, in the cross-section of the sintered metal layer 7a, the area ratio of region R1 to region R2 is greater than 1.

[0091] In the chip varistor T1, in the above cross-section, a plurality of crystal grains CG2 are more likely to be in contact with a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 included in region R3 can be further in contact with region R2 and exists between the plurality of crystal grains CG1 whose contact with each other has been reduced. The denseness of the sintered metal layer 7a is further increased. Therefore, the deterioration of the characteristics of the chip varistor T1 can be reliably suppressed.

[0092] In the chip varistor T1, in the cross-section of the sintered metal layer, the plurality of crystal grains CG1 have a larger particle size than the plurality of crystal grains CG2.

[0093] In the chip varistor T1, in the above cross-section, a plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 included in region R3 can be further in contact with region R2 and exists between the plurality of crystal grains CG1 whose contact with each other has been reduced. The denseness of the sintered metal layer 7a is further increased. Therefore, the deterioration of the characteristics of the chip varistor T1 can be more reliably suppressed.

[0094] In the chip varistor T1, in the surface 7s of the sintered metal layer 7a, the area ratio of region R1 to region R2 is greater than 1.

[0095] In the chip varistor T1, on the surface 7s, a plurality of crystal grains CG2 are more likely to contact a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, the characteristic deterioration of the chip varistor T1 can be reliably suppressed.

[0096] In the chip varistor T1, on the surface 7s of the sintered metal layer 7a, a plurality of crystal grains CG1 have a larger particle size than a plurality of crystal grains CG2.

[0097] In the chip varistor T1, on the surface 7s, a plurality of crystal grains CG2 are likely to be located between a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, the characteristic deterioration of the chip varistor T1 can be more reliably suppressed.

[0098] In the chip varistor T1, voids V1 exposing the region R2 are formed in the sintered metal layer 7a.

[0099] The chip varistor T1 relieves the stress acting on the sintered metal layer 7a and suppresses the generation of cracks in the ceramic green body 3. Therefore, the characteristic deterioration of the chip varistor T1 can be more reliably suppressed.

[0100] In the chip varistor T1, the grain boundary between the crystal grains CG1 and the crystal grains CG2 includes a region where there is no alloy of the first metal and the second metal.

[0101] In the region where there is no alloy of the first metal and the second metal, the first metal and the second metal exist independently of each other. In the chip varistor T1, a plurality of crystal grains CG2 are likely to be located between a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, the characteristic deterioration of the chip varistor T1 can be more reliably suppressed.

[0102] In the chip varistor T1, the second metal has a higher melting point than the first metal.

[0103] In the chip varistor T1, the second metal is more likely to remain in a solid state than the first metal. The plurality of crystal grains CG2 further reduces the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, the deterioration of the characteristics of the chip varistor T1 can be more reliably suppressed.

[0104] In the chip varistor T1, the second metal has a greater ionization tendency than the first metal.

[0105] In the chip varistor T1, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. The plurality of crystal grains CG2 further reduces the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, the deterioration of the characteristics of the chip varistor T1 can be more reliably suppressed.

[0106] In the chip varistor T1, the second metal contained in the region R2 easily inhibits the sintering of the first metal contained in the region R1. In the sintered metal layer 7a where the sintering of the first metal is inhibited, the molten glass easily flows between the plurality of crystal grains CG1. In the sintered metal layer without the second metal, since the sintering of the first metal proceeds first, the molten glass is not easily flowed between the plurality of crystal grains CG1.

[0107] In the chip varistor T1, for example, when a plating layer is formed on the sintered metal layer 7a by a wet plating method, the glass G1 also inhibits the inflow of the moisture-containing plating solution into the sintered metal layer 7a. The glass G1 inhibits the moisture-containing plating solution from passing through the sintered metal layer 7a and reaching the interface between the sintered metal layer 7a and the ceramic green body 3. The deterioration of the characteristics of the chip varistor T1 can be more reliably suppressed.

[0108] The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

[0109] The plurality of crystal grains CG1 may also not have a particle size larger than that of the plurality of crystal grains CG2. In a structure where the plurality of crystal grains CG1 have a particle size larger than that of the plurality of crystal grains CG2, as described above, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, deterioration of the characteristics of the chip varistor T1 can be more reliably suppressed.

[0110] The grain boundary between the crystal grains CG1 and the crystal grains CG2 may also not contain a region where there is no alloy of the first metal and the second metal. In a structure where the grain boundary between the crystal grains CG1 and the crystal grains CG2 contains a region where there is no alloy of the first metal and the second metal, as described above, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, deterioration of the characteristics of the chip varistor T1 can be further reliably suppressed.

[0111] The second metal may also not have a melting point higher than that of the first metal. In a structure where the second metal has a melting point higher than that of the first metal, as described above, the second metal is more likely to remain in a solid state than the first metal. The plurality of crystal grains CG2 further reduce the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, deterioration of the characteristics of the chip varistor T1 can be further reliably suppressed.

[0112] The second metal may also not have a larger ionization tendency than the first metal. In a structure where the second metal has a larger ionization tendency than the first metal, as described above, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. The plurality of crystal grains CG2 further reduce the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 can further contact the region R2 and exists between the plurality of crystal grains CG1 with reduced contact with each other. The density of the sintered metal layer 7a is further increased. Therefore, deterioration of the characteristics of the chip varistor T1 can be further reliably suppressed.

[0113] In the above-described embodiment, a chip varistor is taken as an example of an electronic component for illustration, but the applicable electronic components are not limited to chip varistors. Applicable electronic components are, for example, electronic components such as capacitors, inductors, piezoelectric actuators, thermistors, solid battery components, or composite components. The applicable electronic components may also be multilayer electronic components.

Claims

1. An electronic component, wherein: have: Ceramic body; and a sintered metal layer disposed on the ceramic body, The sintered metal layer has: a first region including a plurality of first grains formed of a first metal; a second region connected to the first region and including a plurality of second crystal grains formed of a second metal different from the first metal; and a third region adjoining the second region and comprising glass, The existence ratio of the first region to the second region is greater than 1 in terms of an area ratio of the first region to the second region.

2. The electronic component according to claim 1, wherein In a cross section of the sintered metal layer, an area ratio of the first region to the second region is greater than 1.

3. The electronic component according to claim 2, wherein: In the cross section, the plurality of first crystal grains have a grain size larger than a grain size of the plurality of second crystal grains.

4. The electronic component according to claim 1, wherein In the surface of the sintered metal layer, an area ratio of the first region to the second region is greater than 1.

5. The electronic component according to claim 4, wherein In the surface, the plurality of first crystal grains have a grain size larger than a grain size of the plurality of second crystal grains.

6. The electronic component according to any one of claims 1 to 5, wherein The sintered metal layer has holes formed therein in which the second region is exposed.

7. The electronic component according to any one of claims 1 to 6, wherein The grain boundary between the first crystal grain and the second crystal grain includes a region where the alloy of the first metal and the second metal does not exist.

8. The electronic component according to any one of claims 1 to 7, wherein The second metal has a melting point higher than that of the first metal.

9. The electronic component according to any one of claims 1 to 8, wherein The second metal has an ionization tendency greater than that of the first metal.

10. The electronic component according to any one of claims 1 to 9, wherein The ceramic body contains a semiconductor ceramic material.

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