Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. A first metal layer is arranged on the surface of a semiconductor substrate, the first metal layer comprises a reserved hole, a dielectric material layer is formed on the first metal layer and the inner surface of the reserved hole, part of the dielectric material layer is removed to expose the reserved hole, the dielectric material layer in the reserved hole is removed, and the reserved hole is formed on the surface of the semiconductor substrate. And forming a second metal layer on the surface of the dielectric material layer, filling the second metal layer in the opening and the preformed hole, and connecting the second metal layer with the first metal layer to form a metal connection structure. The bottom of the through hole part in the generated metal connection structure is embedded in the first metal layer, so that the influence of the thermal stress change of the low dielectric constant material on the metal connection structure is reduced, the hole of the metal connection structure caused by the thermal stress is avoided, and the reliability of the product is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In an interconnect system, in order to solve the problem of resistance-capacitance (RC) delay, low dielectric constant (low-k) materials are usually introduced. However, low dielectric constant materials have low hardness, low density, poor adhesion, and a large difference in thermal stress parameters from surrounding materials. In the manufacturing process of an interconnect structure, when a low dielectric constant material changes from a high temperature to a low temperature, the residual thermal stress generated during the temperature cycle will induce the generation of voids, which will further lead to stress migration reliability problems. It is found that stress migration mostly occurs at the junction of the bottom of a via hole and the lower metal layer.

[0003] How to provide a method for manufacturing a semiconductor structure to solve the stress migration problem of a metal connection structure is of great significance for improving the reliability of products. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can solve the stress migration problem of a metal connection structure.

[0005] To solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, including: providing a semiconductor substrate, the surface of the semiconductor substrate includes a first metal layer, and the first metal layer includes reserved holes; forming a dielectric material layer on the surface of the first metal layer and in the reserved holes; removing a part of the dielectric material layer to form an opening penetrating through the dielectric material layer, the opening exposing the reserved holes; removing the dielectric material layer in the reserved holes; forming a second metal layer, the second metal layer filling the opening and the reserved holes and being connected to the first metal layer, and the second metal layer serving as a metal connection structure.

[0006] In some embodiments, the semiconductor substrate further includes a diffusion barrier layer, and the first metal layer is disposed on the surface of the diffusion barrier layer.

[0007] In some embodiments, the depth of the reserved holes is less than or equal to the thickness of the first metal layer.

[0008] In some embodiments, the dielectric material is a low dielectric constant material.

[0009] In some embodiments, the materials of the first metal layer and the second metal layer are copper.

[0010] In some embodiments, in the step of forming an opening penetrating the dielectric material layer by removing a part of the dielectric material layer of the removed part, a photolithography and etching process is used to remove a part of the dielectric material layer.

[0011] In some embodiments, the width of the opening is greater than or equal to the width of the reserved hole.

[0012] In some embodiments, after the step of removing the dielectric material layer in the reserved hole, it further includes: trimming the opening into an open shape.

[0013] In some embodiments, in the step of forming a second metal layer on the surface of the dielectric material layer, where the second metal layer fills the opening and the reserved hole and is connected to the first metal layer, it further includes: forming a barrier layer on the inner walls of the opening and the reserved hole; forming a seed layer on the surface of the barrier layer; forming a second metal material layer covering the surface of the dielectric material layer and filling the opening and the reserved hole; planarizing the second metal material layer until the dielectric material layer is exposed, and the remaining second metal material layer in the opening and the reserved hole forms the second metal layer, and the second metal layer serves as the metal connection structure and is connected to the first metal layer.

[0014] In some embodiments, an electroplating process is used to form the second metal material layer on the surface of the dielectric material layer.

[0015] To solve the above problems, the present invention also provides a semiconductor structure, including: a semiconductor substrate, the surface of the semiconductor substrate includes a first metal layer, and the first metal layer includes a reserved hole; a dielectric material layer, formed on the surface of the first metal layer, the dielectric material layer includes an opening penetrating the dielectric material layer and exposing the reserved hole; a second metal layer, the second metal layer fills the opening and the reserved hole and is connected to the first metal layer, and the second metal layer serves as a metal connection structure.

[0016] In some embodiments, the depth of the reserved hole is less than or equal to the thickness of the first metal layer.

[0017] In some embodiments, the material of the dielectric material layer includes a low dielectric constant material.

[0018] In some embodiments, the materials of the first metal layer and the second metal layer are the same.

[0019] In some embodiments, a seed layer and a barrier layer are provided on the outer wall of the metal connection structure.

[0020] In the above technical solution, a first metal layer is disposed on the surface of the semiconductor substrate. The first metal layer includes reserved holes. A dielectric material layer is formed on the surface of the first metal layer and within the reserved holes. Part of the dielectric material layer is removed to expose the reserved holes. The dielectric material layer within the reserved holes is removed. A second metal layer is formed on the surface of the dielectric material layer, fills the openings and the reserved holes, and is interconnected with the first metal layer, thereby forming a metal connection structure. The bottom of the through-hole portion in the generated metal connection structure is embedded in the first metal layer, reducing the influence of the thermal stress change of the low dielectric constant material on the metal connection structure, and further avoiding the holes in the metal connection structure caused by thermal stress, improving the reliability of the product.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technologies, methods, and devices should be regarded as part of the authorization specification. Brief Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0024] Figure 2 is a flowchart of the steps for forming a metal connection structure provided by an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a device structure formed by the step of providing a semiconductor substrate provided by an embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a device structure formed by the step of forming a dielectric material layer provided by an embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of a device structure formed by the step of removing part of the dielectric material layer to expose the reserved holes provided by an embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of a device structure formed by the step of removing the dielectric material layer within the reserved holes provided by an embodiment of the present invention;

[0029] Figure 7 It is a schematic diagram of a device structure formed by the step of trimming the opening provided in an embodiment of the present invention;

[0030] Figure 8 It is a schematic diagram of a device structure formed by the step of forming a barrier layer on the inner walls of the opening and the reserved hole provided in an embodiment of the present invention;

[0031] Figure 9 It is a schematic diagram of a device structure formed by the step of forming a seed layer on the surface of the barrier layer provided in an embodiment of the present invention;

[0032] Figure 10 It is a schematic diagram of a device structure formed by the step of forming a second metal material layer on the surface of the dielectric material layer provided in an embodiment of the present invention;

[0033] Figure 11 It is a schematic diagram of a device structure formed by the step of planarizing the second metal material layer provided in an embodiment of the present invention.

[0034] List of reference numerals:

[0035] 10 Semiconductor substrate

[0036] 101 Substrate

[0037] 102 Insulating layer

[0038] 103 Diffusion barrier layer

[0039] 104 Connection structure

[0040] 11 First metal layer

[0041] 12 Dielectric material layer

[0042] 13 Barrier layer

[0043] 14 Seed layer

[0044] 15 Metal connection structure

[0045] 150 Second metal material layer

[0046] 16 Damascene structure

[0047] 18 Opening

[0048] 19 Reserved hole Detailed implementation manners

[0049] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0051] As Figure 1 shown, the method for manufacturing the semiconductor structure includes: Step S11, providing a semiconductor substrate, the semiconductor substrate includes a first metal layer, and the first metal layer includes reserved holes; Step S12, forming a dielectric material layer on the surface of the first metal layer and in the reserved holes; Step S13, removing a part of the dielectric material layer to form an opening penetrating the dielectric material layer, and the opening exposes the reserved holes; Step S14, removing the dielectric material layer in the reserved holes; Step S15, forming a second metal layer, the second metal layer fills the opening and the reserved holes and is connected to the first metal layer, and the second metal layer serves as a metal connection structure.

[0052] Please refer to Figures 2 to 11 together, where Figure 2 is a flowchart of the steps for forming a metal connection structure according to an embodiment of the present invention; Figure 3 is a schematic diagram of a device structure formed by the step of providing a semiconductor substrate according to an embodiment of the present invention; Figure 4 is a schematic diagram of a device structure formed by the step of forming a dielectric material layer according to an embodiment of the present invention; Figure 5 is a schematic diagram of a device structure formed by the step of removing a part of the dielectric material layer to expose the reserved holes according to an embodiment of the present invention; Figure 6 is a schematic diagram of a device structure formed by the step of removing the dielectric material layer in the reserved holes according to an embodiment of the present invention; Figure 7 is a schematic diagram of a device structure formed by the step of trimming the opening according to an embodiment of the present invention; Figure 8 is a schematic diagram of a device structure formed by the step of forming a barrier layer on the inner walls of the opening and the reserved holes according to an embodiment of the present invention; Figure 9 is a schematic diagram of a device structure formed by the step of forming a seed layer on the surface of the barrier layer according to an embodiment of the present invention; Figure 10 is a schematic diagram of a device structure formed by the step of forming a second metal material layer on the surface of the dielectric material layer according to an embodiment of the present invention; Figure 11 is a schematic diagram of a device structure formed by the step of planarizing the second metal material layer according to an embodiment of the present invention.

[0053] Referring to step S11 and Figure 3 , a semiconductor substrate 10 is provided. The surface of the semiconductor substrate 10 includes a first metal layer 11, and a reserved hole 19 is included in the first metal layer 11. As Figure 2 shown, the semiconductor substrate 10 includes: a substrate 101 and an insulating layer 102.

[0054] Among them, the material of the insulating layer 102 is phosphosilicate glass (PSG for short). PSG is a binary glass composed of silicon and phosphorus. Due to the introduction of phosphorus, the fluidity of PSG is enhanced, and it can level at a lower temperature and is used to smooth the underlying layer. In the semiconductor manufacturing process, it is usually used as the inter-metal layer in semiconductor device manufacturing, that is, the insulating layer deposited between consecutive higher metal layers or conductive layers. As Figure 3 shown, a connection structure 104 is further included in the insulating layer 102, and the material of the connection structure 104 is metal.

[0055] In this embodiment, the material of the first metal layer 11 is copper (Cu). The first metal layer 11 is a patterned metal layer. The pattern of the reserved hole 19 is added to the first photomask used to form the patterned first metal layer 11. Correspondingly, in addition to the pattern of the connection line, the pattern of the reserved hole 19 is also generated in the patterned first metal layer 11.

[0056] The depth of the reserved hole 19 is less than or equal to the thickness of the first metal layer 11. In this embodiment, the depth of the reserved hole 19 is the same as the thickness of the first metal layer 11, that is, the bottom of the reserved hole 19 reaches the semiconductor substrate 10 directly.

[0057] In some embodiments, the depth of the reserved hole 19 is less than the thickness of the first metal layer 11, that is, the bottom of the reserved hole 19 is located inside the first metal layer 11.

[0058] A diffusion barrier layer 103 is further formed on the semiconductor substrate 10, and the first metal layer 11 is disposed on the surface of the diffusion barrier layer 103. In this embodiment, the material of the diffusion barrier layer 103 is nitride-doped silicon carbide (NDC for short). The thin film of NDC material is a thin film containing four elements of nitrogen (N), silicon (Si), hydrogen (H), and carbon (C), and can prevent the diffusion of metal copper into the medium.

[0059] In this embodiment, the diffusion barrier layer 103 made of NDC is in contact with metallic copper. It maintains a low dielectric constant (K) and does not contain copper or oxygen elements, thus ensuring good electrical reliability. The diffusion barrier layer 103 made of NDC can also improve the etching selectivity of the diffusion barrier layer 103 at the same time, has good sealing performance, and blocks the diffusion of external moisture and oxygen elements into metallic copper.

[0060] Refer to step S12 and Figure 4 , a dielectric material layer 12 is formed on the surface of the first metal layer 11 and within the reserved holes 19. Among them, the material of the dielectric material layer 12 is a low dielectric constant material. For example, the material of the dielectric material layer 12 is any one of Polyethylene Oxide (PEOX) or Black Diamond (BD).

[0061] In this step, the dielectric material layer 12 is formed on the surface of the first metal layer 11 by means of thin film deposition. The dielectric material layer 12 fills the reserved holes 19 at the same time.

[0062] Refer to step S13 and Figure 5 , a part of the dielectric material layer 12 is removed to expose the reserved holes 19, and an opening 18 is formed in the dielectric material layer. In this step, a part of the dielectric material layer 12 is removed by means of photolithography and etching processes. Figure 5 The exposed part of the dielectric material layer 12 in

[0063] is the opening 18. During the photolithography of the opening 18, the position of the pattern corresponding to the opening 18 in the second photomask is the same as the position of the pattern corresponding to the reserved holes 19 in the first photomask.

[0064] In some embodiments, the width of the opening 18 is greater than the width of the reserved holes 19. Correspondingly, in the second photomask used for photolithographing the opening 18, the width of the pattern corresponding to the opening 18 is greater than the width of the pattern corresponding to the reserved holes 19 in the first photomask.

[0065] Refer to step S14 and Figure 6, remove the dielectric material layer 12 in the reserved hole 19 to make the opening 18 communicate with the reserved hole 19. In this embodiment, the opening 18 reaches the diffusion barrier layer 103 through the reserved hole 19.

[0066] Reference Figure 7 , further include after step S14: trim the opening 18 into an open shape. In this embodiment, etch the opening 18, for example, etch the opening 18 into a damascene structure 16 communicating with the reserved hole 19. The damascene structure 16 is composed of a groove at the top and a hole at the bottom, wherein the hole at the bottom communicates with the reserved hole 19.

[0067] Refer to step S15 and Figure 11 , form a second metal layer, the second metal layer fills the opening 18 and the reserved hole 19 and is interconnected with the first metal layer 11, and the second metal layer serves as a metal connection structure 15. As Figure 2 shown, this step further includes: step S151, form a barrier layer on the inner walls of the opening and the reserved hole; step S152, form a seed layer on the surface of the barrier layer; step S153, form a second metal material layer covering the surface of the dielectric material layer and filling the opening and the reserved hole; step S154, planarize the second metal material layer until the dielectric material layer is exposed, and the remaining second metal material layer in the opening and the reserved hole forms the second metal layer, and the second metal layer serves as the metal connection structure and is interconnected with the first metal layer.

[0068] Refer to step S151 and Figure 8 , form a barrier layer 13 on the inner walls of the opening 18 and the reserved hole 19. The barrier layer 13 can be used to prevent the metal in the second metal material layer 150 from diffusing into the dielectric material layer 12. In this embodiment, the material of the barrier layer 13 is tantalum nitride (TaN).

[0069] Refer to step S152 and Figure 9 , form a seed layer 14 on the surface of the barrier layer 13. In this embodiment, the second metal is also copper. Copper has the disadvantage of being difficult to etch and cannot be deposited first and then etched into a pattern like aluminum. It is necessary to first etch the circuit pattern and then electroplate the copper circuit. However, electroplating requires conductivity, and the seed layer 14 can be used for conductivity.

[0070] Refer to step S153 and Figure 10, a second metal material layer 150 is formed to cover the surface of the dielectric material layer 12 and fill the opening 18 and the reserved hole 19. In this embodiment, the second metal material layer 150 is formed on the surface of the dielectric material layer 12 by an electroplating process. Specifically, an Electro-Chemical Plating (ECP) process is used for filling. When a power supply is applied between copper (anode) and the silicon wafer (cathode), the copper at the anode reacts to convert into copper ions and electrons. At the same time, a reaction also occurs at the cathode. The copper ions on the surface of the seed layer 14 near the cathode combine with the electrons to form copper plated on the surface of the seed layer 14, finally filling the opening 18 and the reserved hole 19, and forming the second metal material layer 150 on the surface of the dielectric material layer 12.

[0071] Refer to step S154 and Figure 11 , planarize the second metal material layer 150 until the dielectric material layer 12 is exposed. The remaining second metal material layer 150 within the opening 18 and the reserved hole 19 forms the second metal layer, and the second metal layer is interconnected with the first metal layer as the metal connection structure 15. As Figure 11 shown, the materials of the second metal material layer 150 are filled in both the damascene structure 16 and the reserved hole 19. The damascene structure 16, the reserved hole 19 and the filling inside both are interconnected with the first metal layer 11. Among them, the bottom of the metal connection structure 15 formed by filling in the damascene structure 16 and the reserved hole 19 extends deeper into the interior of the first metal layer 11. In this embodiment, the bottom of the metal connection structure 15 formed by filling in the damascene structure 16 and the reserved hole 19 extends to the bottom of the first metal layer 11. Thereby, the bottom of the metal connection structure 15 can be relatively far away from the low-dielectric-constant dielectric material layer 12, and further reduce the generation of holes at the bottom of the metal connection structure 15, effectively avoiding the generation of stress migration.

[0072] Based on a common inventive concept, the present invention also provides a semiconductor structure. The semiconductor structure is prepared by using the preparation method of the semiconductor structure described above.

[0073] The schematic diagram of the device structure of the semiconductor structure refers to Figure 11 . The semiconductor structure includes: a semiconductor substrate 10, a first metal layer 11, a dielectric material layer 12, and a metal connection structure 15.

[0074] Specifically, the surface of the semiconductor substrate 10 includes a first metal layer 11, and the first metal layer 11 includes reserved holes (the reserved holes are filled and not marked); the dielectric material layer 12 is formed on the surface of the first metal layer 11, and the dielectric material layer 12 includes an opening that penetrates through the dielectric material layer 12 and exposes the reserved holes (the opening is filled and not marked); the second metal layer fills the opening and the reserved holes and is interconnected with the first metal layer 11, and the second metal layer serves as the metal connection structure 15. In some embodiments, multiple layers of the semiconductor structure can be stacked.

[0075] The depth of the reserved holes is less than or equal to the thickness of the first metal layer 11. In this embodiment, the depth of the reserved holes is equal to the thickness of the first metal layer 11. Correspondingly, the bottom of the metal connection structure 15 reaches the semiconductor substrate 10 directly.

[0076] In some embodiments, the depth of the reserved holes is less than the thickness of the first metal layer 11, that is, the bottom of the metal connection structure 15 is located inside the first metal layer 11.

[0077] In this embodiment, the material of the dielectric material layer 12 is a low dielectric constant material. For example, the dielectric material is any one of PEOX or BD.

[0078] In this embodiment, the materials of the first metal layer 11 and the second metal layer are the same. For example, they are both copper.

[0079] In this embodiment, a seed layer 14 and a barrier layer 13 are provided on the outer wall of the metal connection structure 15. The seed layer 14 is used for conducting electricity when electroplating and filling to form the second metal layer; the barrier layer 13 is used to prevent the metal in the second metal layer from diffusing into the dielectric material layer 12.

[0080] In the above technical solution, by providing a first metal layer on the surface of the semiconductor substrate, the first metal layer includes reserved holes, forming a dielectric material layer on the surface of the first metal layer and in the reserved holes, removing part of the dielectric material layer to expose the reserved holes, removing the dielectric material layer in the reserved holes, forming a second metal layer on the surface of the dielectric material layer, filling the opening and the reserved holes and interconnecting with the first metal layer, thereby forming a metal connection structure. The bottom of the through-hole part in the generated metal connection structure is embedded in the first metal layer, reducing the influence of the thermal stress change of the low dielectric constant material on the metal connection structure, and further avoiding the holes in the metal connection structure caused by thermal stress, improving the reliability of the product.

[0081] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion. Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. The key point of each embodiment is to illustrate the differences from other embodiments.

[0082] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein the surface of the semiconductor substrate comprises a first metal layer, and the first metal layer comprises a reserved hole; forming a dielectric material layer on the surface of the first metal layer and in the reserved hole; Removing a portion of the dielectric material layer to form an opening penetrating the dielectric material layer, wherein the opening exposes the reserved hole; removing the dielectric material layer in the reserved hole; A second metal layer is formed, wherein the second metal layer fills the opening and the reserved hole and is interconnected with the first metal layer, and the second metal layer serves as a metal connection structure.

2. The method according to claim 1, characterized in that The semiconductor substrate further includes a diffusion barrier layer, and the first metal layer is disposed on a surface of the diffusion barrier layer.

3. The method according to claim 1, characterized in that The depth of the reserved hole is less than or equal to the thickness of the first metal layer.

4. The method according to claim 1, characterized in that: In the step of removing part of the dielectric material layer to form an opening penetrating the dielectric material layer, photolithography and etching processes are used to remove part of the dielectric material layer.

5. The method according to claim 1, characterized in that The width of the opening is greater than or equal to the width of the reserved hole.

6. The method according to claim 1, characterized in that After the step of removing the dielectric material layer in the reserved hole, the method further comprises: The opening is trimmed to be open.

7. The method according to claim 1, characterized in that The step of forming a second metal layer, wherein the second metal layer fills the opening and the reserved hole and is interconnected with the first metal layer, further comprises: forming a barrier layer on the inner wall of the opening and the reserved hole; forming a seed layer on a surface of the barrier layer; forming a second metal material layer covering the surface of the dielectric material layer and filling the opening and the reserved hole; The second metal material layer is planarized until the dielectric material layer is exposed, and the remaining second metal material layer in the opening and the reserved hole forms the second metal layer, and the second metal layer is interconnected with the first metal layer as the metal connection structure.

8. The method according to claim 7, characterized in that The second metal material layer is formed by an electroplating process.

9. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein a surface of the semiconductor substrate comprises a first metal layer, and the first metal layer comprises a reserved hole; A dielectric material layer formed on a surface of the first metal layer, wherein the dielectric material layer includes an opening penetrating the dielectric material layer and exposing the reserved hole; A second metal layer is filled in the opening and the reserved hole and is interconnected with the first metal layer, and the second metal layer serves as a metal connection structure.

10. The semiconductor structure according to claim 9, characterized in that: The material of the dielectric material layer includes a low dielectric constant material.

11. The semiconductor structure according to claim 9, characterized in that: The first metal layer and the second metal layer are made of the same material.

12. The semiconductor structure according to claim 9, characterized in that: The outer wall of the metal connection structure is provided with a seed layer and a barrier layer.

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