Method for improving wafer warping degree and semiconductor structure

Abstract

The invention discloses a method for improving the warping degree of a wafer and a semiconductor structure. The method for improving the warping degree of the wafer comprises the steps that the wafer with warping deformation is acquired; determining a first scribing direction and a second scribing direction of the wafer; dividing a plurality of cellular regions in the wafer based on the first scribing direction and the second scribing direction; respectively setting a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction, and generating a scribing channel design layout corresponding to the wafer; manufacturing a photoetching plate according to the scribing channel design layout, so that the photoetching plate marks a corresponding scribing channel; the method comprises the following steps of: after a bonding process of a manufacturing process flow, carrying out photoetching development treatment on a wafer by utilizing a photoetching plate, and etching a corresponding scribing channel on a deposited film layer of the wafer so as to release stress brought by the deposited film layer; according to the technical scheme provided by the invention, the wafer warping degree increased in the manufacturing process flow is effectively reduced, the stability of product performance is improved, and the product yield in the semiconductor preparation process is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for improving the warpage of a wafer and a semiconductor structure. Background Art

[0002] At present, during the semiconductor manufacturing process, various devices are gradually processed and stacked on the surface of the wafer, and unique electrical properties are realized through the functional superposition of various circuit devices. With the development of the semiconductor industry, the size of the wafer is getting larger and larger, the complexity of the devices is constantly increasing, and the types and quantities of the deposition films to be used are also increasing. However, the bonding between different types of film layers introduces new problems. Since the materials of different types of film layers are different, and the wafer structure and chemical bonds are also different, the stress between the film layers in different deposition film layers is different, which easily leads to changes in the warpage of the wafer. Especially during the manufacturing process of the third-generation semiconductor, the large-size third-generation semiconductor itself has a certain degree of warpage. After bonding processes such as chemical vapor deposition, the warpage of the wafer will increase significantly. It can be understood that the device stacking in the manufacturing process flow will cause changes in the warpage of the wafer.

[0003] However, with the miniaturization of device development, the integration degree of the chip is getting higher and higher, the process size is constantly shrinking, and processes such as lithography, etching, and ion implantation have put forward higher requirements for the overall flatness of the wafer. Severe warpage changes of the wafer will cause problems with poor lithography accuracy, resulting in deviations in the edge device structure. Similarly, poor wafer accuracy will also lead to situations where processes such as etching and ion implantation cause fragments due to uneven adsorption of the wafer. It can be seen that the problem of wafer warpage easily occurs in the traditional process flow, resulting in unstable product performance and greatly reducing the product yield. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. For this purpose, the present invention provides a method for improving the warpage of a wafer and a semiconductor structure, which can effectively reduce the increased warpage of the wafer in the manufacturing process flow, is beneficial to improving the stability of product performance, and greatly improves the product yield in the semiconductor manufacturing process.

[0005] In a first aspect, an embodiment of the present invention provides a method for improving the warpage of a wafer, including: Obtaining a wafer with warpage deformation; Determining a first dicing direction and a second dicing direction of the wafer, wherein the first dicing direction and the second dicing direction are perpendicular to each other; Based on the first dicing direction and the second dicing direction, dividing a plurality of cell regions in the wafer, wherein each cell region includes a plurality of chip devices; A plurality of scribing lanes with different widths are respectively arranged in the first scribing direction and the second scribing direction, and a scribing lane design layout corresponding to the wafer is generated, wherein the scribing lanes are located between different cell regions; A photomask is fabricated according to the scribing lane design layout so that the corresponding scribing lanes are marked on the photomask; After the bonding process in the manufacturing process flow, the wafer is subjected to photolithographic development using the photomask, and corresponding scribing lanes are etched on the deposited film layer of the wafer to release the stress brought by the deposited film layer.

[0006] According to a method for improving the warpage of a wafer provided by the present invention, it has at least the following beneficial effects: By obtaining a wafer with warpage deformation and determining the first scribing direction and the second scribing direction of the wafer, multiple cell regions can be divided in the wafer according to actual needs, and then a plurality of scribing lanes with different widths are respectively arranged in the first scribing direction and the second scribing direction, and a scribing lane design layout corresponding to the wafer is generated, that is, the tension problem of each cell region in the wafer is considered at the stage of wafer layout preparation. Then, a photomask is fabricated according to the scribing lane design layout so that the corresponding scribing lanes are marked on the photomask. To solve the problem of wafer warpage in the manufacturing process flow, after the bonding process, the wafer is subjected to photolithographic development using the newly designed photomask, and scribing lanes with different widths are etched on the deposited film layer of the wafer. It can be understood that by designing scribing lanes with different widths, the stress inside the wafer can be released, effectively reducing the increased wafer warpage in the manufacturing process flow, thereby achieving the purpose of improving the wafer warpage, which is beneficial to improving the stability of product performance, greatly improving the product yield in the semiconductor manufacturing process, and this method does not require additional process treatment procedures in the manufacturing process flow, and can effectively save time and cost.

[0007] According to some embodiments of the present invention, the step of respectively arranging a plurality of scribing lanes with different widths in the first scribing direction and the second scribing direction includes: Determine the width ratio of all scribing lane widths, wherein the width ratio is used to reflect the ratio of the maximum width to the minimum width among all scribing lanes; Determine the width range of all scribing lanes according to the width ratio; According to the width range, a plurality of scribing lanes with different widths are respectively arranged in the first scribing direction and the second scribing direction, wherein the width of the scribing lanes gradually increases from the center of the wafer to the edge of the wafer.

[0008] According to some embodiments of the present invention, the step of determining the width range of all scribing lanes according to the width ratio includes: Obtaining a preset target minimum width, and calculating a target maximum width according to the target minimum width and the width ratio; A width range is determined according to the target minimum width and the target maximum width.

[0009] According to some embodiments of the present invention, the step of providing a plurality of scribing lanes of different widths in the first scribing direction and the second scribing direction, respectively, comprises: Determining the number of scribing lanes in the first scribing direction and the second scribing direction respectively according to the size of the wafer; A corresponding number of scribe lines with different widths are respectively arranged in the first scribe direction and the second scribe direction.

[0010] According to some embodiments of the present invention, the step of performing photolithography development processing on the wafer using the photomask includes: Applying photoresist on the deposited film layer of the wafer; irradiating a photolithography light source to the photoresist through the photolithography plate; The wafer is exposed and developed using the photoresist so that the photoresist exposes the scribe lines corresponding to the photoresist.

[0011] According to some embodiments of the present invention, etching corresponding scribe lines on the deposited film layer of the wafer includes: The film layers on the deposited film layer of the wafer are separated by etching, so that the deposited film layer exposes the corresponding scribe lines.

[0012] According to some embodiments of the present invention, the step of separating the film layers on the deposited film layer of the wafer by etching comprises: Dry etching and / or wet etching are used to separate the film layers on the deposited film layer of the wafer.

[0013] According to some embodiments of the present invention, after etching corresponding scribe lines on the deposited film layer of the wafer, the method for improving the wafer warpage further includes: The photoresist on the deposited film layer is removed to obtain a semiconductor structure.

[0014] According to some embodiments of the present invention, the photoresist is a positive photoresist or a negative photoresist, and the photoresist plate matches the characteristics of the photoresist.

[0015] In a second aspect, an embodiment of the present invention provides a semiconductor structure, which is prepared by the method for improving wafer warpage as described in the embodiment of the first aspect above.

[0016] According to the semiconductor structure provided by the present invention, it has at least the following beneficial effects: The method for improving the wafer warpage can divide a plurality of cell regions in the wafer according to actual requirements by obtaining a warped wafer and determining the first dicing direction and the second dicing direction of the wafer. Then, a plurality of dicing channels with different widths are respectively set in the first dicing direction and the second dicing direction, and a dicing channel design layout corresponding to the wafer is generated. That is, the tension problem of each cell region in the wafer is considered at the stage of preparing the wafer layout. Then, a photomask is made according to the dicing channel design layout, so that the corresponding dicing channels are marked on the photomask. In order to solve the problem of wafer warpage in the manufacturing process flow, after the bonding process, the wafer is subjected to photolithography and development processing using the newly designed photomask, and dicing channels with different widths are etched on the deposited film layer of the wafer. It can be understood that the semiconductor structure prepared by using the method for improving the wafer warpage of the present invention can release the stress inside the wafer through the dicing channels with different widths, effectively reduce the increased wafer warpage in the manufacturing process flow, so as to achieve the purpose of improving the wafer warpage, which is beneficial to improving the stability of product performance, greatly improving the product yield in the semiconductor manufacturing process, and facilitating the optimization of the quality of semiconductor products. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specification drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings: Figure 1 is a flowchart of the method for improving the wafer warpage provided by an embodiment of the present invention; Figure 2 is a cross-sectional view of the wafer warped after the bonding effect provided by an embodiment of the present invention; Figure 3 is a schematic diagram of the wafer surface provided with dicing channels in an embodiment of the present invention; Figure 4 is a cross-sectional view of the deposited film layer of the wafer covered with photoresist in an embodiment of the present invention; Figure 5 is a schematic diagram of the wafer passing through the photolithography process in an embodiment of the present invention; Figure 6 is a cross-sectional view of the developed wafer in an embodiment of the present invention; Figure 7 is a cross-sectional view of the wafer with reduced warpage due to stress release after etching in an embodiment of the present invention; Figure 8 is a cross-sectional view of the wafer with the photoresist removed in an embodiment of the present invention; Figure 9 is a flowchart of the method for improving the wafer warpage provided by another embodiment of the present invention; Figure 10 Flow chart of a method for improving the warpage of a wafer provided by another embodiment of the present invention; Figure 11 Flow chart of a method for improving the warpage of a wafer provided by another embodiment of the present invention; Figure 12 Flow chart of a method for improving the warpage of a wafer provided by another embodiment of the present invention. Detailed implementation manners

[0018] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0019] The following detailed descriptions are all exemplary descriptions, aiming to provide further details of the present invention. Unless otherwise specified, all technical terms adopted in the present invention have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains. The terms used in the present invention are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present invention.

[0020] In the description of the present invention, it should be understood that with respect to the orientation description, such as up, down, front, back, left, right, etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0021] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the recited number, above, below, within, etc. are understood as including the recited number. If there is a description of first and second, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. It can be understood that A and / or B can represent the situation where A exists alone, A and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural.

[0022] It should be noted that although the logical order is shown in the flow chart, in some cases, the steps shown or described can be executed in a different order from that in the flow chart.

[0023] The embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0024] As Figures 1 to 8As shown in the figure, an embodiment of the first aspect of the present invention provides a method for improving the warpage of a wafer, including but not limited to steps S110 to S160: Step S110: Obtain a wafer with warpage deformation; It should be noted that by providing the wafer 101 with warpage deformation, it is convenient to design a suitable dicing lane 107 subsequently to solve the wafer warpage problem.

[0025] In one embodiment, the wafer 101 includes substrates such as silicon, gallium arsenide, indium phosphide, silicon carbide, gallium nitride, etc. and an epitaxial layer grown on the substrate.

[0026] Refer to Figure 2 , in one embodiment, there is a deposited film layer 102 on the surface of the wafer 101 after the bonding process, and the wafer 101 has warpage deformation.

[0027] Step S120: Determine a first dicing direction and a second dicing direction of the wafer, wherein the first dicing direction and the second dicing direction are perpendicular to each other; Refer to Figure 3 , it should be noted that after obtaining the wafer 101, the two dicing directions of the wafer 101 can be distinguished according to the chip design requirements. Specifically, the first dicing direction can be understood as parallel to the horizontal direction, and the first dicing direction can be denoted as the A direction. The direction perpendicular to the first dicing direction is the second dicing direction, which can be denoted as the B direction.

[0028] Step S130: Based on the first dicing direction and the second dicing direction, divide a plurality of cell regions in the wafer, wherein each cell region includes a plurality of chip devices; Refer to Figure 3 , in this step, a plurality of different cell regions 106 can be integrated in the wafer 101 according to actual needs. The number of chip devices in each cell region 106 is greater than or equal to 1, and the number of chip devices in each cell region 106 can be the same or different. The cell region 106 is usually a regular rectangle. For example, the chip devices in the cell region 106 can form regular figures such as rectangles or squares. By distinguishing two mutually perpendicular dicing directions, it is convenient to better divide the plurality of cell regions 106.

[0029] In one embodiment, the density of the chip devices in the cell region 106 close to the center of the wafer 101 can be relatively high, and the density of the chip devices in the cell region 106 close to the edge of the wafer 101 can be appropriately reduced, which is beneficial to ensuring the stable performance of the final product.

[0030] Step S140: Set a plurality of dicing lanes with different widths in the first dicing direction and the second dicing direction respectively, and generate a dicing lane design layout corresponding to the wafer, wherein the dicing lanes are located between different cell regions; In this step, a plurality of scribing lanes 107 with different widths are set in the first scribing direction, and a plurality of scribing lanes 107 with different widths are set in the second scribing direction. The scribing lanes 107 can divide different cell regions 106. The spacing between different cell regions 106 is the width of the scribing lane 107. It can be understood that a plurality of scribing lanes 107 are provided in both scribing directions and the widths of the respective scribing lanes 107 can be different. This step can be applied in the layout preparation stage of the wafer 101. By pre-designing the scribing lanes 107 with different widths and generating a scribing lane design layout corresponding to the wafer 101, the above design method can make up for the defects in the subsequent manufacturing process flow.

[0031] Step S150: Fabricate a photomask according to the scribing lane design layout so that the photomask marks the corresponding scribing lanes; In this step, the scribing lane design layout is designed with a plurality of scribing lanes 107. When fabricating the photomask 104, the scribing lane design layout is used for fabrication, so that the photomask 104 can mark the corresponding scribing lanes 107. It can be understood that the positions and widths of the scribing lanes 107 on the photomask 104 correspond to the scribing lanes 107 on the scribing lane design layout.

[0032] Step S160: After the bonding process in the manufacturing process flow, perform photolithography and development processing on the wafer using the photomask, and etch the corresponding scribing lanes on the deposited film layer of the wafer to release the stress caused by the deposited film layer.

[0033] Refer to Figures 4 to 8 , it should be noted that since bonding processes such as chemical vapor deposition are involved in the manufacturing process flow, the wafer warpage will be greatly affected after the bonding process. Refer to Figure 2 As can be seen, the wafer 101 and the deposited film layer 102 will cause warping deformation after the bonding effect. Therefore, in the present invention, by performing photolithography and development processing on the wafer 101 using the newly designed photomask 104, since the positions and widths of the scribing lanes 107 have been pre-designed appropriately, by etching the corresponding scribing lanes 107 on the deposited film layer 102, the internal stress caused by the deposited film layer 102 during the bonding process can be released, effectively reducing the warping deformation of the wafer 101.

[0034] The method for improving the warpage of a wafer provided in the first aspect of the embodiment described above, by obtaining a wafer 101 with warpage deformation and determining a first scribing direction and a second scribing direction of the wafer 101, can divide a plurality of cell regions 106 in the wafer 101 according to actual needs, and then respectively set a plurality of scribing lanes 107 of different widths in the first scribing direction and the second scribing direction, and generate a scribing lane design layout corresponding to the wafer 101, that is, the tension problem of each cell region 106 in the wafer 101 is taken into account in the wafer layout preparation stage, and then a photomask 104 is manufactured according to the scribing lane design layout, so that the photomask 104 marks the corresponding scribing lanes 107, in order to solve the manufacturing problem. There is a problem of wafer warpage in the manufacturing process. After the bonding process, the wafer 101 is subjected to photolithography and development processing using a newly designed photomask 104, and scribe lines 107 of different widths are etched on the deposited film layer 102 of the wafer 101. It can be understood that by designing scribe lines 107 of different widths, the stress inside the wafer 101 can be released, and the increased wafer warpage in the manufacturing process can be effectively reduced, thereby achieving the purpose of improving the wafer warpage, which is beneficial to improving the stability of product performance and greatly improving the product yield in the semiconductor preparation process. In addition, the method does not require additional process processing procedures in the manufacturing process, and can effectively save time and cost.

[0035] It should be noted that since the stacking of devices in the manufacturing process can easily lead to changes in wafer warpage, when the photolithography process is performed, after the wafer 101 is placed on the exposure table, the wafer 101 will be affected by the warping of the light path, resulting in an uneven light path formed by the light source on the surface of the wafer 101, which in turn affects the exposure accuracy of the photolithography process, resulting in inconsistent performance of chip devices in different areas, and ultimately reducing product yield.

[0036] Therefore, in order to solve the problem of wafer warpage in the manufacturing process, different from the traditional design mode, the method for improving wafer warpage provided by the present invention takes into account the tension problem at various locations of the wafer 101 during the wafer layout preparation stage, and takes into account the stress caused by the bonding effect at the beginning of making the photomask 104 by designing the scribing lanes 107 between the cell regions 106. By adjusting the stress in different directions inside the wafer 101 through the scribing lanes 107 of different widths, the warpage in different directions of the wafer 101 can be compensated. It can be understood that this method can be combined with the existing manufacturing process flow. Compared with other methods for reducing warpage, this method can be improved from the source, and the process defects can be compensated by design, without adding redundant process flows. It is highly practical, and the warpage control is more flexible and variable, which can improve the alignment accuracy of the photolithography process, keep the performance of chip devices in different regions consistent, and is conducive to optimizing product quality, thereby achieving the effect of improving yield.

[0037] It should be noted that the deposited film layer 102 of the present invention refers to the bonding effect between film layers, where the film layer may include at least one of a substrate layer, an epitaxial layer, a passivation layer, a metal layer, and a trench layer.

[0038] In one embodiment, the passivation layer may include silicon dioxide, silicon nitride, polyimide, benzocyclobutene, and some temporary photoresist materials.

[0039] In one embodiment, the metal layer may include metal elements such as titanium, nickel, silver, aluminum, and copper.

[0040] In one embodiment, the deposited film layer 102 may be formed by atomic layer deposition on the front or back of the wafer 101.

[0041] In one embodiment, according to the actual usage of the wafer 101, the dicing street 107 may be widened on one side of the wafer 101.

[0042] Such as Figure 3 and Figure 9 shown, according to some embodiments of the present invention, in step S140, a plurality of dicing streets with different widths are respectively set in the first dicing direction and the second dicing direction, including but not limited to steps S210 to S230: Step S210: Determine the width ratio of all the dicing street widths, where the width ratio is used to reflect the ratio of the maximum width to the minimum width among all the dicing streets; Step S220: Determine the width range of all the dicing streets according to the width ratio; Step S230: Set a plurality of dicing streets with different widths respectively in the first dicing direction and the second dicing direction according to the width range, where the width of the dicing street gradually increases from the center of the wafer to the edge of the wafer.

[0043] It should be noted that in this embodiment, first, the width ratio of all the dicing street 107 widths is determined. The width ratio is the ratio of the maximum width to the minimum width of the dicing street 107. This width ratio is convenient for providing guidance for subsequent determination of the specific values of the dicing street 107 widths. According to the width ratio, the width range of all the dicing streets 107 is determined, and within the width range, a plurality of dicing streets 107 with different widths are respectively set in the first dicing direction and the second dicing direction. It can be understood that there are a plurality of dicing streets 107 in both the first dicing direction and the second dicing direction, and the widths of the dicing streets 107 are all within the width range. By adjusting the widths of the dicing streets 107 within the width range, the control of the wafer warpage becomes more flexible. In addition, by making the width of the dicing street 107 gradually increase from the center of the wafer 101 to the edge of the wafer 101, the process stability of the central chip device and the edge chip device can be improved, which is of great significance for improving the yield of the product.

[0044] It should be noted that, based on the width range, the widths of different scribing lanes 107 can be adjusted according to actual production requirements.

[0045] In one embodiment, the width ratio can be determined according to the ratio of the size of the cell region 106 in the first scribing direction or the second scribing direction to the radius of the wafer 101. The sizes of the cell regions 106 in the first scribing direction and the second scribing direction can be the same. For example, the size of the cell region 106 can be the diameter of the wafer 101.

[0046] In one embodiment, the width ratio can be determined according to the ratio of the thickness of the deposited film layer 102 in the semiconductor manufacturing process to the thickness of the wafer 101 itself.

[0047] It should be noted that the width ratio can also be preset according to the actual production requirements of the wafer 101. The embodiments of the present invention do not specifically limit the method for determining the width ratio.

[0048] As Figure 10 shown, according to some embodiments of the present invention, in step S220, determining the width ranges of all scribing lanes according to the width ratio includes, but is not limited to, step S310 and step S320: Step S310: Obtain a preset target minimum width, and calculate a target maximum width according to the target minimum width and the width ratio; Step S320: Determine the width range according to the target minimum width and the target maximum width.

[0049] In this embodiment, after determining the width ratio, a preset target minimum width can be obtained, and then the target maximum width can be calculated through the target minimum width and the width ratio. Thus, the width range can be determined according to the target minimum width and the target maximum width. It can be understood that the target minimum width and the target maximum width are respectively the lower limit value and the upper limit value of the width range, which is convenient for subsequently determining the width of the scribing lane 107 within the width range.

[0050] In one embodiment, the target minimum width can be determined according to the lowest dimension actually required by the scribing process in the production factory, which is determined by the equipment capacity of the production factory. For example, if the lowest dimension that can be scribed in a certain production factory is 50 μm, then the target minimum width is 50 μm, and then the target maximum width is calculated according to the target minimum width and the width ratio.

[0051] As Figure 3 and Figure 11 shown, according to some embodiments of the present invention, in step S230, respectively setting a plurality of scribing lanes with different widths in the first scribing direction and the second scribing direction includes, but is not limited to, step S410 and step S420: Step S410: Determine the number of scribing lanes in the first scribing direction and the second scribing direction respectively according to the size of the wafer. Step S420: Set a plurality of scribing lanes with corresponding numbers and different widths in the first scribing direction and the second scribing direction respectively.

[0052] In this embodiment, since the sizes of different wafers 101 are different, the number of scribing lanes 107 in the first scribing direction and the second scribing direction can be determined respectively according to the size of the wafer 101, that is, determine how many scribing lanes 107 are set in the first scribing direction and the second scribing direction, and then set a plurality of scribing lanes 107 with corresponding numbers and different widths respectively, which is convenient for efficiently and accurately designing the number of scribing lanes 107.

[0053] It should be noted that the size of the wafer 101 is determined according to actual production requirements. For example, the size of the wafer 101 can be 6 inches, 8 inches, 12 inches, etc., and the embodiments of the present invention do not make specific limitations thereto.

[0054] In one embodiment, the number of scribing lanes 107 in the first scribing direction or the second scribing direction can be divided according to an arithmetic progression, so that the scribing lanes 107 are more evenly distributed.

[0055] As Figures 3 to 6 、 Figure 12 shown, according to some embodiments of the present invention, the lithographic development process of the wafer using a photomask includes, but is not limited to, steps S510 to S530: Step S510: Coat a photoresist on the deposited film layer of the wafer. Step S520: Pass the lithographic light source through the photomask and irradiate the photoresist. Step S530: Use the photomask to expose and develop the wafer so that the photoresist exposes the scribing lanes corresponding to the photomask.

[0056] In this embodiment, after the bonding process in the manufacturing process flow, there is a deposited film layer 102 on the surface of the wafer 101. By coating a photoresist 103 on the deposited film layer 102 and then using the lithographic light source emitted by a lithography machine to pass through the photomask 104 and irradiate the photoresist 103, since the photomask 104 is marked with a plurality of scribing lanes 107 with different widths, when the respective light paths of the light source pass through the photomask 104 and irradiate the photoresist 103, and then use the newly designed photomask 104 to expose and develop the wafer 101, the photoresist 103 on the developed wafer 101 exposes the scribing lanes 107 corresponding to the photomask 104, which is convenient for subsequently exposing the corresponding scribing lanes 107 on the deposited film layer 102. The method of the present invention can effectively reduce the warping deformation of the wafer 101 without increasing the process flow.

[0057] AsFigure 7 As shown, according to some embodiments of the present invention, in step S160, etching the corresponding scribing lanes on the deposited film layer of the wafer includes the following steps: Separate the film layers in patches on the deposited film layer of the wafer by etching, so that the corresponding scribing lanes are exposed on the deposited film layer.

[0058] In this embodiment, after the wafer 101 is subjected to photolithography and development processing using the photomask 104, the film layers in patches on the deposited film layer 102 of the wafer 101 are separated by etching, so that the corresponding scribing lanes 107 are exposed on the deposited film layer 102. By exposing the scribing lanes 107, the internal stress caused by the deposited film layer 102 during the bonding process can be released, thereby reducing the warping deformation of the wafer 101 that occurs in the manufacturing process flow, which is beneficial to improving the yield of subsequent products.

[0059] In one embodiment, the etching process can be carried out simultaneously with or separately from the processing process of the deposited film layer 102.

[0060] According to some embodiments of the present invention, separating the film layers in patches on the deposited film layer of the wafer by etching specifically includes: Separate the film layers in patches on the deposited film layer of the wafer by using dry etching and / or wet etching.

[0061] In this embodiment, the method for separating the film layers in patches on the deposited film layer 102 of the wafer 101 can include, but is not limited to, dry etching and wet etching, and can be adaptively selected according to actual production requirements.

[0062] As Figure 8 shown, according to some embodiments of the present invention, after step S160 etches the corresponding scribing lanes on the deposited film layer of the wafer, the method for improving the warpage degree of the wafer further includes the following steps: Remove the photoresist on the deposited film layer to obtain a semiconductor structure.

[0063] In this embodiment, after etching the corresponding scribing lanes 107 on the deposited film layer 102 of the wafer 101, removing the photoresist 103 on the deposited film layer 102 can obtain a semiconductor structure, which is convenient for subsequent processing of the semiconductor structure.

[0064] According to some embodiments of the present invention, the photoresist 103 is a positive photoresist or a negative photoresist, and the photomask 104 matches the characteristics of the photoresist 103.

[0065] In this embodiment, the photoresist 103 used in the photolithography process of the present invention can be a positive photoresist or a negative photoresist, and its corresponding development principle and the production of the photomask 104 are based on the characteristics of the used photoresist 103.

[0066] An embodiment of the second aspect of the present invention provides a semiconductor structure, which is prepared by using the method for improving the warpage of a wafer as described in the embodiment of the first aspect above. The method for improving the warpage of a wafer can obtain a warped wafer 101 and determine the first dicing direction and the second dicing direction of the wafer 101, and can divide a plurality of cell regions 106 in the wafer 101 according to actual requirements. Then, a plurality of dicing channels 107 with different widths are respectively arranged in the first dicing direction and the second dicing direction, and a dicing channel design layout corresponding to the wafer 101 is generated, that is, the tension problem of each cell region 106 in the wafer 101 is considered in the wafer layout preparation stage. Then, a photomask 104 is made according to the dicing channel design layout, so that the photomask 104 marks the corresponding dicing channels 107. In order to solve the problem of wafer warpage existing in the manufacturing process flow, after the bonding process, the wafer 101 is subjected to photolithography and development processing by using the newly designed photomask 104, and dicing channels 107 with different widths are etched on the deposited film layer 102 of the wafer 101. It can be understood that the semiconductor structure prepared by using the method for improving the warpage of a wafer of the present invention can release the stress inside the wafer 101 through the dicing channels 107 with different widths, effectively reduce the increased wafer warpage in the manufacturing process flow, so as to achieve the purpose of improving the wafer warpage, which is beneficial to improving the stability of product performance, greatly improving the product yield in the semiconductor preparation process, and facilitating the optimization of the quality of semiconductor products.

[0067] As is known by technical common sense, the present invention can be implemented by other embodiments without departing from its spirit or essential characteristics. Therefore, the above-disclosed embodiments are illustrative in all respects and are not exclusive. All changes within the scope of the present invention or within the scope equivalent to the present invention are encompassed by the present invention.

[0068] In the present invention, unless otherwise clearly defined and limited, the terms "mounted", "connected", "connected", "fixed", etc. shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0069] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0070] In the description of the present specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In the present specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples.

[0071] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for improving the warpage of a wafer, characterized in that, comprising: obtaining a wafer with warpage deformation; determining a first scribing direction and a second scribing direction of the wafer, wherein the first scribing direction and the second scribing direction are perpendicular to each other; dividing a plurality of cell regions in the wafer based on the first scribing direction and the second scribing direction, wherein each cell region includes a plurality of chip devices; respectively arranging a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction, and generating a scribing channel design layout corresponding to the wafer, wherein the scribing channels are located between different cell regions; manufacturing a photomask according to the scribing channel design layout so that the photomask marks the corresponding scribing channels; after the bonding process in the manufacturing process flow, performing photolithography and developing on the wafer by using the photomask, and etching the corresponding scribing channels on the deposition film layer of the wafer to release the stress brought by the deposition film layer.

2. The method for improving the warpage of a wafer according to claim 1, characterized in that, the step of respectively arranging a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction includes: determining the width ratio of all scribing channels, wherein the width ratio is used to reflect the ratio of the maximum width and the minimum width of all scribing channels; determining the width range of all scribing channels according to the width ratio; respectively arranging a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction according to the width range, wherein the width of the scribing channels gradually increases from the center of the wafer to the edge of the wafer.

3. The method for improving the warpage of a wafer according to claim 2, characterized in that, the step of determining the width range of all scribing channels according to the width ratio includes: obtaining a preset target minimum width, and calculating a target maximum width according to the target minimum width and the width ratio; determining the width range according to the target minimum width and the target maximum width.

4. The method for improving the warpage of a wafer according to claim 2, characterized in that, the step of respectively arranging a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction includes: respectively determining the number of scribing channels in the first scribing direction and the second scribing direction according to the size of the wafer; respectively arranging a corresponding number of a plurality of scribing channels with different widths in the first scribing direction and the second scribing direction.

5. The method for improving the warpage of a wafer according to claim 1, characterized in that, the step of performing photolithography and developing on the wafer by using the photomask includes: coating a photoresist on the deposition film layer of the wafer; shining a photolithography light source through the photomask onto the photoresist; performing exposure and development on the wafer by using the photomask so that the photoresist exposes the scribing channels corresponding to the photomask.

6. The method for improving the warpage of a wafer according to claim 5, characterized in that, the step of etching the corresponding scribing channels on the deposition film layer of the wafer includes: The film layer on the deposited film layer of the wafer is separated by etching so that the corresponding scribing lanes are exposed on the deposited film layer.

7. The method for improving the warpage of a wafer according to claim 6, wherein, the separating of the film layer on the deposited film layer of the wafer by etching includes: separating the film layer on the deposited film layer of the wafer by dry etching and / or wet etching.

8. The method for improving the warpage of a wafer according to claim 5, wherein, after etching the corresponding scribing lanes on the deposited film layer of the wafer, the method for improving the warpage of the wafer further includes: removing the photoresist on the deposited film layer to obtain a semiconductor structure.

9. The method for improving the warpage of a wafer according to claim 5, wherein, the photoresist is a positive photoresist or a negative photoresist, and the photomask matches the characteristics of the photoresist.

10. A semiconductor structure, wherein, it is prepared by using the method for improving the warpage of a wafer according to any one of claims 1-9.

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