Semiconductor structure, electrical connection and method for manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure, an electrical connector and a manufacturing method of the semiconductor structure. The semiconductor structure comprises an electrical connector, a chip, a bonding wire and a plastic sealing layer. The electrical connector comprises a bearing part and a pin. The height of a first bearing surface of the first bearing part is less than the height of a second bearing surface of the second bearing part. The first chip is attached to the first bearing surface with the back surface facing the first bearing surface; the second chip is attached to the second bearing surface with the back surface facing the second bearing surface. The bonding wire comprises adjacent first and second bonding wires. The first section of the first bonding wire is connected to the solder pad of the first chip, and the third section is connected to the solder pad of the second chip. The first section of the second bonding wire is connected to the solder pad of the second chip, and the third section is connected to the solder pad of the first chip or the pin. The height of the second section of the first bonding wire is less than the height of the second section of the second bonding wire. The plastic sealing layer encapsulates the chip, the electrical connector and the bonding wire, and the pin is at least partially exposed from the plastic sealing layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure, an electrical connecting piece and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] In a common semiconductor packaging technology, such as a chip packaging technology, the following processes are usually involved: firstly, a chip is attached to a lead frame, the pins of the lead frame are located on one side of the chip; then, bonding wires are used to electrically connect the pads of the chip with the pins, or to connect two pads; and then, a plastic encapsulation layer is formed to encapsulate the chip, the lead frame and the bonding wires.

[0003] In the above packaging technology, during the process of forming the plastic encapsulation layer, the plastic encapsulation material impacts the bonding wires, which can easily cause the adjacent bonding wires to contact and thus short circuit. That is, the semiconductor product manufactured by the above packaging technology has a low yield. SUMMARY

[0004] The present application provides a semiconductor structure, an electrical connecting piece and a manufacturing method of the semiconductor structure.

[0005] According to a first aspect of the present application, a semiconductor structure is provided. The semiconductor structure comprises:

[0006] An electrical connecting piece, which comprises a plurality of pins located on the side of a bearing part; the bearing part comprises a first bearing part and a second bearing part, the first bearing part comprises a first bearing surface, and the second bearing part comprises a second bearing surface, the first bearing surface and the second bearing surface are located on the same side of the bearing part, and the height of the first bearing surface is less than the height of the second bearing surface;

[0007] A plurality of chips, comprising a first chip and a second chip; the chip comprises a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the first chip is attached to the first bearing surface, and the chip back surface faces the first bearing surface; the second chip is attached to the second bearing surface, and the chip back surface faces the second bearing surface;

[0008] A plurality of bonding wires, comprising a first section, a second section and a third section connected in sequence; the plurality of bonding wires comprises a first bonding wire and a second bonding wire, the first bonding wire is adjacent to the second bonding wire; the first section of the first bonding wire is connected to the pad of the first chip, and the third section is connected to the pad of the second chip; the first section of the second bonding wire is connected to the pad of the second chip, and the third section is connected to the pad of the first chip or the pin; the second section of the first bonding wire is located on the side of the second section of the second bonding wire facing the first bearing part;

[0009] a plastic encapsulation layer encapsulating the chip, the electrical connector and the bonding wires, and at least part of the pins being exposed from the plastic encapsulation layer.

[0010] In one embodiment, the first bonding wire is adjacent to the second bonding wire in a direction perpendicular to a plane in which a chip front surface of the second chip is located, and a second section of the first bonding wire has an overlapping projection on the plane with a second section of the second bonding wire.

[0011] In one embodiment, a height of a surface on a same side of the pins and the first carrier surface is less than a height of the first carrier surface, or the surface on the same side of the pins and the first carrier surface is in a same plane as the first carrier surface, the plurality of bonding wires further comprising a third bonding wire and a fourth bonding wire adjacently arranged, a first section of the third bonding wire being connected to a pad of the first chip, and a third section of the third bonding wire being connected to the pin; a first section of the fourth bonding wire being connected to a pad of the second chip, and a third section of the fourth bonding wire being connected to the pin; and a second section of the third bonding wire being located on a side of a second section of the fourth bonding wire facing the first carrier portion.

[0012] In one embodiment, a height difference between the second carrier surface and the first carrier surface ranges from 100 μm to 300 μm.

[0013] In one embodiment, the semiconductor structure further comprises an insulating portion, the insulating portion at least covering the second section of the first bonding wire; and a temperature at which the insulating portion is transformed from a solid state to a molten state is higher than a solidification temperature of a material of the plastic encapsulation layer.

[0014] In one embodiment, the electrical connector is a lead frame, the carrier portion is an island of the lead frame, and the island is spaced apart from the pins; or,

[0015] The electrical connector is a circuit board, the circuit board comprising a main body portion, the pins being located on the main body portion, and the carrier portion being a portion of the main body portion on which the pins are not arranged.

[0016] According to a second aspect of embodiments of the present application, a manufacturing method of a semiconductor structure is provided, the manufacturing method comprising:

[0017] Provided is an electrical connector, which comprises a carrier and a plurality of pins arranged on the side of the carrier; the carrier comprises a first carrier and a second carrier, the first carrier comprises a first carrier surface, and the second carrier comprises a second carrier surface; the first carrier surface and the second carrier surface are arranged on the same side of the carrier, and the height of the first carrier surface is less than the height of the second carrier surface.

[0018] A first chip is mounted on the first carrier surface, and a second chip is mounted on the second carrier surface; the first chip and the second chip each comprise a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the chip back surface of the first chip faces the first carrier surface; and the chip back surface of the second chip faces the second carrier surface.

[0019] A first bonding wire is formed by welding a first pad of the first chip as a first welding point and a second pad of the second chip as a second welding point; the first bonding wire comprises a first section connected to the first pad, a third section connected to the second pad, and a second section arranged between the first section and the second section.

[0020] A second bonding wire is formed, which comprises a first section, a second section and a third section connected in sequence; the first section of the second bonding wire is welded to a third pad of the second chip, and the third section is welded to a fourth pad of the first chip or the pin; the first bonding wire is adjacent to the second bonding wire, and the second section of the first bonding wire is arranged on the side of the second section of the second bonding wire facing the first carrier.

[0021] A plastic encapsulation layer is formed, which encapsulates the first chip, the second chip, the electrical connector, the first bonding wire and the second bonding wire, and at least part of the pin is exposed from the plastic encapsulation layer.

[0022] In one embodiment, before the step of forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further comprises:

[0023] An insulating material is dropped on the side of the chip front surface of the first chip, and the insulating material is solidified to form an insulating part; the insulating part at least covers the second section of the first bonding wire.

[0024] The projection of the dropping track of the insulating material on the plane where the chip front surface of the first chip is located does not overlap with the projection of the bonding wire on the plane; and / or the included angle between the projection of the dropping track of the insulating material on the plane where the chip front surface of the first chip is located and the plane is an acute angle.

[0025] According to a third aspect of the embodiments of the present application, an electrical connector is provided, which comprises a carrier for mounting a chip and a plurality of pins, the pins being located on a side of the carrier;

[0026] The carrier comprises a first carrier and a second carrier, the first carrier comprises a first carrier surface, and the second carrier comprises a second carrier surface, the first carrier surface and the second carrier surface are located on the same side of the carrier, and the height of the first carrier surface is less than the height of the second carrier surface.

[0027] In one embodiment, the electrical connector is a lead frame, the carrier is an island of the lead frame, and the island is spaced apart from the pins; or,

[0028] The electrical connector is a circuit board, the circuit board comprises a main body, the pins are located on the main body, and the carrier is a portion of the main body where the pins are not located.

[0029] The main technical effects achieved by the embodiments of the present application are as follows:

[0030] The semiconductor structure, the electrical connector and the manufacturing method of the semiconductor structure provided by the embodiments of the present application have the following advantages: since the height of the first carrier surface of the first carrier of the electrical connector is less than the height of the second carrier surface of the second carrier, and the first carrier surface and the second carrier surface are located on the same side of the electrical connector, the first chip is mounted on the first carrier surface, and the second chip is mounted on the second carrier surface, when the first bonding wire is formed, the solder pad of the first chip is used as the first solder point, and the solder pad of the second chip is used as the second solder point, which can make the distance between the third section of the first bonding wire and the second chip less than the distance between the first section and the first chip, relative to the scheme that the first carrier surface and the second carrier surface are located on the same plane, the distance between the second section of the first bonding wire and the second chip is reduced, when the distance between the second section of the second bonding wire and the second chip is unchanged, the height difference between the second section of the first bonding wire and the second section of the second bonding wire is increased, thereby the risk that the impact of the insulating material on the first bonding wire and the second bonding wire when the insulating structure (for example, a plastic encapsulation layer) covering the first bonding wire and the second bonding wire is formed causes the two to contact and results in short circuit can be reduced; and the first carrier surface and the second carrier surface have a height difference, which can increase the distance between the first chip and the second chip, and help to improve the electrical isolation capability between the first chip and the second chip, avoid the occurrence of an unexpected electrical connection between the first chip and the second chip, and improve the reliability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a schematic diagram of a partial structure of a semiconductor structure provided by an exemplary embodiment of the present application;

[0032] Figure 2 This is a side view of a portion of the semiconductor structure provided in an exemplary embodiment of this application;

[0033] Figure 3 This is a side view of a portion of the semiconductor structure provided in an exemplary embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a partial structure of a semiconductor structure provided in another exemplary embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a semiconductor structure provided in another exemplary embodiment of this application;

[0036] Figure 6 This is a flowchart of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of this application. Specific Implementation

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0038] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0039] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0040] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0041] This application provides a semiconductor structure. For example... Figure 1 andFigure 2 As shown, the semiconductor structure comprises a plurality of chips 10, an electrical connector 20, a plurality of bonding wires 30 and a plastic encapsulation layer 40.

[0042] The electrical connector 20 comprises a plurality of pins 22 on the side of a carrier 21, the carrier 21 comprises a first carrier 211 and a second carrier 212, the first carrier 211 comprises a first carrier surface 2111, the second carrier 212 comprises a second carrier surface 2121, the first carrier surface 2111 and the second carrier surface 2121 are on the same side of the carrier 21, and the height of the first carrier surface 2111 is less than the height of the second carrier surface 2121. The height of the first carrier surface 2111 being less than the height of the second carrier surface 2121 means that there is a distance between the first carrier surface 2111 and the second carrier surface 2121 in the direction perpendicular to the plane on which the first carrier surface 2111 lies (i.e. the X direction). The plurality of chips 10 comprises a first chip 11 and a second chip 12. Each of the chips 10 comprises a chip front surface and a chip back surface opposite to the chip front surface, and the chip front surface is provided with a plurality of pads 13. The first chip 11 and the second chip 12 are on the same side of the electrical connector, the first chip 11 is attached to the first carrier surface 2111, and the second chip 12 is attached to the second carrier surface 2121.

[0043] The bonding wires 30 comprise first sections, second sections and third sections connected in sequence to connect the pads of the chips 10 to the pins 22 or to connect the pads of two chips 10. The plurality of bonding wires 30 comprises a first bonding wire 31 and a second bonding wire 32, and the first bonding wire 31 is adjacent to the second bonding wire 32. The first bonding wire 31 being adjacent to the second bonding wire 32 means that there is no other bonding wire between them. The first section 311 of the first bonding wire 31 is connected to the pads 13 of the first chip 11, the third section 313 is connected to the pads 13 of the second chip 12, and the second section 312 is connected to the first section 311 and the third section 313 respectively. The first section 321 of the second bonding wire 32 is connected to the pads 13 of the second chip 12, the third section 323 is connected to the pads 13 of the first chip 11 or the pins 22, and the second section 322 is connected to the first section 321 and the third section 323 respectively. The second section 312 of the first bonding wire 31 is on the side of the second section 322 of the second bonding wire 32 facing the first carrier 211. The plastic encapsulation layer 40 encapsulates the chips 10, the electrical connector 20 and the bonding wires 30, and at least part of the pins 22 is exposed from the plastic encapsulation layer 40. Figure 2In the illustrated embodiment, the second bonding wire 32 connects the solder pad 13 of the second chip 12 to the solder pad 13 of the first chip 11. In other embodiments, the second bonding wire 32 can connect the solder pad 13 of the second chip 12 to the pin 22.

[0044] In forming the first bonding wire 31, the solder pad 13 of the first chip 11 can be used as the first solder point, and the solder pad 13 of the second chip 12 can be used as the second solder point. Specifically, in forming the first bonding wire 31, the end of the conductive wire is first sintered into a ball, the ball is then soldered to the first solder point, the conductive wire is then stretched to form the first section 311, the second section 312 and the third section 313 in sequence, and finally the conductive wire is soldered to the second solder point and the conductive wire is broken. The end of the conductive wire used for soldering to the first solder point is sintered into a ball, so that the grain of the portion of the wire adjacent to the ball (heat-affected zone) is larger and the hardness is reduced. To reduce the impact of this portion of the wire on the shape of the bonding wire, the size of the first section 311 in the X direction is set to be larger. The end of the third section 313 does not need to be sintered into a ball, and therefore does not form a heat-affected zone. Therefore, the size of the third section 313 in the X direction can be set to be smaller than the size of the first section 311 in the longitudinal direction.

[0045] The semiconductor structure provided by the embodiments of the present application has the following advantages. The height of the first bearing surface of the first bearing part of the electrical connector is less than the height of the second bearing surface of the second bearing part, and the first bearing surface and the second bearing surface are located on the same side of the electrical connector, the first chip is attached to the first bearing surface, and the second chip is attached to the second bearing surface. In forming the first bonding wire, the solder pad of the first chip is used as the first solder point, and the solder pad of the second chip is used as the second solder point. This can make the distance between the third section of the first bonding wire and the second chip less than the distance between the first section of the first bonding wire and the first chip. Compared with the scheme in which the first bearing surface and the second bearing surface are located on the same plane, the distance between the second section of the first bonding wire and the second chip is reduced, and when the distance between the second section of the second bonding wire and the second chip remains unchanged, the height difference between the second section of the first bonding wire and the second section of the second bonding wire is increased. Therefore, the risk of short circuit caused by the contact between the first bonding wire and the second bonding wire due to the impact of the insulating material on the first bonding wire and the second bonding wire when forming the insulating structure (e.g., a plastic encapsulation layer) covering the first bonding wire and the second bonding wire can be reduced. In addition, the height difference between the first bearing surface and the second bearing surface can increase the distance between the first chip and the second chip, which helps to improve the electrical isolation capability between the first chip and the second chip, avoids the occurrence of an undesired electrical connection between the first chip and the second chip, and improves the reliability of the semiconductor structure.

[0046] In one embodiment, as Figure 1As shown, the first chip 11 includes a first solder pad 131 and a third solder pad 133, and the second chip 12 includes a second solder pad 132 and a fourth solder pad 134. The two ends of the first bonding wire 31 are connected to the first solder pad 131 and the second solder pad 132, respectively, and the two ends of the second bonding wire 32 are connected to the third solder pad 133 and the fourth solder pad 134, respectively. In other embodiments, the two ends of the second bonding wire 32 may be connected to the fourth solder pad 134 and a pin 22, respectively.

[0047] In one embodiment, the plurality of bonding wires 30 may include two or more first bonding wires 31 and second bonding wires 32 adjacent to each first bonding wire 31; the electrical connector 20 may include a plurality of first carrier portions 211 and a plurality of second carrier portions 212; the plurality of chips 10 may include a plurality of first chips 11 and a plurality of second chips 12.

[0048] In one embodiment, such as Figure 1 As shown, the electrical connector 20 has multiple pins 22 arranged around the first support portion 211 and the second support portion 212. Figure 1 The diagram only shows some of the pins 22 connected to the pads 13 of the chip 10. In practice, each pin 22 can be electrically connected to one pad 13 of the chip 10 via a bonding wire 30.

[0049] In one embodiment, the chip 10 can be attached to one side of the carrier portion 21 using an adhesive. In some embodiments, the adhesive can be a conductive adhesive, for example, an adhesive obtained by curing silver paste. Alternatively, the adhesive can be a non-conductive adhesive.

[0050] In one embodiment, such as Figure 2 As shown, the first support portion 211 and the second support portion 212 are spaced apart. In other embodiments, the electrical connector 20 further includes a connecting portion, through which the first support portion 211 and the second support portion 212 are connected, and the connecting portion can extend obliquely relative to the first support portion 211.

[0051] In one embodiment, the height difference between the second bearing surface 2121 and the first bearing surface 2111 ranges from 100 μm to 300 μm. In this way, the height difference between the second section of the first bonding wire and the second section of the second bonding wire can be avoided to be too small, so that the problem of short circuit between the first bonding wire 31 and the second bonding wire 32 cannot be effectively avoided. In addition, the height difference between the second bearing surface 2121 and the first bearing surface 2111 can be avoided to be too large. Under the premise that the thickness of the plastic sealing layer is certain, the thickness of the part of the plastic sealing layer located on the side of the second section 322 of the second bonding wire 32 away from the second bearing part 212 is too small, and the plastic sealing layer cannot effectively protect the second section 322 of the second bonding wire 32, and even the problem of the second section 322 of the second bonding wire 32 exposed from the plastic sealing layer occurs. In some embodiments, the height difference between the second bearing surface 2121 and the first bearing surface 2111 is 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, etc.

[0052] In one embodiment, as shown in Figure 1 and Figure 2 , the electrical connecting part 20 is a lead frame, the bearing part 21 is the base island of the lead frame, and the bearing part 21 is arranged apart from the lead pin 22. In other embodiments, the electrical connecting part 20 can be a circuit board, the circuit board includes a main body part, the lead pin is located on the main body part, and the bearing part 21 is the part of the main body part which is not arranged with the lead pin or other elements.

[0053] In one embodiment, as shown in Figure 1 and Figure 2 , when the electrical connecting part 20 is a lead frame, the lead frame further includes a web 23. In the manufacturing process of the semiconductor structure, the initially used lead frame further includes a frame body, one end of the web 23 is connected to the frame body, and the other end is connected to the bearing part 21. After the lead frame is cut to remove the frame body, the semiconductor structure is obtained. The web 23 includes a flat part 231 and an inclined part 232 adjacent to the flat part 231. The flat part 231 is connected to the frame body, and the inclined part 232 is connected to the bearing part 21. The distance between the flat part 231 of each web 23 and the second bearing part 212 in the X direction can be the same. The size of the inclined part 232 of the bearing part 21 connected to the first bearing part 211 in the X direction is greater than the size of the inclined part 232 connected to the second bearing part 212 in the X direction, so that the first bearing part 211 and the second bearing part 212 have a height difference.

[0054] In one embodiment, as shown in Figure 1 and Figure 2As shown, the first bonding wire 31 and the second bonding wire 32 are adjacent to each other in a direction perpendicular to a plane in which a chip front surface of the second chip 12 is located, and a second section 312 of the first bonding wire 31 has an intersection with a second section 322 of the second bonding wire 32 in a projection of the first bonding wire 31 and the second bonding wire 32 on the plane. In another embodiment, the first bonding wire 31 and the second bonding wire 32 are adjacent to each other in a direction of a plane in which a chip front surface of the second chip 20 is located.

[0055] In one embodiment, as shown in Figure 1 and Figure 3 As shown, a height of a surface on which the pin 22 and the first bearing surface 2111 are located is less than a height of the first bearing surface 2111, or the surface on which the pin 22 and the first bearing surface 2111 are located and the first bearing surface 2111 are in the same plane; the bonding wire further comprises a third bonding wire 33 and a fourth bonding wire 34 which are adjacent to each other. A first section 331 of the third bonding wire 33 is connected to the pad 135 of the first chip 11, and a third section 333 is connected to the pin 22; a first section 341 of the fourth bonding wire 34 is connected to the pad 136 of the second chip 12, and a third section 343 is connected to the pin 22; a second section 332 of the third bonding wire 33 is located on a side of a second section 342 of the fourth bonding wire 34 facing the first bearing part 211. Wherein the third bonding wire 33 and the fourth bonding wire 34 are adjacent to each other means that there is no other bonding wire between the third bonding wire 33 and the fourth bonding wire 34. Due to the height of the first bearing surface 2111 being less than the height of the second bearing surface 2121, the height of the surface on which the pin 22 and the first bearing surface 2111 are located is less than or equal to the height of the first bearing surface 2111, the height of the surface on which the pin 22 and the first bearing surface 2111 are located is less than or equal to the height of the first bearing surface 2111, and the first bearing surface 2111 and the second bearing surface 2121 are in the same plane, in the case that the third section 333 of the third bonding wire 33 and the third section 343 of the fourth bonding wire 34 have the same size in the X direction, the height difference between the second section 332 of the third bonding wire 33 and the second section 342 of the fourth bonding wire 34 can be increased, and the risk of short circuit caused by the contact between the third bonding wire 33 and the fourth bonding wire 34 due to the impact of the insulating material on the third bonding wire 33 and the fourth bonding wire 34 when forming the insulating structure (such as a plastic sealing layer) covering the third bonding wire and the fourth bonding wire can be reduced.

[0056] In one embodiment, as shown in Figure 1 and Figure 3As shown, the third bonding wire 33 is adjacent to the fourth bonding wire 34 in the direction of the plane in which the chip front surface of the second chip 20 lies. In another embodiment, the third bonding wire 33 is adjacent to the fourth bonding wire 34 in the direction perpendicular to the plane in which the chip front surface of the second chip 12 lies, and the orthographic projection of the second section 332 of the third bonding wire 33 on the plane overlaps the orthographic projection of the second section 342 of the fourth bonding wire 34 on the plane.

[0057] In one embodiment, as shown in Figure 4 and Figure 5 The semiconductor structure further comprises an insulating portion 50, which at least covers the second section 312 of the first bonding wire 31. In this way, even if the first bonding wire and the second bonding wire are impacted by the encapsulating material during the process of forming the encapsulating layer, the first bonding wire and the second bonding wire will not be in contact, and the situation that the adjacent first bonding wire and the second bonding wire are in contact and cause short circuit can be avoided. Also, the bonding wire covered by the insulating portion can be prevented from collapsing due to the impact of the encapsulating material during the process of forming the encapsulating layer, and the part of the bonding wire that has collapsed is in contact with the conductive structure on the chip surface and causes short circuit, thereby improving the yield of the semiconductor structure. The insulating portion is a non-conductive structure, and does not affect the electrical performance of the semiconductor structure.

[0058] Further, as shown in Figure 4 and Figure 5 The insulating portion 50 covers the first bonding wire 31 and the second bonding wire 32. In this way, during the process of forming the encapsulating layer, the first bonding wire 31 and the second bonding wire 32 will not move under the impact of the encapsulating material, and the first bonding wire 31 and the second bonding wire 32 can be more effectively prevented from being in contact.

[0059] Further, as shown in Figure 4 and Figure 5 The insulating portion 50 covers the entire area of the chip front surface of the chip 10. In this way, the insulating portion 50 can protect the solder pad 11 arranged on the chip front surface.

[0060] Further, the insulating portion 50 covers the chip front surface and the area of the carrier portion 21 that is not covered by the chip. In this way, the insulating portion 50 can make the chip 10 fixed more firmly on the carrier portion 21, and further prevent the chip 10 from moving relative to the carrier portion 21.

[0061] In one embodiment, as shown in Figure 4As shown, the insulating portion 50 covers the third bonding wire 33 and the fourth bonding wire 34. With this configuration, even if the molding compound impacts the third bonding wire 33 and the fourth bonding wire 34 during the molding process, the third bonding wire 33 and the fourth bonding wire 34 will not come into contact, thus avoiding the situation where adjacent first bonding wires come into contact with second bonding wires and cause a short circuit.

[0062] In one embodiment, the temperature at which the insulating portion 50 transforms from a solid to a molten state is higher than the curing temperature of the material of the encapsulation layer 40. The encapsulation layer 40 is formed after the insulating portion 50. By setting the temperature at which the insulating portion 50 transforms from a solid to a molten state to a higher temperature than the curing temperature of the material of the encapsulation layer 40, it is possible to avoid the insulating portion 50 transforming into a molten state during the curing process of the encapsulation layer 40, which would prevent the insulating portion 50 from no longer covering the bonding wires it covered before melting, thus avoiding contact between adjacent bonding wires.

[0063] In one embodiment, the insulating portion 50 is made of acrylic hot melt adhesive (AD glue). This results in a lower material cost for the insulating portion 50, without significantly increasing the fabrication cost of the semiconductor structure. In other embodiments, the insulating portion 50 can be made of other materials that can be dynamically converted from a fluid state to a solid state.

[0064] In one embodiment, the insulating portion 50 covers the front side of the chip 10, and the material of the insulating portion 50 is a material with very low transmittance, for example, the material of the insulating portion 50 may be black. This configuration makes it impossible to directly observe the structure of the chip 10, increasing the difficulty of technically deciphering the semiconductor structure.

[0065] In one embodiment, such as Figure 3 As shown, the pin 22 is exposed from the surface of the molding compound 40 away from the front of the chip. In other embodiments, the pin 22 may be exposed from the side of the molding compound 40. The portion of the pin 22 exposed in the molding compound can be electrically connected to external components.

[0066] This application also provides a method for manufacturing a semiconductor structure, such as... Figure 6 As shown, the manufacturing method includes the following steps 110 to 150.

[0067] In step 110, an electrical connector is provided, the electrical connector including a carrier portion and a plurality of pins located on the side of the carrier portion; the carrier portion includes a first carrier portion and a second carrier portion, the first carrier portion including a first carrier surface, the second carrier portion including a second carrier surface, the first carrier surface and the second carrier surface being located on the same side of the carrier portion, and the height of the first carrier surface being less than the height of the second carrier surface.

[0068] In step 120, the first chip is mounted on the first bearing surface, and the second chip is mounted on the second bearing surface; the first chip and the second chip respectively include a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the chip back surface of the first chip faces the first bearing surface; and the chip back surface of the second chip faces the second bearing surface.

[0069] In one embodiment, the step of mounting the first chip on the first bearing surface and mounting the second chip on the second bearing surface can include the following process:

[0070] First, silver paste is applied on the first bearing surface, and silver paste is applied on the second bearing surface;

[0071] Then, the first chip is placed on the silver paste applied on the first bearing surface, and the second chip is placed on the silver paste applied on the second bearing surface;

[0072] Then, the silver paste is cured, and after the silver paste is cured, the first chip is fixed on the first bearing surface through the cured silver paste, and the second chip is fixed on the second bearing surface through the cured silver paste.

[0073] In step 130, the first pad of the first chip is taken as a first soldering point, the second pad of the second chip is taken as a second soldering point, and a first bonding wire is formed which is soldered to the first pad and the second pad respectively; the first bonding wire includes a first section connected to the first pad, a third section connected to the second pad, and a second section between the first section and the second section.

[0074] In one embodiment, the first bonding wire can be bonded to the first pad and the second pad by wire bonding. Wire bonding refers to a method of tightly soldering two structures by using heat, pressure, and ultrasonic energy.

[0075] In step 140, a second bonding wire is formed, which includes a first section, a second section, and a third section connected in sequence; the first section of the second bonding wire is soldered to a third pad of the second chip, and the third section is soldered to a fourth pad of the first chip or a pin; the first bonding wire is adjacent to the second bonding wire, and the second section of the first bonding wire is located on a side of the second section of the second bonding wire facing the first bearing part.

[0076] In one embodiment, the second bonding wire can be bonded to the pad or the pin by wire bonding.

[0077] In step 150, a plastic encapsulation layer is formed to encapsulate the first chip, the second chip, the electrical connector, the first bonding wire and the second bonding wire, and at least part of the pins are exposed from the plastic encapsulation layer.

[0078] In one embodiment, before the plastic encapsulation layer is formed, some pre-treatment steps can be performed, such as chemical cleaning, plasma cleaning, etc., to remove impurities on the surface of the chip and the electrical connector, so that the plastic encapsulation layer can be connected more closely with the chip and the electrical connector, and delamination or cracking does not occur.

[0079] In one embodiment, the material of the plastic encapsulation layer can be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer can be a resin with fillers, and the fillers can be inorganic particles. The plastic encapsulation layer can be formed by injection molding, compression molding or transfer molding, etc.

[0080] The manufacturing method of the semiconductor structure provided by the embodiments of the present application can set the size of the third section of the first bonding wire in the direction perpendicular to the front surface of the chip to be smaller than the size of the first section of the first bonding wire in the direction, and relative to the scheme that the first bearing surface and the second bearing surface are in the same plane, the distance between the second section of the first bonding wire and the second chip is reduced, and the height difference between the second section of the first bonding wire and the second section of the second bonding wire is increased when the distance between the second section of the second bonding wire and the second chip remains unchanged, so that the risk of short circuit caused by the contact between the first bonding wire and the second bonding wire due to the impact of the insulating material on the first bonding wire and the second bonding wire when forming the insulating structure (such as the plastic encapsulation layer) covering the first bonding wire and the second bonding wire can be reduced.

[0081] In one embodiment, before the plastic encapsulation layer is formed, the manufacturing method of the semiconductor structure further includes the following steps: dropping a flowable insulating material to the side of the front surface of the chip of the first chip, and solidifying the insulating material to form an insulating part; and the insulating part at least covers the part of the first bonding wire away from the front surface of the chip of the first chip.

[0082] Further, the orthogonal projection of the dropping track of the insulating material on the plane where the front surface of the chip of the first chip is located does not overlap with the orthogonal projection of the bonding wire on the plane. In this way, the situation that the adjacent bonding wires are in contact and short circuit occurs due to the direct dropping of the insulating material on the bonding wire, or the situation that the bonding wire is collapsed and the collapsed part of the bonding wire is in contact with the conductive structure on the surface of the chip and short circuit occurs can be avoided.

[0083] Further, an angle between a dropping trajectory of the insulating material and a normal projection of the chip front surface on a plane is an acute angle. In this way, the impact force of the insulating material on the bonding wire is reduced, and the short circuit of adjacent bonding wires caused by the impact of the bonding wire and the short circuit caused by the contact between the bonding wire and the conductive structure on the chip surface after the collapse of the bonding wire are improved. When the insulating material is dropped, the structure including the chip, the electrical connector and the bonding wire can be inclined to a certain angle with the horizontal direction, and then the insulating material is dropped, so that the angle between the dropping trajectory of the insulating material and the chip front surface is an acute angle.

[0084] Embodiments of the semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present application belong to the same inventive concept, and the related details and beneficial effects can be referred to each other, which will not be repeated here.

[0085] The embodiments of the present application further provide an electrical connector. The electrical connector includes a bearing part for mounting a chip and a plurality of pins, and the pins are located on the side of the bearing part.

[0086] The bearing part includes a first bearing part and a second bearing part, the first bearing part includes a first bearing surface, the second bearing part includes a second bearing surface, the first bearing surface and the second bearing surface are located on the same side of the bearing part, and the height of the first bearing surface is less than the height of the second bearing surface.

[0087] In one embodiment, the pins are located on the side of the first bearing part away from the second bearing part, or the surface of the pins facing the second bearing part is in the same plane as the surface of the first bearing part facing the second bearing part.

[0088] In one embodiment, the electrical connector is a lead frame, the bearing part is an island of the lead frame, and the island is spaced apart from the pins. In other embodiments, the electrical connector is a circuit board, the circuit board includes a main body part, the pins are located on the main body part, and the bearing part is a part of the main body part where the pins are not arranged.

[0089] The electrical connector and the semiconductor structure provided by the embodiments of the present application belong to the same inventive concept, and the related details and beneficial effects can be referred to each other, which will not be repeated here.

[0090] It is noted that in the drawings the relative sizes of layers and regions can be exaggerated for clarity. Also, it is to be understood that when a layer or element is referred to as being "on" another layer or element, it can be directly on the other layer or element or intervening layers can also be present. In addition, it is to be understood that when a layer or element is referred to as being "beneath" another layer or element, it can be directly beneath the other layer or element or one or more intervening layers or elements can also be present. In addition, it is to be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements or one or more intervening layers or elements can also be present. Like reference numerals refer to like elements throughout.

[0091] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0092] It is to be understood that the application is not limited to the precise details of design or construction set forth above and illustrated in the drawings as modifications can be made by those skilled in the art, and that the scope of the application is to be limited only by the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: an electrical connector comprising a carrier and a plurality of pins located at the side of the carrier; the carrier comprises a first carrier and a second carrier, the first carrier comprises a first carrier surface, and the second carrier comprises a second carrier surface, the first carrier surface and the second carrier surface are located at the same side of the carrier, and the height of the first carrier surface is less than the height of the second carrier surface; a plurality of chips comprising a first chip and a second chip; the chip comprises a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the first chip is attached to the first carrier surface with the chip back surface facing the first carrier surface; the second chip is attached to the second carrier surface with the chip back surface facing the second carrier surface; the height of the surface at the same side of the first carrier surface as the pins is less than the height of the first carrier surface; a plurality of bonding wires comprising a first section, a second section and a third section connected in sequence; the plurality of bonding wires comprises a first bonding wire, a second bonding wire, a third bonding wire and a fourth bonding wire, the first bonding wire is adjacent to the second bonding wire; the first section of the first bonding wire is connected to the pad of the first chip, and the third section is connected to the pad of the second chip; the first section of the second bonding wire is connected to the pad of the second chip, and the third section is connected to the pad of the first chip or the pin; the second section of the first bonding wire is located at the side of the second section of the second bonding wire facing the first carrier; the first section of the third bonding wire is connected to the pad of the first chip, and the third section is connected to the pin; the first section of the fourth bonding wire is connected to the pad of the second chip, and the third section is connected to the pin; the second section of the third bonding wire is located at the side of the second section of the fourth bonding wire facing the first carrier; a plastic encapsulation layer encapsulating the chips, the electrical connector and the bonding wires, and at least part of the pins is exposed from the plastic encapsulation layer.

2. The semiconductor structure of claim 1, wherein, In the direction perpendicular to the plane in which the chip front surface of the second chip is located, the first bonding wire is adjacent to the second bonding wire, and the second section of the first bonding wire has an overlapping projection on the plane with the second section of the second bonding wire; or, in the direction of the plane in which the chip front surface of the second chip is located, the first bonding wire is adjacent to the second bonding wire.

3. The semiconductor structure of claim 1, wherein, The height difference between the second carrier surface and the first carrier surface ranges from 100 μm to 300 μm.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises an insulating part, the insulating part at least covers the second section of the first bonding wire; the temperature at which the insulating part is converted from solid state to molten state is higher than the solidification temperature of the material of the plastic encapsulation layer.

5. The semiconductor structure of claim 1, wherein, The electrical connector is a lead frame, the carrier is an island of the lead frame, and the island is spaced apart from the pins; or, The electrical connector is a circuit board, the circuit board includes a main body part, the pins are located on the main body part, and the bearing part is a part of the main body part where the pins are not arranged.

6. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method includes: providing an electrical connector including a bearing part and a plurality of pins located on the side of the bearing part; the bearing part includes a first bearing part and a second bearing part, the first bearing part includes a first bearing surface, the second bearing part includes a second bearing surface, the first bearing surface and the second bearing surface are located on the same side of the bearing part, and the height of the first bearing surface is less than the height of the second bearing surface; the height of the surface on the same side of the pin and the first bearing surface is less than the height of the first bearing surface; mounting a first chip on the first bearing surface and mounting a second chip on the second bearing surface; the first chip and the second chip respectively include a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the chip back surface of the first chip faces the first bearing surface; and the chip back surface of the second chip faces the second bearing surface; forming a first bonding wire welded with the first pad and a second bonding wire welded with the second pad by taking the first pad of the first chip as a first welding point and taking the second pad of the second chip as a second welding point; the first bonding wire includes a first section connected with the first pad, a third section connected with the second pad, and a second section located between the first section and the second section; forming a second bonding wire including a first section, a second section and a third section connected in sequence; the first section of the second bonding wire is welded with a third pad of the second chip, and the third section is welded with a fourth pad of the first chip or the pin; the first bonding wire is adjacent to the second bonding wire, and the second section of the first bonding wire is located on the side of the second section of the second bonding wire facing the first bearing part; forming a plastic encapsulation layer encapsulating the first chip, the second chip, the electrical connector, the first bonding wire and the second bonding wire, and at least part of the pin is exposed from the plastic encapsulation layer; The manufacturing method of the semiconductor structure further includes: forming a third bonding wire and a fourth bonding wire; the first section of the third bonding wire is connected with a pad of the first chip, and the third section is connected with the pin; the first section of the fourth bonding wire is connected with a pad of the second chip, and the third section is connected with the pin; the second section of the third bonding wire is located on the side of the second section of the fourth bonding wire facing the first bearing part.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein Before forming the plastic encapsulation layer, the manufacturing method of the semiconductor structure further includes: dropping a flowable insulating material to the side of the chip front surface of the first chip, and curing the insulating material to form an insulating part; the insulating part at least covers the second section of the first bonding wire; The insulating material has a drop trajectory that does not overlap with a projection of the bonding wire on a plane in which a front surface of the first chip is located; and / or, an angle between the drop trajectory of the insulating material and a projection of the drop trajectory on the plane in which the front surface of the first chip is located is an acute angle.

8. An electrical connector, characterized by The semiconductor structure of any one of claims 1 to 5, or the manufacturing method of the semiconductor structure of claim 6 or 7; the electrical connector comprises a carrier portion for mounting a chip and a plurality of pins, the pins being located on a side portion of the carrier portion; The carrier portion comprises a first carrier portion and a second carrier portion, the first carrier portion comprises a first carrier surface, and the second carrier portion comprises a second carrier surface, the first carrier surface and the second carrier surface are located on the same side of the carrier portion, and a height of the first carrier surface is less than a height of the second carrier surface.

9. An electrical connection as claimed in claim 8, characterised in that, The electrical connector is a lead frame, the carrier portion is an island of the lead frame, and the island is spaced apart from the pins; or, The electrical connector is a circuit board, the circuit board comprises a main body portion, the pins are located on the main body portion, and the carrier portion is a portion of the main body portion on which the pins are not located.

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