Primary side feedback high-stability sampling circuit

Abstract

The invention provides a primary side feedback high-stability sampling circuit, belongs to the field of switching power supply design, and solves the problem of sampling time hysteresis in the existing scheme. In the circuit, a pull-up current source provides a pull-up current, a pull-down current source provides a pull-down current, and two groups of charge and discharge branches change charge and discharge voltages under the action of the pull-up current and the pull-down current, so that a sampling logic circuit outputs sampling signals outwards according to the change of the charge and discharge voltages; wherein a primary winding peak current source of the pull-down current source detects the change state of a primary winding peak current in adjacent periods before and after, and adjusts the magnitude of an output current of the primary winding peak current source according to the change state; and the output current is superposed with the output current of the lower bias current source to serve as the pull-down current of the pull-down current source. The sampling circuit provided by the invention can ensure that the sampling time point is always in the optimal sampling time period, and can maintain the accuracy and stability of the sampling signal even under the condition that the load fluctuates severely.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supply design and is applied to a flyback switching power supply with primary-side feedback. Specifically, it relates to a highly stable sampling circuit for primary-side feedback. Background Art

[0002] With the continuous growth of the market demand for consumer electronics products and the rapid technological updates, the requirements for power modules are also increasing day by day. The power module provides stable voltage or current for various functional modules and is one of the core components of consumer electronics products. The accuracy and stability of its output voltage are crucial for ensuring the performance of electronic products. In the modern complex and changing load environment, this requirement is particularly strict.

[0003] The primary-side feedback flyback converter is a common solution for achieving efficient and compact power supply design. This type of converter usually has a transformer with three parts: a primary winding, an auxiliary winding, and a secondary winding. The existing primary-side feedback mechanism relies on the auxiliary winding to monitor the output voltage and indirectly sense the change of the load at the output end. By comparing the sampled voltage with the reference voltage set inside the circuit, the amplified error signal VEA is used to adjust the operating frequency, duty cycle of the PWM signal, and the peak current of the primary winding to maintain the stability of the output voltage.

[0004] However, the traditional primary-side feedback method has certain limitations. To obtain the output voltage information, the system usually samples the auxiliary winding at a fixed time point in each switching cycle. This time point is generally selected within the demagnetization time TDEMAG of the secondary winding. But when the load changes, the peak current of the primary winding is adjusted accordingly, resulting in a significant difference in the demagnetization time on the secondary winding between adjacent switching cycles. The traditional sampling strategy determines the sampling moment of the next cycle based on the demagnetization time in the previous PWM cycle. Therefore, in the case of a sharp change in the load, if the demagnetization time changes greatly between two consecutive PWM cycles, it may lead to incorrect sampling results. Such mis-sampling will cause the feedback system to be unable to accurately reflect the actual output voltage condition, and may then cause the power supply to enter an unstable operating state. In this case, the system may repeatedly attempt to adjust the peak current and operating frequency of the primary winding, which not only affects the normal operation of the system but also may damage the entire power module.

[0005] To avoid the occurrence of the above problems, an improved circuit structure is needed to optimize the sampling process of the primary-side feedback flyback converter, ensure accurate and stable output voltage information can still be obtained during load fluctuations, and thus guarantee the reliability and efficiency of the power module. Summary of the Invention

[0006] The object of the present invention is to solve the problem of sampling time lag caused by the large difference in demagnetization signals in adjacent PWM cycles when the load changes in the existing primary-side feedback sampling circuit, as well as the resulting problems of incorrect output voltage sensing and output system disorder. Therefore, a primary-side feedback high-stability sampling circuit is proposed. The sampling circuit of the present invention can ensure that the sampling time point is always within the optimal sampling time period, and can maintain the accuracy and stability of the sampling signal even under severe load fluctuations.

[0007] The present invention adopts the following technical solutions to achieve the object:

[0008] A primary-side feedback high-stability sampling circuit includes a pull-up current source, a pull-down current source, a first charge-discharge branch, a second charge-discharge branch, a clock pair generator, and a sampling logic circuit; the pull-up current source is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously, and is used to provide a pull-up current; the pull-down current source is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously, and is used to provide a pull-down current; both the first charge-discharge branch and the second charge-discharge branch are connected to the sampling logic circuit. When the first charge-discharge branch and the second charge-discharge branch change their charge-discharge voltages under the combined action of the pull-up current and the pull-down current, the sampling logic circuit outputs a sampling signal with a preset sampling time according to the change of the charge-discharge voltage; the clock pair generator is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously, and is used to provide charge-discharge state switching signals corresponding to the two.

[0009] Among them, the pull-down current source includes a lower bias current source and a primary winding peak current source. The primary winding peak current source is used to detect the change state of the primary winding peak current in adjacent cycles before and after, and adjusts the magnitude of its output current according to the change state; the output currents of the lower bias current source and the primary winding peak current source are added together as the pull-down current output by the pull-down current source.

[0010] Furthermore, the pull-up current source includes an upper bias current source and a load current source. The load current source is used to detect the load change of the power supply module and adjusts the magnitude of its output current according to the load change; the output currents of the upper bias current source and the load current source are added together as the pull-up current output by the pull-up current source.

[0011] Specifically, the load current source is an operational amplifier OPD. The load change of the power supply module is characterized by an output voltage error amplification signal VEA corresponding to the load; the output voltage error amplification signal VEA is connected to the positive input terminal of the operational amplifier OPD, and the negative input terminal of the operational amplifier OPD is connected to the internal reference voltage VREF of the power supply module; after the output current IP_EA of the operational amplifier OPD and the output current of the upper bias current source are subjected to an addition operation, a pull-up current IP is obtained and output to the first charge-discharge branch and the second charge-discharge branch.

[0012] Further, the primary winding peak current source realizes the detection of the change state of the primary winding peak current through the primary winding peak voltage VCS; the primary winding peak current source includes operational amplifiers OPA, OPB, and OPC, capacitors C3, C4, switch CS_CTR, and resistor RES;

[0013] The primary winding peak voltage VCS is connected to the positive input terminal of operational amplifier OPA, and the output terminal of operational amplifier OPA is connected to its negative input terminal to form a negative feedback structure; the output terminal of operational amplifier OPA is also connected to capacitor C3, capacitor C3 is connected to capacitor C4, and switch CS_CTR is set between the two. The on / off of capacitor C3 and C4 is controlled by switch CS_CTR under the clock logic signal of the clock pair generator;

[0014] Capacitor C4 is also connected to the positive input terminal of operational amplifier OPB, the primary winding peak voltage VCS is also connected to the negative input terminal of operational amplifier OPB, and the output terminal of operational amplifier OPB is connected to the positive input terminal of operational amplifier OPC; one end of resistor RES is grounded, and the other end is connected to the negative input terminal and the output terminal of operational amplifier OPC. After the output current IN_CS of operational amplifier OPC is added to the output current of the lower bias current source, the pull-down current IN is obtained and output to the first charge and discharge branch and the second charge and discharge branch;

[0015] When the voltage of the positive input terminal of operational amplifier OPB is compared with the voltage of the negative input terminal, if the positive difference is larger, the output current IN_CS of operational amplifier OPC is larger; conversely, if the negative difference is larger, the output current IN_CS of operational amplifier OPC is smaller.

[0016] Further, both the first charge and discharge branch and the second charge and discharge branch include their respective corresponding charging capacitors, charging switches, and discharging switches; the charging switches are connected to the upper pull current source, and the discharging switches are connected to the lower pull current source; the common terminal of the charging switch and the discharging switch is connected to the corresponding charging capacitor, and at the same time, this common terminal is also connected to the input terminal of the sampling logic circuit;

[0017] The control terminals of the charging switch and the discharging switch are both connected to the clock signal output terminal of the clock pair generator; the clock pair generator uses its output two pairs of clock signals as the charge and discharge state switching signals of the first charge and discharge branch and the second charge and discharge branch; the two pairs of clock signals make the second charge and discharge branch work in the discharge state when the first charge and discharge branch works in the charge state; conversely, when the first charge and discharge branch works in the discharge state, the second charge and discharge branch works in the charge state.

[0018] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:

[0019] The original-side feedback high-stability sampling circuit proposed by the present invention realizes the precise comparison between the output voltage error amplified signal VEA and the internal reference voltage. This process generates a linear charging current that varies according to the load size, ensuring that the sampling time point can dynamically adapt to the load conditions. Specifically, when the load increases, the sampling time point will be shifted backward accordingly; conversely, when the load decreases, the sampling time point will be adjusted forward. This design enables the sampling moment to always fall within the optimal sampling time period, thus effectively avoiding large errors caused by improper sampling time.

[0020] In addition, the present invention also introduces a detection mechanism for the change of the primary winding peak current. By monitoring the signal VCS of the primary winding peak detection current, the trend of current change can be detected between the front and back PWM cycles. If the VCS signal shows that the primary winding peak current increases in adjacent PWM cycles, the sampling time point will be delayed; conversely, if the VCS signal indicates that the peak current decreases, the sampling time point will be advanced. Such dynamic adjustment not only keeps the sampling time point always within the preset optimal range, but also ensures the accuracy and reliability of the sampling results even under severe load fluctuations.

[0021] In summary, the present invention effectively solves the problems of hysteresis and inaccuracy existing in the traditional sampling scheme. On the one hand, the present invention optimizes the selection of the sampling time point, avoiding the time period that may cause large sampling errors, and improving the sampling accuracy and the ability to reflect load changes. On the other hand, in the face of the challenge of severe load fluctuations, the present invention also ensures that the sampling time point falls within a reasonable range, maintaining the stability of the sampling signal. These improvements work together to provide a more stable and reliable operation guarantee for the power supply module. Description of the Drawings

[0022] Figure 1 It is a schematic structural diagram of the sampling circuit of the present invention;

[0023] Figure 2 It is a schematic diagram of the electrical connection principle of the sampling circuit of the present invention;

[0024] Figure 3 It is a schematic diagram of the electrical connection principle of the primary winding peak current source in the present invention;

[0025] Figure 4 It is a schematic diagram of the electrical connection principle of the load current source in the present invention;

[0026] Figure 5 It is a schematic diagram of the sampling signal generated by the combination of the pull-up current source and the pull-down current source and the clock pair in the present invention;

[0027] Figure 6Schematic diagram for comparing the optimized stable sampling signal and the traditional sampling signal of the present invention under load fluctuations. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0030] Embodiment 1

[0031] As Figure 1 shown, a primary-side feedback highly stable sampling circuit includes a pull-up current source, a pull-down current source, a first charge-discharge branch, a second charge-discharge branch, a clock pair generator, and a sampling logic circuit; the pull-up current source is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously to provide a pull-up current; the pull-down current source is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously to provide a pull-down current; both the first charge-discharge branch and the second charge-discharge branch are connected to the sampling logic circuit. When the first charge-discharge branch and the second charge-discharge branch change their charge-discharge voltages under the combined action of the pull-up current and the pull-down current, the sampling logic circuit outputs a sampling signal with a preset sampling time according to the change of the charge-discharge voltage; the clock pair generator is connected to the first charge-discharge branch and the second charge-discharge branch simultaneously to provide charge-discharge state switching signals corresponding to both of them.

[0032] The key of the sampling circuit in this embodiment is that the pull-down current source includes a lower bias current source and a primary winding peak current source. The primary winding peak current source is used to detect the change state of the primary winding peak current in adjacent cycles before and after, and adjust the magnitude of its output current according to the change state; the output currents of the lower bias current source and the primary winding peak current source are added together as the pull-down current output by the pull-down current source.

[0033] Combined with the above overall structure, this embodiment will introduce the preferred structures of the pull-up current source and the pull-down current source in the sampling circuit.

[0034] As Figure 2As shown, the pull-up current source includes an upper bias current source and a load current source. The load current source is used to detect the load change of the power supply module and adjust the magnitude of its output current according to the load change; the output currents of the upper bias current source and the load current source are added together as the pull-up current output by the pull-up current source.

[0035] Combined with Figure 2 and Figure 4 In the schematic diagram, the load current source is the operational amplifier OPD. The load change of the power supply module is characterized by the output voltage error amplification signal VEA corresponding to the load; the output voltage error amplification signal VEA is connected to the positive input terminal of the operational amplifier OPD, and the negative input terminal of the operational amplifier OPD is connected to the internal reference voltage VREF of the power supply module; after the output current IP_EA of the operational amplifier OPD and the output current of the upper bias current source are added, the pull-up current IP is obtained and output to the first charge-discharge branch and the second charge-discharge branch.

[0036] In this embodiment, the output current IP_BIAS of the upper bias current source is a fixed current; the larger the output voltage error amplification signal VEA, the larger the output current IP_EA of the operational amplifier OPD, and the larger the pull-up current IP after adding with the output current IP_BIAS; conversely, the smaller the output current IP_EA, the smaller the corresponding pull-up current IP.

[0037] For the key structure of the pull-down current source, it can be combined with Figure 2 and Figure 3 In the schematic diagram, the primary winding peak current source realizes the detection of the change state of the primary winding peak current through the primary winding peak voltage VCS. The preferred structure is: the primary winding peak current source includes operational amplifiers OPA, OPB, and OPC, capacitors C3, C4, switch CS_CTR, and resistor RES.

[0038] As Figure 3 shown, the primary winding peak voltage VCS is connected to the positive input terminal of the operational amplifier OPA. The output terminal of the operational amplifier OPA is connected to its negative input terminal to form a negative feedback structure; the output terminal of the operational amplifier OPA is also connected to the capacitor C3. The capacitor C3 is connected to the capacitor C4, and the switch CS_CTR is set between them. The switch CS_CTR controls the on-off of the capacitor C3 and C4 under the clock logic signal of the clock pair generator.

[0039] The capacitor C4 is also connected to the positive input terminal of the operational amplifier OPB, and the peak voltage VCS of the primary winding is also connected to the negative input terminal of the operational amplifier OPB. The output terminal of the operational amplifier OPB is connected to the positive input terminal of the operational amplifier OPC. One end of the resistor RES is grounded, and the other end is connected to the negative input terminal and the output terminal of the operational amplifier OPC. After the output current IN_CS of the operational amplifier OPC and the output current of the lower bias current source are added, the pull-down current IN is obtained and output to the first charge-discharge branch and the second charge-discharge branch.

[0040] When comparing the voltage of the positive input terminal and the negative input terminal of the operational amplifier OPB, if the positive difference is larger, the output current IN_CS of the operational amplifier OPC is larger; conversely, if the negative difference is larger, the output current IN_CS of the operational amplifier OPC is smaller.

[0041] In this embodiment, during the period of the peak current of the primary winding, the clock generator outputs the clock logic signal for disconnecting the switch CS_CTR corresponding to the high-level time of the PWM signal; and outputs the clock logic signal for turning on the switch CS_CTR corresponding to the low-level time of the PWM signal.

[0042] At the same time, the output terminal of the operational amplifier OPB outputs a voltage signal CS_EA and a logic signal CS_EA_CTR. The larger the voltage difference between the positive and negative input terminals of the operational amplifier OPB, the larger the output voltage signal CS_EA, and vice versa. At the same time, if the voltage of the positive input terminal of the operational amplifier OPB is higher than its negative input terminal voltage, the output logic signal CS_EA_CTR is a logic high level, otherwise it is a logic low level.

[0043] In this embodiment, the voltage signal CS_EA output by the operational amplifier OPB is connected to the positive input terminal of the operational amplifier OPC, and the logic signal CS_EA_CTR output by the operational amplifier OPB is connected to the control terminal of the operational amplifier OPC. The operational amplifier OPC operates under the control of the logic signal CS_EA_CTR.

[0044] For the lower bias current source in the pull-down current source, its output current IN_BIAS is also a fixed current. After the output current IN_CS of the operational amplifier OPC and the output current IN_BIAS are added, the pull-down current IN is output.

[0045] Embodiment 2

[0046] Based on Embodiment 1, this embodiment introduces the remaining component structures of the primary-side feedback high-stability sampling circuit in detail. Please refer to Figure 1 and Figure 2 for the schematic diagram.

[0047] First, both the first charge-discharge branch and the second charge-discharge branch include their respective corresponding charging capacitors, charging switches, and discharging switches. In this embodiment, as Figure 2 shown, the first charge-discharge branch has a charging capacitor C1, a charging switch PM1, and a discharging switch NM1; the corresponding second charge-discharge branch also has its charging capacitor C2, a charging switch PM2, and a discharging switch NM2. For these two sets of charge-discharge branches, their charging switches are connected to the pull-up current source, the discharging switches are connected to the pull-down current source, and the common terminal of the charging switch and the discharging switch is connected to the corresponding charging capacitor, and this common terminal is also connected to the input terminal of the sampling logic circuit. Figure 2 In, out1 is the output of the first charge-discharge branch, and out2 is the output of the second charge-discharge branch.

[0048] As Figure 2 shown, the control terminals of the charging switch and the discharging switch are both connected to the clock signal output terminal of the clock pair generator. The clock pair generator uses the two pairs of clock signals output by it as the charge-discharge state switching signals for the first charge-discharge branch and the second charge-discharge branch; the two pairs of clock signals cause the second charge-discharge branch to operate in the discharging state when the first charge-discharge branch operates in the charging state; conversely, when the first charge-discharge branch operates in the discharging state, the second charge-discharge branch operates in the charging state.

[0049] In this embodiment, the first pair of clock signals cp1 and cp2 act on the charging switch PM1 and the charging switch PM2, and the second pair of clock signals cn1 and cn2 act on the discharging switch NM1 and the discharging switch NM2. Each pair of clock signals includes a demagnetization time signal and its inverted signal, so that when the charging switch PM1 is turned on, the charging switch PM2 is turned off; similarly, when the discharging switch NM1 is turned on, the discharging switch NM2 is turned off. Taking the first charge-discharge branch as an example again, when it is in the charging state, the charging switch PM1 is turned on and the discharging switch NM1 is turned off. Thus, through the control of the clock pair generator, the charge-discharge states of the first charge-discharge branch and the second charge-discharge branch are alternately switched.

[0050] Finally, the sampling logic circuit detects the voltages of the charging capacitors of the first charge-discharge branch and the second charge-discharge branch through the common terminal of the charging switch and the discharging switch; when the voltage of the charging capacitor of any branch reaches the preset threshold level, the sampling logic circuit outputs a square wave signal with a width value of D as the sampling signal, and its width value D is used to represent the preset sampling time. In this embodiment, preferably, the sampling time range represented by the square wave signal width value D is from 200 nanoseconds to 400 nanoseconds.

[0051] Under the preferred structure of the primary side feedback high-stability sampling circuit in this embodiment, the pull-down current provided by the pull-down current source is greater than the pull-up current provided by the pull-up current source.

[0052] Based on the preferred combinations of the structural features in the above embodiments, the working principle and effects of the primary-side feedback high-stability sampling circuit of the present invention will be described in detail below. The content here can be referred to Figure 4 and Figure 5 the signal schematic diagrams and comparison diagrams of

[0053] The primary-side feedback high-stability sampling circuit provided by the present invention is a sampling circuit that can be stable as the load state changes, and this circuit structure can be specifically applied to the control of primary-side feedback switching power supplies.

[0054] The output voltage is sampled through an auxiliary winding, and the sampled voltage is amplified by an operation with the internal reference voltage of the circuit to obtain an output voltage error amplification signal VEA, which is input to the positive terminal of the operational amplifier OPD. The internal reference voltage VREF is also connected to the negative terminal of the current operational amplifier OPD. When the load increases, the signal VEA output by the error amplifier increases, then the output current IP_EA of the operational amplifier OPD increases. After being superimposed with the output current IP_BIAS of the fixed-size upper bias current source, the pull-up current IP increases. At this time, at the pull-down current source, the voltage rise slope on the capacitor C3 or C4 of the primary winding peak current source will increase. In the same time, the voltage peak of the capacitor C3 or C4 rises higher. Then, in the next cycle, if the pull-down current IN remains unchanged, it will take more time for the voltage on the capacitor C3 or capacitor C4 to fall back to the threshold voltage, which will cause the sampling point to shift backward.

[0055] When the load decreases, the output voltage error amplification signal VEA decreases, the output current IP_EA of the operational amplifier OPD decreases. After being superimposed with the output current IP_BIAS of the fixed-size upper bias current source, the pull-up current IP decreases. At this time, at the pull-down current source, the voltage rise slope on the capacitor C3 or C4 of the primary winding peak current source will decrease. In the same time, the voltage peak of the capacitor C3 or C4 rises lower. Then, in the next cycle, if the pull-down current IN remains unchanged, it will only take less time for the voltage on the capacitor C3 or C4 to fall back to the threshold voltage, which will cause the sampling point to shift forward.

[0056] At the primary winding peak current source, the primary winding peak voltage VCS is connected to the positive terminal of the operational amplifier OPA. Through the negative feedback circuit structure, the peak voltage VCS of the current PWM cycle is stored on the capacitor C3. At the same time, during the conduction stage of the current PWM cycle, that is, the high-level time of the PWM signal, the switch CS_CTR is disconnected, and the voltage of the capacitor C4 remains unchanged; during the off stage of the current PWM cycle, the switch CS_CTR is turned on, and then the peak voltage VCS of the current PWM cycle is transferred from the capacitor C3 to the capacitor C4. Therefore, the primary winding peak voltage VCS of the previous PWM cycle is stored on the capacitor C4.

[0057] The primary winding peak voltage VCS of the previous PWM cycle stored on the capacitor C4, described here as VCSA, will be amplified and calculated by the operational amplifier OPB together with the primary winding peak voltage VCS of this PWM cycle, described here as VCSB, to amplify the tiny difference between the two and obtain the primary winding peak current error amplified signal, that is, the output voltage signal CS_EA of the operational amplifier OPB.

[0058] The operational amplifier OPB will also compare the magnitudes of VCSA of the previous PWM cycle and VCSB of this PWM cycle; if the peak voltage VCSB is lower than VCSA, its output logic signal CS_EA_CTR is at a high level. At this time, if the difference between the two is larger, it indicates that the load of the power supply module has decreased sharply, the primary winding peak current in this PWM cycle will decrease sharply, and the demagnetization time TDEMAG on the secondary winding in this PWM cycle will necessarily decrease. At this time, the output current IN_CS of the corresponding operational amplifier OPC is larger, and the pull-down current IN after superimposing the output current IN_BIAS of the internal fixed lower bias current source increases. The voltage drop slope of the capacitors C1 or C2 corresponding to the two charge and discharge branches is faster, so the time from the demagnetization start moment to the time when the capacitor voltage drops to the threshold voltage is shorter, causing the sampling point to shift forward.

[0059] Similarly, if the peak voltage VCSB is higher than VCSA, the operational amplifier OPB outputs a logic signal CS_EA_CTR at a low level. At this time, if the difference between the two is larger, it indicates that the load of the power supply module has increased sharply, the primary winding peak current in this PWM cycle will increase sharply, and the demagnetization time TDEMAG on the secondary winding in this PWM cycle will necessarily increase. At this time, the output current IN_CS of the corresponding operational amplifier OPC is smaller, and the pull-down current IN after superimposing the output current IN_BIAS of the internal fixed lower bias current source decreases. The voltage drop slope of the capacitors C1 or C2 corresponding to the two charge and discharge branches is slower, so the time from the demagnetization start moment to the time when the capacitor voltage drops to the threshold voltage is longer, causing the sampling point to shift backward.

[0060] The present invention thus adjusts the pull-up current IP by outputting a voltage error amplification signal VEA, and combines the detection of the change in the peak voltage VCS of the primary winding in the previous PWM cycle and the present PWM cycle to adjust the pull-down current IN, so as to not only ensure the high precision of the finally output sampling signal, but also ensure the stability of the sampling signal.

Claims

1. A primary-side feedback high-stability sampling circuit, characterized in that: It includes a pull-up current source, a pull-down current source, a first charge-discharge branch, a second charge-discharge branch, a clock pair generator and a sampling logic circuit; the pull-up current source is connected to the first charge-discharge branch and the second charge-discharge branch at the same time, and is used to provide a pull-up current; the pull-down current source is connected to the first charge-discharge branch and the second charge-discharge branch at the same time, and is used to provide a pull-down current; the first charge-discharge branch and the second charge-discharge branch are both connected to the sampling logic circuit, and when the first charge-discharge branch and the second charge-discharge branch change their charge-discharge voltages under the combined action of the pull-up current and the pull-down current, the sampling logic circuit outputs a sampling signal with a preset sampling time according to the change of the charge-discharge voltage; the clock pair generator is connected to the first charge-discharge branch and the second charge-discharge branch at the same time, and is used to provide corresponding charge-discharge state switching signals for the two; Among them, the pull-down current source includes a lower bias current source and a primary winding peak current source. The primary winding peak current source is used to detect the change state of the primary winding peak current in the adjacent cycles and adjust its own output current size according to the change state; the output currents of the lower bias current source and the primary winding peak current source are added together to serve as the pull-down current output by the pull-down current source.

2. The primary-side feedback high-stability sampling circuit according to claim 1, characterized in that: The pull-up current source includes an upper bias current source and a load current source. The load current source is used to detect the load change of the power module and adjust its own output current according to the load change. The output currents of the upper bias current source and the load current source are added together to serve as the pull-up current output by the pull-up current source.

3. The primary-side feedback high-stability sampling circuit according to claim 2, characterized in that: The load current source is an operational amplifier OPD, and the load change of the power module is characterized by the output voltage error amplification signal VEA corresponding to the load; the output voltage error amplification signal VEA is connected to the positive input terminal of the operational amplifier OPD, and the negative input terminal of the operational amplifier OPD is connected to the internal reference voltage VREF of the power module; after the output current IP_EA of the operational amplifier OPD is added to the output current of the upper bias current source, the pull-up current IP is obtained and output to the first charge and discharge branch and the second charge and discharge branch.

4. The primary-side feedback high-stability sampling circuit according to claim 3, characterized in that: The output current IP_BIAS of the upper bias current source is a fixed current; the larger the output voltage error amplification signal VEA is, the larger the output current IP_EA of the operational amplifier OPD is, and the larger the pull-up current IP after adding the output current IP_BIAS is; conversely, the smaller the output current IP_EA is, the smaller the corresponding pull-up current IP is.

5. The primary-side feedback high-stability sampling circuit according to claim 1, characterized in that: The primary winding peak current source realizes the change state detection of the primary winding peak current through the primary winding peak voltage VCS; the primary winding peak current source includes operational amplifiers OPA, OPB and OPC, capacitors C3 and C4, a switch CS_CTR and a resistor RES; The primary winding peak voltage VCS is connected to the positive input terminal of the operational amplifier OPA, and the output terminal of the operational amplifier OPA is connected to its negative input terminal to form a negative feedback structure; the output terminal of the operational amplifier OPA is also connected to the capacitor C3, and the capacitor C3 is connected to the capacitor C4, and a switch CS_CTR is set between the two, and the switch CS_CTR controls the on and off of the capacitors C3 and C4 under the clock logic signal of the clock pair generator; The capacitor C4 is also connected to the positive input terminal of the operational amplifier OPB, the primary winding peak voltage VCS is also connected to the negative input terminal of the operational amplifier OPB, and the output terminal of the operational amplifier OPB is connected to the positive input terminal of the operational amplifier OPC; one end of the resistor RES is grounded, and the other end is connected to the negative input terminal and the output terminal of the operational amplifier OPC, and the output current IN_CS of the operational amplifier OPC is added to the output current of the lower bias current source to obtain the pull-down current IN and output it to the first charge-discharge branch and the second charge-discharge branch; Compared with the voltage at the positive input terminal and the voltage at the negative input terminal of the operational amplifier OPB, if the positive difference is larger, the output current IN_CS of the operational amplifier OPC is larger; conversely, if the negative difference is larger, the output current IN_CS of the operational amplifier OPC is smaller.

6. The primary-side feedback high-stability sampling circuit according to claim 5, characterized in that: The clock pair generator outputs a clock logic signal for disconnecting the switch CS_CTR corresponding to the high level time of the PWM signal during the period of the primary winding peak current; and outputs a clock logic signal for turning on the switch CS_CTR corresponding to the low level time of the PWM signal.

7. The primary-side feedback high-stability sampling circuit according to claim 5, characterized in that: The output terminal of the operational amplifier OPB outputs a voltage signal CS_EA and a logic signal CS_EA_CTR. The greater the voltage difference between the positive and negative input terminals of the operational amplifier OPB, the greater the output voltage signal CS_EA, and vice versa. At the same time, if the voltage of the positive input terminal of the operational amplifier OPB is higher than the voltage of its negative input terminal, the output logic signal CS_EA_CTR is a logic high level, otherwise it is a logic low level. The voltage signal CS_EA output by the operational amplifier OPB is connected to the positive input terminal of the operational amplifier OPC, and the logic signal CS_EA_CTR output by the operational amplifier OPB is connected to the control terminal of the operational amplifier OPC; the operational amplifier OPC operates under the control of the logic signal CS_EA_CTR; The output current IN_BIAS of the lower bias current source is a fixed current. After the output current IN_CS of the operational amplifier OPC is added to the output current IN_BIAS, the pull-down current IN is output.

8. The primary-side feedback high-stability sampling circuit according to claim 1, characterized in that: The first charging and discharging branch and the second charging and discharging branch each include a corresponding charging capacitor, a charging switch and a discharging switch; the charging switch is connected to a pull-up current source, and the discharging switch is connected to a pull-down current source; a common end of the charging switch and the discharging switch is connected to a corresponding charging capacitor, and the common end is also connected to an input end of a sampling logic circuit; The control ends of the charging switch and the discharging switch are both connected to the clock signal output end of the clock pair generator; the clock pair generator uses the two pairs of clock signals outputted by it as the charging and discharging state switching signals of the first charging and discharging branch and the second charging and discharging branch; the two pairs of clock signals make the second charging and discharging branch work in the discharging state when the first charging and discharging branch works in the charging state; conversely, when the first charging and discharging branch works in the discharging state, the second charging and discharging branch works in the charging state.

9. The primary-side feedback high-stability sampling circuit according to claim 8, characterized in that: The sampling logic circuit performs voltage detection on the charging capacitors of the first charging and discharging branch and the second charging and discharging branch through the common end of the charging switch and the discharging switch; when the voltage of the charging capacitor of any branch reaches a preset threshold level, the sampling logic circuit outputs a square wave signal with a width value of D as a sampling signal, and its width value D is used to characterize a preset sampling time.

10. The primary-side feedback high-stability sampling circuit according to claim 8, characterized in that: In the two pairs of clock signals output by the clock pair generator, each pair of clock signals includes a demagnetization time signal and an inverted signal thereof; the pull-down current provided by the pull-down current source is greater than the pull-up current provided by the pull-up current source.

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